XC17S100XLPSO201 [ETC]
Peripheral IC ; 周边IC\n
ETC 
0
R
Spartan Family of PROMs
0
5*
DS030 (v1.5) April 4, 2000
Product Specification
Introduction
Spartan PROM Features
The Spartan™ family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan device configura-
tion bitstreams.
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan, Spartan-XL, and Spartan-II FPGA devices
Simple interface to the Spartan device requires only
one user I/O pin
•
When the Spartan device is in Master Serial mode, it gen-
erates a configuration clock that drives the Spartan PROM.
A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
the Spartan device DIN pin. The Spartan device generates
the appropriate number of clock pulses to complete the
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an incom-
ing signal.
•
•
•
•
Programmable reset polarity (active High or active Low)
Low-power CMOS floating gate process
Available in 5V and 3.3V versions
Available in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC (XC17S40 only) packages.
Programming support by leading programmer
manufacturers.
•
•
Design support using the Xilinx Alliance and
Foundation series software packages.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the
Spartan device design file into a standard HEX format
which is then transferred to most commercial PROM pro-
grammers.
Spartan FPGA
XCS05
Configuration Bits
53,984
Compatible Spartan PROM
XC17S05
XCS05XL
XCS10
54,544
XC17S05XL
XC17S10
95,008
XCS10XL
XC2S15
XCS20
95,752
XC17S10XL
XC17S15XL
XC17S20
197,728
178,144
179,160
247,968
249,168
336,768
329,312
330,696
559,232
781,248
1,040,128
1,335,872
XCS20XL
XCS30
XC17S20XL
XC17S30
XCS30XL
XC2S30
XCS40
XC17S30XL
XC17S30XL
XC17S40
XCS40XL
XC2S50
XC2S100
XC2S150
XC2S200
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
XC17S200XL
DS030 (v1.5) April 4, 2000
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Spartan Family of PROMs
Pin Description
Table 1: Spartan PROM Pinouts
8-pin
PDIP & VOIC
20-pin
SOIC
Pin Name
Pin Description
DATA
1
1
Data output, 3-stated when either CE or OE are inactive. During pro-
gramming, the DATA pin is I/O. Note that OE can be programmed to
be either active High or active Low.
CLK
2
3
Each rising edge on the CLK input increments the internal address
counter, if both CE and OE are active.
When High, this input holds the address counter reset and 3-states
the DATA output. The polarity of this input pin is programmable as ei-
ther RESET/OE or OE/RESET. To avoid confusion, this document
describes the pin as RESET/OE, although the opposite polarity is
possible on all devices. When RESET is active, the address counter
is held at zero, and the DATA output is 3-stated. The polarity of this
input is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be driven by
the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This
input pin is easily inverted using the Xilinx HW-130 programmer soft-
ware. Third-party programmers have different methods to invert this
pin.
RESET/OE
(OE/RESET)
3
4
8
CE
10
11
When High, this pin disables the internal address counter, 3-states
the DATA output, and forces the device into low-ICC standby mode.
GND
VCC
5
GND is the ground connection.
7, 8
18, 20 The VCC pins are to be connected to the positive voltage supply.
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Spartan Family of PROMs
Programming the FPGA With Counters
Unchanged Upon Completion
Controlling PROMs
Connecting the Spartan device with the PROM:
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
•
•
•
The DATA output of the PROM drives the DIN input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is driven by the INIT
output of the Spartan device. This connection assures
that the PROM address counter is reset before the start
of any (re)configuration, even when a reconfiguration is
initiated by a VCC glitch. Other methods – such as
This method fails if a user applies RESET during the Spar-
tan device configuration process. The Spartan device
aborts the configuration and then restarts a new configura-
tion, as intended, but the PROM does not reset its address
counter, since it never saw a High level on its OE input. The
new configuration, therefore, reads the remaining data in
the PROM and interprets it as preamble, length count etc.
Since the Spartan device is the Master, it issues the neces-
sary number of CCLK pulses, up to 16 million (224) and
DONE goes High. However, the Spartan device configura-
tion will be completely wrong, with potential contentions
inside the Spartan device and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
driving RESET/OE from LDC or system reset – assume
that the PROM internal power-on-reset is always in step
with the FPGA’s internal power-on-reset, which may not
be a safe assumption.
The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is not
permanently grounded. Otherwise, LDC can be used to
drive CE, but must then be unconditionally High during
user operation. CE can also be permanently tied Low,
but this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
•
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are estab-
lished by a configuration program. The program is loaded
either automatically upon power up, or on command,
depending on the state of the Spartan device MODE pin. In
Master Serial mode, the Spartan device automatically
loads the configuration program from an external memory.
The Spartan PROM has been designed for compatibility
with the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the MODE pin is Low.
Data is read from the PROM sequentially on a single data
line. Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during configu-
ration.
Master Serial mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure the Spartan device. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The Spar-
tan family takes care of this automatically with an on-chip
default pull-up resistor.
DS030 (v1.5) April 4, 2000
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Spartan Family of PROMs
Spartan
Master Serial
3.3V
V
V
CC
MODE
4.7K
V
PP
CC
DATA
CLK
DIN
CCLK
DONE
INIT
Spartan
PROM
CE
OE/RESET
(Low Resets the Address Pointer)
CCLK
(Output)
DIN
DOUT
(Output)
DS030_01_040400
Figure 1: Master Serial Mode. The one-time-programmable Spartan PROM supports automatic loading of configuration
programs. An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.
4
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Spartan Family of PROMs
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high imped-
ance state regardless of the state of the OE input.
Programming the Spartan Family
PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
V
CC
GND
RESET/
CE
OE
or
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
OE
Output
DATA
Matrix
DS030_02_011300
Figure 2: Simplified Block Diagram (does not show programming circuit)
Important: Always tie the two VCC pins together in your application.
Table 2: Truth Table for XC17S00 Control Inputs
Control Inputs
Outputs
DATA
Internal Address
RESET
CE
Icc
Inactive
Low
If address < TC: increment
Active
Active
If address > TC: don’t change
3-state
Reduced
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
3-state
3-state
3-state
Active
Standby
Standby
Notes: 1. The XC17S00 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC+1 = address 0.
DS030 (v1.5) April 4, 2000
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Spartan Family of PROMs
XC17S05, XC17S10, XC17S20, XC17S30, XC17S40
Absolute Maximum Ratings
Symbol
Description
Value
Units
VCC
–0.5 to +7.0
Supply voltage relative to GND
V
VIN
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
+260
Input voltage relative to GND
V
V
VTS
Voltage applied to 3-state output
Storage temperature (ambient)
TSTG
TSOL
Note:
°C
°C
Maximum soldering temperature (10 s @ 1/16 in.)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
Operating Conditions
Symbol
Description
Commercial
Industrial
Min
4.75
4.50
Max
5.25
5.50
Units
VCC
Supply voltage relative to GND (TA = 0°C to +70°C)
Supply voltage relative to GND (TA = –40°C to +85°C)
V
V
Note: During normal read operation both VCC pins must be connected together.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
Max
Units
V
High-level input voltage
Low-level input voltage
2.0
0
VCC
0.8
VIL
V
VOH
VOL
VOH
VOL
ICCA
ICCS
High-level output voltage (IOH = –4 mA)
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = –4 mA)
Low-level output voltage (IOL = +4 mA)
Commercial
Industrial
3.86
V
0.32
V
3.76
V
0.37
10.0
50.0
V
Supply current, active mode (at maximum frequency)
mA
µA
Supply current, standby mode
XC17S05, XC17S10,
XC17S20, XC17S30
XC17S40
100.0
10.0
10.0
10.0
µA
µA
pF
pF
IL
Input or output leakage current
–10.0
CIN
COUT
Input Capacitance (VIN = GND, f = 1.0 MHz)
Output Capacitance (VIN = GND, f = 1.0 MHz)
6
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Spartan Family of PROMs
XC17S05XL, XC17S10XL, XC17S15XL, XC17S20XL, XC17S30XL,
XC17S40XL, XC17S50XL, XC17S100XL, XC17S150XL, XC17S200XL
Absolute Maximum Ratings
Symbol
Description
Supply voltage relative to GND
Value
Units
VCC
–0.5 to +4.0
V
VIN
Input voltage with respect to GND
Voltage applied to 3-state output
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
+260
V
V
VTS
TSTG
TSOL
Storage temperature (ambient)
°C
°C
Maximum soldering temperature (10 s @ 1/16 in.)
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.
Operating Conditions
Symbol
Description
Commercial
Industrial
Min
3.0
3.0
Max
3.6
Units
VCC
Supply voltage relative to GND (TA = 0°C to +70°C)
Supply voltage relative to GND (TA = –40°C to +85°C)
V
V
3.6
Note: During normal read operation both VCC pins must be connected together.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
Max
Units
V
High-level input voltage
Low-level input voltage
2.0
0
VCC
0.8
VIL
V
VOH
VOL
ICCA
ICCS
IL
High-level output voltage (IOH = –3 mA)
Low-level output voltage (IOL = +3 mA)
Supply current, active mode (at maximum frequency)
Supply current, standby mode
2.4
V
0.4
5.0
V
mA
µA
µA
pF
pF
50.0
10.0
10.0
10.0
Input or output leakage current
–10.0
CIN
Input Capacitance (VIN = GND, f = 1.0 MHz)
Output Capacitance (VIN = GND, f = 1.0 MHz)
COUT
DS030 (v1.5) April 4, 2000
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Spartan Family of PROMs
AC Characteristics Over Operating Condition
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS0306_03_011300
Symbol
TOE
Description
Min
Max
45
Units
ns
RESET/OE to Data Delay
CE to Data Delay
TCE
60
ns
TCAC
TOH
CLK to Data Delay
80
ns
Data Hold From CE, RESET/OE, or CLK(2)
CE or RESET/OE to Data Float Delay(2,3)
Clock Periods
0
ns
TDF
50
ns
TCYC
TLC
100
50
50
25
0
ns
CLK Low Time(2)
ns
THC
CLK High Time(2)
ns
TSCE
THCE
THOE
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLK (to guarantee proper counting)
RESET/OE Hold Time (guarantees counters are reset)
ns
ns
25
ns
Notes: 1. AC test load = 50 pF
2. Guaranteed by design, not tested.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
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Spartan Family of PROMs
Ordering Information
XC17S20XL VO8 C
Device Number
Operating Range/Processing
XC17S05
XC17S05XL
XC17S10
XC17S10XL
XC17S15XL
XC17S20
C
I
= Commercial (TA = 0°C to +70°C)
= Industrial (TA = –40°C to +85°C)
Package Type
PD8 = 8-pin Plastic DIP
VO8 = 8-pin Plastic Small-Outline Thin Package
SO20 = 20-pin Plastic Small-Outline Package
XC17S20XL
XC17S30
XC17S30XL
XC17S40
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
XC17S200XL
Valid Ordering Combinations
Spartan 5V
Spartan 5V
Spartan 3.3V
Spartan 3.3V
Spartan3.3V
XC17S05PD8C
XC17S05VO8C
XC17S05PD8I
XC17S05VO8I
XC17S10PD8C
XC17S10VO8C
XC17S10PD8I
XC17S10VO8I
XC17S20PD8C
XC17S20VO8C
XC17S20PD8I
XC17S20VO8I
XC17S30PD8C
XC17S30VO8C
XC17S30PD8I
XC17S30VO8I
XC17S40PD8C
XC17S05XLPD8C
XC17S05XLVO8C
XC17S05XLPD8I
XC17S05XLVO8I
XC17S10XLPD8C
XC17S10XLVO8C
XC17S10XLPD8I
XC17S10XLVO8I
XC17S15XLPD8C
XC17S20XLPD8C
XC17S20XLVO8C
XC17S20XLPD8I
XC17S20XLVO8I
XC17S30XLPD8C
XC17S30XLVO8C
XC17S30XLPD8I
XC17S30XLVO8I
XC17S40XLPD8C
XC17S40XLSO20C
XC17S40XLVO8C*
XC17S40XLPD8I
XC17S40XLSO20I
XC17S40XLVO8I*
XC17S50XLPD8C
XC17S50XLSO20C
XC17S50XLPD8I
XC17S50XLSO20I
XC17S100XLPD8C
XC17S100XLSO20C
XC17S100XLPD8I
XC17S100XLSO20I
XC17S150XLPD8C
XC17S150XLSO20C
XC17S150XLPD8I
XC17S150XLSO20I
XC17S40SO20C XC17S15XLVO8C
XC17S40PD8I
XC17S40SO20I
XC17S15XLPD8I
XC17S15XLVO8I
XC17S200XLPD8C
XC17S200XLSO20C
XC17S200XLPD8I
XC17S200XLSO20I
* In development
DS030 (v1.5) April 4, 2000
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Spartan Family of PROMs
Marking Information
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC
prefix is deleted and the package code is simplified. Device marking is as follows.
17S20L V C
Device Number
Operating Range/Processing
XC17S05
XC17S05L
XC17S10
XC17S10L
XC17S15L
XC17S20
C = Commercial (TA = 0°C to +70°C)
Package Type
I
= Industrial (TA = –40°C to +85°C)
P
V
S
= 8-pin Plastic DIP
= 8-pin Plastic Small-Outline Thin Package
= 20-pin Plastic Small-Outline Package
XC17S20L
XC17S30
XC17S30L
XC17S40
XC17S40L
XC17S50L
XC17S100L
XC17S150L
XC17S200L
Note: When marking the device number on the XL parts, an L is used in place of an XL.
Revision Control
Date
7/14/98
9/8/98
Revision
1.1
Revision
Cosmetic edits for pages 1, 2, 3 & 4.
1.2
Clarified the SPARTAN FPGA and PROM interface by removing references to CEO pin. Re-
moved the ESD notation in Absolute Maximum table since it is now included in Xilinx’s Reliability
Monitor Report.
01/20/00
02/18/00
04/04/00
1.3
1.4
1.5
Added additional Spartan-XL parts, changed SPROM to PROM.
Changed device ordering numbers, added 4.7K resistor to OE/RESET in Figure 1.
Added XC17S200XL PROM for Spartan XC2S200.
10
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