X5325S8T1_技术文档

Replaces X25323/X25325

X5323/X5325

CPU Supervisor with 32Kb SPI EEPROM

FEATURES

• Selectable watchdog timer

• Low V detection and reset assertion

DESCRIPTION

These devices combine four popular functions, Power-on

Reset Control, Watchdog Timer, Supply Voltage

Supervision, and Block Lock Protect Serial EEPROM

Memory in one package. This combination lowers

system cost, reduces board space requirements, and

increases reliability.

CC

—Five standard reset threshold voltages

—Re-program low V reset threshold voltage

CC

using special programming sequence

—Reset signal valid to V = 1V

CC

• Determine watchdog or low voltage reset with a

volatile ﬂag bit

Applying power to the device activates the power on

reset circuit which holds RESET/RESET active for a

period of time. This allows the power supply and oscilla-

tor to stabilize before the processor can execute code.

• Long battery life with low power consumption

—<50µA max standby current, watchdog on

—<1µA max standby current, watchdog off

—<400µA max active current during read

• 32Kbits of EEPROM

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—Protect 0, 1/4, 1/2 or all of EEPROM array with

Block Lock^™protection

—In circuit programmable ROM mode

• 2MHz SPI interface modes (0,0 & 1,1)

• Minimize EEPROM programming time

—32-byte page write mode

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a selectable

time out interval, the device activates the RESET/

RESET signal. The user selects the interval from three

preset values. Once selected, the interval does not

change, even after cycling the power.

The device’s low V

detection circuitry protects the

CC

user’s system from low voltage conditions, resetting the

system when V falls below the minimum V trip

CC

—Self-timed write cycle

point. RESET/RESET is asserted until V

returns to

CC

—5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V power supply

operation

• Available packages

—14-lead TSSOP, 8-lead SOIC

proper operating level and stabilizes. Five industry stan-

dard V thresholds are available, however, Xicor’s

TRIP

unique circuits allow the threshold to be reprogrammed

to meet custom requirements or to ﬁne-tune the thresh-

old for applications requiring higher precision.

BLOCK DIAGRAM

Watchdog Transition

Detector

Watchdog

Timer Reset

WP

Protect Logic

RESET/RESET

SI

Data

Register

Status

Register

SO

X5323 = RESET

X5325 = RESET

Command

Decode &

Control

Reset &

Watchdog

Timebase

SCK

8Kbits

CS/WDI

Logic

V

Threshold

Reset Logic

CC

16Kbits

Power On and

Low Voltage

Reset

V

+

-

CC

Generation

V

TRIP

Characteristics subject to change without notice. 1 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

PIN CONFIGURATION

14-Lead TSSOP

8-Lead SOIC/PDIP

1

V

CS/WDT

SO

14

CC

2

RESET/RESET

13

V

1

8

CS/WDT

SO

CC

NC

X5323/25

3

4

5

12

NC

2

3

7

6

RESET/RESET

X5323/25

NC

WP

11

10

9

WP

SCK

SI

NC

V

SS

4

5

SCK

6

7

V

SS

SI

8

PIN DESCRIPTION

(SOIC/PDIP) TSSOP

Name

Function

1

CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at

a high impedance state. Unless a nonvolatile write cycle is underway, the

device will be in the standby power mode. CS LOW enables the device, placing

it in the active power mode. Prior to the start of any operation after power up, a

HIGH to LOW transition on CS is required.

Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-

dog timer. The absence of a HIGH to LOW transition within the watchdog time

out period results in RESET/RESET going active.

2

5

2

8

SO

SI

Serial Output. SO is a push/pull serial data output pin.A read cycle shifts data out

on this pin.The falling edge of the serial clock (SCK) clocks the data out.

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and

memory data on this pin.The rising edge of the serial clock (SCK) latches the input

data. Send all opcodes (Table 1), addresses and data MSB ﬁrst.

6

3

9

6

SCK

WP

Serial Clock. The serial clock controls the serial bus timing for data input and

output.The rising edge of SCK latches in the opcode, address, or data bits present

on the SI pin.The falling edge of SCK changes the data output on the SO pin.

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to

“lock” the setting of the watchdog timer control and the memory write protect bits.

4

8

7

V

Ground

SS

14

13

V

Supply Voltage

CC

RESET/ Reset Output. RESET/RESET is an active LOW/HIGH, open drain output

which goes active whenever V falls below the minimum V sense level. It

RESET

CC

will remain active until V rises above the minimum V sense level for

CC

200ms. RESET/RESET goes active if the watchdog timer is enabled and CS

remains either HIGH or LOW longer than the selectable watchdog time out

period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes

active on power up at about 1V and remains active for 200ms after the power

supply stabilizes.

3-5,10-12

NC

No internal connections

Characteristics subject to change without notice. 2 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

PRINCIPLES OF OPERATION

Power On Reset

change. If the new setting is lower than the current set-

ting, then it is necessary to reset the trip point before

setting the new value.

Application of power to the X5323/X5325 activates a

power on reset circuit. This circuit goes active at about

1V and pulls the RESET/RESET pin active. This signal

prevents the system microprocessor from starting to

operate with insufﬁcient voltage or prior to stabilization

of the oscillator. As long as RESET/RESET pin is active,

the device will not respond to any Read/Write instruc-

To set the new V

threshold to the Vcc pin and tie the CS/WDI pin and the

WP pin HIGH. RESET/RESET and SO pins are left

unconnected. Then apply the programming voltage V

to both SCK and SI and pulse CS/WDI LOW then

HIGH. Remove V and the sequence is complete.

voltage, apply the desired V

TRIP

P

tion. When V

exceeds the device V

value for

CC

TRIP

Figure 1. Set V

Voltage

TRIP

200ms (nominal) the circuit releases RESET/RESET,

allowing the processor to begin executing code.

CS

Low Voltage Monitoring

V

P

During operation, the X5323/X5325 monitors the V

CC

SCK

SI

level and asserts RESET/RESET if supply voltage falls

below a preset minimum V . The RESET/RESET

TRIP

V

P

signal prevents the microprocessor from operating in a

power fail or brownout condition. The RESET/RESET

signal remains active until the voltage drops below 1V.

It also remains active until V

returns and exceeds

CC

Resetting the V

Voltage

V

for 200ms.

TRIP

This procedure sets the V

level. For example, if the current V

to a “native” voltage

TRIP

Watchdog Timer

is 4.4V and the

TRIP

V

is reset, the new V

is something less than

The watchdog timer circuit monitors the microprocessor

activity by monitoring the WDI input. The microprocessor

must toggle the CS/WDI pin periodically to prevent a

RESET/RESET signal. The CS/WDI pin must be tog-

gled from HIGH to LOW prior to the expiration of the

watchdog time out period. The state of two nonvolatile

control bits in the status register determine the watch-

dog timer period. The microprocessor can change these

watchdog bits, or they may be “locked” by tying the WP

pin LOW and setting the WPEN bit HIGH.

TRIP

1.7V. This procedure must be used to set the voltage to

a lower value.

To reset the V

2.7 and 5.5V to the V

WP pin, and the SCK pin HIGH. RESET/RESET and

SO pins are left unconnected. Then apply the program-

ming voltage V to the SI pin ONLY and pulse CS/WDI

voltage, apply a voltage between

TRIP

pin. Tie the CS/WDI pin, the

CC

P

LOW then HIGH. Remove V and the sequence is

complete.

P

V

Threshold Reset Procedure

CC

Figure 2. Reset V

Voltage

TRIP

The X5323/X5325 has a standard V

threshold

CC

(V

) voltage. This value will not change over normal

TRIP

operating and storage conditions. However, in applica-

CS

tions where the standard V

for higher precision in the V

is not exactly right, or

value, the X5323/

TRIP

V

TRIP

CC

SCK

X5325 threshold may be adjusted.

V

P

Setting the V Voltage

TRIP

SI

This procedure sets the V

to a higher voltage

TRIP

value. For example, if the current V

is 4.4V and the

TRIP

new V

is 4.6V, this procedure directly makes the

TRIP

Characteristics subject to change without notice. 3 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Figure 3. V

Programming Sequence Flow Chart

TRIP

V

Programming

TRIP

Execute

Reset V

TRIP

Sequence

Set V

= V

Applied =

TRIP

CC

Desired V

Execute

Set V

Sequence

New V

Applied =

New V

Applied =

Applied - Error

CC

TRIP

Old V

Applied + Error

CC

Execute

Apply 5V to V

CC

Reset V

TRIP

Sequence

Decrement V

(V

= V

- 10mV)

CC

NO

RESET pin

goes active?

YES

Error ≤ Emax

Error ≥ Emax

Measured V

Desired V

-

TRIP

Error < Emax

DONE

Emax = Maximum Desired Error

Characteristics subject to change without notice. 4 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Figure 4. Sample V

Reset Circuit

TRIP

V

P

4.7K

NC

4.7K

RESET

1

2

3

4

8

7

6

5

NC

X5323/25

V

TRIP

+

Adj.

Program

Reset V

TRIP

10K

Test V

TRIP

Set V

TRIP

SPI SERIAL MEMORY

Write Enable Latch

The device contains a write enable latch. This latch

must be SET before a write operation is initiated. The

WREN instruction will set the latch and the WRDI

instruction will reset the latch (Figure 3). This latch is

automatically reset upon a power-up condition and

after the completion of a valid write cycle.

The memory portion of the device is a CMOS serial

EEPROM array with Xicor’s block lock protection. The

array is internally organized as x 8.The device features

a Serial Peripheral Interface (SPI) and software proto-

col allowing operation on a simple four-wire bus.

The device utilizes Xicor’s proprietary Direct Write^™

cell, providing a minimum endurance of 100,000 cycles

and a minimum data retention of 100 years.

Status Register

The RDSR instruction provides access to the status reg-

ister. The status register may be read at any time, even

during a write cycle. The status register is formatted as

follows:

The device is designed to interface directly with the

synchronous Serial Peripheral Interface (SPI) of many

popular microcontroller families. It contains an 8-bit

instruction register that is accessed via the SI input,

with data being clocked in on the rising edge of SCK.

CS must be LOW during the entire operation.

7

6

5

4

3

2

1

0

WPEN FLB WD1 WD0 BL1 BL0 WEL WIP

All instructions (Table 1), addresses and data are trans-

ferred MSB ﬁrst. Data input on the SI line is latched on

the ﬁrst rising edge of SCK after CS goes LOW. Data is

output on the SO line by the falling edge of SCK. SCK is

static, allowing the user to stop the clock and then start it

again to resume operations where left off.

The Write-In-Progress (WIP) bit is a volatile, read only

bit and indicates whether the device is busy with an

internal nonvolatile write operation. The WIP bit is read

using the RDSR instruction. When set to a “1”, a non-

volatile write operation is in progress. When set to a

“0”, no write is in progress.

Table 1. Instruction Set

Instruction Name Instruction Format*

Operation

WREN

SFLB

0000 0110

0000 0000

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

Set the write enable latch (enable write operations)

Set flag bit

WRDI/RFLB

RSDR

Reset the write enable latch/reset flag bit

Read status register

WRSR

Write status register (watchdog, block lock, WPEN & flag bits)

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

READ

WRITE

Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB ﬁrst.

Characteristics subject to change without notice. 5 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Table 2. Block Protect Matrix

WREN CMD Status Register Device Pin

Block

Status Register

WPEN, BL0, BL1

WD0, WD1

WEL

WPEN

WP#

Protected Block Unprotected Block

0

1

X

1

0

X

0

Protected

Writable

Protected

Writable

X

1

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch. When WEL = 1, the latch is

set HIGH and when WEL = 0 the latch is reset LOW.

The WEL bit is a volatile, read only bit. It can be set by

the WREN instruction and can be reset by the WRDS

instruction.

The FLAG bit shows the status of a volatile latch that

can be set and reset by the system using the SFLB

and RFLB instructions. The ﬂag bit is automatically

reset upon power up. This ﬂag can be used by the sys-

tem to determine whether a reset occurs as a result of

a watchdog time out or power failure.

Notes: 1. The Watch Dog Timer is shipped disabled. (WD1 = 1,

WD0 = 1)

The block lock bits, BL0 and BL1, set the level of block

lock protection. These nonvolatile bits are programmed

using the WRSR instruction and allow the user to protect

one quarter, one half, all or none of the EEPROM array.

Any portion of the array that is block lock protected can be

read but not written. It will remain protected until the BL

bits are altered to disable block lock protection of that

portion of memory.

2. The factory default for Memory Block Protection is

‘None’. (BL1 = 0), BL0 = 0)

The nonvolatile WPEN bit is programmed using the

WRSR instruction. This bit works in conjunction with the

WP pin to provide an in-circuit programmable ROM func-

tion (Table 2). WP is LOW and WPEN bit programmed

HIGH disables all status register write operations.

Status

Register Bits

Array Addresses Protected

X5323/X5325

In Circuit Programmable ROM Mode

BL1

BL0

This mechanism protects the block lock and watchdog

bits from inadvertent corruption.

0

1

0

1

0

1

None (factory default)

$0C00–$0FFF

In the locked state (programmable ROM mode) the WP

pin is LOW and the nonvolatile bit WPEN is “1”. This

mode disables nonvolatile writes to the device’s status

register.

$0800–$0FFF

$0000–$0FFF

The watchdog timer bits, WD0 and WD1, select the

watchdog time out period. These nonvolatile bits are

programmed with the WRSR instruction.

Status Register Bits

Watchdog Time Out

WD1

WD0

(Typical)

0

1

0

1

0

1

1.4 seconds

600 milliseconds

200 milliseconds

disabled (factory default)

Characteristics subject to change without notice. 6 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Figure 5. Read EEPROM Array Sequence

CS

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30

SCK

SI

Instruction

16 Bit Address

15 14 13

3

2

1

0

Data Out

High Impedance

7

6

5

4

3

2

1

0

SO

MSB

Setting the WP pin LOW while WPEN is a “1” while an

internal write cycle to the status register is in progress

will not stop this write operation, but the operation dis-

ables subsequent write attempts to the status register.

higher address after each byte of data is shifted out.

When the highest address is reached, the address

counter rolls over to address $0000 allowing the read

cycle to be continued indeﬁnitely. The read operation is

terminated by taking CS high. Refer to the read

EEPROM Array Sequence (Figure 1).

When WP is HIGH, all functions, including nonvolatile

writes to the status register operate normally. Setting

the WPEN bit in the status register to “0” blocks the WP

pin function, allowing writes to the status register when

WP is HIGH or LOW. Setting the WPEN bit to “1” while

the WP pin is LOW activates the programmable ROM

mode, thus requiring a change in the WP pin prior to

subsequent status register changes. This allows manu-

facturing to install the device in a system with WP pin

grounded and still be able to program the status regis-

ter. Manufacturing can then load conﬁguration data,

manufacturing time and other parameters into the

EEPROM, then set the portion of memory to be pro-

tected by setting the block lock bits, and ﬁnally set the

“OTP mode” by setting the WPEN bit. Data changes

now require a hardware change.

To read the status register, the CS line is ﬁrst pulled low

to select the device followed by the 8-bit RDSR instruc-

tion. After the RDSR opcode is sent, the contents of the

status register are shifted out on the SO line. Refer to

the read status register sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the

“Write Enable” Latch (WEL) must ﬁrst be set by issuing

the WREN instruction (Figure 3). CS is ﬁrst taken LOW,

then the WREN instruction is clocked into the device.

After all eight bits of the instruction are transmitted, CS

must then be taken HIGH. If the user continues the write

operation without taking CS HIGH after issuing the

WREN instruction, the write operation will be ignored.

Read Sequence

To write data to the EEPROM memory array, the user

then issues the WRITE instruction followed by the 16

bit address and then the data to be written. Any

unused address bits are speciﬁed to be “0’s”. The

WRITE operation minimally takes 32 clocks. CS must

go low and remain low for the duration of the operation.

If the address counter reaches the end of a page and

the clock continues, the counter will roll back to the ﬁrst

address of the page and overwrite any data that may

have been previously written.

When reading from the EEPROM memory array, CS is

ﬁrst pulled low to select the device. The 8-bit READ

instruction is transmitted to the device, followed by the

16-bit address. After the READ opcode and address

are sent, the data stored in the memory at the selected

address is shifted out on the SO line. The data stored

in memory at the next address can be read sequen-

tially by continuing to provide clock pulses. The

address is automatically incremented to the next

Characteristics subject to change without notice. 7 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

For the page write operation (byte or page write) to be

completed, CS can only be brought HIGH after bit 0 of

the last data byte to be written is clocked in. If it is

brought HIGH at any other time, the write operation will

not be completed (Figure 4).

– SO pin is high impedance.

– The write enable latch is reset.

– The ﬂag bit is reset.

– Reset signal is active for t

.

PURST

To write to the status register, the WRSR instruction is

followed by the data to be written (Figure 5). Data bits

0 and 1 must be “0”.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

While the write is in progress following a status register

or EEPROM Sequence, the status register may be

read to check the WIP bit. During this time the WIP bit

will be high.

– A WREN instruction must be issued to set the write

enable latch.

– CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

OPERATIONAL NOTES

The device powers-up in the following state:

– The device is in the low power standby state.

– A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

Figure 6. Read Status Register Sequence

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

SCK

Instruction

SI

Data Out

High Impedance

SO

7

6

5

4

3

2

1

0

MSB

Figure 7. Write Enable Latch Sequence

CS

0

1

2

3

4

5

6

7

SCK

SI

High Impedance

SO

Characteristics subject to change without notice. 8 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Figure 8. Write Sequence

CS

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

SCK

Instruction

16 Bit Address

15 14 13

Data Byte 1

3

2

1

0

7

6

5

4

3

2

1

0

SI

CS

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCK

SI

Data Byte 2

Data Byte 3

Data Byte N

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

Figure 9. Status Register Write Sequence

CS

0

1

2

3

4

5

6

7

8

7

9

10 11 12 13 14 15

SCK

Instruction

Data Byte

6

5

4

3

2

1

0

SI

High Impedance

SO

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

Characteristics subject to change without notice. 9 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias ...................–65°C to +135°C

Storage temperature ........................–65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; the functional operation of

the device (at these or any other conditions above those

listed in the operational sections of this speciﬁcation) is

not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect device reliability.

Voltage on any pin with respect to V ....–1.0V to +7V

SS

D.C. output current ............................................... 5mA

Lead temperature (soldering, 10 seconds).........300°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Commercial

Industrial

Min.

0°C

Max.

70°C

Device Option

–2.7 or -2.7A

Supply Voltage

2.7V to 5.5V

4.5V–5.5V

–40°C

+85°C

Blank or -4.5A

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise speciﬁed.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

I

V

write current (active)

5

mA

SCK = V x 0.1/V x 0.9 @ 2MHz,

CC CC

CC1

CC

SO = Open

I

read current (active)

0.4

1

mA

µA

SCK = V x 0.1/V x 0.9 @ 2MHz,

CC CC

SO = Open

CC2

I

standby current

CS = V , V = V or V

,

SB1

SB2

SB3

CC IN

SS

CC

WDT = OFF

V

= 5.5V

CC

V

standby current

50

20

CS = V , V = V or V

CC IN SS

CC

WDT = ON

V

= 5.5V

CC

V

standby current

CS = V , V = V or V

CC IN SS

CC

WDT = ON

V

=3.6V

CC

I

Input leakage current

Output leakage current

Input LOW voltage

Input HIGH voltage

Output LOW voltage

Output HIGH voltage

Reset output LOW voltage

0.1

10

µA

V

= V to V

SS CC

LI

IN

I

= V to V

SS CC

LO

OUT

(1)

IL

V

–0.5

V

x 0.3

CC

(1)

IH

V

x 0.7

V

+ 0.5

V

CC

V

0.4

V

> 3.3V, I = 2.1mA

OL1

OL2

OL3

OH1

OH2

OH3

OLS

CC OL

0.4

V

2V < V_CC≤ 3.3V, I = 1mA

OL

V

V_CC≤ 2V, I = 0.5mA

OL

V

– 0.8

– 0.4

– 0.2

V

> 3.3V, I

= –1.0mA

CC

OH

V

2V < V_CC≤ 3.3V, I

= –0.4mA

OH

V

V_CC≤ 2V, I

= –0.25mA

OH

0.4

V

I

= 1mA

OL

Characteristics subject to change without notice. 10 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

CAPACITANCE T = +25°C, f = 1MHz, V

= 5V

A

CC

Symbol

Test

Max.

Unit

pF

Conditions

= 0V

(2)

OUT

C

Output capacitance (SO, RESET/RESET)

Input capacitance (SCK, SI, CS, WP)

8

6

V

OUT

(2)

IN

C

pF

V

= 0V

IN

Notes: (1) V min. and V max. are for reference only and are not tested.

IL

IH

(2) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. TEST CONDITIONS

CC

Input pulse levels

V

x 0.1 to V x 0.9

CC

5V

Input rise and fall times

10ns

Input and output timing level

V

x0.5

4.6KΩ

CC

2.06KΩ

Output

3.03KΩ

RESET/RESET

30pF

100pF

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise speciﬁed)

Serial Input Timing

2.7–5.5V

Symbol

Parameter

Min.

0

Max.

Unit

MHz

ns

f

Clock frequency

Cycle time

2

SCK

CYC

t

500

250

200

250

50

t

CS lead time

ns

LEAD

t

CS lag time

ns

LAG

t

Clock HIGH time

Clock LOW time

Data setup time

Data hold time

Input rise time

Input fall time

CS deselect time

Write cycle time

ns

WH

t

ns

WL

t

ns

SU

t

50

ns

H

(3)

t

100

ns

RI

(3)

ns

FI

t

500

ns

CS

(4)

WC

t

10

ms

Characteristics subject to change without notice. 11 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Serial Input Timing

t

CS

t

LAG

LEAD

SCK

t

FI

SU

H

RI

SI

MSB IN

LSB IN

High Impedance

SO

Serial Output Timing

Symbol

2.7–5.5V

Parameter

Min.

Max.

2

Unit

MHz

ns

f

Clock frequency

0

SCK

t

Output disable time

250

DIS

t

Output valid from clock low

Output hold time

ns

V

t

0

ns

HO

(3)

t

Output rise time

100

ns

RO

(3)

Output fall time

ns

FO

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

WC

write cycle.

Serial Output Timing

CS

SCK

SO

t

LAG

CYC

WH

t

DIS

V

HO

WL

MSB Out

MSB–1 Out

LSB Out

ADDR

LSB IN

SI

Characteristics subject to change without notice. 12 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Power-Up and Power-Down Timing

V

TRIP

V

CC

t

PURST

0 Volts

t

F

PURST

t

RPD

t

R

RESET (X5323)

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

Reset trip point voltage, X5323-4.5A, X5323-4.5A

Reset trip point voltage, X5323, X5325

Reset trip point voltage, X5323-2.7A, X5325-2.7A

Reset trip point voltage, X5323-2.7, X5325-2.7

4.5

4.63

4.38

2.92

2.63

4.75

4.5

3.0

2.7

TRIP

4.25

2.85

2.55

V

hysteresis (HIGH to LOW vs. LOW to HIGH V voltage)

TRIP

20

mV

ms

ns

µs

V

TH

TRIP

t

Power-up reset time out

100

200

280

500

PURST

(5)

RPD

t

V

detect to reset/output

fall time

CC

(5)

t

100

1

F

(5)

t

rise time

R

V

Reset valid V

CC

RVALID

Note: (5) This parameter is periodically sampled and not 100% tested.

CS/WDI vs. RESET/RESET Timing

CS/WDI

t

CST

RESET

t

RST

t

RST

WDO

Characteristics subject to change without notice. 13 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

RESET/RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

t

Watchdog time out period,

WD1 = 1, WD0 = 0

WD1 = 0, WD0 = 1

WD1 = 0, WD0 = 0

WDO

100

450

1

200

600

1.4

300

800

2

ms

sec

t

CS pulse width to reset the watchdog

Reset time out

400

100

ns

CST

t

200

300

ms

RST

V

Set Conditions

TRIP

t

THD

V

CC

TRIP

t

TSU

t

RP

t

VPH

t

P

VPS

CS

t

VPO

VPH

VPS

V

P

SCK

V

t

P

VPO

SI

V

Reset Conditions

TRIP

V

*

CC

t

RP

t

VP1

t

P

VPS

t

CS

t

VPS

VPO

VPH

V

CC

V

SCK

SI

t

P

VPO

*V

> Programmed V

TRIP

CC

Characteristics subject to change without notice. 14 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

V

Programming Specifications V = 1.7–5.5V; Temperature = 0°C to 70°C

CC

TRIP

Parameter

Description

program voltage setup time

Min. Max. Unit

t

SCK V

1

µs

ms

V

VPS

VPH

TRIP

t

program voltage hold time

TRIP

t

V

program pulse width

1

P

TRIP

t

level setup time

10

TSU

THD

t

level hold (stable) time

t

write cycle time

10

WC

t

program cycle recovery period (between successive programming cycles)

10

0

RP

t

SCK V

program voltage off time before next cycle

VPO

TRIP

V

Programming voltage

programed voltage range

15

18

5.0

P

V

1.7

-0.1

-25

V

TRAN

TRIP

V

Initial V

program voltage accuracy (V applied—V ) (programmed at 25°C)

TRIP

+0.4

+25

V

ta1

TRIP

CC

Subsequent V

(programmed at 25°C)

program voltage accuracy [(V applied—V )–V )

TRIP

mV

ta2

TRIP

CC

ta1

V

program voltage repeatability (successive program operations) (programmed

-25

+25

mV

tr

TRIP

at 25°C)

V

TRIP

program variation after programming (0–75°C). (programmed at 25°C)

tv

V

programming parameters are periodically sampled and are not 100% tested.

TRIP

Characteristics subject to change without notice. 15 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

TYPICAL PERFORMANCE

V

Supply Current vs. Temperature (I

)

t

vs. Voltage/Temperature (WD1,0 = 1, 1)

CC

SB

WDO

1.9

18

Watchdog Timer On (V

= 5V)

1.8

1.7

1.6

1.5

1.4

CC

16

14

12

10

8

–40°C

25°C

Watchdog Timer On (V

= 5V)

CC

90°C

1.3

1.2

1.1

1

6

4

Watchdog Timer Off (V = 3V, 5V)

CC

2

0

1.7

2.4

3.1

3.8

4.5

5.2

–40

25

90

Voltage

Temp (°C)

t

vs. Voltage/Temperature (WD1, 0 = 1, 0)

V

vs. Temperature (programmed at 25°C)

WDO

TRIP

0.8

5.025

V

= 5V

TRIP

0.75

5.000

–40°C

0.7

0.65

4.975

3.525

3.500

25°C

V

= 3.5V

= 2.5V

TRIP

90°C

0.6

3.475

0.55

0.5

2.525

2.500

2.475

0.45

1.7

2.4

3.1

Voltage

3.8

4.5

5.2

0

25

85

Temperature

t

vs. Temperature

t

vs. Voltage/Temperature (WD1, 0 0 = 0, 1)

PURST

WDO

205

200

205

200

195

190

185

180

175

170

165

–40°C

25°C

195

190

185

180

175

90°C

170

165

160

1.7

2.4

3.1

3.8

4.5

5.2

–40

25

Degrees °C

90

Voltage

Characteristics subject to change without notice. 16 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

PACKAGING INFORMATION

8-Lead Plastic Small Outline Gull Wing Package Type S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

Pin 1 Index

Pin 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.19)

0.010 (0.25)

0.050 (1.27)

0.010 (0.25)

0.050"Typical

X 45°

0.020 (0.50)

0.050"

Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.250"

0.016 (0.410)

0.037 (0.937)

0.030"

Typical

8 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 17 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

PACKAGING INFORMATION

8-Lead Plastic Dual In-Line Package Type P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

Pin 1 Index

Pin 1

0.060 (1.52)

0.020 (0.51)

0.300

(7.62) Ref.

Half Shoulder Width On

All End Pins Optional

0.145 (3.68)

0.128 (3.25)

Seating

Plane

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.150 (3.81)

0.125 (3.18)

0.045 (1.14)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

0.325 (8.25)

0.300 (7.62)

.073 (1.84)

Max.

0°

Typ. 0.010 (0.25)

15°

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

Characteristics subject to change without notice. 18 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

PACKAGING INFORMATION

14-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.193 (4.9)

.200 (5.1)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.05)

.006 (.15)

.010 (.25)

Gage Plane

0° - 8°

Seating Plane

.019 (.50)

.029 (.75)

Detail A (20X)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 19 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

Ordering Information

V

Operating

Temperature Range

Part Number RESET Part Number RESET

CC

TRIP

Range

Package

8-Pin PDIP

8L SOIC

(Active LOW)

X5323P-4.5A

X5323S8-4.5A

X5323S8I-4.5A

X5323P

(Active HIGH)

X5325P-4.5A

X5325S8-4.5A

X5325S8I-4.5A

X5325P

4.5-5.5V

4.5-4.75

0–70°C

-40–85°C

0–70°C

-40–85°C

0–70°C

-40–85°C

0–70°C

-40–85°C

4.5-5.5V

4.25-4.5

8-Pin PDIP

8L SOIC

X5323S8

X5325S8

X5323S8I

X5325S8I

14L TSSOP

8L SOIC

X5323V14

X5325V14

2.7-5.5V

2.85-3.0

2.55-2.7

X5323S8-2.7A

X5323S8I-2.7A

X5323V14-2.7A

X5323S8-2.7

X5323V14-2.7

X5323V14I-2.7

X5325S8-2.7A

X5325S8I-2.7A

X5325V14-2.7A

X5325S8-2.7

X5325V14-2.7

X5325V14I-2.7

14L TSSOP

8L SOIC

14L TSSOP

Part Mark Information

X5323/25 W

P = 8-Pin DIP

Blank = 8-Lead SOIC

V = 14 Lead TSSOP

X

Blank = 5V ±10%, 0°C to +70°C, V

= 4.25-4.5

TRIP

AL= 5V±10%, 0°C to +70°C, V

= 4.5-4.75

TRIP

I = 5V ±10%, –40°C to +85°C, V

= 4.25-4.5

TRIP

AM = 5V ±10%, –40°C to +85°C, V

= 4.5-4.75

TRIP

F = 2.7V to 5.5V, 0°C to +70°C, V

= 2.55-2.7

TRIP

AN = 2.7V to 5.5V, 0°C to +70°C, V

= 2.85-3.0

TRIP

G = 2.7V to 5.5V, –40°C to +85°C, V

= 2.55-2.7

TRIP

AP = 2.7V to 5.5V, –40°C to +85°C, V

= 2.85-3.0

TRIP

Characteristics subject to change without notice. 20 of 21

REV 1.1.2 11/13/01

www.xicor.com

X5323/X5325

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices

at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

COPYRIGHTS ANDTRADEMARKS

Xicor, Inc., the Xicor logo, E²POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,

E²KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are

used for identification purposes only, and are trademarks or registered trademarks of their respective holders.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;

5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Characteristics subject to change without notice. 21 of 21

REV 1.1.2 11/13/01

www.xicor.com


型号：	X5325S8T1
厂家：	XICOR INC.
描述：	Power Supply Management Circuit, Adjustable, 1 Channel, PDSO8, PLASTIC, SOIC-8 光电二极管
文件：	总21页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X5325S8T1 [XICOR]

相关型号：

X5325S8Z

X5325S8Z-2.7

X5325S8Z-2.7-T

X5325S8Z-2.7-T1

X5325S8Z-2.7A

X5325S8Z-2.7A-T1

X5325S8Z-4.5A

X5325S8Z-4.5A-T1

X5325S8Z-T

X5325V14

X5325V14-1.8

X5325V14-2.7