X5325S8Z-2.7A-T1 [RENESAS]
IC,SERIAL EEPROM,4KX8,CMOS,SOP,8PIN,PLASTIC;
| 型号： | X5325S8Z-2.7A-T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SERIAL EEPROM,4KX8,CMOS,SOP,8PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总21页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X5323, X5325
®
(Replaces X25323, X25325)
Data Sheet
October 27, 2005
FN8131.1
DESCRIPTION
CPU Supervisor with 32Kb SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
FEATURES
• Selectable watchdog timer
• Low V detection and reset assertion
CC
—Five standard reset threshold voltages
—Re-program low V reset threshold voltage
CC
using special programming sequence
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
—Reset signal valid to V = 1V
CC
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 32Kbits of EEPROM
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
™
Block Lock protection
The device’s low V
detection circuitry protects the
CC
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
user’s system from low voltage conditions, resetting the
system when V falls below the minimum V trip
CC
CC
point. RESET/RESET is asserted until V
returns to
CC
proper operating level and stabilizes. Five industry stan-
dard V thresholds are available, however, Intersil’s
—Self-timed write cycle
TRIP
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET/RESET
X5323 = RESET
SI
Data
Register
Status
Register
SO
Command
Decode &
Control
Reset &
Watchdog
Timebase
X5325 = RESET
SCK
8Kbits
8Kbits
CS/WDI
Logic
VCC Threshold
Reset Logic
16Kbits
Power-on and
Low Voltage
Reset
V
+
-
CC
Generation
V
TRIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X5323, X5325
Ordering Information
PART NUMBER
PART NUMBER
RESET
RESET
PART
PART
V
CC RANGE
(V)
TEMP
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKNIG
V
TRIP RANGE RANGE (°C)
PACKAGE
8 Ld PDIP
8 Ld PDIP (Pb-free)
X5323P-4.5A
X5323P AL
X5325P-4.5A
X5325P AL
X5325P Z AL
X5325P AM
X5325P Z AM
X5325 AL
4.5-5.5
4.5-4.75
0 to 70
0 to 70
X5323PZ-4.5A (Note) X5323P Z AL X5325PZ-4.5A
X5323PI-4.5A X5323P AM X5325PI-4.5A
X5323PIZ-4.5A (Note) X5323P Z AM X5325PIZ-4.5A
X5323S8-4.5A X5323 AL X5325S8-4.5A
-40 to 85 8 Ld PDIP
-40 to 85 8 Ld PDIP (Pb-free)
0 to 70
0 to 70
8 Ld SOIC
X5323S8Z-4.5A (Note) X5323 Z AL X5325S8Z-4.5A (Note) X5325 Z AL
8 Ld SOIC (Pb-free)
X5323S8I-4.5A*
X5323 AM
X5325S8I-4.5A
X5325 AM
-40 to 85 8 Ld SOIC
X5323S8IZ-4.5A*
(Note)
X5323 Z AM X5325S8IZ-4.5A
(Note)
X5325 Z AM
-40 to 85 8 Ld SOIC (Pb-free)
X5323V14-4.5A
X5325V14-4.5A
0 to 70
0 to 70
14 Ld TSSOP
X5323V14Z-4.5A
(Note)
X5323V Z AL X5325V14Z-4.5A
(Note)
X5325V Z AL
X5325V Z AM
14 Ld TSSOP
(Pb-free)
X5323V14I-4.5A
X5325V14I-4.5A
-40 to 85 14 Ld TSSOP
X5323V14IZ-4.5A
(Note)
X5323V Z AM X5325V14IZ-4.5A
(Note)
-40 to 85 14 Ld TSSOP
(Pb-free)
X5323P
X5323P
X5325P
X5325P
4.5-5.5
4.25-4.5
0 to 70
0 to 70
8 Ld PDIP
X5323PZ (Note)
X5323PI
X5323P Z
X5323P I
X5323P Z I
X5323
X5325PZ
X5325P Z
X5325P I
X5325P Z I
X5325
8 Ld PDIP (Pb-free)
X5325PI
-40 to 85 8 Ld PDIP
X5323PIZ (Note)
X5323S8*
X5325PIZ
-40 to 85 8 Ld PDIP (Pb-free)
X5325S8*
0 to 70
0 to 70
8 Ld SOIC
X5323S8Z* (Note)
X5323S8I*
X5323 Z
X5323 I
X5325S8Z* (Note)
X5325S8I*
X5325 Z
X5325 I
8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC
X5323S8IZ* (Note)
X5323V14*
X5323 Z I
X5323V
X5325S8IZ* (Note)
X5325V14*
X5325 Z I
-40 to 85 8 Ld SOIC (Pb-free)
0 to 70
0 to 70
14 Ld TSSOP
X5323V14Z* (Note)
X5323V Z
X5325V14Z* (Note)
X5325V Z
14 Ld TSSOP
(Pb-free)
X5323V14I*
X5325V14I*
-40 to 85 14 Ld TSSOP
X5323V14IZ* (Note)
X5323V Z I
X5323P AN
X5325V14IZ* (Note)
X5325V Z I
-40 to 85 14 Ld TSSOP
(Pb-free)
X5323P-2.7A
X5325P-2.7A
X5325P AN
X5325P Z AN
X5325P AP
X5325P Z AP
X5325 AN
2.7-5.5
2.85-3.0
0 to 70
0 to 70
8 Ld PDIP
X5323PZ-2.7A (Note) X5323P Z AN X5325PZ-2.7A
X5323PI-2.7A X5323P AP X5325PI-2.7A
X5323PIZ-2.7A (Note) X5323P Z AP X5325PIZ-2.7A
8 Ld PDIP (Pb-free)
-40 to 85 8 Ld PDIP
-40 to 85 8 Ld PDIP (Pb-free)
X5323S8-2.7A*
X5323 AN
X5325S8-2.7A
0 to 70
0 to 70
8 Ld SOIC
X5323S8Z-2.7A*
(Note)
X5323 Z AN X5325S8Z-2.7A (Note) X5325 Z AN
8 Ld SOIC (Pb-free)
X5323S8I-2.7A*
X5323 AP
X5325S8I-2.7A
X5325 AP
-40 to 85 8 Ld SOIC
X5323S8IZ-2.7A*
(Note)
X5323 Z AP X5325S8IZ-2.7A
(Note)
X5325 Z AP
-40 to 85 8 Ld SOIC (Pb-free)
FN8131.1
2
October 27, 2005
X5323, X5325
Ordering Information (Continued)
PART NUMBER
PART NUMBER
RESET
PART
RESET
PART
V
CC RANGE
(V)
TEMP
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKNIG
V
TRIP RANGE RANGE (°C)
PACKAGE
X5323V14-2.7A
X5323V AN
X5325V14-2.7A
2.7-5.5
2.85-3.0
0 to 70
0 to 70
14 Ld TSSOP
X5323V14Z-2.7A
(Note)
X5323V Z AN X5325V14Z-2.7A
(Note)
X5325V Z AN
14 Ld TSSOP
(Pb-free)
X5323V14I-2.7A
X5325V14I-2.7A
-40 to 85 14 Ld TSSOP
X5323V14IZ-2.7A
(Note)
X5323V Z AP X5325V14IZ-2.7A
(Note)
X5325V Z AP
-40 to 85 14 Ld TSSOP
(Pb-free)
X5323P-2.7
X5323P F
X5323P Z F X5325PZ-2.7
X5323P G X5325PI-2.7
X5323P Z G X5325PIZ-2.7
X5323 F X5325S8-2.7*
X5325P-2.7
X5325P F
X5325P Z F
X5325P G
X5325P Z G
X5325 F
2.7-5.5
2.55-2.7
0 to 70
0 to 70
8 Ld PDIP
X5323PZ-2.7 (Note)
X5323PI-2.7
8 Ld PDIP (Pb-free)
-40 to 85 8 Ld PDIP
X5323PIZ-2.7 (Note)
X5323S8-2.7*
-40 to 85 8 Ld PDIP (Pb-free)
0 to 70
0 to 70
8 Ld SOIC
X5323S8Z-2.7* (Note) X5323 Z F
X5323S8I-2.7* X5323 G
X5325S8Z-2.7* (Note) X5325 Z F
X5325S8I-2.7* X5325 G
X5325S8IZ-2.7* (Note) X5325 Z G
8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC
X5323S8IZ-2.7* (Note) X5323 Z G
X5323V14-2.7*
-40 to 85 8 Ld SOIC (Pb-free)
X5325V14-2.7*
X5325V F
0 to 70
0 to 70
14 Ld TSSOP
X5323V14Z-2.7*
(Note)
X5323V Z F X5325V14Z-2.7*
(Note)
X5325V Z F
14 Ld TSSOP
(Pb-free)
X5323V14I-2.7*
X5325V14I-2.7*
-40 to 85 14 Ld TSSOP
X5323V14IZ-2.7*
(Note)
X5323V Z G X5325V14IZ-2.7*
(Note)
X5325V Z G
-40 to 85 14 Ld TSSOP
(Pb-free)
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8131.1
3
October 27, 2005
X5323, X5325
PIN CONFIGURATION
14 Ld TSSOP
8 Ld SOIC/PDIP
1
VCC
CS/WDT
14
13
12
SO
NC
2
3
4
5
RESET/RESET
V
1
8
CS/WDT
SO
CC
X5323/25
NC
NC
2
3
7
6
RESET/RESET
X5323/25
NC
NC
11
10
9
WP
SCK
SI
NC
V
SS
4
5
WP
VSS
SCK
6
7
SI
8
PIN DESCRIPTION
Pin
Pin
(SOIC/PDIP) TSSOP
Name
Function
1
1
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a
high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, placing
it in the active power mode. Prior to the start of any operation after power-up, a
HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
2
5
2
8
SO
SI
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
3
9
6
SCK
WP
Serial Clock. The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits present
on the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
4
8
7
7
VSS
VCC
Ground
14
13
Supply Voltage
RESET/ Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
RESET
goes active whenever VCC falls below the minimum VCC sense level. It will re-
main active until VCC rises above the minimum VCC sense level for 200ms. RE-
SET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power-up at about 1V and remains active for 200ms after the power
supply stabilizes.
3-5,10-12
NC
No internal connections
FN8131.1
October 27, 2005
4
X5323, X5325
PRINCIPLES OF OPERATION
Power-on Reset
To set the new V
voltage, apply the desired V
TRIP TRIP
threshold to the Vcc pin and tie the CS/WDI pin and
the WP pin HIGH. RESET/RESET and SO pins are
left unconnected. Then apply the programming voltage
Application of power to the X5323/X5325 activates a
power-on reset circuit. This circuit goes active at about
1V and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. As long as RESET/RESET pin is
active, the device will not respond to any Read/Write
V to both SCK and SI and pulse CS/WDI LOW then
P
HIGH. Remove V and the sequence is complete.
P
Figure 1. Set V
Voltage
TRIP
CS
instruction. When V exceeds the device V
value
releases
CC
TRIP
VP
for
200ms
(nominal)
the
circuit
RESET/RESET, allowing the processor to begin exe-
cuting code.
SCK
VP
Low Voltage Monitoring
SI
During operation, the X5323/X5325 monitors the V
CC
level and asserts RESET/RESET if supply voltage
falls below preset minimum The
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
a
V
.
TRIP
Resetting the V
Voltage
TRIP
This procedure sets the V
level. For example, if the current V
to a “native” voltage
TRIP
is 4.4V and the
TRIP
V
is reset, the new V
is something less than
TRIP
TRIP
1.7V. This procedure must be used to set the voltage
to a lower value.
V
returns and exceeds V
for 200ms.
CC
TRIP
Watchdog Timer
To reset the V
voltage, apply a voltage between
TRIP
2.7 and 5.5V to the V
WP pin, and the SCK pin HIGH. RESET/RESET and
SO pins are left unconnected. Then apply the pro-
pin. Tie the CS/WDI pin, the
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be tog-
gled from HIGH to LOW prior to the expiration of the
watchdog time out period. The state of two nonvolatile
control bits in the status register determine the watch-
dog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin LOW and setting the WPEN bit HIGH.
CC
gramming voltage V to the SI pin ONLY and pulse
P
CS/WDI LOW then HIGH. Remove V and the
sequence is complete.
P
Figure 2. Reset V
Voltage
TRIP
CS
V
Threshold Reset Procedure
CC
VCC
SCK
The X5323/X5325 has a standard V
threshold
CC
(V
) voltage. This value will not change over normal
TRIP
VP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or
for higher precision in the
TRIP
SI
V
value, the
TRIP
X5323/X5325 threshold may be adjusted.
Setting the V
Voltage
TRIP
This procedure sets the V
to a higher voltage
TRIP
value. For example, if the current V
is 4.4V and
TRIP
the new V
is 4.6V, this procedure directly makes
TRIP
the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.
FN8131.1
5
October 27, 2005
X5323, X5325
Figure 3. V
Programming Sequence Flow Chart
TRIP
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
New VCC Applied =
New VCC Applied =
Old VCC Applied - Error
Old VCC Applied + Error
Execute
Reset VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 10mV)
NO
RESET pin
goes active?
YES
Error ≤ Emax
Error ≥ Emax
Measured VTRIP
Desired VTRIP
-
Error < Emax
DONE
Emax = Maximum Desired Error
Figure 4. Sample V
Reset Circuit
TRIP
VP
4.7K
NC
NC
4.7K
RESET
1
2
3
4
8
7
6
5
NC
X5323/25
VTRIP
Adj.
+
Program
Reset VTRIP
Test VTRIP
Set VTRIP
10K
10K
FN8131.1
October 27, 2005
6
X5323, X5325
SPI SERIAL MEMORY
Write Enable Latch
The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid write cycle.
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
™
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
7
6
5
4
3
2
1
0
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start
it again to resume operations where left off.
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
SFLB
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the write enable latch (enable write operations)
Set flag bit
WRDI/RFLB
RSDR
Reset the write enable latch/reset flag bit
Read status register
WRSR
Write status register (watchdog, block lock, WPEN & flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
READ
WRITE
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD Status Register Device Pin
Block
Block
Status Register
WPEN, BL0, BL1
WD0, WD1
WEL
WPEN
WP#
Protected Block Unprotected Block
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Protected
Writable
Writable
FN8131.1
October 27, 2005
7
X5323, X5325
The Write Enable Latch (WEL) bit indicates the sta-
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction.
tus of the write enable latch. When WEL = 1, the
latch is set HIGH and when WEL = 0 the latch is reset
LOW. The WEL bit is a volatile, read only bit. It can
be set by the WREN instruction and can be reset by
the WRDS instruction.
Status Register Bits
Watchdog Time Out
WD1
WD0
(Typical)
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to protect
one quarter, one half, all or none of the EEPROM array.
Any portion of the array that is block lock protected can
be read but not written. It will remain protected until the
BL bits are altered to disable block lock protection of that
portion of memory.
0
0
1
1
0
1
0
1
1.4 seconds
600 milliseconds
200 milliseconds
disabled (factory default)
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The flag bit is automatically
reset upon power-up. This flag can be used by the
system to determine whether a reset occurs as a
result of a watchdog time out or power failure.
Status
Register Bits
Array Addresses Protected
X5323/X5325
BL1
BL0
0
0
1
1
0
1
0
1
None (factory default)
$0C00-$0FFF
Notes: 1. The Watch Dog Timer is shipped disabled. (WD1 = 1,
WD0 = 1)
2. The factory default for Memory Block Protection is
‘None’. (BL1 = 0, BL0 = 0)
$0800-$0FFF
$0000-$0FFF
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
FN8131.1
8
October 27, 2005
X5323, X5325
In Circuit Programmable ROM Mode
Write Sequence
This mechanism protects the block lock and watchdog
bits from inadvertent corruption.
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
write operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
In the locked state (programmable ROM mode) the WP pin
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s status register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the status register.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the opera-
tion. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to
the first address of the page and overwrite any data
that may have been previously written.
When WP is HIGH, all functions, including nonvolatile
writes to the status register operate normally. Setting
the WPEN bit in the status register to “0” blocks the
WP pin function, allowing writes to the status register
when WP is HIGH or LOW. Setting the WPEN bit to
“1” while the WP pin is LOW activates the programma-
ble ROM mode, thus requiring a change in the WP pin
prior to subsequent status register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
status register. Manufacturing can then load configura-
tion data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation
will not be completed (Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
Read Sequence
While the write is in progress following a status regis-
ter or EEPROM Sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be high.
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation
is terminated by taking CS high. Refer to the read
EEPROM Array Sequence (Figure 1).
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The write enable latch is reset.
– The flag bit is reset.
– Reset signal is active for t
.
PURST
To read the status register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
status register are shifted out on the SO line. Refer to
the read status register sequence (Figure 2).
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the write
enable latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
FN8131.1
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October 27, 2005
X5323, X5325
Figure 6. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Figure 7. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Figure 8. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FN8131.1
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October 27, 2005
X5323, X5325
Figure 9. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
Instruction
Data Byte
5
4
3
2
1
0
SI
High Impedance
SO
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8131.1
11
October 27, 2005
X5323, X5325
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to+135°C
Storage temperature ........................ -65°C to+150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Voltage on any pin with respect to V .... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Device Option
-2.7 or -2.7A
Supply Voltage
2.7V to 5.5V
4.5V-5.5V
-40°C
+85°C
Blank or -4.5A
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ICC1
VCC write current (active)
5
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ICC2
ISB1
ISB2
ISB3
VCC read current (active)
0.4
1
mA
µA
µA
µA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
VCC standby current
WDT = OFF
CS = VCC, VIN = VSS or VCC
VCC = 5.5V
,
,
,
VCC standby current
WDT = ON
50
20
CS = VCC, VIN = VSS or VCC
VCC = 5.5V
VCC standby current
WDT = ON
CS = VCC, VIN = VSS or VCC
V
CC =3.6V
ILI
Input leakage current
Output leakage current
Input LOW voltage
0.1
0.1
10
10
µA
µA
V
VIN = VSS to VCC
ILO
VOUT = VSS to VCC
(1)
VIL
-0.5
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
Input HIGH voltage
VCC x 0.7
V
VOL1
VOL2
VOL3
VOH1
VOH2
VOH3
VOLS
Output LOW voltage
Output LOW voltage
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
Reset output LOW voltage
V
VCC > 3.3V, IOL = 2.1mA
0.4
V
2V < VCC ≤ 3.3V, IOL = 1mA
VCC ≤ 2V, IOL = 0.5mA
0.4
V
VCC - 0.8
VCC - 0.4
VCC - 0.2
V
VCC > 3.3V, IOH = -1.0mA
2V < VCC ≤ 3.3V, IOH = -0.4mA
VCC ≤ 2V, IOH = -0.25mA
V
V
0.4
V
IOL = 1mA
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Test
Max.
Unit
Conditions
VOUT = 0V
VIN = 0V
(2)
COUT
Output capacitance (SO, RESET/RESET)
Input capacitance (SCK, SI, CS, WP)
8
6
pF
pF
(2)
CIN
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
FN8131.1
October 27, 2005
12
X5323, X5325
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
5V
5V
Input rise and fall times
Input and output timing level
V
CC x0.5
4.6kΩ
2.06kΩ
Output
3.03kΩ
RESET/RESET
30pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7–5.5V
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
Parameter
Min.
0
Max.
Unit
MHz
ns
Clock frequency
Cycle time
2
500
250
250
200
250
50
CS lead time
ns
CS lag time
ns
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
Write cycle time
ns
tWL
ns
tSU
ns
tH
50
ns
(3)
tRI
100
100
ns
(3)
tFI
ns
tCS
500
ns
(4)
tWC
10
ms
FN8131.1
October 27, 2005
13
X5323, X5325
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
High Impedance
SO
Serial Output Timing
Symbol
2.7-5.5V
Max.
Parameter
Min.
Unit
MHz
ns
fSCK
tDIS
tV
Clock frequency
Output disable time
0
2
250
250
Output valid from clock low
Output hold time
ns
tHO
0
ns
(3)
tRO
Output rise time
100
100
ns
(3)
tFO
Output fall time
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
SO
tCYC
tWH
tLAG
tV
tHO
tWL
tDIS
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
FN8131.1
14
October 27, 2005
X5323, X5325
Power-Up and Power-Down Timing
VTRIP
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tRPD
tR
RESET (X5323)
RESET (X5323)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset trip point voltage, X5323-4.5A, X5323-4.5A
Reset trip point voltage, X5323, X5325
Reset trip point voltage, X5323-2.7A, X5325-2.7A
Reset trip point voltage, X5323-2.7, X5325-2.7
4.5
4.63
4.38
2.92
2.63
4.75
4.5
3.0
4.25
2.85
2.55
V
2.7
VTH
VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
20
mV
ms
ns
µs
µs
V
tPURST
Power-up reset time out
VCC detect to reset/output
VCC fall time
100
200
280
500
(5)
tRPD
(5)
tF
100
100
1
(5)
tR
VCC rise time
VRVALID
Reset valid VCC
Note: (5) This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
tCST
RESET
tWDO
tRST
tWDO
tRST
RESET
FN8131.1
15
October 27, 2005
X5323, X5325
RESET/RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
tWDO
Watchdog time out period,
WD1 = 1, WD0 = 0
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
tCST
tRST
CS pulse width to reset the watchdog
Reset time out
400
100
ns
200
300
ms
V
Set Conditions
TRIP
tTHD
VCC
VTRIP
tTSU
tRP
tP
tVPH
tVPS
CS
tVPO
tVPH
tVPS
VP
SCK
VP
tVPO
SI
V
Reset Conditions
TRIP
VCC
*
tRP
tP
tVP1
tVPS
CS
tVPS
tVPO
tVPH
VCC
SCK
SI
VP
tVPO
*VCC > Programmed VTRIP
FN8131.1
October 27, 2005
16
X5323, X5325
V
Programming Specifications V = 1.7–5.5V; Temperature = 0°C to 70°C
CC
TRIP
Parameter
tVPS
tVPH
tP
Description
SCK VTRIP program voltage setup time
Min. Max. Unit
1
1
µs
µs
µs
µs
ms
ms
ms
ms
V
SCK VTRIP program voltage hold time
VTRIP program pulse width
1
tTSU
tTHD
tWC
VTRIP level setup time
10
10
VTRIP level hold (stable) time
VTRIP write cycle time
10
tRP
VTRIP program cycle recovery period (between successive programming cycles)
SCK VTRIP program voltage off time before next cycle
Programming voltage
10
0
tVPO
VP
VTRAN
Vta1
15
18
5.0
VTRIP programed voltage range
1.7
-0.1
-25
V
Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C)
+0.4
+25
V
Vta2
Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP
]
mV
(programmed at 25°C)
Vtr
VTRIP program voltage repeatability (successive program operations) (programmed
at 25°C)
-25
-25
+25
+25
mV
mV
Vtv
VTRIP program variation after programming (0–75°C). (programmed at 25°C)
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8131.1
17
October 27, 2005
X5323, X5325
TYPICAL PERFORMANCE
V
Supply Current vs. Temperature (I
)
t vs. Voltage/Temperature (WD1,0 = 1, 1)
WDO
CC
SB
1.9
1.8
18
Watchdog Timer On (VCC = 5V)
16
1.7
1.6
1.5
1.4
-40°C
14
12
25°C
Watchdog Timer On (VCC = 5V)
10
8
90°C
1.3
1.2
1.1
1
6
4
Watchdog Timer Off (VCC= 3V, 5V)
2
0
1.7
2.4
3.1
3.8
4.5
5.2
-40
25
90
Voltage
Temp (°C)
t
vs. Voltage/Temperature (WD1, 0 = 1, 0)
V
vs. Temperature (programmed at 25°C)
WDO
TRIP
0.8
5.025
V
TRIP = 5V
0.75
5.000
-40°C
0.7
0.65
4.975
3.525
3.500
25°C
V
TRIP = 3.5V
90°C
0.6
3.475
0.55
0.5
2.525
2.500
2.475
VTRIP = 2.5V
0.45
1.7
2.4
3.1
Voltage
3.8
4.5
5.2
0
25
85
Temperature
t
vs. Temperature
t
vs. Voltage/Temperature (WD1, 0 0 = 0, 1)
WDO
PURST
205
200
205
200
195
190
185
180
175
170
165
-40°C
195
190
185
180
175
25°C
90°C
170
165
160
160
1.7
2.4
3.1
3.8
4.5
5.2
-40
25
90
Voltage
Degrees °C
FN8131.1
October 27, 2005
18
X5323, X5325
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.050 (1.27)
0.010 (0.25)
0.010 (0.25)
0.020 (0.50)
0.050"Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8131.1
19
October 27, 2005
X5323, X5325
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
FN8131.1
20
October 27, 2005
X5323, X5325
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8131.1
21
October 27, 2005
相关型号：
X5325V14-2.7A
Power Supply Management Circuit, Adjustable, 1 Channel, PDSO14, PLASTIC, TSSOP-14
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