W83977EF-PW [WINBOND]
WINBOND I/O; WINBOND I / O
| 型号： | W83977EF-PW |
| 厂家： | 
WINBOND |
| 描述： | WINBOND I/O |
| 文件： | 总150页 (文件大小：726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W83977EF
WINBOND I/O
W83977EF Data Sheet Revision History
Version
on Web
Pages
Dates
Version
Main Contents
First published.
1
n.a.
06/01/98
0.40
For Beta Site customers only
4,7,49,50,53,55,
90,91
2
06/16/98
12/30/03
03/07/03
04/25/03
0.41
0.5
Data correction
3
n.a.
Remove W83977CTF Part
Update the new version on web
Add Chapter 10 Configuration Register
4
1.0
1.1
P86~P110
5
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result in
personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
W83977EF
TABLE OF CONTENTS
GENERAL DESCRIPTION ..................................................................................................................... 1
FEATURES ............................................................................................................................................. 2
PIN CONFIGURATION........................................................................................................................... 5
1.0 PIN DESCRIPTION.......................................................................................................................... 6
1.1 HOST INTERFACE ............................................................................................................................. 6
1.2 GENERAL PURPOSE I/O PORT .......................................................................................................... 8
1.3 SERIAL PORT INTERFACE.................................................................................................................. 9
1.4 INFRARED INTERFACE..................................................................................................................... 10
1.5 MULTI-MODE PARALLEL PORT ........................................................................................................ 11
1.6 FDC INTERFACE ............................................................................................................................ 16
1.7 KBC INTERFACE ............................................................................................................................ 18
1.8 POWER PINS.............................................................................................................................. 18
1.9 ACPI INTERFACE ........................................................................................................................... 18
2.0 FDC FUNCTIONAL DESCRIPTION............................................................................................... 19
2.1 W83977EF FDC .......................................................................................................................... 19
2.1.1 AT interface........................................................................................................................... 19
2.1.2 FIFO (Data)........................................................................................................................... 19
2.1.3 Data Separator...................................................................................................................... 20
2.1.4 Write Precompensation......................................................................................................... 20
2.1.5 Perpendicular Recording Mode ............................................................................................ 21
2.1.5 Perpendicular Recording Mode ............................................................................................ 21
2.1.6 FDC Core.............................................................................................................................. 21
2.1.7 FDC Commands ................................................................................................................... 21
2.2 REGISTER DESCRIPTIONS............................................................................................................... 33
2.2.1 Status Register A (SA Register) (Read base address + 0) .................................................. 33
2.2.2 Status Register B (SB Register) (Read base address + 1) .................................................. 35
2.2.3 Digital Output Register (DO Register) (Write base address + 2).......................................... 37
2.2.4 Tape Drive Register (TD Register) (Read base address + 3) .............................................. 37
2.2.5 Main Status Register (MS Register) (Read base address + 4) ............................................ 38
2.2.6 Data Rate Register (DR Register) (Write base address + 4) ............................................... 38
2.2.7 FIFO Register (R/W base address + 5) ................................................................................ 40
2.2.8 Digital Input Register (DI Register) (Read base address + 7).............................................. 42
2.2.9 Configuration Control Register (CC Register) (Write base address + 7) ............................. 43
3.0 UART PORT.................................................................................................................................... 45
3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) .................................... 45
3.2 REGISTER ADDRESS ...................................................................................................................... 45
3.2.1 UART Control Register (UCR) (Read/Write) ........................................................................ 45
3.2.2 UART Status Register (USR) (Read/Write).......................................................................... 48
3.2.3 Handshake Control Register (HCR) (Read/Write)................................................................ 48
Publication Release Date: April 2003
-II -
Revision 1.1
W83977EF
3.2.4 Handshake Status Register (HSR) (Read/Write) ................................................................. 49
3.2.5 UART FIFO Control Register (UFR) (Write only).................................................................. 50
3.2.6 Interrupt Status Register (ISR) (Read only).......................................................................... 51
3.2.7 Interrupt Control Register (ICR) (Read/Write) ...................................................................... 52
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) .................................................... 52
3.2.9 User-defined Register (UDR) (Read/Write) .......................................................................... 52
4.0 INFRARED (IR) PORTS ................................................................................................................. 54
4.1 IR PORT ...................................................................................................................................... 54
5.0 PARALLEL PORT ......................................................................................................................... 55
5.1 PRINTER INTERFACE LOGIC ............................................................................................................ 55
5.2 ENHANCED PARALLEL PORT (EPP)................................................................................................. 56
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Data Swapper................................................................................................................. 56
Printer Status Buffer ........................................................................................................ 57
Printer Control Latch and Printer Control Swapper........................................................ 58
EPP Address Port............................................................................................................ 58
EPP Data Port 0-3 ........................................................................................................... 59
Bit Map of Parallel Port and EPP Registers .................................................................... 59
EPP Pin Descriptions...................................................................................................... 60
EPP Operation................................................................................................................. 60
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT........................................................................... 61
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
ECP Register and Mode Definitions................................................................................ 61
Data and ecpAFifo Port ................................................................................................... 62
Device Status Register (DSR)........................................................................................ 62
Device Control Register (DCR) ....................................................................................... 63
CFIFO (Parallel Port Data FIFO) Mode = 010................................................................. 64
ECPDFIFO (ECP Data FIFO) Mode = 011...................................................................... 64
TFIFO (Test FIFO Mode) Mode = 110 ............................................................................ 64
CNFGA (Configuration Register A) Mode = 111............................................................. 64
CNFGB (Configuration Register B) Mode = 111............................................................. 64
5.3.10 ECR (Extended Control Register) Mode = all ................................................................. 65
5.3.11 Bit Map of ECP Port Registers ........................................................................................ 66
5.3.12 ECP Pin Descriptions ...................................................................................................... 67
5.3.13 ECP Operation................................................................................................................. 68
5.3.14 FIFO Operation................................................................................................................ 68
5.3.15 DMA Transfers................................................................................................................. 69
5.3.16 Programmed I/O (NON-DMA) Mode ............................................................................... 69
5.4
EXTENSION FDD MODE (EXTFDD).......................................................................................... 69
5.5
EXTENSION 2FDD MODE (EXT2FDD)...................................................................................... 69
6.
KEYBOARD CONTROLLER..................................................................................................... 70
6.1 OUTPUT BUFFER........................................................................................................................... 70
6.2 INPUT BUFFER .............................................................................................................................. 70
66..34 STCATOUMSMRAENGDISS.T..E..R.................................................................................................................................................................................................................................................. 7721
6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC........................................................... 73
6.5.1
6.5.2
KB Control Register (Logic Device 5, CR-F0)................................................................. 74
Port 92 Control Register (Default Value = 0x24)............................................................. 74
6.6
ONNOW / SECURITY KEYBOARD AND MOUSE WAKE-UP.............................................................. 75
Publication Release Date: April 2003
-III -
Revision 1.1
W83977EF
6.6.1
6.6.2
6.6.3
Keyboard Wake-Up Function .......................................................................................... 75
Keyboard Password Wake-Up Function ........................................................................ 75
Mouse Wake-Up Function............................................................................................... 75
7.0 GENERAL PURPOSE I/O .............................................................................................................. 76
7.1
7.2
BASIC I/O FUNCTIONS................................................................................................................ 78
ALTERNATE I/O FUNCTIONS....................................................................................................... 80
7.2.1
7.2.2
Interrupt Steering............................................................................................................. 80
Watch Dog Timer Output................................................................................................. 81
Power LED....................................................................................................................... 81
General Purpose Address Decoder ................................................................................ 81
7.2.3
7.2.4
8.0
8.1
8.1.1
8.1.2
PLUG AND PLAY CONFIGURATION....................................................................................... 82
COMPATIBLE PNP ..................................................................................................................... 82
Extended Function Registers .......................................................................................... 82
Extended Functions Enable Registers (EFERs) ............................................................. 83
Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)
83
8.1.3
8.2 CONFIGURATION SEQUENCE.......................................................................................................... 83
8.2.1 Enter the extended function mode........................................................................................ 83
8.2.2 Configurate the configuration registers................................................................................. 84
8.2.3 Exit the extended function mode........................................................................................... 84
8.2.4 Software programming example........................................................................................... 84
9.0
ACPI REGISTERS FEATURES................................................................................................. 85
10.0 CONFIGURATION REGISTER ................................................................................................... 86
10.1 CHIP (GLOBAL) CONTROL REGISTER ............................................................................................ 86
10.2 LOGICAL DEVICE 0 (FDC) ........................................................................................................... 92
10.3 LOGICAL DEVICE 1 (PARALLEL PORT) .......................................................................................... 96
10.4 LOGICAL DEVICE 2 (UART A)¢) .................................................................................................. 96
10.5 LOGICAL DEVICE 3 (UART B) ..................................................................................................... 97
10.6 LOGICAL DEVICE 5 (KBC) ......................................................................................................... 100
10.7 LOGICAL DEVICE 7 (GP I/O PORT I) .......................................................................................... 101
10.8 LOGICAL DEVICE 8 (GP I/O PORT II) ......................................................................................... 105
10.9 LOGICAL DEVICE A (ACPI) ........................................................................................................ 110
11.0 SPECIFICATIONS ...................................................................................................................... 117
11.1 ABSOLUTE MAXIMUM RATINGS................................................................................................... 117
11.2 DC CHARACTERISTICS........................................................................................................ 117
11.3 AC CHARACTERISTICS .............................................................................................................. 121
11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec.................................................... 121
11.3.2 UART/Parallel Port........................................................................................................... 123
11.3.3 Parallel Port Mode Parameters........................................................................................ 123
11.3.4 EPP Data or Address Read Cycle Timing Parameters ................................................... 124
11.3.5 EPP Data or Address Write Cycle Timing Parameters.................................................... 125
11.3.6 Parallel Port FIFO Timing Parameters............................................................................. 126
11.3.7 ECP Parallel Port Forward Timing Parameters ............................................................... 126
11.3.8 ECP Parallel Port Reverse Timing Parameters............................................................... 126
Publication Release Date: April 2003
-IV -
Revision 1.1
W83977EF
11.3.9 KBC Timing Parameters .................................................................................................. 127
11.3.10 GPIO Timing Parameters............................................................................................... 127
11.3.11 Keyboard/Mouse Timing Parameters ............................................................................ 128
12.0 TIMING WAVEFORMS.............................................................................................................. 129
12.1 FDC......................................................................................................................................... 129
12.2 UART/PARALLEL ...................................................................................................................... 130
12.2.1 Modem Control Timing..................................................................................................... 131
12.3 PARALLEL PORT........................................................................................................................ 132
12.3.1 Parallel Port Timing.......................................................................................................... 132
12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)..................................................... 133
12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) ..................................................... 134
12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)..................................................... 135
12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) ..................................................... 136
12.3.6 Parallel Port FIFO Timing................................................................................................. 136
12.3.7 ECP Parallel Port Forward Timing................................................................................... 137
12.3.8 ECP Parallel Port Reverse Timing................................................................................... 137
12.4 KBC......................................................................................................................................... 138
12.4.1 Write Cycle Timing........................................................................................................... 138
12.4.2 Read Cycle Timing........................................................................................................... 138
12.4.3 Send Data to K/B ............................................................................................................. 138
12.4.4 Receive Data from K/B..................................................................................................... 138
12.4.5 Input Clock ....................................................................................................................... 139
12.4.6 Send Data to Mouse ........................................................................................................ 139
12.4.7 Receive Data from Mouse ............................................................................................... 139
12.5 GPIO WRITE TIMING DIAGRAM.................................................................................................. 140
12.6 MASTER RESET (MR) TIMING.................................................................................................... 140
12.7 KEYBOARD/MOUSE WAKE-UP TIMING......................................................................................... 140
13.0 APPLICATION CIRCUITS.......................................................................................................... 141
13.1 PARALLEL PORT EXTENSION FDD ............................................................................................. 141
13.2 PARALLEL PORT EXTENSION 2FDD ........................................................................................... 142
13.3 FOUR FDD MODE..................................................................................................................... 143
14.0 ORDERING INFORMATION ...................................................................................................... 143
15.0 HOW TO READ THE TOP MARKING ...................................................................................... 143
16.0 PACKAGE DIMENSIONS.......................................................................................................... 144
Publication Release Date: April 2003
-V -
Revision 1.1
W83977EF
GENERAL DESCRIPTION
The W83977EF is an evolving product from Winbond's most popular I/O chip W83877F --- which
integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plug-
and-play registers for the whole chip --- plus additional powerful features: ACPI, 8042 keyboard
controller with PS/2 mouse support, 14 general purpose I/O ports, full 16-bit address decoding,
OnNow keyboard Wake-Up, OnNow mouse Wake-Up.
The disk drive adapter functions of W83977EF include a floppy disk drive controller compatible with
the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data
rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide
range of functions integrated onto the W83977EF greatly reduces the number of components required
for interfacing with floppy disk drives. The W83977EF supports four 360K, 720K, 1.2M, 1.44M, or
2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The W83977EF provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system. Both
UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud
rates of
,
, or
which support higher speed modems.
921k bps
230k 460k
The W83977EF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or
two external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95TM, which makes system resource allocation more efficient than ever.
W83977EF provides functions that complies with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through SMI or SCI
function pins. W83977EF also has auto power management to reduce power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable
ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEYTM -2,
Phoenix MultiKey/42TM, or customer code.
The W83977EF provides a set of flexible I/O control functions to the system designer through a set of
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a predefined alternate function.
The W83977EF also supports Power-loss control, and makes the system never miss to detect any
Wake-Up event provided by the chipset such as INTEL PIIX4 TM
.
W83977EF is made to fully comply with Microsoft PC98 Hardware Design Guide. IRQs, DMAs, and
I/O space resource are flexible to adjust to meet ISA PnP requirement. Moreover W83977EF is made
to meet the specification of PC98's requirement in the power management:
Power Management).
and
(Device
DPM
ACPI
Another benifit is that W83977EF is of the same pin assignment of W83977AF, W83977F, W83977TF,
W83977ATF. Thus makes the design very flexible.
Publication Release Date: April 2003
-1 -
Revision 1.1
W83977EF
FEATURES
General
• Plug & Play 1.0A compatible
• Support 12 IRQs, 4 DMA channels, full 16-bit address decoding
• Capable of ISA Bus IRQ Sharing
• Compliant with Microsoft PC98 Hardware Design Guide
• Support DPM (Device Power Management), ACPI
• Report ACPI status interrupt by SCI# signal issued from any of the 12 IQRs pins or GPIO xx
• Programmable configuration settings
• single 24/48 Mhz clock input
FDC
• Compatible with IBM PC AT disk drive systems
• Variable write pre-compensation with track selectable capability
• Support vertical recording format
• DMA enable logic
• 16-byte data FIFOs
• Support floppy disk drives and tape drives
• Detects all overrun and underrun conditions
• Built-in address mark detection circuit to simplify the read electronics
• FDD anti-virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive)
• Support up to four 3.5-inch or 5.25-inch floppy disk drives
• Completely compatible with industry standard 82077
• 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
• Support 3-mode FDD, and its Win95 driver
UART
• Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
• MIDI compatible
• Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
Publication Release Date: April 2003
-2 -
Revision 1.1
W83977EF
• Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
• Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (216-1)
• Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz
Infrared
• Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
• Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
Parallel Port
• Compatible with IBM parallel port
• Support PS/2 compatible bi-directional parallel port
• Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification
• Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification
• Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and
B through parallel port
• Enhanced printer port back-drive current protection
Keyboard Controller
• 8042 based with optional F/W from AMIKKEYTM-2, Phoenix MultiKey/42TM or customer code
• With 2K bytes of programmable ROM, and 256 bytes of RAM
• Asynchronous Access to Two Data Registers and One status Register
• Software compatibility with the 8042 and PC87911 microcontrollers
• Support PS/2 mouse
• Support port 92
• Support both interrupt and polling modes
• Fast Gate A20 and Hardware Keyboard Reset
• 8 Bit Timer/ Counter
• Support binary and BCD arithmetic
• 6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
Publication Release Date: April 2003
-3 -
Revision 1.1
W83977EF
General Purpose I/O Ports
• 14 programmable general purpose I/O ports; 6 dedicate, 8 optional
• General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog
timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control
I/O pins
OnNow Funtions
• Keyboard Wake-Up by programmable keys
• Mouse Wake-Up by programmable buttons
Package
• 128-pin PQFP
Publication Release Date: April 2003
-4 -
Revision 1.1
W83977EF
PIN CONFIGURATION
P
A
N
S
W
O
U
T
#
P
A
N
S
W
I
P
W
R
C
T
S
M
I
L
N
#
/
#
#
/
I
I I
/
P
2
0
/
R R RI
I
I
I
I
I
I
G
G G
2
G
P
2
K /
M
C
L
/
Q Q QR R R R R R
R
A V A A A
1 S 1 1 1
A
V
S
B
A
P P
3 2
V
C R
L I
R
I
1 1 1 Q Q Q Q Q Q N Q
1 A A A A A A A A A
1 C
2
A
0
2 1 0 1 3 4 5 6 7 C 9
5 S 4 3 2 1 C0 9 8 7 6 5 4 3 2 1
1
K B
K
A
9
7
9
8 8
6 5
7 7 7 7
7 6
0 9
6
6
1 1 1
9
9
9 8 8 8
8 8 8 7 7
7
7
6
6
5
9
9 9 9 9
8
4
8
7
1
7 6 4 3
6
0 0 0 9 8
2 1 0
6 5 4 3 2 0 9 8 7
3 2 1 0 9 8
5
2 1
8 7
64
103
104
IRQ14/GP14
IRQ15/GP15
VBAT
63
62
61
60
59
XTAL1
VSS
105
106
107
108
109
110
111
112
113
IOR#
IOW#
AEN
XTAL2
MDATA
KDATA
IOCHRDY
KBLOCK/GP13
KBRST/GP12
GA20/GP11
VCC
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
D0
D1
D2
D3
DCDB#
D4
D5
SOUTB/PEN48
114
115
116
117
118
119
120
121
SINB
VCC
D6
DTRB#
RTSB
D7
MR
DSRB#
CTSB#
DACK0#/GP16
VSS
DCDA#
SCI#/DRQ0/GP17
SOUTA/PENKBC
SINA
122
123
124
DACK1#
DRQ1
DTRA#/PNPCSV#
RTSA#/HEFRAS
DSRA#
DACK2#
DRQ2
125
126
127
CTSA#
DACK3#
DRQ3
TC
CIRRX/GP24
128
SUSCIN#/GP25
2
0
2
3
1 1 1 1 1 1
2 2 2 2 2 2
2 3 3 3
3
5
1 1 1 1
2
3
4
3
6
3
8
3
7
4
7
3
1 2 3 5 6
9
4
8 9
3
6 7 8 9
0 1
2
8
1
5 6 7
1 2 4 5
0
2 3
P
S
P
D
0
D
R
V
D
E
N
/
/
P
D
1
/
I
I
D
R
V
D
/
/
/
/
V
C
C
/
P P
P
S 5
P P
4 3 2
/
/
/
/
/
D
/
V
C
L
K
I
/ /
/
/
/
/
B
U
S
Y
P
E
L
M
O
B
I
D
S I
R
T
X
W
E
S D
T I
M
O
A
A D
D D D D
E A
R
W
D
S
A
S
S
D H R
T
D
S
B
W
N
D
E
X
L
I
C
C 7 6
K
N R F T R
S E P R
D
E
P
K
R
T
I
R D B X
A
A
K
0
A
T
A
N E
N
N T
C
H
G
D
1
,
0
G
P
1
0
,
/
S
C
I
Publication Release Date: April 2003
Revision 1.1
-5 -
W83977EF
1.0 PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O
I/O
I/O
I/O
I/O
I/O
- TTL level bi-directional pin with 6 mA source-sink capability
- TTL level bi-directional pin with 8 mA source-sink capability
- CMOS level bi-directional pin with 8 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability
- CMOS level bi-directional pin with 12 mA source-sink capability
- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
6t
8t
8
12t
12
16u
I/OD
I/O
24t
OUT
OUT
- CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 8 mA source-sink capability
- TTL level output pin with 12 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- TTL level input pin
- CMOS level input pin
- CMOS level input pin with internal pull-up resitor
- CMOS level Schmitt-triggered input pin
16u
8t
12t
OD
OD
12
24
IN
IN
IN
IN
IN
IN
t
c
cu
cs
ts
- TTL level Schmitt-triggered input pin
- TTL level Schmitt-triggered input pin with internal pull-up resistor
tsu
1.1 Host Interface
SYMBOL
A0−A10
A11-A14
A15
PIN
I/O
INt
INt
INt
FUNCTION
System address bus bits 0-10
74-84
86-89
91
System address bus bits 11-14
System address bus bit 15
109-114
116-117
105
106
107
I/O12t System data bus bits 0-5
I/O12t System data bus bits 6-7
D0−D5
D6−D7
IOR#
IOW#
AEN
INts
INts
INts
CPU I/O read signal
CPU I/O write signal
System address bus enable
IOCHRDY
108
OD24 In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
MR
118
INts
Master Reset; Active high; MR is low during normal operations.
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Revision 1.1
W83977EF
1.1 Host Interface, continued
SYMBOL
PIN
I/O
FUNCTION
DACK0#
119
INtsu
DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,
default)
GP16
I/O12t
General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)
Alternate function from GP16: Watch dog timer output
KBC P15 I/O port. (CR2C bit 5_4 = 10)
(WDTO)
P15
I/O12t
DRQ0
121
OUT12t DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)
GP17
I/O12t
General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)
Alternate Function from GP17: Power LED output.
KBC P14 I/O port (CR2C bit 7_6 = 10)
(PLEDO)
P14
I/O12t
SCI#
OUT12t System Control Interrupt (CR2C bit 7_6 = 11)
INts DMA Channel 1 Acknowledge signal
OUT12t DMA Channel 1 request signal
INts DMA Channel 2 Acknowledge signal
OUT12t DMA Channel 2 request signal
INts DMA Channel 3 Acknowledge signal
OUT12t DMA Channel 3 request signal
INts Terminal Count. When active, this pin indicates termination of a
DMA transfer.
DACK1#
DRQ1
DACK2#
DRQ2
DACK3#
DRQ3
TC
122
123
124
125
126
127
128
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
99
98
97
96
95
94
92
100
101
102
OUT12t Interrupt request 1
OUT12t Interrupt request 3
OUT12t Interrupt request 4
OUT12t Interrupt request 5
OUT12t Interrupt request 6
OUT12t Interrupt request 7
OUT12t Interrupt request 9
OUT12t Interrupt request 10
OUT12t Interrupt request 11
OUT12t Interrupt request 12
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Revision 1.1
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W83977EF
1.1 Host Interface, continued
SYMBOL
IRQ14
PIN
103
I/O
FUNCTION
OUT12t Interrupt request 14. (CR2C bit 1_0 = 00, default)
GP14
I/O12t
General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01)
(GPACS1#)
Alternate Function 1 from GP14: General purpose address
decode output.
(P17)
Alternate Function 2 from GP14: KBC P17 I/O port.
PLEDO
IRQ15
OUT12t Power LED output. (CR2C bit 1_0 = 10)
OUT12t Interrupt request 15.(CR2C bit 3_2 = 00, default)
104
GP15
I/O12t
General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01)
(GPACS2#)
Alternate Function 1 from GP15: General purpose address write
enable output.
(P12)
WDT
Alternate Function 2 from GP15: KBC P12 I/O port.
OUT12t Watch-Dog timer output. (CR2C bit 3_2 = 10)
CLKIN
1
INt
24 or 48 MHz clock input, selectable through bit 5 of CR24.
1.2 General Purpose I/O Port
SYMBOL
PWR_CTL#
GP20
PIN
69
I/O
OD16u
FUNCTION
Power supply control
I/O16tu General purpose I/O port 2 bit 0.
(KBRST)
SMI #
Alternate Function from GP20: Keyboard reset (KBC P20)
70
72
OD12t
I/O12t
For the power management, the SMI is active low by the power
management events, that generate and SCI in ACPI mode.
(CR2B bit 4_3 = 00, default)
GP21
(P13)
P16
PANSWOT#
GP22
(P14)
General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01)
Alternate Function from GP21: KBC P13 I/O port.
KBC P16 I/O port. (CR2B bit 4_3 = 10)
Panel Switch output. (CR2B bit 5 = 0, default)
General purpose I/O port 2 bit 2. (CR2B bit 5 = 1)
Alternate Function from GP22: KBC P14 I/O port.
I/O12t
OD12t
I/O12t
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Revision 1.1
W83977EF
1.2 General Purpose I/O Port ,continued
SYMBOL
PANSWIN#
GP23
(P15)
SUSC#
PIN
73
I/O
INt
I/O12t
FUNCTION
Panel Switch input. (CR2B bit 7_6 = 00, default)
General purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01)
Alternate Function from GP23: KBC P15 I/O port
Suspend C input
39
INts
(GA20)
GP25
Alternate Function from GP25: GATE A20 (KBC P21)
General purpose I/O port 2 bit 5.
I/O12
1.3 Serial Port Interface
SYMBOL
CTSA#
PIN
41
I/O
INt
FUNCTION
Clear To Send is the modem control input.
48
CTSB#
The function of these pins can be tested by reading Bit 4 of the
handshake status register.
42
49
INt
DSRA#
DSRB#
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
43
I/O8t
UART A Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
RTSA#
During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for
CR26 bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to
pull up. (select 370H as configuration I/O port′s address)
HEFRAS
50
I/O8t
UART B Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
RTSB#
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Revision 1.1
W83977EF
1.3 Serial Port Interface, continued
SYMBOL
PIN
I/O
FUNCTION
44
I/O8t
UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.
DTRA#
During power-on reset, this pin is pulled down internally and is
defined as PNPCSV#, which provides the power-on value for
CR24 bit 0 (PNPCSV#). A 4.7 kΩ is recommended if intends to
pull up. (clear the default value of FDC, UARTs, and PRT)
PNPCSV#
51
I/O8t
UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.
DTRB#
45, 52
46
INt
SINA
SINB
Serial Input. Used to receive serial data through the
communication link.
UART A Serial Output. Used to transmit serial data out to the
communication link.
I/O8t
SOUTA
During power-on reset, this pin is pulled down internally and is
defined as PENKBC, which provides the power-on value for
CR24 bit 2 (ENKBC). A 4.7 kΩ resistor is recommended if
intends to pull up. (enable KBC)
PENKBC
SOUTB
PEN48
53
I/O8t
UART B Serial Output. During power-on reset, this pin is pulled
down internally and is defined as PEN48, which provides the
power-on value for CR24 bit 6 (EN48). A 4.7 kΩ resistor is
recommended if intends to pull up.
47
54
INt
INt
DCDA#
DCDB#
RIA#
Data Carrier Detect. An active low signal indicates the modem or
data set has detected a data carrier.
65
66
Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.
RIB#
1.4 Infrared Interface
SYMBOL
IRRX
IRTX
PIN
37
38
I/O
INcs
FUNCTION
Infrared Receiver input.
OUT12t Infrared Transmitter Output.
Publication Release Date: April 2003
Revision 1.1
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W83977EF
1.5 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SYMBOL
SLCT
PIN
18
I/O
INt
FUNCTION
PRINTER MODE: SLCT
An active high input on this pin indicates that the printer is
selected. This pin is pulled high internally. Refer to description of
the parallel port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE:
This pin is for Extension FDD B; its function is the same as the
WE# pin of FDC.
OD12
OD12
INt
WE2#
EXTENSION 2FDD MODE: WE2#
This pin is for Extension FDD A and B; it function is the same as
the WE# pin of FDC.
PRINTER MODE: PE
PE
19
An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
EXTENSION FDD MODE: WD2#
OD12
OD12
This pin is for Extension FDD B; its function is the same as the
WD# pin of FDC.
EXTENSION 2FDD MODE: WD2#
This pin is for Extension FDD A and B; its function is the same as
the WD# pin of FDC.
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Revision 1.1
W83977EF
1.5 Multi-Mode Parallel Port, continued
SYMBOL
BUSY
PIN
21
I/O
INt
FUNCTION
PRINTER MODE: BUSY
An active high input indicates that the printer is not ready to
receive data. This pin is pulled high internally. Refer to
description of the parallel port for definition of this pin in ECP and
EPP mode.
OD12
OD12
EXTENSION FDD MODE: MOB2#
This pin is for Extension FDD B; the function of this pin is the
same as the MOB# pin of FDC.
EXTENSION 2FDD MODE:MOB2#
This pin is for Extension FDD A and B; the function of this pin is
the same as the MOB# pin of FDC.
ACK#
22
INt
PRINTER MODE: ACK#
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is
pulled high internally. Refer to description of the parallel port for
definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSB2#
OD12
OD12
INt
This pin is for the Extension FDD B; its functions is the same as
the DSB# pin of FDC.
EXTENSION 2FDD MODE: DSB2#
This pin is for Extension FDD A and B; it functions is the same as
the DSB# pin of FDC.
ERR#
34
PRINTER MODE: ERR#
An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
EXTENSION FDD MODE: HEAD2#
OD12
OD12
This pin is for Extension FDD B; its function is the same as the
HEAD#pin of FDC.
EXTENSION 2FDD MODE: HEAD2#
This pin is for Extension FDD A and B; its function is the same as
the HEAD# pin of FDC.
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Revision 1.1
W83977EF
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PIN
I/O
FUNCTION
SLIN#
32
OD12
PRINTER MODE: SLIN#
Output line for detection of printer selection. This pin is pulled
high internally. Refer to description of the parallel port for
definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE:STEP2#
OD12
This pin is for Extension FDD B; its function is the same as the
STEP# pin of FDC.
EXTENSION 2FDD MODE: STEP2#
OD12
OD12
This pin is for Extension FDD A and B; its function is the same as
the STEP# pin of FDC.
INIT#
33
PRINTER MODE: INIT#
Output line for the printer initialization. This pin is pulled high
internally. Refer to description of the parallel port for definition of
this pin in ECP and EPP mode.
EXTENSION FDD MODE: DIR2#
OD12
This pin is for Extension FDD B; its function is the same as the
DIR# pin of FDC.
EXTENSION 2FDD MODE: DIR2#
OD12
OD12
This pin is for Extension FDD A and B; its function is the same as
the DIR# pin of FDC.
AFD#
35
PRINTER MODE: AFD#
An active low output from this pin causes the printer to auto feed
a line after a line is printed. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
EXTENSION FDD MODE: DRVDEN0
OD12
OD12
This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.
EXTENSION 2FDD MODE: DRVDEN0
This pin is for Extension FDD A and B; its function is the same as
the DRVDEN0 pin of FDC.
Publication Release Date: April 2003
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Revision 1.1
W83977EF
1.5 Multi-Mode Parallel Port, continued
SYMBOL
STB#
PIN
36
I/O
OD12
FUNCTION
PRINTER MODE: STB#
An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to description of
the parallel port for definition of this pin in ECP and EPP mode.
-
-
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
PRINTER MODE: PD0
31
30
29
I/O24t
PD0
PD1
PD2
Parallel port data bus bit 0. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
INt
INt
EXTENSION FDD MODE: INDEX2#
This pin is for Extension FDD B; the function of this pin is the
same as the INDEX# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: INDEX2#
This pin is for Extension FDD A and B; the function of this pin is
the same as the INDEX# pin of FDC. It is pulled high internally.
I/O24t
INt
PRINTER MODE: PD1
Parallel port data bus bit 1. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: TRAK02#
This pin is for Extension FDD B; the function of this pin is the
same as the TRAK0# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: TRAK02#
INt
This pin is for Extension FDD A and B; the function of this pin is
the same as the TRAK0# pin of FDC. It is pulled high internally.
I/O24t
PRINTER MODE: PD2
Parallel port data bus bit 2. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
INt
INt
EXTENSION FDD MODE: WP2#
This pin is for Extension FDD B; the function of this pin is the
same as the WP# pin of FDC. It is pulled high internally.
EXTENSION. 2FDD MODE: WP2#
This pin is for Extension FDD A and B; the function of this pin is
the same as the WP# pin of FDC. It is pulled high internally.
Publication Release Date: April 2003
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Revision 1.1
W83977EF
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PD3
PIN
28
I/O
I/O24t
FUNCTION
PRINTER MODE: PD3
Parallel port data bus bit 3. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
INt
INt
EXTENSION FDD MODE: RDATA2#
This pin is for Extension FDD B; the function of this pin is the
same as the RDATA# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: RDATA2#
This pin is for Extension FDD A and B; this function of this pin is
the same as the RDATA# pin of FDC. It is pulled high internally.
27
I/O24t
INt
PRINTER MODE: PD4
PD4
Parallel port data bus bit 4. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DSKCHG2#
This pin is for Extension FDD B; the function of this pin is the
same as the DSKCHG# pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: DSKCHG2#
INt
This pin is for Extension FDD A and B; this function of this pin is
the same as the DSKCHG# pin of FDC. It is pulled high internally.
26
24
I/O24t
PRINTER MODE: PD5
PD5
PD6
Parallel port data bus bit 5. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
-
-
I/O24t
PRINTER MODE: PD6
Parallel port data bus bit 6. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION. 2FDD MODE: MOA2#
OD24
This pin is for Extension FDD A; its function is the same as the
MOA# pin of FDC.
Publication Release Date: April 2003
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Revision 1.1
W83977EF
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PD7
PIN
23
I/O
I/O24t
FUNCTION
PRINTER MODE: PD7
Parallel port data bus bit 7. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: DSA2#
-
OD24
This pin is for Extension FDD A; its function is the same as the
DSA# pin of FDC.
1.6 FDC Interface
SYMBOL
DRVDEN0
DRVDEN1
GP10
(IRQIN1)
P12
PIN
2
3
I/O
FUNCTION
OD24
OD24
IO24t
Drive Density Select bit 0.
Drive Density Select bit 1. (CR2A bit 1_0 = 00, default)
General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01)
Alternate Function from GP10: Interrupt channel input.
KBC P12 I/O port. (CR2A bit 1_0 = 10)
IO24t
SCI#
OUT12t System Control Interrupt (CR2A bit 1_0 = 11)
HEAD#
5
OD24
Head select. This open drain output determines which disk drive
head is active.
Logic 1 = side 0
Logic 0 = side 1
WE#
WD#
9
10
OD24
OD24
Write enable. An open drain output.
Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.
STEP#
DIR#
11
12
OD24
OD24
Step output pulses. This active low open drain output produces
a pulse to move the head to another track.
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
MOB#
13
OD24
Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.
Publication Release Date: April 2003
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Revision 1.1
W83977EF
1.6 FDC Interface, continued
SYMBOL
DSA#
PIN
14
I/O
OD24
FUNCTION
Drive Select A. When set to 0, this pin enables disk drive A.
This is an open drain output.
DSB#
15
16
4
OD24
OD24
INcs
Drive Select B. When set to 0, this pin enables disk drive B.
This is an open drain output.
Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.
Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by a 1 KΩ resistor. The resistor can be disabled by bit
7 of L0-CRF0 (FIPURDWN).
MOA#
DSKCHG#
RDATA#
WP#
6
7
INcs
INcs
The read data input signal from the FDD. This input pin is pulled
up internally by a 1 KΩ resistor. The resistor can be disabled by
bit 7 of L0-CRF0 (FIPURDWN).
Write protected. This active low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
pulled up internally by a 1 KΩ resistor. The resistor can be
disabled by bit 7 of L0-CRF0 (FIPURDWN).
TRAK0#
INDEX#
8
INcs
INcs
Track 0. This Schmitt-triggered input from the disk drive is active
low when the head is positioned over the outermost track. This
input pin is pulled up internally by a 1 KΩ resistor. The resistor
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
This Schmitt-triggered input from the disk drive is active low
when the head is positioned over the beginning of a track marked
by an index hole. This input pin is pulled up internally by a 1 KΩ
resistor. The resistor can be disabled by bit 7 of L0-CRF0
(FIPURDWN).
17
Publication Release Date: April 2003
-17 -
Revision 1.1
W83977EF
1.7 KBC Interface
SYMBOL
KDATA
MDATA
KCLK
MCLK
GA20
PIN
59
60
67
68
56
I/O
FUNCTION
I/O16u
I/O16u
I/O16u
I/O16u
I/O12t
I/O12t
Keyboard Data
PS2 Mouse Data
Keyboard Clock
PS2 Mouse Clock
KBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default)
General purpose I/O port 1 bit 1. (CR2A bit 6 = 1)
Alternate Function from GP11: Interrupt channel input.
W83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default)
General purpose I/O port 1 bit 2. (CR2A bit 7 = 1)
Alternate Function 1 from GP12 : Watchdog timer output.
W83C45 KINH (P17) Input. (CR2B bit 0 = 0, default)
General purpose I/O port 1 bit 3. (CR2B bit 0 = 1)
GP11
(IRQIN2)
KBRST
GP12
(WDTO)
KBLOCK
GP13
57
58
I/O12t
I/O12t
INts
I/O16t
1.8 POWER PINS
SYMBOL
PIN
FUNCTION
VCC
20, 55, 85,
+5V power supply for the digital circuitry
115
VSB
GND
71
+5V stand-by power supply for the digital circuitry
Ground
25, 62, 90,
120
1.9 ACPI Interface
SYMBOL
VBAT
XTAL1
XTAL2
PIN
64
63
I/O
NA
INC
O8t
FUNCTION
battery voltage input
32.768Khz Clock Input
61
32.768Khz Clock Output
Publication Release Date: April 2003
-18 -
Revision 1.1
W83977EF
2.0 FDC FUNCTIONAL DESCRIPTION
2.1 W83977EF FDC
The floppy disk controller of the W83977EF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to 2 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
2.1.1 AT interface
The interface consists of the standard asynchronous signals:RD#, WR#, A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following
formula:
THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS = DELAY
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 × 16 µS - 1.5 µS = 14.5 µS
2 × 16 µS - 1.5 µS = 30.5 µS
8 × 16 µS - 1.5 µS = 6.5 µS
15 × 16 µS - 1.5 µS = 238.5 µS
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 × 8 µS - 1.5 µS = 6.5 µS
2 × 8 µS - 1.5 µS = 14.5 µS
8 × 8 µS - 1.5 µS = 62.5 µS
15 × 8 µS - 1.5 µS = 118.5 µS
Publication Release Date: April 2003
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Revision 1.1
W83977EF
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the
DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only onDACK#. This mode is only available when the FDC has been configured
into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.
¡
2.1.3 Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is provided with a clock which is synchronized to the
read data. The synchronized clock, called the Data Window, is used to internally sample the serial
data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel
conversion logic separates the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on
speed. A digital integrator is used to keep track of the speed changes in the input data stream.
2.1.4 Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.
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2.1.5 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented
vertically. This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
2.1.6 FDC Core
The W83977EF FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information is provided to
the microprocessor.
2.1.7 FDC Commands
Command Symbol Descriptions:
C:
D:
Cylinder number 0 - 256
Data Pattern
DIR:
Step Direction
DIR = 0, step out
DIR = 1, step in
Disk Drive Select 0
Disk Drive Select 1
Data Length
DS0:
DS1:
DTL:
EC:
Enable Count
EOT:
End of Track
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EFIFO:
EIS:
Enable FIFO
Enable Implied Seek
End of track
FIFO Threshold
Gap length selection
Gap Length
EOT:
FIFOTHR:
GAP:
GPL:
H:
Head number
HDS:
HLT:
HUT:
LOCK:
MFM:
MT:
Head number select
Head Load Time
Head Unload Time
Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM or FM Mode
Multitrack
N:
NCN:
ND:
The number of data bytes written in a sector
New Cylinder Number
Non-DMA Mode
OW:
Overwritten
PCN:
POLL:
PRETRK:
R:
Present Cylinder Number
Polling Disable
Precompensation Start Track Number
Record
RCN:
R/W:
SC:
Relative Cylinder Number
Read/Write
Sector/per cylinder
SK:
Skip deleted data address mark
Step Rate Time
Status Register 0
Status Register 1
Status Register 2
SRT:
ST0:
ST1:
ST2:
ST3:
WG:
Status Register 3
Write gate alters timing of WE
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(1) Read Data
PHASE
Command
R/W
W
W
D7
D6 D5 D4
D3
0
0
D2 D1 D0
REMARKS
Command codes
MT MFM SK
0
0
0
1
1
0
0
0
HDS DS1 DS0
W
W
W
W
W
W
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
Execution
Result
Data transfer between the
FDD and system
Status information after
command execution
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
R
R
R
R
Sector ID information after
command execution
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(2) Read Deleted Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM SK
0
0
1
0
1
0
0
Command codes
W
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
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(3) Read A Track
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
W
W
W
W
W
W
W
0
0
MFM
0
0
0
0
0
0
0
0
1
0
Command codes
HDS DS1 DS0
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
Execution
Result
Data transfer between the
FDD and system; FDD
reads contents of all
cylinders from index hole to
EOT
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
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(4) Read ID
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
0
0
MFM
0
0
0
0
0
1
0
0
1
0
HDS DS1 DS0
Execution
Result
The first correct ID
information on the cylinder
is stored in Data Register
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
Disk status after the
command has been
completed
R
R
R
(5) Verify
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
MT MFM SK
EC
1
0
0
0
1
1
0
0
0
HDS DS1 DS0
W
W
W
W
W
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL/SC -------------------
Sector ID information prior
to command execution
Execution
Result
No data transfer takes
place
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
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(6) Version
PHASE
Command
Result
R/W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command code
Enhanced controller
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
(7) Write Data
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
MT MFM
0
0
0
0
0
0
1
0
1
0
0
HDS DS1 DS0
W
W
W
W
W
W
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to Command execution
Execution
Result
Data transfer between the
FDD and system
Status information after
Command execution
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Sector ID information after
Command execution
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(8) Write Deleted Data
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
MT MFM
0
0
0
0
1
0
0
1
0
0
0
HDS DS1 DS0
W
W
W
W
W
W
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
Execution
Result
Data transfer between the
FDD and system
Status information after
command execution
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Sector ID information after
command execution
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(9) Format A Track
PHASE
Command
R/W
W
W
W
W
W
W
W
W
W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
0
0
MFM
0
0
0
0
0
1
0
1
0
1
HDS DS1 DS0
---------------------- N ------------------------
--------------------- SC -----------------------
--------------------- GPL ---------------------
---------------------- D ------------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
Bytes/Sector
Sectors/Cylinder
Gap 3
Filler Byte
Input Sector Parameters
Execution
for Each
Sector
Repeat:
Result
Status information after
command execution
R
R
R
R
R
R
(10) Recalibrate
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
0
0
0
0
0
0
0
0
0
0
1
0
1
1
Command codes
DS1 DS0
Execution
Head retracted to Track 0
Interrupt
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(11) Sense Interrupt Status
PHASE
Command
Result
R/W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command code
Status information at the end
of each seek operation
0
0
0
0
1
0
0
0
---------------- ST0 -------------------------
---------------- PCN -------------------------
R
(12) Specify
PHASE
Command
R/W
W
D7
0
D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
0
0
0
0
0
1
1
W
W
| ---------SRT ----------- | --------- HUT ---------- |
|------------ HLT ----------------------------------| ND
(13) Seek
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
0
0
0
0
0
0
0
0
1
0
1
1
1
HDS DS1 DS0
W
-------------------- NCN -----------------------
Execution
R
Head positioned over proper
cylinder on diskette
(14) Configure
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Configure information
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
W
0
EIS EFIFO POLL | ------ FIFOTHR ----|
W
| --------------------PRETRK ----------------------- |
Execution
Internal registers written
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(15) Relative Seek
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
1
0
DIR
0
0
0
0
0
1
0
1
1
1
HDS DS1 DS0
W
| -------------------- RCN ---------------------------- |
(16) Dumpreg
PHASE
Command
Result
R/W
W
R
R
R
R
R
R
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Registers placed in FIFO
0
0
0
0
1
1
1
0
----------------------- PCN-Drive 0--------------------
----------------------- PCN-Drive 1 -------------------
----------------------- PCN-Drive 2--------------------
----------------------- PCN-Drive 3 -------------------
--------SRT ------------------ | --------- HUT --------
----------- HLT -----------------------------------| ND
------------------------ SC/EOT ----------------------
LOCK 0 D3 D2 D1 D0 GAP WG
0 EIS EFIFO POLL | ------ FIFOTHR --------
-----------------------PRETRK -------------------------
R
R
R
(17) Perpendicular Mode
PHASE
Command
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command Code
0
0
0
1
0
0
1
0
W
OW
0
D3
D2 D1 D0 GAP WG
(18) Lock
PHASE
Command
Result
R/W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command Code
LOCK 0
0
0
1
0
0
1
0
0
0
0
0
0
LOCK
0
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(19) Sense Drive Status
PHASE
Command
R/W
W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command Code
0
0
0
0
0
0
0
0
0
0
1
0
0
HDS DS1 DS0
Result
R
---------------- ST3 -------------------------
Status information about
disk drive
(20) Invalid
PHASE
Command
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Invalid codes (no
operation- FDC goes to
standby state)
------------- Invalid Codes -----------------
Result
R
-------------------- ST0 ----------------------
ST0 = 80H
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2.2 Register Descriptions
There are several status, data, and control registers in W83977EF. These registers are defined below:
ADDRESS
OFFSET
REGISTER
READ
WRITE
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
SA REGISTER
SB REGISTER
DO REGISTER
TD REGISTER
TD REGISTER
MS REGISTER
DT (FIFO) REGISTER
DI REGISTER
DR REGISTER
DT (FIFO) REGISTER
CC REGISTER
2.2.1 Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR
WP#
INDEX#
HEAD
TRAK0#
STEP
DRV2#
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2# (Bit 6):
0
1
A second drive has been installed
A second drive has not been installed
STEP (Bit 5):
This bit indicates the complement of STEP# output.
TRAK0#(Bit 4):
This bit indicates the value of TRAK0# input.
HEAD (Bit 3):
This bit indicates the complement of HEAD# output.
0
side 0
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1
side 1
INDEX#(Bit 2):
This bit indicates the value of INDEX# output.
WP#(Bit 1):
0
1
disk is write-protected
disk is not write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
1
outward direction
inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR#
WP
INDEX
HEAD#
TRAK0
STEP F/F
DRQ
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRQ (Bit 6):
This bit indicates the value of DRQ output pin.
STEP F/F (Bit 5):
This bit indicates the complement of latched STEP# output.
TRAK0 (Bit 4):
This bit indicates the complement of TRAK0# input.
HEAD# (Bit 3):
This bit indicates the value of HEAD# output.
0
1
side 1
side 0
INDEX (Bit 2):
This bit indicates the complement of INDEX# output.
WP (Bit 1):
0
disk is not write-protected
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1
disk is write-protected
DIR#(Bit 0)
This bit indicates the direction of head movement.
0
1
inward direction
outward direction
2.2.2 Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
1
1
MOT EN A
MOT EN B
WE
RDATA Toggle
WDATA Toggle
Drive SEL0
Drive SEL0 (Bit 5):
This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).
WDATA Toggle (Bit 4):
This bit changes state at every rising edge of the WD# output pin.
RDATA Toggle (Bit 3):
This bit changes state at every rising edge of the RDATA# output pin.
WE (Bit 2):
This bit indicates the complement of the WE# output pin.
MOT EN B (Bit 1)
This bit indicates the complement of the MOB# output pin.
MOT EN A (Bit 0)
This bit indicates the complement of the MOA# output pin.
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
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2
1
7
6
5
4
3
0
DSC#
DSD#
WE F/F
RDATA F/F
WD F/F
DSA#
DSB#
DRV2#
DRV2# (Bit 7):
0
1
A second drive has been installed
A second drive has not been installed
DSB# (Bit 6):
This bit indicates the status of DSB# output pin.
DSA# (Bit 5):
This bit indicates the status of DSA# output pin.
WD F/F(Bit 4):
This bit indicates the complement of the latched WD# output pin at every rising edge of the WD#
output pin.
RDATA F/F(Bit 3):
This bit indicates the complement of the latched RDATA# output pin .
WE F/F (Bit 2):
This bit indicates the complement of latched WE# output pin.
DSD# (Bit 1):
0
1
Drive D has been selected
Drive D has not been selected
DSC# (Bit 0):
0
1
Drive C has been selected
Drive C has not been selected
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2.2.3 Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ
enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are
as follows:
7
6
3
1-0
5
4
2
Drive Select: 00 select drive A
01 select drive B
10 select drive C
11 select drive D
Floppy Disk Controller Reset
Active low resets FDC
DMA and INT Enable
Active high enable DRQ/IRQ
Motor Enable A. Motor A on when active high
Motor Enable B. Motor B on when active high
Motor Enable C. Motor C on when active high
Motor Enable D. Motor D on when active high
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information of the
floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are
as follows:
2
1
7
6
5
4
3
0
X
X
X
X
X
X
Tape sel 0
Tape sel 1
If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:
2
1
7
6
5
4
3
0
Tape Sel 0
Tape Sel 1
Floppy boot drive 0
Floppy boot drive 1
Drive type ID0
Drive type ID1
Media ID0
Media ID1
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Media ID1 Media ID0 (Bit 7, 6):
These two bits are read only. These two bits reflect the value of CR8 bit 3, 2.
Drive type ID1 Drive type ID0 (Bit 5, 4):
These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive
selected in the DO REGISTER.
Floppy Boot drive 1, 0 (Bit 3, 2):
These two bits reflect the value of CR8 bit 1, 0.
Tape Sel 1, Tape Sel 0 (Bit 1, 0):
These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved as the floppy disk boot drive.
TAPE SEL 1
TAPE SEL 0
DRIVE SELECTED
0
0
1
1
0
1
0
1
None
1
2
3
2.2.5 Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
6
0
7
5
4
3
2
1
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.
FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.
FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
2.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of
the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and
not by the DR REGISTER. The real data rate is determined by the most recent write to either of the
DR REGISTER or CC REGISTER.
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1
7
6
5
0
4
3
2
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
1
FDC in normal mode
FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
PRECOMP
PRECOMPENSATION DELAY
2
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
250K - 1 Mbps
Default Delays
41.67 nS
2 Mbps Tape drive
Default Delays
20.8 nS
0
0
0
0
1
1
1
1
83.34 nS
41.17 nS
125.00 nS
62.5nS
166.67 nS
83.3 nS
208.33 nS
104.2 nS
250.00 nS
125.00 nS
0.00 nS (disabled)
0.00 nS (disabled)
DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
DEFAULT PRECOMPENSATION DELAYS
125 nS
125 nS
125 nS
41.67nS
20.8 nS
2 MB/S
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DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
00 500 KB/S (MFM), 250 KB/S (FM), RWC#= 1
01 300 KB/S (MFM), 150 KB/S (FM), RWC#= 0
10 250 KB/S (MFM), 125 KB/S (FM), RWC#= 0
11 1 MB/S (MFM), Illegal (FM), RWC#= 1
The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits
in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for
individual data rates setting.
2.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the
data bus at a time. This register stores data, commands, and parameters and provides diskette-drive
status information. Data bytes are passed through the data register to program or obtain results after
a command. In the W83977EF, this register defaults to FIFO disabled mode after reset. The FIFO can
change its value and enable its operation through the CONFIGURE command.
Status Register 0 (ST0)
7-6
5
3
2
1-0
4
US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command executio
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Status Register 1 (ST1)
7
6
5
4
3
2
1
0
Missing Address Mark. 1 When the FDC cannot detect the data address mark
or the data address mark has been deleted.
NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during
execution of write data.
ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data.
Not used. This bit is always 0.
OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.
DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.
Not used. This bit is always 0.
EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7
1
0
4
3
2
6
5
MD (Missing Address Mark in Data Field).
1 If the FDC cannot find a data address mark
(or the address mark has been deleted)
when reading data from the media
0 No error
BC (Bad Cylinder)
1 Bad Cylinder
0 No error
SN (Scan Not satisfied)
1 During execution of the Scan command
0 No error
SH (Scan Equal Hit)
1 During execution of the Scan command, if the equal condition is satisfied
0 No error
WC (Wrong Cylinder)
1 Indicates wrong Cylinder
DD (Data error in the Data field)
1 If the FDC detects a CRC error in the data field
0 No error
CM (Control Mark)
1 During execution of the read data or scan command
0 No error
Not used. This bit is always 0
Status Register 3 (ST3)
6
4
2
1
0
7
5
3
US0 Unit Select 0
US1 Unit Select 1
HD Head Address
TS Two-Side
TO Track 0
RY Ready
WP Write Protected
FT Fault
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2.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT
only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement
ofDSKCHG#, while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7
6
5
4
3
2
1
0
x x x
x x x
x
Reserved for the hard disk controller
x
During a read of this register, these bits are in tri-stat
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
7
6
1
5
4
3
1
2
0
1
1
1
HIGH DENS#
DRATE0
DRATE1
DSKCHG
DSKCHG (Bit 7):
This bit indicates the complement of the DSKCHG# input.
Bit 6-3: These bits are always a logic 1 during a read.
DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings
corresponding to the individual data rates.
HIGHDENS#(Bit 0):
0
1
500 KB/S or 1 MB/S data rate (high density FDD)
250 KB/S or 300 KB/S data rate
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In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
0
5
0
4
3
2
0
1
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG#
DSKCHG (Bit 7):
This bit indicates the status of DSKCHG# input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
4
2
3
1
6
5
7
0
x
x
x
x
x
x
DRATE0
DRATE1
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
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2
1
7
6
5
4
3
0
X
X
X
X
X
DRATE0
DRATE1
NOPREC
X: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
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3.0 UART PORT
3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-
bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-
byte FIFOs for both receive and transmit mode.
3.2 Register Address
3.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
5
4
2
6
7
3
0
1
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
format) from the divisor latches of the baudrate generator during a read or write operation.
When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the
Interrupt Control Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
TABLE 3-1 UART Register Bit Map
Bit Number
Register Address Base
0
1
2
3
4
5
6
7
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+ 0
BDLAB = 0
Receiver
Buffer
RBR
TBR
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data
Bit 5
RX Data
Bit 6
RX Data
Bit 7
Register
(Read Only)
+ 0
BDLAB = 0
Transmitter
Buffer Register
(Write Only)
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
+ 1
BDLAB = 0
Interrupt Control ICR
Register
RBR Data
Ready
TBR
Empty
USR
HSR
0
0
0
0
Interrupt
Enable
Interrupt
Enable
Interrupt
Enable
Interrupt
Enable
(ETBREI)
(EUSRI)
(EHSRI)
(ERDRI)
+ 2
+ 2
Interrupt Status
Register
ISR
"0" if
Interrupt
Interrupt
Status
Bit (1)
Interrupt
Status
Bit (2)**
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
Interrupt
Pending
Status
(Read Only)
Bit (0)
UART FIFO
Control
UFR
FIFO
RCVR
FIFO
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
Reversed
RX
RX
Enable
Interrupt
Interrupt
Register
Reset
Active Level Active Level
(Write Only)
(LSB)
(MSB)
+ 3
UART Control
Register
UCR
Data
Length
Select
Bit 0
Data
Length
Select
Bit 1
Multiple
Stop Bits
Enable
Parity
Bit
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Baudrate
Divisor
Silence
Enable
Enable
Latch
Access Bit
(BDLAB)
(MSBE)
(PBE)
(EPE)
PBFE)
(SSE)
0
(DLS0)
(DLS1)
+ 4
+ 5
Handshake
Control
HCR
USR
HSR
Data
Terminal
Ready
(DTR)
Request
to
Loopback
RI
IRQ
Internal
Loopback
Enable
0
0
Enable
Register
Send
Input
(RTS)
UART Status
Register
RBR Data
Overrun
Error
(OER)
Parity Bit
Error
(PBER)
No Stop
Bit
Silent
Byte
TBR
TSR
RX FIFO
Error
Ready
Empty
Empty
Error
Detected
(SBD)
Indication
(RFEI) **
(RDR)
(TBRE)
(TSRE)
(NSER)
+ 6
+ 7
Handshake
CTS
DSR
RI Falling
Edge
(FERI)
DCD
Clear
Data Set
Ready
(DSR)
Ring
Data Carrier
Status Register
Toggling
Toggling
Toggling
to Send
Indicator
Detect
(DCD)
(TCTS)
Bit 0
(TDSR)
Bit 1
(TDCD)
Bit 3
(CTS)
Bit 4
(RI)
Bit 6
User Defined
Register
Baudrate
Divisor Latch
Low
Baudrate
Divisor Latch
High
UDR
BLL
Bit 2
Bit 5
Bit 7
+ 0
BDLAB = 1
Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+ 1
BDLAB = 1
BHL
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit
3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
TABLE 3-2 WORD LENGTH DEFINITION
DLS1
DLS0
DATA LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
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3.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
2
7
6
4
3
1
0
5
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1
when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In
16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in
the FIFO.
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
thanthese two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set
to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to
write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is
empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to
a logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
3.2.3 Handshake Control Register (HCR) (Read/Write)
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This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
2
7
0
5
0
4
3
1
0
6
0
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the
TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
(bit 0 of HCR) →DSR#, RTS ( bit 1 of HCR) →CTS#, Loopback RI input ( bit 2 of HCR) →
RI#and IRQ enable ( bit 3 of HCR) →DCD#.
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
bit is internally connected to the modem control input DCD#.
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
connected to the modem control input RI#.
Bit 1: This bit controls the RTS# output. The value of this bit is inverted and output to RTS#.
Bit 0: This bit controls the DTR# output. The value of this bit is inverted and output to DTR#.
3.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
7
6
5
4
3
2
1
0
toggling (TCTS)
toggling (TDSR)
CTS#
DSR#
RI falling edge (FERI)
toggling (TDCD)
DCD#
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD# input. This bit is equivalent to bit 3 of HCR in loopback
mode.
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Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback
mode.
Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback
mode.
Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback
mode.
Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high state after HSR was
read by the CPU.
Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read.
3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
2
1
7
6
5
4
3
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
TABLE 3-3 FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
1
1
0
1
0
1
01
04
08
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
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Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
other bits of UFR are programmed.
3.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
7
6
5
0
4
3
2
1
0
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
out interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
TABLE 3-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit
3
Bit Bit Bit Interrupt
Interrupt Type
-
Interrupt Source
Clear Interrupt
2
1
0
priority
0
0
0
1
0
1
1
0
-
No Interrupt pending
-
First
UART Receive
Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
Read USR
0
1
1
1
0
0
0
0
Second
Second
RBR Data Ready
1. RBR data ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
FIFO Data Timeout
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
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0
0
0
0
1
0
0
0
Third
TBR Empty
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
3.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
5
0
3
6
0
4
0
2
0
7
0
1
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
16
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table in the next page illustrates the use of the baud generator with a frequency of
1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud
generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed
mode, the data transmission rate can be as high as 1.5M bps.
3.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
TABLE 3-5 BAUD RATE TABLE
BAUD RATE FROM DIFFERENT PRE-DIVIDER
Pre-Div: 13
1.8461M Hz
Pre-Div:1.625 Pre-Div: 1.0
14.769M Hz 24M Hz
Decimal divisor used
to generate 16X
clock
Error Percentage between
desired and actual
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50
75
110
134.5
150
300
400
600
880
1076
1200
2400
4800
9600
14400
16000
19200
28800
38400
57600
76800
153600
307200
460800
921600
650
975
1430
1478.5
1950
3900
**
**
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
0.18%
0.099%
**
**
**
**
**
600
7800
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
15600
23400
26000
31200
46800
62400
93600
124800
249600
499200
748800
1497600
0.53%
**
**
**
**
**
**
**
**
**
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
Note. Pre-Divisor is determined by CRF0 of UART A and B.
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4.0 INFRARED (IR) PORTS
4.1 IR PORT
The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication
which can operate under various transmission protocols including IrDA 1.0 SIR, SHARP ASK-IR. IR
port shares the same port with UART B port in W83977EF. Please refer to section 11.5 for
configuration information.
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5.0 PARALLEL PORT
5.1 Printer Interface Logic
The parallel port of the W83977EF makes possible the attachment of various devices that accept eight
bits of parallel data at standard TTL level. The W83977EF supports an IBM XT/AT compatible parallel
port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities
Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the
parallel port. Refer to the configuration registers for more information on disabling, power-down, and
on selecting the mode of operation.
Table 5-1 shows the pin definitions for different modes of the parallel port.
TABLE 5-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
PIN NUMBER
HOST
PIN
OF W83977EF
SPP
EPP
ECP
CONNECTOR
ATTRIBUTE
2
1
36
O
I/O
I
I
I
I
O
I
O
O
nSTB
PD<0:7>
nACK
BUSY
PE
SLCT
nAFD
nERR
nINIT
nSLIN
nWrite
PD<0:7>
Intr
nWait
PE
Select
nDStrb
nError
nInit
nSTB, HostClk
2-9
10
11
12
13
14
15
16
17
31-26, 24-23
PD<0:7>
2
22
21
19
18
35
34
33
32
nACK, PeriphClk
2
BUSY, PeriphAck
2
PEerror, nAckReverse
2
SLCT, Xflag
2
nAFD, HostAck
1
2
nFault , nPeriphRequest
nINIT , nReverseRqst
nSLIN , ECPMode
1
2
1
2
nAStrb
Notes:
n<name > : Active Low
1. Compatible Mode
2. High Speed Mode
3. For more information, refer to the IEEE 1284 standard.
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TABLE 5-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
HOST
PIN NUMBER OF
W83977EF
PIN
SPP
PIN
EXT2FDD
PIN
EXTFDD
CONNECTOR
ATTRIBUTE
ATTRIBUTE
ATTRIBUTE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
36
31
30
29
28
27
26
24
23
22
21
19
18
35
34
33
32
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
O
I
O
O
nSTB
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
nACK
BUSY
PE
SLCT
nAFD
nERR
nINIT
nSLIN
---
I
I
I
I
---
INDEX2#
TRAK02#
WP2#
RDATA2#
DSKCHG2#
---
MOA2#
DSA2#
DSB2#
MOB2#
WD2#
---
I
I
I
I
---
INDEX2#
TRAK02#
WP2#
RDATA2#
DSKCHG2#
---
---
---
DSB2#
MOB2#
WD2#
I
I
---
OD
OD
OD
OD
OD
OD
OD
OD
OD
OD
---
---
---
OD
OD
OD
OD
OD
OD
OD
OD
WE2#
WE2#
RWC2#
HEAD2#
DIR2#
RWC2#
HEAD2#
DIR2#
STEP2#
STEP2#
5.2 Enhanced Parallel Port (EPP)
TABLE 5-2 PRINTER MODE AND EPP REGISTER ADDRESS
A2
0
0
0
0
0
1
1
1
A1
0
0
1
1
1
0
0
1
A0
0
1
0
0
1
0
1
0
REGISTER
NOTE
Data port (R/W)
1
1
1
1
2
2
2
2
2
Printer status buffer (Read)
Printer control latch (Write)
Printer control swapper (Read)
EPP address port (R/W)
EPP data port 0 (R/W)
EPP data port 1 (R/W)
EPP data port 2 (R/W)
1
1
1
EPP data port 2 (R/W)
Notes:
1. These registers are available in all modes.
2. These registers are available only in EPP mode.
5.2.1
Data Swapper
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The system microprocessor can read the contents of the printer's data latch by reading the data
swapper.
5.2.2
Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the printer status
buffer. The bit definitions are as follows:
7
6
5
4
3
2
1
1
1
0
TMOUT
ERROR#
SLCT
PE
ACK#
BUSY#
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print
head is changing position, or during an error state. When this signal is active, the printer is busy
and cannot accept data.
Bit 6: This bit represents the current state of the printer's ACK# signal. A 0 means the printer has
received a character and is ready to accept another. Normally, this signal will be active for
approximately 5 microseconds before BUSY# stops.
Bit 5: Logical 1 means the printer has detected the end of paper.
Bit 4: Logical 1 means the printer is selected.
Bit 3: Logical 0 means the printer has encountered an error condition.
Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.
Bit 0: This bit is valid in EPP mode only. It indicates that a 10 µS time-out has occurred on the EPP
bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error
has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0
has no effect.
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5.2.3
Printer Control Latch and Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the printer
control swapper. Bit definitions are as follows:
7
1
6
1
5
4
3
2
1
0
STROBE
AUTO FD
INIT#
SLCT IN
IRQ ENABLE
DIR
Bit 7, 6: These two bits are a logic one during a read. They can be written.
Bit 5: Direction control bit
When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the
parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is
invalid and fixed at zero.
Bit 4: A 1 in this position allows an interrupt to occur when ACK# changes from low to high.
Bit 3: A 1 in this bit position selects the printer.
Bit 2: A 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A 1 causes the printer to line-feed after a line is printed.
Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microseconds before and after the strobe pulse.
5.2.4
EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
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The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
5.2.5
EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
5.2.6
Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
3
2
PD2
1
1
PD1
0
PD0
Data Port (R/W)
PD7
PD6
PD5
PE
PD4
SLCT
IRQEN
IRQ
PD3
Status Buffer (Read)
Control Swapper (Read)
Control Latch (Write)
EPP Address Port R/W)
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
BUSY# ACK#
ERROR#
SLIN
SLIN
PD3
1
TMOUT
STROBE#
STROBE#
PD0
1
1
1
INIT#
INIT#
PD2
PD2
PD2
PD2
PD2
AUTOFD#
AUTOFD#
PD1
1
1
DIR
PD5
PD5
PD5
PD5
PD5
PD7
PD7
PD7
PD7
PD7
PD6
PD6
PD6
PD6
PD6
PD4
PD4
PD4
PD4
PD4
PD3
PD1
PD0
PD3
PD1
PD0
PD3
PD1
PD0
PD3
PD1
PD0
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5.2.7
EPP Pin Descriptions
EPP NAME
TYPE
EPP DESCRIPTION
nWrite
PD<0:7>
Intr
O
I/O
I
Denotes an address or data read or write operation.
Bi-directional EPP address and data bus.
Used by peripheral device to interrupt the host.
nWait
I
Inactive to acknowledge that data transfer is completed. Active to indicate
that the device is ready for the next transfer.
PE
I
I
O
I
Paper end; same as SPP mode.
Select
nDStrb
nError
nInits
Printer selected status; same as SPP mode.
This signal is active low. It denotes a data read or write operation.
Error; same as SPP mode.
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
O
nAStrb
O
This signal is active low. It denotes an address read or write operation.
5.2.8
EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP
Control Port and the direction is controlled by DIR of the Control Port.
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 µS have
elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is
aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.
5.2.8.1 EPP Operation
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address
Read, and Data Read. All operations on the EPP device are performed asynchronously.
5.2.8.2 EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or
write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally
and will be completed when nWait goes inactive high.
b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active
low, at which time it will start as described above.
5.2.8.3 EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive
high.
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5.3 Extended Capabilities Parallel (ECP) Port
This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel
that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host)
directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the
standard parallel port to improve compatibility mode transfer speed.
The ECP port supports run-length-encoded (RLE) decompression (required) in hardware.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates
how many times the next byte is to be repeated. Hardware support for compression is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA
Interface Standard.
5.3.1
NAME
data
ecpAFifo
dsr
ECP Register and Mode Definitions
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
R/W
R/W
R
R/W
R/W
R/W
R/W
R
ECP MODES
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
000-001
011
All
dcr
All
Control Register
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
010
011
110
111
111
All
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
R/W
R/W
Note: The base addresses are specified by CR60 and 61, which are determined by configuration register or hardware setting.
MODE
000
001
010
011
100
101
110
111
DESCRIPTION
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
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5.3.2
Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports
PD0-PD7 are read and output to the host. The bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this
register is defined only for the forward direction. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Address or RLE
Address/RLE
5.3.3
Device Status Register (DSR)
These bits are at low level during a read of the Printer Status Register. The bits of this status register
are defined as follows:
7
6
5
4
3
2
1
0
1
1
1
nFault
Select
PError
nAck
nBusy
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Bit 7: This bit reflects the complement of the Busy input.
Bit 6: This bit reflects the nAck input.
Bit 5: This bit reflects the PError input.
Bit 4: This bit reflects the Select input.
Bit 3: This bit reflects the nFault input.
Bit 2-0: These three bits are not implemented and are always logic one during a read.
5.3.4
Device Control Register (DCR)
The bit definitions are as follows:
7
1
6
5
4
3
2
1
0
1
strobe
autofd
nInit
SelectIn
ackIntEn
Direction
Bit 6, 7: These two bits are logic one during a read and cannot be written.
Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is
valid in all other modes.
0
1
the parallel port is in output mode.
the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt
requests from the parallel port to the CPU due to a low to high transition on the ACK# input.
Bit 3: This bit is inverted and output to the SLIN# output.
0
1
The printer is not selected.
The printer is selected.
Bit 2: This bit is output to the INIT# output.
Bit 1: This bit is inverted and output to the AFD# output.
Bit 0: This bit is inverted and output to the STB# output.
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5.3.5
CFIFO (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this
FIFO. Transfers to the FIFO are byte aligned.
5.3.6
ECPDFIFO (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to
the system.
5.3.7
TFIFO (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in
the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be
displayed on the parallel port data lines.
5.3.8
CNFGA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
5.3.9
CNFGB (Configuration Register B) Mode = 111
The bit definitions are as follows:
7
6
5
4
3
2
1
1
0
1
1
IRQx 0
IRQx 1
IRQx 2
intrValue
compress
Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support
hardware RLE compression.
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
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Bit 5-3: Reflect the IRQ resource assigned for ECP port.
cnfgB[5:3]
000
IRQ resource
reflect other IRQ resources selected by PnP register (default)
001
IRQ7
010
IRQ9
011
IRQ10
IRQ11
IRQ14
IRQ15
IRQ5
100
101
110
111
Bit 2-0: These five bits are at high level during a read and can be written.
5.3.10
ECR (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7
6
5
4
3
2
1
0
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Bit 7-5: These bits are read/write and select the mode.
000
001
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be used
to tri-state the data lines and reading the data register returns the value on the data
lines and not the value in the data register.
010
011
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
auto transmitted to the peripheral using ECP Protocol. When the direction is 1
(reverse direction), bytes are moved from the ECP parallel port and packed into
bytes in the ecpDFifo.
100
101
110
Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
111
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Bit 4: Read/Write (Valid only in ECP Mode)
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1
0
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
Enables DMA.
0
Disables DMA unconditionally.
Bit 2: Read/Write
1
0
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr
Threshold or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr
Threshold or more valid bytes to be read from the FIFO.
Bit 1: Read only
0
1
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
1
The FIFO contains at least 1 byte of data.
The FIFO is completely empty.
5.3.11
Bit Map of ECP Port Registers
D7
D6
D5
D4
D3
D2
D1
D0
NOTE
PD7
Addr/RLE
nBusy
1
PD6
PD5
PD4
PD3
PD2
PD1
PD0
data
ecpAFifo
dsr
Address or RLE field
2
1
1
2
2
2
nAck
1
PError
Select
nFault
1
1
1
Directio
ackIntEn
SelectIn
nInit
autofd
strobe
dcr
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
0
0
0
1
1
1
0
1
0
1
0
1
0
1
compress
intrValue
MODE
nErrIntrEn
dmaEn
serviceIntr
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
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5.3.12
ECP Pin Descriptions
NAME
TYPE DESCRIPTION
nStrobe (HostClk)
O
The nStrobe registers data or address into the slave on the
asserting edge during write operations. This signal handshakes
with Busy.
PD<7:0>
nAck (PeriphClk)
I/O
I
These signals contains address or data or RLE data.
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
Busy (PeriphAck)
I
This signal deasserts to indicate that the peripheral can accept
data. It indicates whether the data lines contain ECP command
information or data in the reverse direction. When in reverse
direction, normal data are transferred when Busy (PeriphAck) is
high and an 8-bit command is transferred when it is low.
PError (nAckReverse)
I
This signal is used to acknowledge a change in the direction of
the transfer (asserted = forward). The peripheral drives this
signal low to acknowledge nReverseRequest. The host relies
upon nAckReverse to determine when it is permitted to drive
the data bus.
Select (Xflag)
I
Indicates printer on line.
nAutoFd (HostAck)
O
Requests a byte of data from the peripheral when it is asserted.
This signal indicates whether the data lines contain ECP
address or data in the forward direction. When in forward
direction, normal data are transferred when nAutoFd (HostAck)
is high and an 8-bit command is transferred when it is low.
nFault (nPeriphRequest)
I
Generates an error interrupt when it is asserted. This signal is
valid only in the forward direction. The peripheral is permitted
(but not required) to drive this pin low to request a reverse
transfer during ECP Mode.
nInit (nReverseRequest)
nSelectIn (ECPMode)
O
O
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the
channel in the reverse direction.
This signal is always deasserted in ECP mode.
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5.3.13
ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol
before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The
following are required:
(a) Set direction = 0, enabling the drivers.
(b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
(c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
(d) Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo,
respectively.
5.3.13.1 Mode Switching
Software will execute P1284 negotiation and all operations prior to a data transfer phase under
programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake,
moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001
it can only be switched into mode 000 or 001. The direction can be changed only in mode 001.
When in extended forward mode, the software should wait for the FIFO to be empty before switching
back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the
FIFO before changing back to mode 000 or 001.
5.3.13.2 Command/Data
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal
data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low.
The most significant bits of the command indicate whether it is a run-length count (for compression) or
a channel address.
In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
5.3.13.3 Data Compression
The W83977EF supports run length encoded (RLE) decompression in hardware and can transfer
compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported.
In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data
byte is written to the ecpDFifo.
5.3.14
FIFO Operation
The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO
is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is
disabled.
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5.3.15
DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC
DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the
DMA.
5.3.16
Programmed I/O (NON-DMA) Mode
The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo
located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and
serviceIntr = 0 in the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The
programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
5.4
Extension FDD Mode (EXTFDD)
In this mode, the W83977EF changes the printer interface pins to FDC input/output pins, allowing the
user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin
assignments for the FDC input/output pins are shown in Table 5-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOB# and DSB# will be forced to inactive state.
(2) PinsDSKCHG#, RDATA#, WP#, TRAK0#, INDEX# will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
5.5
Extension 2FDD Mode (EXT2FDD)
In this mode, the W83977EF changes the printer interface pins to FDC input/output pins, allowing the
user to install two external floppy disk drives through the DB-25 printer connector to replace internal
floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table5-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOA#, DSA#, MOB#, and DSB# will be forced to inactive state.
(2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, and INDEX# will be logically ORed with pins PD4-PD0
to serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
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6.
KEYBOARD CONTROLLER
The KBC (8042 with licensed KB BIOS) circuit of W83977EF is designed to provide the functions
-
needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM
compatible personal computers or PS/2-based systems. The controller receives serial data from the
keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte
of data in its output buffer. Then, the controller will assert an interrupt to the system when data are
placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data
transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge
is received for the previous data byte.
P24
P25
P21
P20
KIRQ
MIRQ
GATEA20
KBRST
KINH
P17
KDAT
KCLK
P27
P10
P26
8042
T0
GP I/O PINS
Multiplex I/O PINS
MCLK
MDAT
P23
T1
P12~P16
P22
P11
Keyboard and Mouse Interface
6.1 Output Buffer
The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O
address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan
code received from the keyboard and data bytes required by commands to the system. The output
buffer can only be read when the output buffer full bit in the register is "1".
6.2 Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable
I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag
to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written
to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte)
through the controller's input buffer only if the input buffer full bit in the status register is “0”.
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6.3 Status Register
The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O
address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller
and interface. It may be read at any time.
BIT
0
BIT FUNCTION
Output Buffer Full
DESCRIPTION
0: Output buffer empty
1: Output buffer full
1
2
Input Buffer Full
System Flag
0: Input buffer empty
1: Input buffer full
This bit may be set to 0 or 1 by writing to the system flag
bit in the command byte of the keyboard controller. It
defaults to 0 after a power-on reset.
3
4
5
6
7
Command/Data
Inhibit Switch
0: Data byte
1: Command byte
0: Keyboard is inhibited
1: Keyboard is not inhibited
Auxiliary Device Output
Buffer
0: Auxiliary device output buffer empty
1: Auxiliary device output buffer full
General Purpose Time-
0: No time-out error
1: Time-out error
out
Parity Error
0: Odd parity
1: Even parity (error)
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6.4
Commands
COMMAND
20h
FUNCTION
Read Command Byte of Keyboard Controller
Write Command Byte of Keyboard Controller
60h
BIT
BIT DEFINITION
7
6
Reserved
IBM Keyboard Translate Mode
Disable Auxiliary Device
Disable Keyboard
5
4
3
2
1
Reserve
System Flag
Enable Auxiliary Interrupt
Enable Keyboard Interrupt
0
A4h
Test Password
Returns 0Fah if Password is loaded
Returns 0F1h if Password is not loaded
Load Password
A5h
A6h
Load Password until a "0" is received from the system
Enable Password
Enable the checking of keystrokes for a match with the password
Disable Auxiliary Device Interface
Enable Auxiliary Device Interface
Interface Test
A7h
A8h
A9h
BIT
BIT DEFINITION
No Error Detected
00
01
Auxiliary Device "Clock" line is stuck low
Auxiliary Device "Clock" line is stuck high
Auxiliary Device "Data" line is stuck low
02
03
04
Auxiliary Device "Data" line is stuck low
AAh
Self-test
Returns 055h if self test succeeds
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6.4
Commands,CONTINUED
COMMAND
FUNCTION
ABh
Interface Test
BIT DEFINITION
BIT
00
No Error Detected
01
Keyboard "Clock" line is stuck low
02
03
04
Keyboard "Clock" line is stuck high
Keyboard "Data" line is stuck low
Keyboard "Data" line is stuck high
ADh
AEh
C0h
C1h
C2h
D0h
D1h
D2h
D3h
D4h
E0h
FXh
Disable Keyboard Interface
Enable Keyboard Interface
Read Input Port(P1) and send data to the system
Continuously puts the lower four bits of Port1 into STATUS register
Continuously puts the upper four bits of Port1 into STATUS register
Send Port2 value to the system
Only set/reset GateA20 line based on the system data bit 1
Send data back to the system as if it came from Keyboard
Send data back to the system as if it came from Auxiliary Device
Output next received byte of data from system to Auxiliary Device
Reports the status of the test inputs
Pulse only RC(the reset line) low for 6µS if Command byte is even
6.5 Hardware GATEA20/Keyboard Reset Control Logic
The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control
logic is controlled by LD5-CRF0 as follows:
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6.5.1
KB Control Register (Logic Device 5, CR-F0)
BIT
7
6
5
4
3
2
1
0
KCLKS1 KCLKS0 Reserved Reserved Reserved P92EN
HGA20 HKBRST
NAME
KCLKS1, KCLKS0
This 2 bits are for the KBC clock rate selection.
= 0 0
= 0 1
= 1 0
= 1 1
KBC clock input is 6 Mhz
KBC clock input is 8 Mhz
KBC clock input is 12 Mhz
KBC clock input is 16 Mhz
P92EN (Port 92 Enable)
A "1" on this bit enables Port 92 to control GATEA20 and KBRESET.
A "0" on this bit disables Port 92 functions.
HGA20 (Hardware GATE A20)
A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal.
A "0" on this bit disables hardware GATEA20 control logic function.
HKBRST (Hardware Keyboard Reset)
A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal.
A "0" on this bit disables hardware KB RESET control logic function.
When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears
GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears
KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the
KBRESET is pulse low for 6µS(Min.) with 14µS(Min.) delay.
GATEA20 and KBRESET are controlled by either the software control or the hardware control logic
and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when
P92EN bit is set.
6.5.2
Port 92 Control Register (Default Value = 0x24)
BIT
7
6
5
4
3
2
1
0
NAME
Res. (0) Res. (0) Res. (1)
Res. (0)
Res. (0)
Res. (1)
SGA20 PLKBRST
SGA20 (Special GATE A20 Control)
A "1" on this bit drives GATE A20 signal to high.
A "0" on this bit drives GATE A20 signal to low.
PLKBRST (Pull-Low KBRESET)
A "1" on this bit causes KBRESET to drive low for 6µS(Min.) with 14µS(Min.) delay. Before issuing
another keyboard reset command, the bit must be cleared.
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6.6
OnNow / Security Keyboard and Mouse Wake-Up
---- Programmable Keyboard / Mouse Wake-Up Functions
Winbond's unique programmable keyboard/ mouse Wake-Up functions provide the system diversified
methods for either OnNow Wake-Up application, or security control application. The keyboard or
mouse can Wake-Up the system by producing a panel switch low pulse on PANSWOT# pin, and
TM
connect it to chipset (for example Intel
chipset TX, LX PIIX4) panel switch input. The Wake-Up
conditions can be programmed as pre-determined or any keys/buttons. To implement this function, a
32.768KHz crystal must be installed between XTAL1 and XTAL2, or a 32.768KHz clock to be
connected to XTAL1 and leave XTAL2 open. The VSB pin must be connected to +5V VSB of ATX
power supply, and an external battery should be installed on VBAT pin to store the data (the
passwords and Wake-Up status which had been set already) when power fails.
6.6.1
Keyboard Wake-Up Function
The keyboard Wake-Up function is enable by setting LD-0A CR-E0 bit 6. The pre-determined keys
data are stored in registers, and they can be access by an indirection method. At first, write their index
address to LD-0A CR-E1, then access them by reading/writing LD-0A CR-E2. A zero data is written
to the register means the comparison of this register will be ignored. The pre-programmed keys may
be 1 to 5 keys with various combinations. If LD-0A CR-E0 bit 0 is set, the system will be waken up
after any key struck.
6.6.2
Keyboard Password Wake-Up Function
To implement this function, the bit 7 of LD-0A CR-E0 must be set, and panel switch input is connected
to PANSWIN# pin. Thus PANSWIN# is blocked to PANSWOUT#, by setting LD-0A CR-E0 properly
and make only keyboard can Wake-Up the system with preset keys (password).
6.6.3
Mouse Wake-Up Function
The mouse Wake-Up function is activated by setting bit 5 of LD-0A CR-E0. If bit 1 of LD-0A CR-E0 is
set, any movement or button clicking will make up the system. Otherwise, the mouse can Wake-Up
the system only by clicking its button twice successively with the mouse unmoved. The bit 4 of LD-0A
CR-E0 determines which button (left or right) to perform Wake-Up function.
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7.0 General Purpose I/O
W83977EF provides 14 Input/Output ports that can be individually configured to perform a simple
basic I/O function or a pre-defined alternate function. Those 14 GP I/O ports are divided into three
groups, the first group contains 8 ports, and the second group contains only 6 ports. Each port in first
group corresponds to a configuration register in logical device 7, and the second group in logical
device 8. Users can select those I/O ports functions by independently programming those
configuration registers. Figure 7.1, 7.2, and 7.3 respectively show the GP I/O port's structure of
logical device 7 and 8. Right after Power-on reset, those ports default to perform basic I/O functions.
Figure 7.1
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Figure 7.2
Figure 7.3
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7.1
Basic I/O functions
The Basic I/O functions of W83977EF provide several I/O operations including driving a logic value to
output port, latching a logic value from input port, inverting the input/output logic value, and steering
Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the
ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects to
a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There are two 8-bit
registers (GP1 and GP2) which are directly connected to those GP I/O ports. Each GP I/O port is
represented as a bit in one of three 8-bit registers. Only 6 bits of GP2 are implemented. Table 7.1.1
shows their combinations of Basic I/O functions, and Table 7.1.2 shows the register bit assignments of
GP1 and GP2.
Table 7.1.1
I/O BIT
ENABLE INT BIT
POLARITY BIT
BASIC I/O OPERATIONS
0 = OUTPUT
0 = DISABLE
0 = NON INVERT
1 = INPUT
1 = ENABLE
1 = INVERT
0
0
0
0
0
1
0
1
0
Basic non-inverting output
Basic inverting output
Non-inverted output bit value of GP2
drive to Common Interrupt
0
1
1
Inverted output bit value of GP2 drive
to Common Interrupt
1
1
1
0
0
1
0
1
0
Basic non-inverting input
Basic inverting input
Non-inverted input drive to Common
Interrupt
1
1
1
Inverted input drive to Common
Interrupt
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Table 7.1.2
GP I/O PORT ACCESSED
REGISTER
REGISTER BIT
ASSIGNMENT
GP I/O PORT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
GP1
GP2
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7.2
Alternate I/O Functions
W83977EF provides several alternate functions which are scattered among the GP I/O ports. Table
7.2.1 shows their assignments. Polarity bit can also be set to alter their polarity.
Table 7.2.1
GP I/O PORT
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
ALTERNATE FUNCTION
Interrupt Steering
Interrupt Steering
Watch Dog Timer Output/IRRX input
Power LED output/IRTX output
General Purpose Address Decoder/Keyboard Inhibit(P17)
General Purpose Write Strobe/ 8042 P12
Watch Dog Timer Output
Power LED output
Keyboard Reset (8042 P20)
8042 P13
8042 P14
8042 P15
8042 P16
GATE A20 (8042 P21)
7.2.1
Interrupt Steering
GP10, and GP11can be programmed to map their own interrupt channels. The selection of IRQ
channel can be done in configuration registers CR70 and CR72 of logical device 7 and logical device
9. Each interrupt channel also has its own 1 ms debounce filter that is used to reject any noise whose
width is equal to or less than 1 ms.
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7.2.2
Watch Dog Timer Output
Watch Dog Timer contains a one second/minute resolution down counter, CRF2 of Logical Device 8,
and two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down
counter can be programmed within the range from 1 to 255 seconds/minutes. Writing any new non-
zero value to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also
contains non-zero value) will cause the Watch Dog Timer to reload and start to count down from the
new value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of
WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable
in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is
enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1.
7.2.3
Power LED
The Power LED function provides 1~1/8 Hertz rate toggle pulse output with 50 percent duty cycle.
Table 7.2.2 shows how to enable Power LED.
Table 7.2.2
WDT_CTRL1 BIT[1]
WDT_CTRL0 BIT[3]
WDT_CTRL1 BIT[0]
POWER LED STATE
Toggle pulse
Continuous high or low *
Continuous high or low *
Toggle pulse
1
0
0
0
X
0
1
1
X
X
0
1
* Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configuration registers.
7.2.4
General Purpose Address Decoder
General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The
address base is stored at CR62, CR63, CR64, and CR65 of logical device 7 for GP14 and GP15. The
decoding range can be programmed to 1~8 byte boundary. The decoding output is normally active
low. Users can alter its polarity through the polarity bit of the GP14 and GP15 configuration register.
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8.0
Plug and Play Configuration
The W83977EF uses Compatible PNP protocol to access configuration registers for setting up
different types of configurations. In W83977EF, there are nine Logical Devices (from Logical Device 0
to Logical Device A with the exception of logical device 4 and 6 for compatibility) which correspond to
nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2),
UART2 (logical device 3), KBC (logical device 5), GPIO1 (logical device 7), GPIO2 (logical device 8),
and ACPI ((logical device A). Each Logical Device has its own configuration registers (above CR30).
Host can access those registers by writing an appropriate logical device number into logical device
select register at CR7.
8.1
Compatible PnP
8.1.1 Extended Function Registers
In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration
registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the
Extended Function mode as follows:
HEFRAS
address and value
write 87h to the location 3F0h twice
write 87h to the location 370h twice
0
1
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After Power-on reset, the value on (pin 43) is latched by HEFRAS of CR26. In Compatible
PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port
address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended
Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable
Register) to identify which configuration register is to be accessed. The designer can then access the
desired configuration register through the Extended Functions Data Register (I/O port address 3F1h
or 371h).
After programming of the configuration register is finished, an additional value (AAh) should be written
to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration
registers against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
8.1.2
Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83977EF enters the default operating mode. Before the W83977EF
enters the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are
3F0h or 370h (as described in previous section).
8.1.3
Extended Function Index Registers (EFIRs), Extended Function
Data Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as
described in section 8.1.1) on PC/AT systems; the EFDRs are read/write registers with port address
3F1h or 371h (as described in section 8.1.1) on PC/AT systems.
8.2 Configuration Sequence
To program W83977ATF configuration registers, the following configuration sequence must be
followed:
(1). Enter the extended function mode
(2). Configure the configuration registers
(3). Exit the extended function mode
8.2.1 Enter the extended function mode
To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to
Extended Function Enable Registers(EFERs, i.e. 3F0h or 370h).
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8.2.2 Configurate the configuration registers
The chip selects the logical device and activates the desired logical devices through Extended
Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the
same address as EFER, and EFDR is located at address (EFIR+1).
First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired
logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required.
Secondly, write the address of the desired configuration register within the logical device to the EFIR
and then write (or read) the desired configuration register through EFDR.
8.2.3 Exit the extended function mode
To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the
extended function mode, it is in the normal running mode and is ready to enter the configuration
mode.
8.2.4 Software programming example
The following example is written in Intel 8086 assembly language. It assumes that the EFER is located
at 3F0h, so EFIR is located at 3F0h and EFDR is located at 3F1h. If HEFRAS (CR26 bit 6) is set,
3F0h can be directly replaced by 370h and 3F1h replaced by 371h.
;-----------------------------------------------------------------------------------
; Enter the extended function mode ,interruptible double-write
;-----------------------------------------------------------------------------------
MOV DX,3F0H
|
MOV AL,87H
OUT DX,AL
OUT DX,AL
;-----------------------------------------------------------------------------
; Configurate logical device 1, configuration register CRF0 |
;-----------------------------------------------------------------------------
MOV DX,3F0H
MOV AL,07H
OUT DX,AL
MOV DX,3F1H
MOV AL,01H
OUT DX,AL
;
; point to Logical Device Number Reg.
; select logical device 1
MOV DX,3F0H
MOV AL,F0H
OUT DX,AL
MOV DX,3F1H
MOV AL,3CH
OUT DX,AL
; select CRF0
; update CRF0 with value 3CH
;------------------------------------------
; Exit extended function mode
;------------------------------------------
MOV DX,3F0H
|
MOV AL,AAH
OUT DX,AL
Publication Release Date: April 2003
Revision 1.1
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9.0
ACPI Registers Features
W83977EF supports both ACPI and legacy power managements. The switch logic of the power
management block generates an SMI# interrupt in the legacy mode and an SCI# interrupt in the ACPI
mode. The new ACPI feature routes SMI#/SCI# logic output either to SMI# or toSCI#. The SMI#/SCI#
logic routes to SMI# only when both SCI_EN = 0 and SMISCI_OE = 1.Similarly, the SMI#/SCI#
logicroutes to SCI# only when both SCI_EN = 1 and SMISCI_OE = 1.
SCI_EN
SMISCI_OE
IRQ events
SCI# Logic
SMI# /
SMI#
SCI#
0
1
SMISCI_OE
Device Idle
Timers
WAK_STS
IRQs
Clock
Sleep/Wake
State machine
Control
Device Trap
Global STBY
Timer
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10.0 Configuration Register
10.1 Chip (Global) Control Register
CR02 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: SWRST --> Soft Reset.
CR07
Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0
CR20
Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x52 (read only).
CR21
Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0xFx (read only).
CR22 (Default 0xff)
Bit 7 - 6: Reserved.
Bit 5: URBPWD
= 0 Power down
= 1 No Power down
Bit 4: URAPWD
= 0 Power down
= 1 No Power down
Bit 3: PRTPWD
= 0 Power down
= 1 No Power down
Bit 2, 1: Reserved.
Bit 0: FDCPWD
= 0 Power down
= 1 No Power down
CR23 (Default 0xFE)
Bit 7 - 1: Reserved.
Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down
mode immediately.
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CR24 (Default 0b1s000s0s)
Bit 7: EN16SA
= 0 12 bit Address Qualification
= 1 16 bit Address Qualification
Bit 6: EN48
= 0 The clock input on Pin 1 should be 24 Mhz.
= 1 The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 53).
Bit 5 - 3: Reserved.
Bit 2: ENKBC
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
setting pin is SOUTA (pin 46).
Bit 1: Reserved
Bit 0: PNPCSV#
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.
When trying to make a change to this bit, new value of PNPCSV# must be complementary to
the old one to make an effective change. For example, the user must set PNPCSV# to 0 first
and then reset it to 1 to reset these PnP registers if the present value of PNPCSV# is 1. The
corresponding power-on setting pin is NDTRA (pin 44).
CR25 (Default 0x00)
Bit 7 - 6: Reserved
Bit 5: URBTRI
Bit 4: URATRI
Bit 3: PRTTRI
Bit 2 - 1 : Reserved
Bit 0: FDCTRI.
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Revision 1.1
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CR26 (Default 0b0s000000)
Bit 7: SEL4FDD
= 0 Select two FDD mode.
= 1 Select four FDD mode.
Bit 6: HEFRAS
These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is NRTSA (pin 43).
HEFRAS Address and Value
= 0 Write 87h to the location 3F0h twice.
= 1 Write 87h to the location 370h twice.
Bit 5: LOCKREG
= 0 Enable R/W Configuration Registers.
= 1 Disable R/W Configuration Registers.
Bit 4: Reserved.
Bit 3: DSFDLGRQ
= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective
on selecting IRQ
= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
effective on selecting IRQ
Bit 2: DSPRLGRQ
= 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
selecting IRQ
= 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
on selecting IRQ
Bit 1: DSUALGRQ
= 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
Bit 0: DSUBLGRQ
= 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
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CR28 (Default 0x00)
Bit 7 - 5: Reserved.
Bit 4: IRQ Sharing selection.
= 0
= 1
Disable IRQ Sharing
Enable IRQ Sharing
Bit 3:Reserved
Bit 2 - 0: PRTMODS2 - PRTMODS0
= 0xx Parallel Port Mode
= 100 Reserved
= 101 External FDC Mode
= 110 Reserved
= 111 External two FDC Mode
CR2A (Default 0x00)
Bit 7: PIN57S
= 0 KBRST
= 1 GP12
Bit 6: PIN56S
= 0 GA20
= 1 GP11
Bit 5 - 4: PIN40S1, PIN40S0
= 00 CIRRX
= 01 GP24
= 10 8042 P13
= 11 Reserved
Bit 3 - 2: PIN39S1, PIN39S0
= 00 SUSCIN#
= 01 Reserved
= 10 GP25
= 11 Reserved
Bit 1 - 0: PIN3S1, PIN3S0
= 00 DRVDEN1
= 01 GP10
= 10 8042 P12
= 11 SCI#
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CR2B (Default 0x00)
Bit 7 - 6: PIN73S1, PIN73S0
= 00 PANSWIN#
= 01 GP23
= 10 Reserved
= 11 Reserved
Bit 5: PIN72S
= 0 PANSWOUT#
= 1 GP22
Bit 4 - 3: PIN70S1, PIN70S0
= 00 SMI#
= 01 GP21
= 10 8042 P16
= 11 Reserved
Bit 2 - 1: PIN69S1, PIN69S0
= 00 PWRCTL#
= 01 GP20
= 10 Reserved
= 11 Reserved
Bit 0: PIN58S
= 0 KBLOCK
= 1 GP13
CR2C (Default 0x00)
Bit 7 - 6: PIN121S1, PIN121S0
= 00 DRQ0
= 01 GP17
= 10 8042 P14
= 11 SCI#
Bit 5 - 4: PIN119S1, PIN119S0
= 00 NDACK0
= 01 GP16
= 10 8042 P15
= 11 Reserved
Bit 3 - 2: PIN104S1, PIN104S0
= 00 IRQ15
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= 01 GP15
= 10 WDTO
= 11 Reserved
Bit 1 - 0: PIN103S1, PIN103S0
= 00 IRQ14
= 01 GP14
= 10 PLEDO
= 11 Reserved
CR2D (Default 0x00)
Test Modes: Reserved for Winbond.
CR2E (Default 0x00)
Test Modes: Reserved for Winbond.
CR2F (Default 0x00)
Test Modes: Reserved for Winbond.
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10.2 Logical Device 0 (FDC)
CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x06 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for FDC.
CR74 (Default 0x02 if PNPCSV# = 0 during POR, default 0x04 otherwise)
Bit 7 - 3: Reserved.
Bit 2 - 0: These bits select DRQ resource for FDC.
= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04 - 0x07 No DMA active
CRF0 (Default 0x0E)
FDD Mode Register
Bit 7: FIPURDWN
This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0,
DSKCHG, and WP.
= 0 The internal pull-up resistors of FDC are turned on.(Default)
= 1 The internal pull-up resistors of FDC are turned off.
Bit 6: INTVERTZ
This bit determines the polarity of all FDD interface signals.
= 0 FDD interface signals are active low.
= 1 FDD interface signals are active high.
Bit 5: DRV2EN (PS2 mode only)
When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status
register A.
Bit 4: Swap Drive 0, 1 Mode
= 0 No Swap (Default)
= 1 Drive and Motor sel 0 and 1 are swapped.
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Bit 3 - 2 Interface Mode
= 11 AT Mode (Default)
= 10 (Reserved)
= 01 PS/2
= 00 Model 30
Bit 1: FDC DMA Mode
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (Default)
Bit 0: Floppy Mode
= 0 Normal Floppy Mode (Default)
= 1 Enhanced 3-mode FDD
CRF1 (Default 0x00)
Bit 7 - 6: Boot Floppy
= 00 FDD A
= 01 FDD B
= 10 FDD C
= 11 FDD D
Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6.
Bit 3 - 2: Density Select
= 00 Normal (Default)
= 01 Normal
= 10 1 ( Forced to logic 1)
= 11 0 ( Forced to logic 0)
Bit 1: DISFDDWR
= 0 Enable FDD write.
= 1 Disable FDD write(forces pins WE, WD stay high).
Bit 0: SWWP
= 0 Normal, use WP to determine whether the FDD is write protected or not.
= 1 FDD is always write-protected.
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CRF2 (Default 0xFF)
Bit 7 - 6: FDD D Drive Type
Bit 5 - 4: FDD C Drive Type
Bit 3 - 2: FDD B Drive Type
Bit 1:0: FDD A Drive Type
When FDD is in enhanced 3-mode(CRF0.bit0=1),these bits determine SELDEN value in TABLE A
of CRF4 and CRF5 as follows.
DTYPE1
DPYTE0
DRATE1
DRATE0
SELDEN
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
1
X
X
0
1
0
1
0
X
X
1
1
1
0
0
0
1
0
Note: X means don't care.
CRF4 (Default 0x00)
FDD0 Selection:
Bit 7: Reserved.
Bit 6: Precomp. Disable.
= 1 Disable FDC Precompensation.
= 0 Enable FDC Precompensation.
Bit 5: Reserved.
Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A).
= 00 Select Regular drives and 2.88 format
= 01 Specifical application
= 10 2 Meg Tape
= 11 Reserved
Bit 2: Reserved.
Bit 1:0: DMOD0, DMOD1 : Drive Model select (Refer to TABLE B).
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Revision 1.1
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CRF5 (Default 0x00)
FDD1 Selection: Same as FDD0 of CRF4.
TABLE A
Drive Rate Table
Select
Data Rate
Selected Data Rate
SELDEN
DRTS1
DRTS0
DRATE1
DRATE0
MFM
1Meg
500K
300K
250K
1Meg
500K
500K
250K
1Meg
500K
2Meg
250K
FM
---
250K
150K
125K
---
250K
250K
125K
---
250K
---
CRF0 bit 0=0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
125K
Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1.
TABLE B
DMOD0
DMOD1
DRVDEN0(pin 2)
DRVDEN1(pin 3)
DRIVE TYPE
0
0
SELDEN
DRATE0
4/2/1 MB 3.5”“
2/1 MB 5.25”
2/1.6/1 MB 3.5” (3-MODE)
0
1
1
0
DRATE1
DRATE0
DRATE0
SELDEN
DRATE0
1
1
DRATE1
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Revision 1.1
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10.3 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0x78 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Parallel Port I/O base address.
[0x100:0xFFC] on 4 byte boundary (EPP not supported) or
[0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base
address is on 8 byte boundary).
CR70 (Default 0x07 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for Parallel Port.
CR74 (Default 0x04)
Bit 7 - 3: Reserved.
Bit 2 - 0: These bits select DRQ resource for Parallel Port.
0x00=DMA0
0x01=DMA1
0x02=DMA2
0x03=DMA3
0x04 - 0x07= No DMA active
CRF0 (Default 0x3F)
Bit 7: PP Interrupt Type:
Not valid when the parallel port is in the printer Mode (100) or the standard & Bi-directional
Mode (000).
= 1 Pulsed Low, released to high-Z .
= 0 IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP.
Bit [6:3]: ECP FIFO Threshold.
Bit 2 - 0 Parallel Port Mode
= 100 Printer Mode (Default)
= 000 Standard and Bi-direction (SPP) mode
= 001 EPP - 1.9 and SPP mode
= 101 EPP - 1.7 and SPP mode
= 010 ECP mode
= 011 ECP and EPP - 1.9 mode
= 111 ECP and EPP - 1.7 mode.
10.4 Logical Device 2 (UART A)¢)
CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise)
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Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x04 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Serial Port 1.
CRF0 (Default 0x00)
Bit 7 - 2: Reserved.
Bit 1 - 0: SUACLKB1, SUACLKB0
= 00 UART A clock source is 1.8462 Mhz (24MHz/13)
= 01 UART A clock source is 2 Mhz (24MHz/12)
= 10 UART A clock source is 24 Mhz (24MHz/1)
= 11 UART A clock source is 14.769 Mhz (24MHz/1.625)
10.5 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x03 if PNPCSV# = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for Serial Port 2.
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CRF0 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3: RXW4C
= 0
= 1
No reception delay when SIR is changed from TX mode to RX mode.
Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode
to RX mode.
Bit 2: TXW4C
= 0
= 1
No transmission delay when SIR is changed from RX mode to TX mode.
Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX
mode to TX mode.
Bit 1 - 0: SUBCLKB1, SUBCLKB0
= 00 UART B clock source is 1.8462 Mhz (24MHz/13)
= 01 UART B clock source is 2 Mhz (24MHz/12)
= 10 UART B clock source is 24 Mhz (24MHz/1)
= 11 UART B clock source is 14.769 Mhz (24MHz/1.625)
CRF1 (Default 0x00)
Bit 7: Reserved.
Bit 6: IRLOCSEL. IR I/O pins' location select.
= 0
= 1
Through SINB/SOUTB.
Through IRRX/IRTX.
Bit 5: IRMODE2. IR function mode selection bit 2.
Bit 4: IRMODE1. IR function mode selection bit 1.
Bit 3: IRMODE0. IR function mode selection bit 0.
IR MODE
00X
010*
IR FUNCTION
Disable
IrDA
IRTX
IRRX
tri-state
high
Demodulation into SINB/IRRX
Demodulation into SINB/IRRX
routed to SINB/IRRX
Active pulse 1.6 µS
Active pulse 3/16 bit time
Inverting IRTX/SOUTB pin
Inverting IRTX/SOUTB & 500
KHZ clock
011*
100
101
IrDA
ASK-IR
ASK-IR
routed to SINB/IRRX
110
111*
ASK-IR
ASK-IR
Inverting IRTX/SOUTB
Inverting IRTX/SOUTB & 500
KHZ clock
Demodulation into SINB/IRRX
Demodulation into SINB/IRRX
Note: The notation is normal mode in the IR function.
Bit 2: HDUPLX. IR half/full duplex function select.
= 0
The IR function is Full Duplex.
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= 1
The IR function is Half Duplex.
Bit 1: TX2INV.
= 0
= 1
the SOUTB pin of UART B function or IRTX pin of IR function in normal condition.
inverse the SOUTB pin of UART B function or IRTX pin of IR function.
Bit 0: RX2INV.
= 0
= 1
the SINB pin of UART B function or IRRX pin of IR function in normal condition.
inverse the SINB pin of UART B function or IRRX pin of IR function
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10.6 Logical Device 5 (KBC)
CR30 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x60 if PENKBC= 1 during POR, default 0x00 otherwise)
These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x64 if PENKBC= 1 during POR, default 0x00 otherwise)
These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
CR70 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for KINT (keyboard).
CR72 (Default 0x0C if PENKBC= 1 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for MINT (PS2 Mouse)
CRF0 (Default 0x83)
Bit 7 - 6: KBC clock rate selection
= 00 Select 6MHz as KBC clock input.
= 01 Select 8MHz as KBC clock input.
= 10 Select 12Mhz as KBC clock input.
= 11 Select 16Mhz as KBC clock input.
Bit 5 - 3: Reserved.
Bit 2: = 0 Port 92 disable.
= 1 Port 92 enable.
Bit 1: = 0 Gate20 software control.
= 1 Gate20 hardware speed up.
Bit 0: = 0 KBRST software control.
= 1 KBRST hardware speed up.
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10.7 Logical Device 7 (GP I/O Port I)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP1 I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x00)
These two registers select GP14 alternate function Primary I/O base address [0x100:0xFFx] on
1~8 byte boundary; They are available as you setting GP14 to be an alternate function (General
Purpose Address Decode).
CR64, CR 65 (Default 0x00, 0x00)
These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFx] on
1~8
byte boundary; They are available as you setting GP15 to be an alternate function (General
Purpose Address Decode).
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP10 as you setting GP10 to be an alternate function
(Interrupt Steering).
CR72 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP11 as you setting GP11 to be an alternate function
(Interrupt Steering).
CRE0 (GP10, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4: IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 3: Select Function.
= 1 Select Alternate Function: Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity.
= 1 Invert.
= 0 No Invert.
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Bit 0: In/Out selection.
= 1 Input.
= 0 Output.
CRE1 (GP11, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4: IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 3: Select Function.
= 1 Select Alternate Function: Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity.
= 1 Invert.
= 0 No Invert.
Bit 0: In/Out selection.
= 1 Input.
= 0 Output.
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CRE2 (GP12, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Watch Dog Timer Output.
= 10 Reserved
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE3 (GP13, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Power LED output.
= 10 Reserved
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE4 (GP14, Default 0x01)
Bit 7 - 6:
= 00 Address decoder is 1-Byte boundary.
= 01 Address decoder is 2-Byte boundary.
= 10 Address decoder is 4-Byte boundary.
= 11 Address decoder is 8-Byte boundary.
Bit 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: General Purpose Address Decoder(Active Low when
Bit 1 = 0, Decode two byte address).
= 10 Select 2nd alternate function: Keyboard Inhibit(P17).
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE5 (GP15, Default 0x01)
Bit 7 - 6:
= 00 Address decoder is 1-Byte boundary.
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= 01 Address decoder is 2-Byte boundary.
= 10 Address decoder is 4-Byte boundary.
= 11 Address decoder is 8-Byte boundary.
Bit 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 General Purpose Write Strobe(Active Low when Bit 1 = 0).
= 10 8042 P12.
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE6 (GP16, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Watch Dog Timer Output.
= 1x Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE7 (GP17, Default 0x01)
Bit 7 - 4: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Power LED output. Please refer to TABLE C
= 1x Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
TABLE C
WDT_CTRL1* BIT[1]*
WDT_CTRL0* BIT[3] WDT_CTRL1 BIT[0] POWER LED STATE
1
0
X
0
X
X
1 Hertz Toggle pulse
Continuous high or low*
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0
0
1
1
0
1
Continuous high or low*
1 Hertz Toggle pulse
*Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8.
2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers.
CRF1 ( Default 0x00)
General Purpose Read/Write Enable*
Bit 7 - 2: Reserved
Bit 1:
= 1 Enable GP15 General Purpose Address Decode
= 0 Disable GP15 General Purpose Address Decode
Bit 0:
= 1 Enable GP14 General Purpose Address Decode
= 0 Disable GP14 General Purpose Address Decode
*Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect.
10.8 Logical Device 8 (GP I/O Port II)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE] on 2 byte
boundary. I/O base address + 1: Watch Dog I/O base address.
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Common IRQ of GP20~GP26 at Logic Device 8.
CR72 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Watch Dog.
CRE8 (GP20, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select basic I/O function
= 01 Reserved
= 10 Select alternate function: Keyboard Reset (connected to KBC P20)
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= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE9 (GP21, Default 0x01)
Bit 7 - 5: Reserved
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P13 I/O
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CREA (GP22, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P14 I/O.
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CREB (GP23, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P15 I/O
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
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Bit 0: In/Out: 1: Input, 0: Output
CREC (GP24, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P16 I/O
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRED (GP25, Default 0x01)
Bit 7 - 4: Reserved.
Bit 3: Select Function.
= 1 Select alternate function: GATE A20(Connect to KBC P21).
= 0 Select basic I/O function
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRF0 (Default 0x00)
Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter
can reject a pulse with 1ms width or less.
Bit 7 - 4: Reserved
Bit 3: GP Common IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 2 - 0: Reserved
CRF1 (Reserved)
CRF2 (Default 0x00)
Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load
the value to Watch Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any Mouse
Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to Watch Dog
Counter and count down. Read this register can not access Watch Dog Timer Time-out value, but
can access the current value in Watch Dog Counter.
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Bit 7 - 0:
= 0x00 Time-out Disable
= 0x01 Time-out occurs after 1 minute/second
= 0x02 Time-out occurs after 2 minutes/seconds
= 0x03 Time-out occurs after 3 minutes/seconds
................................................
= 0xFF Time-out occurs after 255 minutes
CRF3 (WDT_CTRL0, Default 0x00)
Watch Dog Timer Control Register #0
Bit 7 - 4: Reserved
Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output.
= 1 Enable
= 0 Disable
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Bit 2: Mouse interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Mouse interrupt
= 0 Watch Dog Timer is not affected by Mouse interrupt
Bit 1: Keyboard interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Keyboard interrupt
= 0 Watch Dog Timer is not affected by Keyboard interrupt
Bit 0: Reserved.
CRF4 (WDT_CTRL1, Default 0x00)
Watch Dog Timer Control Register #1
Bit 7: Reserved
Bit 6:
= 1 Watch Dog counter counts in seconds.
= 0 Watch Dog counter counts in minutes.
Bit 5-4: Power LED toggle pulse frequency select
= 00 Power LED toggle pulse frequency is 1Hz
= 01 Power LED toggle pulse frequency is 1/2Hz
= 10 Power LED toggle pulse frequency is 1/4Hz
= 11 Power LED toggle pulse frequency is 1/8Hz
Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
= 1 Enable
= 0 Disable
Bit 2: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.
Bit 1: Enable Power LED toggle pulse with 50% duty cycle , R/W
= 1 Enable
= 0 Disable
Bit 0: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred.
= 0 Watch Dog Timer counting
*Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and
then
connect to set the Bit 0(Watch Dog Timer Status). The ORed signal is self-clearing.
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10.9 Logical Device A (ACPI)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resources for SCI#.
CRE0 (Default 0x00)
Bit 7: DIS-PANSWIN. Disable panel switch input to turn system power supply on.
= 0
= 1
PANSWIN# is wire-ANDed and connected to PANSWOUT#.
PANSWIN# is blocked and can not affect PANSWOUT#.
Bit 6: ENKBWAKEUP. Enable Keyboard to Wake-Up system via PANSWOUT#.
= 0
= 1
Disable Keyboard Wake-Up function.
Enable Keyboard Wake-Up function.
Bit 5: ENMSWAKEUP. Enable Mouse to Wake-Up system via PANSWOUT#.
= 0
= 1
Disable Mouse Wake-Up function.
Enable Mouse Wake-Up function.
Bit 4: MSRKEY. Select Mouse Left/Right Botton to Wake-Up system via PANSWOUT#.
= 0
= 1
Select click on Mouse Left-botton to Wake the system up.
Select click on Mouse right-botton to Wake the system up.
Bit 3: Reserved.
Bit 2: KB/MS Swap. Enable Keyboard/Mouse port-swap.
= 0
= 1
Keyboard/Mouse ports are not swapped.
Keyboard/Mouse ports are swapped.
Bit 1: MSXKEY. Enable any character received from Mouse to Wake-Up the system.
= 0
= 1
Just clicking Mouse left/right-botton twice can Wake the system up.
Just clicking Mouse left/right-botton once can Wake the system up.
Bit 0: KBXKEY. Enable any character received from Keyboard to Wake-Up the system.
= 0
= 1
Only predetermined specific key combination can Wake-Up the system.
Any character received from Keyboard can Wake-Up the system.
CRE1 (Default 0x00) Keyboard Wake-Up Index Register
This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key
Register is to be read/written via CRE2. The range of Keyboard Wake-Up index register is 0x00 -
0x0E,
CRE2 Keyboard Wake-Up Data Register
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CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register
Bit 7-4: Reserved.
Bit 4: POWERRESUME_STS. The bit is set after powerloss occured and cleared by
reading this register.
Bit 3: Revered
Bit 2: PANSW_STS. The Panel switch event is caused by PANSWIN#. This bit is cleared by
reading this register.
Bit 1: Mouse_STS. The Panel switch event is caused by Mouse Wake-Up event. This bit is
cleared by reading this register.
Bit 0: Keyboard_STS. The Panel switch event is caused by Keyboard Wake-Up event. This bit is
cleared by reading this register.
CRE4 OnNow/Powerloss Control Register.
Bit 7: Powerloss Control bit 2.
Bit 6: Powerloss Control bit 1.
Bit 5: Powerloss Control bit 0.
Bit 4: 32KHz clock source select.
Bit 3: Reserved.
Bit 2: Reserved.
Bit 1-0: Reserved.
CRE5 (Default 0x00)
Bit 7: Reserved.
Bit 6 - 0: Compared Code Length. When the compared codes are storaged in the data register,
these data length should be written to this register.
CRE6 (Default 0x00)
Bit 7 - 0: Reserved.
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CRE7 (Default 0x00)
Bit 7 - 3: Reserved.
Bit 2: Reserved
Bit 1: Invert RX Data.
= 1 Inverting RX Data.
= 0 Not inverting RX Data.
Bit 0: Enable Demodulation.
= 1 Enable received signal to demodulate.
= 0 Disable received signal to demodulate.
CRF0 (Default 0x00)
Bit 7: CHIPPME. Chip level auto power management enable.
= 0
= 1
disable the auto power management functions
enable the auto power management functions.
Bit 6: URCPME. UART C auto power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions.
Bit 5 - 4: Reserved. Return zero when read.
Bit 3: PRTPME. Printer port auto power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions.
Bit 2: FDCPME. FDC auto power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions.
Bit 1: URAPME. UART A auto power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions.
Bit 0: URBPME. UART B auto power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions.
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CRF1 (Default 0x00)
Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume
event occurs. Upon setting this bit, the sleeping/working state machine will transition the
system to the working state. This bit is only set by hardware and is cleared by writing a 1 to
this bit position or by the sleeping/working state machine automatically when the global
standby timer expires.
= 0
= 1
the chip is in the sleeping state.
the chip is in the working state.
Bit 6: Device's trap status.
Bit 5 - 4: Reserved. Return zero when read.
Bit 3 - 0: Devices' trap status.
These bits of trap status indicate that the individual device Wakes-Up due to any I/O access,
IRQ, and external input to the device. The device's idle timer reloads the preset expiry
depending on which device wakes up. These 5 bits are controlled by the UART C, printer
port,
and
power
FDC, UART A and UART B power down machines respectively . Writing a 1 clears this bit
writing a 0 has no effect. Note that: the user is not supposed to change the status while
management function is enabled.
Bit 6: URCTRAPSTS. UART C trap status.
= 0
= 1
UART C is now in the sleeping state.
UART C is now in the working state due to any UART C access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
start bit, and any transition on MODEM control input lines.
transmitting a
Bit 3: PRTTRAPSTS. Printer port trap status.
= 0
= 1
the printer port is now in the sleeping state.
the printer port is now in the workinging state due to any printer port access, any IRQ,
any DMA acknowledge, and any transition on BUSY, ACK#, PE, SLCT, and
ERR# pins.
Bit 2: FDCTRAPSTS. FDC trap status.
= 0
= 1
FDC is now in the sleeping state.
FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, and any enabling of the motor enable bits in the DOR register.
Bit 1: URATRAPSTS. UART A trap status.
= 0
= 1
UART A is now in the sleeping state.
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
start bit, and any transition on MODEM control input lines.
transmitting a
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Bit 0: URBTRAPSTS. UART B trap status.
= 0
= 1
UART B is now in the sleeping state.
UART B is now in the workinging state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
start bit, and any transition on MODEM control input lines.
transmitting a
CRF3 (Default 0x00)
Bit 7: Reserved. Return zero when read.
Bit 6 - 0: Device's IRQ status.
These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit
is set by their source device and is cleared by writing a 1. Writing a 0 has no effect.
Bit 6: URCIRQSTS. UART C IRQ status.
Bit 5: MOUIRQSTS. MOUSE IRQ status.
Bit 4: KBCIRQSTS. KBC IRQ status.
Bit 3: PRTIRQSTS. printer port IRQ status.
Bit 2: FDCIRQSTS. FDC IRQ status.
Bit 1: URAIRQSTS. UART A IRQ status.
Bit 0: URBIRQSTS. UART B IRQ status.
CRF4 (Default 0x00)
Bit 7 - 5: Reserved. Return zero when read.
Bit 3: Reserved. Return zero when read.
Bit 4 and Bit 2 - 0:These bits indicate the status of the individual GPIO function respectively. The
status is set by their source function and is cleared by writing a 1. Writing a 0 has no effect.
Bit 4: WDTIRQSTS. Watch dog timer IRQ status at logical device 8.
Bit 2: COMIRQSTS. Common IRQ status of GP20 - GP25 at logical device 8.
Bit 1: GP11IRQSTS. GP11 interrupt steering status at logical device 7.
Bit 0: GP10IRQSTS. GP10 interrupt steering status at logical device 7.
CRF6 (Default 0x00)
Bit 7: Reserved. Return zero when read.
Bit 6 - 0: Enable bits of the SMI#/SCI# generation due to the device's IRQ.
These bits enable the generation of an SMI#/SCI# interrupt due to any IRQ of the devices.
SMI#/SCI# logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or
(FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (KBCIRQEN and
KBCIRQSTS) or (MOUIRQEN and MOUIRQSTS) or (URCIRQEN and URCIRQSTS) or
(WDTIRQEN and
WDTIRQSTS) or (COMIRQEN and COMIRQSTS) or (GP11IRQEN and
(GP10IRQEN and GP10IRQSTS)
GP11IRQSTS) or
Bit 6: URCIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to UART C's IRQ.
enable the generation of an SMI#/SCI# interrupt due to UART C's IRQ.
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Bit 5: MOUIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to MOUSE's IRQ.
enable the generation of an SMI#/SCI# interrupt due to MOUSE's IRQ.
Bit 4: KBCIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to KBC's IRQ.
enable the generation of an SMI#/SCI# interrupt due to KBC's IRQ.
Bit 3: PRTIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to printer port's IRQ.
enable the generation of an SMI#/SCI# interrupt due to printer port's IRQ.
Bit 2: FDCIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to FDC's IRQ.
enable the generation of an SMI#/SCI# interrupt due to FDC's IRQ.
Bit 1: URAIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to UART A's IRQ.
enable the generation of an SMI#/SCI# interrupt due to UART A's IRQ.
Bit 0: URBIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to UART B's IRQ.
enable the generation of an SMI#/SCI# interrupt due to UART B's IRQ.
CRF7 (Default 0x00)
Bit 7 - 5: Reserved. Return zero when read.
Bit 3: Reserved. Return zero when read.
Bit 4 and Bit 2 - 0:Enable bits of the SMI#/SCI# generation due to the individual GPIO IRQ
functions.
Bit 4: WDTIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ.
enable the generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ.
Bit 2: COMIRQEN.
= 0
= 1
disable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ.
enable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ.
Bit 1: GP11IRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's
IRQ.
IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's
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Bit 0: GP10IRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's
IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's
IRQ.
CRF9 (Default 0x00)
Bit 7 - 3: Reserved. Return zero when read.
Bit 2: SCI_EN: Select the power management events to be either an SCI# OR SMII# interrupt for
the IRQ events. Note that: this bit is valid only when SMISCI_OE = 1.
= 0
= 1
the power management events will generate an SMI# event.
the power management events will generate an SCI# event.
Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices
= 0
= 1
1 second.
8 milli-seconds.
Bit 0: SMISCI_OE: This is the SMI# and SCI# enable bit.
= 0
= 1
neither SMI# nor SCI# will be generated. Only the IRQ status bit is set.
an SMI# or SCI# event will be generated.
CRFE, FF (Default 0x00)
Reserved for Winbond test.
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11.0 SPECIFICATIONS
11.1 Absolute Maximum Ratings
PARAMETER
Power Supply Voltage
Input Voltage
Battery Voltage VBAT
5V Standby VSB
RATING
-0.5 to 7.0
-0.5 to VDD+0.5
4.0 to 1.8
UNIT
V
V
V
V
4.5 to 5.5
Operating Temperature
Storage Temperature
0 to +70
-55 to +150
° C
° C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
11.2 DC CHARACTERISTICS
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER
Battery Quiescent Current
SYM. MIN.
IBAT
TYP.
MAX.
≤1
UNIT
uA
CONDITIONS
VBAT = 2.5 V
Stand-by Power Supply
IVSB
2.0
mA
VSB = 5.0 V, All ACPI pins are
not connected.
Quiescent Current
I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
V
V
µA
µA
2.0
2.4
0.4
IOL = 8 mA
IOH = - 8 mA
VIN = VDD
VIN = 0V
+10
-10
I/O6t - TTL level bi-directional pin with source-sink capability of 6 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
V
V
µA
µA
2.0
2.4
0.4
IOL = 6 mA
IOH = - 6 mA
VIN = VDD
VIN = 0V
+10
-10
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11.2 DC CHARACTERISTICS, continued
PARAMETER SYM. MIN.
I/O8 - CMOS level bi-directional pin with source-sink capability of 8 mA
TYP.
MAX.
UNIT
CONDITIONS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
V
V
V
V
µA
µA
0.7xVDD
3.5
0.4
IOL = 8 mA
IOH = - 8 mA
VIN = VDD
VIN = 0V
+ 10
- 10
I/O12 - CMOS level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
V
V
V
V
µA
µA
0.7xVDD
3.5
0.4
IOL = 12 mA
IOH = - 12 mA
VIN = VDD
+ 10
- 10
VIN = 0V
I/O16u - CMOS level bi-directional pin with source-sink capability of 16 mA, with internal pull-up
resistor
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
0.4
V
V
V
V
µA
µA
0.7xVDD
3.5
IOL = 16 mA
IOH = - 16 mA
VIN = VDD
+ 10
- 10
VIN = 0V
I/OD16u - CMOS level Open-Drain pin with source-sink capability of 16 mA, with internal pull-up
resistor
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
0.4
V
V
V
V
µA
µA
0.7xVDD
3.5
IOL = 16 mA
IOH = - 16 mA
VIN = VDD
+ 10
- 10
VIN = 0V
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11.2 DC CHARACTERISTICS, continued
PARAMETER SYM. MIN.
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
TYP.
MAX.
UNIT
CONDITIONS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
V
V
µA
µA
2.0
2.4
0.4
IOL = 12 mA
IOH = - 12 mA
VIN = VDD
VIN = 0V
+ 10
- 10
I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
V
V
µA
µA
2.0
2.4
0.4
IOL = 24 mA
IOH = - 24 mA
VIN = VDD
+ 10
- 10
VIN = 0V
OUT8t - TTL level output pin with source-sink capability of 8 mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 8 mA
IOH = - 8 mA
2.4
OUT12t - TTL level output pin with source-sink capability of 12 mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 12 mA
IOH = -12 mA
2.4
OD12 - Open-drain output pin with sink capability of 12 mA
Output Low Voltage 0.4
OD24 - Open-drain output pin with sink capability of 24 mA
VOL
V
V
IOL = 12 mA
IOL = 24 mA
Output Low Voltage
INt - TTL level input pin
Input Low Voltage
VOL
0.4
VIL
VIH
ILIH
ILIL
0.8
V
V
µA
µA
Input High Voltage
Input High Leakage
Input Low Leakage
2.0
+10
-10
VIN = VDD
VIN = 0 V
Publication Release Date: April 2003
Revision 1.1
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11.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
INc
- CMOS level input pin
Input Low Voltage
Input High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
ILIH
ILIL
V
V
0.3×VDD
0.7×VDD
+10
-10
VIN = VDD
µA
µA
VIN = 0 V
INcs
- CMOS level Schmitt-triggered input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Input High Leakage
Input Low Leakage
Vt-
Vt+
1.3
3.2
1.5
1.5
3.5
2
1.7
3.8
V
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0 V
VTH
ILIH
ILIL
+10
-10
µA
µA
INcu - CMOS level input pin with internal pull-up resistor
Input Low Voltage
Input High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
ILIH
ILIL
0.7xVDD
V
V
0.7xVDD
+10
-10
VIN = VDD
VIN = 0 V
µA
µA
INts
- TTL level Schmitt-triggered input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Input High Leakage
Input Low Leakage
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0 V
VTH
ILIH
ILIL
+10
-10
µA
µA
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Input High Leakage
Input Low Leakage
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0 V
VTH
ILIH
ILIL
+10
-10
µA
µA
Publication Release Date: April 2003
Revision 1.1
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W83977EF
11.3 AC Characteristics
11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec.
PARAMETER
SYM. TEST
MIN.
TYP.
MAX.
UNIT
(NOTE 1)
CONDITIONS
SA9-SA0, AEN, DACK#,
TAR
TAR
25
nS
CS#, setup time to IOR#↓
SA9-SA0, AEN, DACK#,
0
nS
hold time for IOR#↑
TRR
TFD
80
nS
nS
IOR width
Data access time from
CL = 100 pf
80
IOR#↓
CL = 100 pf
CL = 100 pf
TDH
TDF
TRI
10
10
nS
nS
nS
Data hold from IOR#↓
SD to from IOR# ↑
IRQ delay from IOR#↑
50
360/570
/675
SA9-SA0, AEN, DACK#,
TAW
TWA
25
0
nS
nS
setup time to IOW#↓
SA9-SA0, AEN, DACK#,
hold time for IOW#↑
IOW# width
TWW
TDW
60
60
0
nS
nS
nS
nS
Data setup time to IOW#↑
Data hold time from IOW#↑
IRQ delay from IOW#↑
TWD
TWI
360/570
/675
DRQ cycle time
TMCY
TAM
27
0
260/430
/510
µS
nS
nS
nS
50
DRQ delay time DACK#↓
DRQ to DACK# delay
DACK# width
TMA
TAA
TMR
TMW
0
0
nS
nS
IOR# delay from DRQ
IOW# delay from DRQ
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11.3.1 AC Characteristics, FDC continued
PARAMETER
SYM. TEST
MIN.
TYP.
MAX.
UNIT
µS
CONDITIONS
(NOTE 1)
IOW# or IOR# response
time from DRQ
TC width
TMRW
TTC
6/12
/20/24
135/220
/260
nS
RESET width
TRST
TIDX
1.8/3/3.
5
0.5/0.9
/1.0
1.0/1.6
/2.0
24/40/4
8
µS
µS
µS
µS
µS
INDEX# width
DIR# setup time to STEP#
DIR# hold time from STEP#
STEP# pulse width
TDST
TSTD
TSTP
6.8/11.5
/13.8
7/11.7
/14
7.2/11.9
/14.2
STEP# cycle width
WD# pulse width
TSC
Note 2
Note 2
Note 2
µS
µS
TWDD
100/185
/225
125/210
/250
150/235
/275
Write precompensation
TWPC
100/138
/225
125/210
/250
150/235
/275
µS
Notes:
1. Typical values for T = 25° C and normal supply voltage.
2. Programmable from 2 mS through 32 mS in 2 mS increments.
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11.3.2 UART/Parallel Port
PARAMETER
SYMBOL
TEST
MIN.
9/16
MAX.
UNIT
CONDITIONS
Delay from Stop to Set Interrupt
Delay from IOR# Reset Interrupt
TSINT
Baud
Rate
TRINT
TIRS
100 pf Loading
100 pf Loading
1
µS
Baud
Rate
nS
Baud
Rate
Delay from Initial IRQ Reset to
Transmit Start
Delay from IOW# to Reset interrupt
Delay from Initial IOW# to interrupt
1/16
9/16
8/16
THR
TSI
175
16/16
Delay from Stop to Set Interrupt
TSTI
1/2
Baud
Rate
Delay from IOR# to Reset Interrupt
Delay from IOR# to Output
Set Interrupt Delay from Modem
Input
TIR
100 pF Loading
100 pF Loading
250
200
250
nS
nS
nS
TMWO
TSIM
Reset Interrupt Delay from IOR#
Interrupt Active Delay
Interrupt Inactive Delay
Baud Divisor
TRIM
TIAD
250
25
30
216-1
nS
nS
nS
100 pF Loading
100 pF Loading
100 pF Loading
TIID
N
11.3.3 Parallel Port Mode Parameters
PARAMETER
SYM.
MIN.
TYP. MAX.
UNIT
PD0-7, INDEX#, STROBE#, AUTOFD# Delay from
t1
100
nS
IOW#
IRQ Delay from ACK#, nFAULT
IRQ Delay from IOW#
IRQ Active Low in ECP and EPP Modes
ERROR# Active to IRQ Active
t2
t3
t4
t5
60
nS
nS
nS
nS
105
300
105
200
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11.3.4 EPP Data or Address Read Cycle Timing Parameters
PARAMETER
SYM.
MIN.
40
MAX.
UNIT
Ax Valid to IOR# Asserted
IOCHRDY Deasserted to IOR# Deasserted
IOR# Deasserted to Ax Valid
IOR# Deasserted to IOW# or IOR# Asserted
IOR# Asserted to IOCHRDY Asserted
PD Valid to SD Valid
IOR# Deasserted to SD Hi-Z (Hold Time)
SD Valid to IOCHRDY Deasserted
WAIT# Deasserted to IOCHRDY Deasserted
PD Hi-Z to PDBIR Set
t1
t2
t3
t4
t5
nS
nS
nS
0
10
40
0
0
0
10
24
75
40
nS
nS
µS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
t6
t7
t8
t9
0
60
0
0
0
60
0
60
0
0
60
1
0
0
0
60
10
0
85
160
t10
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
WRITE# Deasserted to IOR# Asserted
WAIT# Asserted to WRITE# Deasserted
Deasserted to WRITE# Modified
IOR# Asserted to PD Hi-Z
185
190
50
WAIT# Asserted to PD Hi-Z
180
Command Asserted to PD Valid
Command Deasserted to PD Hi-Z
WAIT# Deasserted to PD Drive
WRITE# Deasserted to Command
PBDIR Set to Command
PD Hi-Z to Command Asserted
Asserted to Command Asserted
WAIT# Deasserted to Command Deasserted
Time out
190
20
30
195
180
12
PD Valid to WAIT# Deasserted
PD Hi-Z to WAIT# Deasserted
0
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11.3.5 EPP Data or Address Write Cycle Timing Parameters
PARAMETER
SYM.
MIN.
40
MAX.
UNIT
nS
Ax Valid to IOW# Asserted
SD Valid to Asserted
IOW# Deasserted to Ax Invalid
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
10
10
0
10
40
0
60
0
0
60
60
0
0
10
5
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
µS
nS
nS
WAIT# Deasserted to IOCHRDY Deasserted
Command Asserted to WAIT# Deasserted
IOW# Deasserted to IOW# or IOR# Asserted
IOCHRDY Deasserted to IOW# Deasserted
WAIT# Asserted to Command Asserted
IOW# Asserted to WAIT# Asserted
PBDIR Low to WRITE# Asserted
WAIT# Asserted to WARIT# Asserted
WAIT# Asserted to WRITE# Change
IOW# Asserted to PD Valid
WAIT# Asserted to PD Invalid
PD Invalid to Command Asserted
IOW# to Command Asserted
WAIT# Asserted to Command Asserted
WAIT# Deasserted to Command Deasserted
Command Asserted to WAIT# Deasserted
Time out
24
160
70
185
185
50
35
210
190
10
60
60
0
10
0
0
12
Command Deasserted to WAIT# Asserted
IOW# Deasserted to WRITE# Deasserted and PD
invalid
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W83977EF
11.3.6 Parallel Port FIFO Timing Parameters
PARAMETER
SYMBOL
MIN.
600
MAX.
UNIT
nS
DATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
DATA Hold from nSTROBE Inactive
BUSY Inactive to PD Inactive
BUSY Inactive to nSTROBE Active
nSTROBE Active to BUSY Active
t1
t2
t3
t4
t5
t6
600
450
80
nS
nS
nS
nS
nS
680
500
11.3.7 ECP Parallel Port Forward Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
nAUTOFD Valid to nSTROBE Asserted
PD Valid to nSTROBE Asserted
BUSY Deasserted to nAUTOFD Changed
BUSY Deasserted to PD Changed
nSTROBE Deasserted to BUSY Deasserted
BUSY Deasserted to nSTROBE Asserted
nSTROBE Asserted to BUSY Asserted
BUSY Asserted to nSTROBE Deasserted
t1
t2
t3
t4
t5
t6
t7
t8
0
0
80
80
0
80
0
80
60
60
180
180
nS
nS
nS
nS
nS
nS
nS
nS
200
180
11.3.8 ECP Parallel Port Reverse Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
PD Valid to nACK Asserted
t1
t2
t3
t4
t5
t6
0
0
0
0
80
80
nS
nS
nS
nS
nS
nS
nAUTOFD Deasserted to PD Changed
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK Deasserted
nACK Deasserted to nAUTOFD Asserted
PD Changed to nAUTOFD Deasserted
200
200
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Revision 1.1
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11.3.9 KBC Timing Parameters
NO.
T1
T2
T3
T4
T5
T6
T7
T8
DESCRIPTION
MIN.
0
0
20
20
0
0
50
0
MAX.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
µS
µS
µS
µS
µS
µS
mS
µS
nS
Address Setup Time from WRB
Address Setup Time from RDB
WRB Strobe Width
RDB Strobe Width
Address Hold Time from WRB
Address Hold Time from RDB
Data Setup Time
Data Hold Time
T9
Gate Delay Time from WRB
RDB to Drive Data Delay
RDB to Floating Data Delay
Data Valid After Clock Falling (SEND)
K/B Clock Period
10
30
40
20
4
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
0
20
10
4
20
2
K/B Clock Pulse Width
Data Valid Before Clock Falling (RECEIVE)
K/B ACK After Finish Receiving
RC Fast Reset Pulse Delay (8 Mhz)
RC Pulse Width (8 Mhz)
Transmit Timeout
3
2
6
Data Valid Hold Time
0
83
30
30
5
167
50
50
Input Clock Period (6−12 Mhz)
Duration of CLK inactive
Duration of CLK active
µS
µS
µS
Time from inactive CLK transition, used to time when
25
the auxiliary device sample DATA
T25
T26
T27
T28
T29
Time of inhibit mode
Time from rising edge of CLK to DATA transition
Duration of CLK inactive
Duration of CLK active
Time from DATA transition to falling edge of CLK
100
5
30
30
5
300
T28-5
50
50
25
µS
µS
µS
µS
µS
11.3.10 GPIO Timing Parameters
Publication Release Date: April 2003
Revision 1.1
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W83977EF
SYMBOL
tWGO
PARAMETER
Write data to GPIO update
MIN.
MIN.
MAX.
300(Note 1)
UNIT
ns
Note : Refer to Microprocessor Interface Timing for Read Timing.
11.3.11 Keyboard/Mouse Timing Parameters
SYMBOL
tSWL
PARAMETER
PANSWIN# falling edge to PANSWOUT# falling edge
MAX.
20
UNIT
ns
tSWH
50
ns
PANSWIN# falling edge to PANSWOUT# Hi-Z
tWKUPD
KCLK/MCLK falling edge to PANSWOUT# falling
200
ns
edge delay
tWKUPW
0.5
1
sec
PANSWOUT# active pulse width
Publication Release Date: April 2003
Revision 1.1
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W83977EF
12.0 TIMING WAVEFORMS
12.1 FDC
Write Date
Processor Read Operation
WD#
SA0-SA9
AEN
TWDD
CS#
DACK#
TAR
TRA
TDH
TRR
IOR#
Index
TFD
TDF
D0-D7
IRQ
INDEX#
TR
TIDX
TIDX
Processor Write Operation
Terminal Count
SA0-SA9
AEN
TC
TAW
TWA
DACK#
IOW#
TTC
TWW
TDW
TWD
Reset
D0-D7
IRQ
RESET
TWI
TRST
DMA Operation
Drive Seek operation
TAM
DRQ
DIR#
TMCY
TAA
DACK#
TMA
TSTP
TSTD
TDST
TMRW
IOW# or
IOR#
STEP
TMW (IOW#)
TMR (IOR#)
TSC
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12.2 UART/Parallel
Receiver Timing
SIN
(RECEIVER
INPUT DATA)
STAR
DATA BITS
(5-8)
PARITY
STOP
TSINT
IRQ3 or IRQ4
IOR
(READ RECEIVER
TRINT
BUFFER REGISTER)
Transmitter Timing
SERIAL OUT
(SOUT)
STAR
STAR
DATA
(5-8)
PARITY
STOP
(1-2)
THRS
THR
TSTI
IRQ3 or IRQ4
THR
IOW
(WRITE THR)
TSI
TIR
IOR
(READ TIR)
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12.2.1 Modem Control Timing
MODEM Control Timing
IOW#
(WRITE MCR)
│
│
│
│
│
│
│
TMWO
│
TMWO
→
→
←
←
│
│
│
│
RTS#,DTR#
│
│
│
│
?
│
│
│
│
│
│
│
CTS#,DSR#
DCD#
TSIM
→
TSIM
←
│
←
│
│
→
│
│
│
│
│
│
│
│
│
│
│
│
│
IRQ3 or
│
│
│
←
IRQ4
│
│
│
│
│
TRIM
TRIM
←
→
│
→
IOR#
│
│
│
(READ MSR)
TSIM
→
│
│
←
│
│
│
│
│
│
?
RI#
Printer Interrupt Timing
│
│
│
│
│
│
│
│
│
│
│
ACK#
IRQ7
│
│
│
│
│
TLAD
TLID
│
→
←
→
←
│
│
│
│
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12.3 Parallel Port
12.3.1 Parallel Port Timing
IOW#
t1
INIT#, STROBE#
AUTOFD, SLCTIN#
PD<0:7>
ACK#
t2
IRQ (SPP)
IRQ
(EPP or ECP)
t3
t4
nFAULT
(ECP)
ERROR#
(ECP)
t5
t2
t4
IRQ
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12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)
t3
A<0:10>
t1
t2
t4
IOR
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE#
PD<0:7>
t16
t18
t19
t20
t17
t21
t22
t23
t25
t24
ADDRSTB
DATASTB
t27
t28
t26
WAIT#
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12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)
t3
t4
A10-A0
SD<0:7>
t5
t1
t2
t6
IOW#
IOCHRDY
t7
t8
t9
t10
t12
t14
t11
WRITE#
PD<0:7>
t13
t15
t16
t17
t18
DATAST#
ADDRSTB#
t19
t21
t20
WAIT#
PBDIR
t22
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12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)
t3
A<0:10>
t1
t2
t4
IOR
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE#
PD<0:7>
t16
t18
t19
t20
t17
t21
t24
t22
t23
t25
ADDRSTB
DATASTB
t26
t28
t27
WAIT#
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12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)
t3
t4
A10-A0
SD<0:7>
t5
t1
t2
t6
IOW#
t7
t8
IOCHRDY
t9
t10
t22
t22
t11
WRITE#
PD<0:7>
t13
t15
t16
t17
t18
DATAST#
ADDRSTB#
t19
t20
WAIT#
12.3.6 Parallel Port FIFO Timing
t4
>|
>|
t3
PD<0:7>
t1
t2
t5
>|
>
>|
nSTROBE
t6
>|
BUSY
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12.3.7 ECP Parallel Port Forward Timing
t3
t4
nAUTOFD
PD<0:7>
t1
t2
t6
t8
nSTROBE
t5
t5
t7
BUSY
12.3.8 ECP Parallel Port Reverse Timing
t2
PD<0:7>
t1
t3
t4
nACK
t5
t5
t6
nAUTOFD
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Revision 1.1
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12.4 KBC
12.4.1 Write Cycle Timing
A2, CSB
WRB
T1
T5
T3
ACTIVE
T7
T8
D0~D7
DATA IN
T9
GA20
OUTPUT PORT
T17
T18
FAST RESET PULSE RC
FE COMMAND
12.4.2 Read Cycle Timing
A2,CSB
AEN
T2
T6
T4
RDB
ACTIVE
T10
T11
D0-D7
DATA OUT
12.4.3 Send Data to K/B
CLOCK
(KCLK)
T12
T13
D4
T19
T16
T14
D3
SERIAL DATA
D5
START
D1
D2
D0
D6
D7
P
STOP
(KDAT)
12.4.4 Receive Data from K/B
Publication Release Date: April 2003
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W83977EF
CLOCK
(KCLK)
T14
D3
T13
D5
T15
SERIAL DATA
(T1)
START
T20
D1
D2
D4
D0
D6
D7
P
STOP
12.4.5 Input Clock
CLCOLCOKCK
T21
12.4.6 Send Data to Mouse
MCLK
T25
T23
T24
T22
MDAT
START
D5
D1
D2
D3
D4
D0
D6
D7
P
Bit
STOP
Bit
12.4.7 Receive Data from Mouse
MCLK
T29
T26
D1
T27
T28
D3
MDAT
D5
START
D2
D4
D0
D6
D7
P
STOP
Bit
Publication Release Date: April 2003
Revision 1.1
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W83977EF
12.5 GPIO Write Timing Diagram
VALID
VALID
A0-A15
IOW#
D0-7
GPIO10-17
PREVIOUS STATE
VALID
GPIO20-25
tWGO
12.6 Master Reset (MR) Timing
Vcc
MR
tVMR
12.7 Keyboard/Mouse Wake-up Timing
KCLK
MCLK
PANSWIN#
tWKUPW
PANSWOUT#
HI-Z
tWKUPD
tSWZ
tSWL
Publication Release Date: April 2003
Revision 1.1
-140 -
W83977EF
13.0 APPLICATION CIRCUITS
13.1 Parallel Port Extension FDD
JP13
13
WE2#/SLCT
25
12
JP 13A
WD2#/PE
24
DCH2#
HEAD2#
RDD2#
WP2#
TRK02#
WE2#
WD2#
STEP2#
DIR2#
MOB2#
34
32
30
28
26
24
22
20
18
16
14
12
10
8
33
31
29
27
25
23
21
19
17
15
13
11
9
11
MOB2#/BUSY
23
10
22
9
DSB2#/ACK
PD7
21
8
PD6
PD5
20
7
19
6
DSB2#
IDX2#
DCH2#/PD4
RDD2#/PD3
STEP2#/SLIN#
WP2#/PD2
DIR2#/INIT#
TRK02#/PD1
HEAD2#/ERR#
IDX2#/PD0
RWC2#/AFD#
STB#
18
5
17
4
7
6
5
16
3
4
2
3
RWC2#
1
15
2
EXT FDC
14
1
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
Publication Release Date: April 2003
Revision 1.1
-141 -
W83977EF
13.2 Parallel Port Extension 2FDD
JP13
13
25
12
WE2#/SLCT
JP 13A
WD2#/PE
DCH2#
HEAD2#
RDD2#
WP2#
24
34
32
30
28
26
24
22
20
18
16
14
12
10
8
33
31
29
27
25
23
21
19
17
15
13
11
9
11
MOB2#/BUSY
23
10
22
9
DSB2#/ACK
TRK02#
DSA2#/PD7
MOA2#/PD6
WE2#
WD2#
STEP2#
DIR2#
21
8
20
7
19
6
PD5
MOB2#
DSA2#
DSB2#
MOA2#
IDX2#
DCH2#/PD4
RDD2#/PD3
STEP2#/SLIN#
WP2#/PD2
DIR2#/INIT#
TRK02#/PD1#
HEAD2#/ERR#
IDX2#/PD0
RWC2#/AFD#
STB#
18
5
7
17
4
6
5
4
3
16
3
RWC2#
2
1
15
2
EXT FDC
14
1
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
Publication Release Date: April 2003
Revision 1.1
-142 -
W83977EF
13.3 Four FDD Mode
74LS139
G1
A1
B1
7407(2)
W83977EF
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
DSA#
DSA#
DSB#
DSB#
DSC#
DSD#
MOA#
MOA#
MOB#
MOB#
MOC#
MOD#
G2
A2
B2
2Y2
2Y3
14.0 ORDERING INFORMATION
PART NO.
W83977EF-PW
W83977EF-AW
KBC FIRMWARE
REMARKS
with OnNow / security keyboard Wake-Up
with OnNow / security keyboard Wake-Up
Phoenix MultiKey/42TM
AMIKEYTM-2
15.0 HOW TO READ THE TOP MARKING
Example: The top marking of W83977EF-AW
inbond
W83977EF-AW
AM. MEGA. 87-96
821A2B282012345
1st line: Winbond logo
2nd line: the type number: W83977EF-AW
3rd line: the source of KBC F/W -- American Megatrends IncorporatedTM
4th line: the tracking code
821 A 2 C 282012345
821: packages made in '98, week 21
A: assembly house ID; A means ASE, S means SPIL.... etc.
2: Winbond internal use.
B: IC revision; A means version A, B means version B
282012345: wafer production series lot number
Publication Release Date: April 2003
Revision 1.1
-143 -
W83977EF
16.0 PACKAGE DIMENSIONS
(128-pin PQFP)
Dimension in mm
Dimension in inch
HE
E
Symbol
Min
0.25
2.57
Nom
0.35
Max
0.45
2.87
Min Nom Max
65
102
1
0.010
0.014
0.018
A
2.72
0.101
0.107
0.113
A
2
64
103
0.10
0.10
0.20
0.15
0.30
0.20
0.004 0.008 0.012
0.004 0.006 0.008
0.547 0.551 0.555
b
c
13.90
19.90
14.00
20.00
0.50
14.10
20.10
D
0.783 0.787
0.020
0.791
E
e
HD
D
H
HE
L
D
17.20
23.20
0.669
0.677 0.685
0.921
17.40
23.40
0.95
17.00
23.00
0.905 0.913
0.80
1.60
0.025 0.031 0.037
0.65
39
128
0.063
0.003
1
L
0.08
7
y
0
1
38
e
b
0
7
0
c
Note:
A
1.Dimension D & E do not include interlead
flash.
2
A
2.Dimension b does not include dambar
protrusion/intrusion
.
3.Controlling dimension : Millimeter
1
A
See Detail F
Seating Plane
L
y
4.General appearance spec. should be based
L 1
5.oPn fCinaBl vliasuyaol iunstppecletioanssepeuc.se the "mm".
Detail F
Headquarters
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
Science-Based Industrial Park
Hsinchu, Taiwan
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
TEL: 886-35-770066
FAX: 886-35-789467
TEL: 852-27516023-7
FAX: 852-27552064
FAX: 1-408-9436668
www: http://www.winbond.com.tw/
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
original owners.
Publication Release Date: April 2003
-144 -
Revision 1.1
相关型号：
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