W83977F [WINBOND]
PLUG & PLAY 1.0A COMPLIANT; PLUG &PLAY 1.0A柔顺![W83977F](http://pdffile.icpdf.com/pdf1/p00056/img/icpdf/W83977_295733_icpdf.jpg)
型号: | W83977F |
厂家: | ![]() |
描述: | PLUG & PLAY 1.0A COMPLIANT |
文件: | 总181页 (文件大小:2540K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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WINBOND I/O
W83977F
&
W83977AF
W83977F/ AF Data Sheet Revision History
Pages
Dates
Versio Versio
Main Contents
n
n
on
Web
1
2
n.a.
01/20/97
01/27/97
0.50
0.51
First publication
2,3,6,8,9,10,
Spec. Correction; typo correction
122,126,128-
132,134,138,168
3
4
5
6
7
8
117-125,127
9,10,120-122
127,135,136,169
VIII,IX,166-169
P118
01/30/97
02/13/97
03/03/97
05/24/97
7/15/97
0.52
0.53
0.54
0.55
0.56
0.57
Register Correction; pages rearranging.
Spec. Correction; typo correction
Spec. Correction; typo correction
Add section 15.0; pages rearranging.
CR24: Pin 22àPin1
53,54,58,61,62,
63,65,124,125
11/17/97
Register Correction
9
1,3,11,52,91,105, 03/10/97
109,110,111,113,
114,115,119,124,
130,131,148
0.58
Typo correction and data calibrated
10
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Winbond for any damages resulting from such
improper use or sales.
W83977F/ W83977AF
PRELIMINARY
TABLE OF CONTENTS
1. PIN DESCRIPTION........................................................................................................6
1.1 HOST INTERFACE....................................................................................................................................6
1.2 ADVANCED POWER MANAGEMENT....................................................................................................8
1.3 SERIAL PORT INTERFACE......................................................................................................................9
1.4 INFRARED INTERFACE.........................................................................................................................10
1.5 MULTI-MODE PARALLEL PORT ..........................................................................................................11
1.6 FDC INTERFACE ....................................................................................................................................16
1.7 KBC INTERFACE....................................................................................................................................17
1.8 RTC INTERFACE ....................................................................................................................................17
1.9 POWER PINS...........................................................................................................................................17
2. FDC FUNCTIONAL DESCRIPTION...........................................................................18
2.1 W83977F/ AF FDC...................................................................................................................................18
2.1.1 AT interface........................................................................................................................................18
2.1.2 FIFO (Data) .......................................................................................................................................18
2.1.3 Data Separator...................................................................................................................................19
2.1.4 Write Precompensation.......................................................................................................................19
2.1.5 Perpendicular Recording Mode..........................................................................................................19
2.1.6 FDC Core...........................................................................................................................................20
2.1.7 FDC Commands .................................................................................................................................20
2.2 REGISTER DESCRIPTIONS....................................................................................................................31
2.2.1 Status Register A (SA Register) (Read base address + 0) ....................................................................31
2.2.2 Status Register B (SB Register) (Read base address + 1) ....................................................................33
2.2.3 Digital Output Register (DO Register) (Write base address + 2).........................................................35
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)...............................................................35
2.2.5 Main Status Register (MS Register) (Read base address + 4)..............................................................36
2.2.6 Data Rate Register (DR Register) (Write base address + 4)................................................................36
2.2.7 FIFO Register (R/W base address + 5) ...............................................................................................38
2.2.8 Digital Input Register (DI Register) (Read base address + 7) .............................................................40
Publication Release Date:March 1998
-I -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2.2.9 Configuration Control Register (CC Register) (Write base address + 7).............................................42
3. UART PORT ..................................................................................................................43
3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)............................43
3.2 REGISTER ADDRESS .............................................................................................................................43
3.2.1 UART Control Register (UCR) (Read/Write).......................................................................................43
3.2.2 UART Status Register (USR) (Read/Write)..........................................................................................45
3.2.3 Handshake Control Register (HCR) (Read/Write)...............................................................................46
3.2.4 Handshake Status Register (HSR) (Read/Write) ..................................................................................47
3.2.5 UART FIFO Control Register (UFR) (Write only)...............................................................................48
3.2.6 Interrupt Status Register (ISR) (Read only).........................................................................................48
3.2.7 Interrupt Control Register (ICR) (Read/Write)....................................................................................49
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)...................................................................50
3.2.9 User-defined Register (UDR) (Read/Write).........................................................................................50
4. INFRARED (IR) PORT .................................................................................................52
4.1 IR REGISTER DESCRIPTION.................................................................................................................52
4.2 SET0-LEGACY/ADVANCED IR CONTROL AND STATUS REGISTERS.............................................53
4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) ......................................53
4.2.2 Set0.Reg1 - Interrupt Control Register (ICR)......................................................................................53
4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)........................................54
4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): ........................................................57
4.2.5 Set0.Reg4 - Handshake Control Register (HCR).................................................................................58
4.2.6 Set0.Reg5 - IR Status Register (USR)..................................................................................................59
4.2.7 Set0.Reg6 - Reserved..........................................................................................................................59
4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR) ...............................................................................59
4.3 SET1 - LEGACY BAUD RATE DIVISOR REGISTER ............................................................................60
4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ...........................................................................61
4.3.2 Set1.Reg 2~7 ......................................................................................................................................61
4.4 SET2 - INTERRUPT STATUS OR IR FIFO CONTROL REGISTER (ISR/UFR)......................................61
4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) ..............................................................61
4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)...............................................................................61
4.4.3 Reg3 - Sets Select Register (SSR)........................................................................................................62
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)...............................................................................62
Publication Release Date:March 1998
-II -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) ....................................................................64
4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only).........................................................................64
4.5 SET3 - VERSION ID AND MAPPED CONTROL REGISTERS...............................................................64
4.5.1 Reg0 - Advanced IR ID (AUID) ..........................................................................................................64
4.5.2 Reg1 - Mapped IR Control Register (MP_UCR) .................................................................................64
4.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR)........................................................................65
4.5.4 Reg3 - Sets Select Register (SSR)........................................................................................................65
4.6 SET4 - TX/RX/TIMER COUNTER REGISTERS AND IR CONTROL REGISTERS. ..............................65
4.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)...........................................................................65
4.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL) .......................................................................................65
4.6.3 Set4.Reg3 - Set Select Register (SSR)..................................................................................................66
4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) ................................................................66
4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) ....................................................................66
4.7 SET 5 - FLOW CONTROL AND IR CONTROL AND FRAME STATUS FIFO REGISTERS .................67
4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL).............................67
4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD).........................................................................67
4.7.3 Set5.Reg3 - Sets Select Register (SSR) ................................................................................................68
4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)..........................................................................68
4.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO)..............................................................................68
4.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU)......69
4.8 SET6 - IR PHYSICAL LAYER CONTROL REGISTERS.........................................................................69
4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)........................................................................70
4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width ...........................................................................70
4.8.3 Set6.Reg2 - SIR Pulse Width...............................................................................................................71
4.8.4 Set6.Reg3 - Set Select Register ...........................................................................................................71
4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU)..............................................71
4.9 SET7 - REMOTE CONTROL AND IR MODULE SELECTION REGISTERS.........................................72
4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC).................................................................72
4.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC).............................................................74
4.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)...................................................................74
4.9.4 Set7.Reg3 - Sets Select Register (SSR) ................................................................................................75
4.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) ............................................................76
4.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) ............................................................76
Publication Release Date:March 1998
-III -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) ............................................................76
4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)...................................................................77
5. PARALLEL PORT........................................................................................................78
5.1 PRINTER INTERFACE LOGIC ...............................................................................................................78
5.2 ENHANCED PARALLEL PORT (EPP)....................................................................................................79
5.2.1 Data Swapper.....................................................................................................................................79
5.2.2 Printer Status Buffer...........................................................................................................................80
5.2.3 Printer Control Latch and Printer Control Swapper ...........................................................................80
5.2.4 EPP Address Port...............................................................................................................................81
5.2.5 EPP Data Port 0-3 .............................................................................................................................82
5.2.6 Bit Map of Parallel Port and EPP Registers.......................................................................................82
5.2.7 EPP Pin Descriptions.........................................................................................................................83
5.2.8 EPP Operation ...................................................................................................................................83
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .........................................................................84
5.3.1 ECP Register and Mode Definitions ...................................................................................................84
5.3.2 Data and ecpAFifo Port......................................................................................................................85
5.3.3 Device Status Register (DSR)..............................................................................................................85
5.3.4 Device Control Register (DCR) ..........................................................................................................86
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.....................................................................................87
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................................87
5.3.7 tFifo (Test FIFO Mode) Mode = 110 ..................................................................................................87
5.3.8 cnfgA (Configuration Register A) Mode = 111....................................................................................87
5.3.9 cnfgB (Configuration Register B) Mode = 111....................................................................................87
5.3.10 ecr (Extended Control Register) Mode = all .....................................................................................88
5.3.11 Bit Map of ECP Port Registers .........................................................................................................89
5.3.12 ECP Pin Descriptions.......................................................................................................................90
5.3.13 ECP Operation.................................................................................................................................91
5.3.14 FIFO Operation................................................................................................................................91
5.3.15 DMA Transfers.................................................................................................................................92
5.3.16 Programmed I/O (NON-DMA) Mode ................................................................................................92
5.4 EXTENSION FDD MODE (EXTFDD).....................................................................................................92
5.5 EXTENSION 2FDD MODE (EXT2FDD).................................................................................................92
6. REAL-TIME CLOCK (RTC) AND "ON-NOW" CONTROL ....................................93
Publication Release Date:March 1998
-IV -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
6.1 REGISTER ADDRESS MAP....................................................................................................................93
6.2 UPDATE CYCLE.....................................................................................................................................95
6.3 REGISTERS .............................................................................................................................................96
6.3.1 Register 0Ah.......................................................................................................................................96
6.3.2 Register 0Bh (Read/Write)..................................................................................................................98
6.3.3 Register 0Ch (Read only)....................................................................................................................99
6.3.4 Register D (Read only) .......................................................................................................................99
6.4 "ON-NOW" CONTROL..........................................................................................................................100
6.5 POWER-ON EVENTS............................................................................................................................100
6.6 POWER-OFF EVENTS ..........................................................................................................................100
6.7 REGISTERS ...........................................................................................................................................101
6.7.1 "ON-Now" Register 1 (Bank2 Register 49h).....................................................................................101
6.7.2 "On-Now" Register 2 (Bank2 Register 4Ah) ....................................................................................102
6.7.3 "On-Now" Register 3 (Bank2 Register 4Bh)......................................................................................103
6.7.4 "On-Now" Register 4 (Bank2 Register 4Ch)......................................................................................104
7. KEYBOARD CONTROLLER ....................................................................................105
7.1 OUTPUT BUFFER..................................................................................................................................106
7.2 INPUT BUFFER .....................................................................................................................................106
7.3 STATUS REGISTER..............................................................................................................................106
7.4 COMMANDS .........................................................................................................................................107
7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC......................................................109
7.5.1 KB Control Register (Logic Device 5, CR-F0)..................................................................................109
7.5.2 Port 92 Control Register (Default Value = 0x24)..............................................................................109
8. GENERAL PURPOSE I/O...........................................................................................110
8.1 BASIC I/O FUNCTIONS........................................................................................................................111
8.2 ALTERNATE I/O FUNCTIONS.............................................................................................................113
8.2.1 Interrupt Steering .............................................................................................................................113
8.2.2 Watch Dog Timer Output..................................................................................................................113
8.2.3 Power LED.......................................................................................................................................114
8.2.4 General Purpose Address Decoder ...................................................................................................114
8.2.5 General Purpose Write Strobe ..........................................................................................................114
9. PLUG AND PLAY CONFIGURATION .....................................................................114
9.1 COMPLY PNP........................................................................................................................................115
Publication Release Date:March 1998
-V -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
9.1.1 Wait for Key State ............................................................................................................................115
9.1.2 Sleep State........................................................................................................................................115
9.1.3 Isolation State ..................................................................................................................................115
9.1.4 Configure State.................................................................................................................................115
9.2 COMPATIBLE PNP ...............................................................................................................................116
9.2.1 Extended Function Registers ............................................................................................................116
9.2.2 Extended Functions Enable Registers (EFERs).................................................................................116
9.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs).................116
10. CONFIGURATION REGISTER...............................................................................117
10.1 CHIP (GLOBAL) CONTROL REGISTER ............................................................................................117
10.2 LOGICAL DEVICE 0 (FDC) ................................................................................................................122
10.3 LOGICAL DEVICE 1 (PARALLEL PORT)..........................................................................................126
¢)
10.4 LOGICAL DEVICE 2 (UART A) ......................................................................................................128
10.5 LOGICAL DEVICE 3 (UART B)..........................................................................................................129
10.6 LOGICAL DEVICE 4 (REAL TIME CLOCK)......................................................................................130
10.7 LOGICAL DEVICE 5 (KBC)................................................................................................................131
10.8 LOGICAL DEVICE 6 (IR)....................................................................................................................132
10.9 LOGICAL DEVICE 7 (AUXILIARY I/O PART I)................................................................................134
10.10 LOGICAL DEVICE 8 (AUXILIARY I/O PART II).............................................................................138
11. SPECIFICATIONS.....................................................................................................142
11.1 ABSOLUTE MAXIMUM RATINGS....................................................................................................142
11.2 DC CHARACTERISTICS.....................................................................................................................142
11.3 AC CHARACTERISTICS.....................................................................................................................146
11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. .................................................................146
11.3.2 UART/Parallel Port........................................................................................................................148
11.3.3 Parallel Port Mode Parameters ......................................................................................................148
11.3.4 EPP Data or Address Read Cycle Timing Parameters ....................................................................149
11.3.5 EPP Data or Address Write Cycle Timing Parameters....................................................................150
11.3.6 Parallel Port FIFO Timing Parameters...........................................................................................151
11.3.7 ECP Parallel Port Forward Timing Parameters..............................................................................151
11.3.8 ECP Parallel Port Reverse Timing Parameters...............................................................................151
11.3.9 KBC Timing Parameters.................................................................................................................152
Publication Release Date:March 1998
-VI -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
11.3.10 GPIO, ACPI, ROM Interface Timing Parameters..........................................................................153
12. TIMING WAVEFORMS ...........................................................................................154
12.1 FDC ......................................................................................................................................................154
12.2 UART/PARALLEL...............................................................................................................................155
12.2.1 Modem Control Timing...................................................................................................................156
12.3 PARALLEL PORT................................................................................................................................157
12.3.1 Parallel Port Timing.......................................................................................................................157
12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)......................................................................158
12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)......................................................................159
12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)......................................................................160
12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)......................................................................161
12.3.6 Parallel Port FIFO Timing .............................................................................................................161
12.3.7 ECP Parallel Port Forward Timing ................................................................................................162
12.3.8 ECP Parallel Port Reverse Timing .................................................................................................162
12.4 KBC......................................................................................................................................................163
12.4.1 Write Cycle Timing.........................................................................................................................163
12.4.2 Read Cycle Timing .........................................................................................................................163
12.4.3 Send Data to K/B............................................................................................................................163
12.4.4 Receive Data from K/B...................................................................................................................164
12.4.5 Input Clock.....................................................................................................................................164
12.4.6 Send Data to Mouse........................................................................................................................164
12.4.7 Receive Data from Mouse...............................................................................................................164
12.5 GPIO WRITE TIMING DIAGRAM......................................................................................................165
12.6 MASTER RESET (MR) TIMING .........................................................................................................165
12.7 ACPI.....................................................................................................................................................165
PANSW
PSCTRL
12.7.1
12.7.2
12.7.3
Trigger and
Timing.....................................................................................165
PSCTRL
Timing.....................166
RIA RIB
,
, KLCK, MCLK, PWAKIN1, PWAKIN2 Trigger and
PSCTRL
PHRI
Trigger and
Timing..........................................................................................166
13. APPLICATION CIRCUITS.......................................................................................166
13.1 PARALLEL PORT EXTENSION FDD.................................................................................................166
13.2 PARALLEL PORT EXTENSION 2FDD...............................................................................................167
13.3 FOUR FDD MODE...............................................................................................................................167
Publication Release Date:March 1998
-VII -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
14. ORDERING INFORMATION ..................................................................................168
15. HOW TO READ THE TOP MARKING ..................................................................168
16. PACKAGE DIMENSIONS........................................................................................169
Publication Release Date:March 1998
-VIII -
Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
GENERAL DESCRIPTION
This data sheet covers two products: W83977F, and W83977AF whose pin assignment, and most of
the functions are the same. W83977AF is an advanced version of W83977F featuring the FIR
function.
’ s
W83977F/ AF is an evolving product from Winbond most popular I/O chip W83877F --- which
integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plug-
and-play registers in one chip --- plus additional powerful features: ACPI, 8042 keyboard controller
with PS/2 mouse support, Real Time Clock, 14 general purpose I/O ports, full 16-bit address
decoding, TV remote IR (Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80
protocols). In addition, W83977AF provides the functions of IrDA 1.1 (MIR for 1.152M bps or FIR for
4M bps).
The disk drive adapter functions of W83977F/ AF include a floppy disk drive controller compatible
with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic,
data rate selection, clock generator, drive interface control logic, and interrupt/ DMA logic. The wide
range of functions integrated onto the W83977F/ AF greatly reduces the number of components
required for interfacing with floppy disk drives. The W83977F/ AF supports up to four 360K, 720K,
1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s,
and 2 Mb/s.
The W83977F/ AF provides two high-speed serial communication ports (UARTs), one of which
supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a
programmable baud rate generator, complete modem control capability, and a processor interrupt
system. Both UARTs provide legacy speed with baud rate 115.2k and provide advanced speed with
baud rate 230k, 460k, and 921k bps which support higher speed modems. W83977AF alone
provides independent 3rd UART (32-byte FIFO) dedicated for IR function.
The W83977F/ AF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP)
and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer
port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one
or two external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95TM, which makes system resource allocation more efficient than ever.
W83977F/ AF provides functions that comply with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through SMI or SCI
function pins. W83977F/ AF also has auto power management to reduce power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable
ROM and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEYTM -2,
Phoenix MultiKey/42TM, or customer code.
The W83977F/ AF provides a set of flexible I/O control functions to the system designer through a set
of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a pre-defined alternate function.
W83977F/ AF is made to fully comply with MicrosoftTM PC97 Hardware Design Guide. IRQs,
DMAs, and I/O space resource are flexible to adjust to meet ISA PnP requirement. Full 16-bit
address decoding is also provided. Moreover W83977F/ AF is made to meet the specification of
‘ s
PC97 requirement in the power management: ACPI and DPM (Device Power Management).
Publication Release Date: March 1998
-1-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
FEATURES
General
· Plug & Play 1.0A Compliant
· Support 13 IRQs, 4 DMA channels, full 16-bit addresses decoding
· Capable of ISA Bus IRQ Sharing
· Compliant with Microsoft PC97 Hardware Design Guide
·
Support DPM (Device Power Management), ACPI
· Programmable configuration settings
· 24 or 14.318 Mhz clock input
FDC
· Compatible with IBM PC AT disk drive systems
· Variable write pre-compensation with track selectable capability
· Support vertical recording format
· DMA enable logic
· 16-byte data FIFOs
· Support floppy disk drives and tape drives
· Detects all overrun and underrun conditions
· Built-in address mark detection circuit to simplify the read electronics
· FDD anti-virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive)
· Support up to four 3.5-inch or 5.25-inch floppy disk drives
· Completely compatible with industry standard 82077
· 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
·
Support 3-mode FDD, and its Win95 driver
UART
· Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
· 3rd UART with 32-byte send/receive FIFO is supported for IR function [W83977AF only]
· MIDI compatible
· Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
· Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
· Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (216-1)
· Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz
Publication Release Date: March 1998
-2- Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Infrared
· Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
· Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
· Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol [W83977AF only]
--- Single DMA channel for transmitter or receiver
--- 3rd UART with 32-byte FIFO is supported in both TX/RX transmission [W83977AF only]
--- 8-byte status FIFO is supported to store received frame status (such as overrun CRC error, etc.)
· Support auto-config SIR and FIR [W83977AF only]
Parallel Port
· Compatible with IBM parallel port
· Support PS/2 compatible bi-directional parallel port
· Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification
· Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification
· Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and
B through parallel port
· Enhanced printer port back-drive current protection
Advanced Power Management (APM) Controlling
· Power turned on when RTC reaches a preset date and time
· Power turned on when a ring pulse or pulse train is detected on the PHRI, or when a high to low
transition on PWAKIN1, or PWAKIN2 input signals
· Power turned on when PANSW input signal indicates a switch on event
· Power turned off when PANSW input signal indicates a switch off event
· Power turned off when a fail-safe event occurs (power-save mode detected but system is hung up)
· Power turned off when software issues a power off command
Keyboard Controller
· 8042 based with optional F/W from AMIKKEYTM-2, Phoenix MultiKey/42TM or customer code
with 2K bytes of programmable ROM, and 256 bytes of RAM
· Asynchronous Access to Two Data Registers and One status Register
·
Software compatibility with the 8042 and PC87911 microcontrollers
· Support PS/2 mouse
· Support port 92
· Support both interrupt and polling modes
·
Fast Gate A20 and Hardware Keyboard Reset
· 8 Bit Timer/ Counter; support binary and BCD arithmetic
· 6, 8, 12, or 16 Mhz operating frequency (16 Mhz available only if input clock rate = 14.318 Mhz)
Publication Release Date: March 1998
-3 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Real Time Clock
·
27 bytes of clock, On-Now, and control/status register (14 bytes in Bank 0 and 13 bytes in Bank
2); 242 bytes of general purpose RAM
·
·
·
·
·
·
·
BCD or Binary representation of time, calendar, and alarm registers
Counts seconds, minutes, hours, days of week, days of month, month, year, and century
12-hour/ 24-hour clock with AM/PM in 12-hour mode
Daylight saving time option; automatic leap-year adjustment
Dedicated alarm (Alarm B) for On-Now function
Programmable delay-time between panel switch off and power supply control
Software control power-off; various and maskable events to activate system Power-On
·
System Management Interrupt (SMI ) for panel switch power-off event
General Purpose I/O Ports
· 14 programmable general purpose I/O ports; 6 dedicate, 8 optional
· General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog
timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control
I/O pins.
Package
· 128-pin PQFP
Publication Release Date: March 1998
-4-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
PIN CONFIGURATION
/
/
P
S
C
T
P
A
N
S
/
P
S
H
M R
L
W
,
I
G
P
2
I
I
I I
,
,
,
R R R I
I I I I I I I
G
G
/
K
G
P
2
M
C
L
/
Q Q Q R R R R R R R R
1 1 1 Q Q Q Q Q Q Q Q
2 1 0 1 3 4 5 6 7 8 9
A V A A A
A
V
S
B
A
P P
2 2
3 2
V
C R
R
I
1
S 1 1 1
1 A A A A A A A A A
C
1
I
L
A
0
5
S 4 3 2 1 C 0 9 8 7 6 5 4 3 2 1
0
1
K B
K
A
9
9
8
7
7
6
6
6
1 1
9
9 8 8 8 8
8
7 7
7
7 7
7
7
6
1 9
0 9
0
9 9 9 9 9
8
8 8
7
6
5
8
4
0
8 7
1
6 5
7 6
4 3
0 9
6
0
6 5 4 3 2
0 9 8 7
3 2 1 0 9 8
5
2 1
8 7
1
2
64
103
104
IRQ14/GP14
IRQ15/GP15
VBAT
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
XTAL1
VSS
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
IOR
IOW
AEN
XTAL2
MDATA
KDATA
IOCHRDY
KBLOCK/GP13
KBRST/GP12
GA20/GP11
VCC
D0
D1
D2
D3
DCDB
SOUTB
SINB
D4
D5
VCC
D6
D7
MR
DTRB/ENCPNP
RTSB/PENPLL
DSRB
CTSB
DCDA
DACK0/GP16
VSS
DRQ0/GP17
DACK1
SOUTA/PENKRC
SINA
122
123
124
125
126
127
DRQ1
DTRA/PNPCSV
RTSA/HEFRAS
DSRA
DACK2
DRQ2
CTSA
CIRRX/GP24
IRRXH/IRSL0
DACK3
DRQ3
TC
128
2
3
1
2
8
1 1 1 1 1
2 2 2 2 2 2
2 3 3 3
3
3
1 1 1 1
2
1
3
3
8
3
7
4
/
7
3
1 2 3
5
9 0
6
8 9
4 5 6 7 8
2 3 4 5 6 7
9 0 1 2
5
4
6
0 1 2 3
P
V
P
D
0
D
R
V
D
E
N
/
/
P
D
1
/
I
R
I
D
R
V
D
E
N
0
/
/
/
/
S
L
/
P P
P
P P
/
/ /
/
/
/
V
C
L
K
I
/
/
/
W
/
/
B
U
S
Y
P
E
C
M
O
B
I
D
S I
R
T
X
W
S D
M
O
A
A D
D D D D
E A
S
W
D
D
S
A
S
D H
T
D
S
B
R
N
D
E
X
L
E
T I
C
T
C
C 7 6
4
3 2
N R F T R
S 5
S E P R
D
I
E
R
K
I
D B
R X
K
A
A
K
0
A
T
A
T
N
N
P
C
H
G
D
1
,
G
P
1
0
Publication Release Date: March 1998
-5 - Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O6t
- TTL level bi-directional pin with 6 mA source-sink capability
- TTL level bi-directional pin with 8 mA source-sink capability
- CMOS level bi-directional pin with 8 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability
- CMOS level bi-directional pin with 12 mA source-sink capability
I/O8t
I/O8
I/O12t
I/O12
I/O16u
- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor
I/O24t
OUT8t
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12
OD24
INt
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- TTL level input pin
INc
- CMOS level input pin
INcu
INcs
INts
- CMOS level input pin with internal pull-up resitor
- CMOS level Schmitt-triggered input pin
- TTL level Schmitt-triggered input pin
INtsu
- TTL level Schmitt-triggered input pin with internal pull-up resistor
1.1 Host Interface
SYMBOL
A0- A10
A11-A14
A15
PIN
I/O
INt
FUNCTION
System address bus bits 0-10
74-84
86-89
91
INt
System address bus bits 11-14
System address bus bit 15
System data bus bits 0-5
System data bus bits 6-7
CPU I/O read signal
INt
109-114
116-117
105
I/O12t
I/O12t
INts
D0- D5
D6- D7
IOR
106
INts
CPU I/O write signal
IOW
AEN
107
108
INt
System address bus enable
IOCHRDY
OD24
In EPP Mode, this pin is the IO Channel Ready output to
extend the host read/write cycle.
MR
118
INts
Master Reset. Active high. MR is low during normal
operations.
Publication Release Date: March 1998
-6-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.1 Host Interface, continued
SYMBOL
PIN
I/O
INts
FUNCTION
119
CR2C bit5, 4= 00 (default): DMA Channel 0 Acknowledge
signal.
DACK0
GP16
I/O12t
CR2C bit5, 4= 01: General purpose I/O port 1 bit 6. It can be
configured as a watchdog timer output.
(WDTO)
I/O12t
P15
CR2C bit5, 4= 10: Keyboard P15 I/O port.
OUT12t
RTSC
CR2C bit5, 4= 11: RTS output of UART C. [W83977AF only]
DRQ0
121
122
OUT12t CR2C bit7, 6= 00 (default): DMA Channel 0 request signal.
GP17
(PLEDO)
I/O12t
CR2C bit7, 6= 01: General purpose I/O port 1, bit 7. It can be
configured as power LED output.
I/O12t
P14
CR2C bit7, 6= 10: Keyboard P14 I/O port.
OUT12t
DTRC
CR2C bit7, 6= 11: DTR output of UART C. [W83977AF only]
INts
DMA Channel 1 Acknowledge signal
DACK1
DRQ1
123
124
OUT12t DMA Channel 1 request signal
INts DMA Channel 2 Acknowledge signal
OUT12t DMA Channel 2 request signal
INts DMA Channel 3 Acknowledge signal
OUT12t DMA Channel 3 request signal
INts Terminal Count. When active, this pin indicates termination of a
DMA transfer.
DACK2
DRQ2
125
126
DACK3
DRQ3
TC
127
128
IRQ1
99
98
OUT12t Interrupt request 1
OUT12t Interrupt request 3
OUT12t Interrupt request 4
OUT12t Interrupt request 5
OUT12t Interrupt request 6
OUT12t Interrupt request 7
OUT12t Interrupt request 8; default is nIRQ8 for RTC
OUT12t Interrupt request 9
OUT12t Interrupt request 10
OUT12t Interrupt request 11
OUT12t Interrupt request 12
IRQ3
IRQ4
97
IRQ5
96
IRQ6
95
IRQ7
94
IRQ8/ nIRQ8
IRQ9
93
92
IRQ10
IRQ11
IRQ12
100
101
102
Publication Release Date: March 1998
-7 - Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.1 Host Interface, continued
SYMBOL
PIN
I/O
FUNCTION
IRQ14
GP14
103
OUT12t CR2C bit1, 0= 00 (default): Interrupt request 14
I/O12t
CR2C bit1, 0= 01: General purpose I/O port 1, bit 4. It can be
configured as a general purpose address decode output.
( GPACS)
PLED
CR2C bit1, 0= 10: Power LED output.
OUT12t
OUT12t
CR2C bit1, 0= 11: IR module select signal 1. [W83977AF only]
IRSL1
IRQ15
104
OUT12t CR2C bit3, 2= 00 (default): Interrupt request 15
GP15
I/O12t
CR2C bit3, 2= 01: General purpose I/O port 1, bit 5. It can be
configured as a general purpose address write enable output.
( GPAWE)
WDT
CR2C bit3, 2= 10: Watch-Dog timer output.
OUT12t
OUT12t
INt
CR2C bit3, 2= 11: IR module select signal 2. [W83977AF only]
IRSL2
CLKIN
1
14.318/ 24 Mhz clock input, selectable through bit 5 of CR24.
1.2 Advanced Power Management
SYMBOL
PHRI
PIN
I/O
FUNCTION
69
INt
CR2B bit2, 1=00 (default): Advanced Power Management (APM)
phone ring indicator. Detection of an active PHRI pulse or pulse
train activates the PSCTL signal.
CR2B bit2, 1=01: General purpose I/O port 2, bit 0. It can be
configured as keyboard reset (Keyboard P20).
GP20
(KBRST)
I/O12t
POFIRQ
GP21 (P13)
P16
70
OUT12t CR2B bit4, 3=00 (default): Advanced Power Management (APM)
power off interrupt request.
I/O12t
CR2B bit4, 3=01: General purpose I/O port 2, bit 1. It can be
configured as Keyboard P13 I/O port.
I/O12t
INt
CR2B bit4, 3=10: Keyboard P16 I/O port.
RIC
CR2B bit4, 3=11: RI input of UART C. [W83977AF only]
VSB
71
72
-
Advanced Power Management (APM) standby current source
OUT12t CR2B bit5=0 (default): On/Off control for Advanced Power
Management (APM). This signal tells the main power supply
whether power should be turned on.
PSCTL
CR2B bit5=1: General purpose I/O port 2, bit 2. It can be
configured as Keyboard P14 I/O port.
I/O12t
GP22 (P14)
Publication Release Date: March 1998
-8-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.2 Advanced Power Management, continued
SYMBOL
PIN
I/O
FUNCTION
73
INt
CR2B bit7, 6=00 (default): On/Off switch for Advanced Power
Management (APM). This signal indicates a request to switch
the power on or off. When the VDD of the chip is disrupted, a
high to low transition on this pin indicates a switch on request.
When VDD returns, a high to low transition on this pin indicates a
switch off request.
PANSW
CR2B bit7, 6=01: General purpose I/O port 2, bit 3. It can be
configured as Keyboard P15 I/O port.
GP23 (P15)
DCDC
I/O12t
INt
CR2B bit7, 6=11: DCD input of UART C. [W83977AF only]
1.3 Serial Port Interface
SYMBOL
PIN
41
I/O
FUNCTION
INt
Clear To Send is the modem control input.
CTSA
CTSB
48
The function of these pins can be tested by reading Bit 4 of the
handshake status register.
42
49
INt
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
DSRA
DSRB
43
50
44
I/O8t
UART A Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
RTSA
During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for
CR26 bit 6 (HEFRAS). A 4.7 kW is recommended if intends to
pull up. (select 370H as configuration I/O port address)
HEFRAS
I/O8t
UART B Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
RTSB
During power-on reset, this pin is pulled down internally and is
nPENPLL
defined as n , which provides the power-on value for
PENPLL
CR24 bit 5 (ENPLL) and bit 6. A 4.7 kW is recommended if
intends to pull up. (PLL is disabled)
I/O8t
UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.
DTRA
During power-on reset, this pin is pulled down internally and is
defined as PNPCSV , which provides the power-on value for
PNPCSV
CR24 bit 0 (PNPCSV ). A 4.7 kW is recommended if intends to
pull up. (clear the default value of FDC, UARTs, and PTR)
Publication Release Date: March 1998
-9 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.3 Serial Port Interface, continued
SYMBOL
DTRB
PIN
I/O
FUNCTION
51
I/O8t
UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.
During power-on reset, this pin is pulled down internally and is
defined as ENCPNP, which provides the power-on value for
CR24 bit 1 (ENPNP). A 4.7 kW is recommended if intends to
pull up. (enable comply PnP mode)
ENCPNP
45,
52
INt
SINA
SINB
Serial Input. Used to receive serial data through the
communication link.
46
I/O8t
UART A Serial Output. Used to transmit serial data out to the
communication link.
SOUTA
During power-on reset, this pin is pulled down internally and is
defined as PENKRC, which provides the power-on value for
CR24 bit 2 (ENKBRTC). A 4.7 kW is recommended if intends to
pull up. (enable KBC and RTC)
PENKRC
SOUTB
53
47
I/O8t
UART B Serial Output. Used to transmit serial data out to the
communication link.
INt
INt
Data Carrier Detect. An active low signal indicates the modem
or data set has detected a data carrier.
DCDA
DCDB
54
65
Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.
RIA
RIB
66
1.4 Infrared Interface
SYMBOL
PIN
I/O
FUNCTION
IRRX (SINC)
37
INcs
Infrared Receiver input. It functions as SIN input if UART C is
configured as a simple serial port. [W83977AF only]
IRTX
(SOUTC)
38
39
OUT12t Infrared Transmitter Output. It functions as SOUT output if
UART C is configured as a simple serial port. [W83977AF only]
IRRXH
IRSL0
I/O12t
CR2A bit3, 2=00 (default): High speed IR receiving terminal.
OUT12t CR2A bit3, 2=01: IR module select 0.
GP25
(GA20)
I/O12t
INt
CR2A bit3, 2=10: General purpose I/O port 2, bit 5. It can be
configured as GATE A20 (Keyboard P21).
CTSC
CR2A bit3, 2=11: CTS input of UART C. [W83977AF only]
CIRRX
40
INt
CR2A bit5, 4=00 (default): Consumer IR receiving terminal.
GP24 (P16)
I/O12t
CR2A bit5, 4=01: General purpose I/O port 2, bit 4. It can be
configured as Keyboard P16 I/O port.
I/O12t
P13
CR2A bit5, 4=10: Keyboard P13 I/O
Publication Release Date: March 1998
-10-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SYMBOL
SLCT
PIN
I/O
FUNCTION
PRINTER MODE: SLCT
18
INt
An active high input on this pin indicates that the printer is
selected. This pin is pulled high internally. Refer to description
of the parallel port for definition of this pin in ECP and EPP
mode.
OD12
OD12
INt
EXTENSION FDD MODE: WE2
This pin is for Extension FDD B; its function is the same as the
pin of FDC.
WE
EXTENSION 2FDD MODE: WE2
This pin is for Extension FDD A and B; its function is the same
as the WE pin of FDC.
PRINTER MODE: PE
PE
19
An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
OD12
OD12
INt
EXTENSION FDD MODE: WD2
This pin is for Extension FDD B; its function is the same as the
WD pin of FDC.
EXTENSION 2FDD MODE: WD2
This pin is for Extension FDD A and B; its function is the same
as the WD pin of FDC.
BUSY
21
PRINTER MODE: BUSY
An active high input indicates that the printer is not ready to
receive data. This pin is pulled high internally. Refer to
description of the parallel port for definition of this pin in ECP
and EPP mode.
OD12
OD12
EXTENSION FDD MODE: MOB2
This pin is for Extension FDD B; the function of this pin is the
same as the MOB pin of FDC.
EXTENSION 2FDD MODE: MOB2
This pin is for Extension FDD A and B; the function of this pin is
the same as the MOB pin of FDC.
Publication Release Date: March 1998
-11 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PIN
I/O
FUNCTION
22
INt
PRINTER MODE: ACK
ACK
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is
pulled high internally. Refer to description of the parallel port for
definition of this pin in ECP and EPP mode.
OD12
OD12
INt
EXTENSION FDD MODE: DSB2
This pin is for the Extension FDD B; its functions is the same as
the DSB pin of FDC.
EXTENSION 2FDD MODE: DSB2
This pin is for Extension FDD A and B; it functions is the same
as the DSB pin of FDC.
34
PRINTER MODE: ERR
ERR
An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
OD12
OD12
OD12
EXTENSION FDD MODE: HEAD2
This pin is for Extension FDD B; its function is the same as the
HEADpin of FDC.
EXTENSION 2FDD MODE: HEAD2
This pin is for Extension FDD A and B; its function is the same
as the HEAD pin of FDC.
32
SLIN
PRINTER MODE: SLIN
Output line for detection of printer selection. This pin is pulled
high internally. Refer to description of the parallel port for
definition of this pin in ECP and EPP mode.
OD12
OD12
EXTENSION FDD MODE: STEP2
This pin is for Extension FDD B; its function is the same as the
STEP pin of FDC.
EXTENSION 2FDD MODE: STEP2
This pin is for Extension FDD A and B; its function is the same
as the STEP pin of FDC.
Publication Release Date: March 1998
-12-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
INIT
PIN
I/O
FUNCTION
33
OD12
PRINTER MODE: INIT
Output line for the printer initialization. This pin is pulled high
internally. Refer to description of the parallel port for definition
of this pin in ECP and EPP mode.
EXTENSION FDD MODE: DIR2
OD12
This pin is for Extension FDD B; its function is the same as the
DIR pin of FDC.
EXTENSION 2FDD MODE: DIR2
OD12
OD12
This pin is for Extension FDD A and B; its function is the same
as the DIR pin of FDC.
35
PRINTER MODE: AFD
AFD
An active low output from this pin causes the printer to auto feed
a line after a line is printed. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
EXTENSION FDD MODE: DRVDEN0
OD12
This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.
EXTENSION 2FDD MODE: DRVDEN0
OD12
OD12
This pin is for Extension FDD A and B; its function is the same
as the DRVDEN0 pin of FDC.
36
31
STB
PD0
PRINTER MODE: STB
An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to description of
the parallel port for definition of this pin in ECP and EPP mode.
-
-
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
PRINTER MODE: PD0
I/O24t
Parallel port data bus bit 0. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: INDEX2
INt
INt
This pin is for Extension FDD B; the function of this pin is the
same as the INDEX pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: INDEX2
This pin is for Extension FDD A and B; the function of this pin is
the same as the INDEX pin of FDC. It is pulled high internally.
Publication Release Date: March 1998
-13 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PD1
PIN
I/O
FUNCTION
30
I/O24t
PRINTER MODE: PD1
Parallel port data bus bit 1. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode. .
INt
INt
EXTENSION FDD MODE: TRAK02
This pin is for Extension FDD B; the function of this pin is the
same as the TRAK0 pin of FDC. It is pulled high internally..
EXTENSION. 2FDD MODE: TRAK02
This pin is for Extension FDD A and B; the function of this pin is
the same as the TRAK0 pin of FDC. It is pulled high internally.
29
I/O24t
PRINTER MODE: PD2
PD2
Parallel port data bus bit 2. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode..
INt
EXTENSION FDD MODE: WP2
This pin is for Extension FDD B; the function of this pin is the
same as the
pin of FDC. It is pulled high internally.
WP
INt
EXTENSION. 2FDD MODE: WP2
This pin is for Extension FDD A and B; the function of this pin is
the same as the WP pin of FDC. It is pulled high internally.
28
I/O24t
INt
PRINTER MODE: PD3
PD3
Parallel port data bus bit 3. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: RDATA2
This pin is for Extension FDD B; the function of this pin is the
same as the RDATA pin of FDC. It is pulled high internally.
INt
EXTENSION 2FDD MODE: RDATA2
This pin is for Extension FDD A and B; this function of this pin is
the same as the RDATA pin of FDC. It is pulled high internally.
Publication Release Date: March 1998
-14-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PD4
PIN
I/O
FUNCTION
27
I/O24t
PRINTER MODE: PD4
Parallel port data bus bit 4. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
INt
INt
EXTENSION FDD MODE: DSKCHG2
This pin is for Extension FDD B; the function of this pin is the
same as the DSKCHG pin of FDC. It is pulled high internally.
EXTENSION 2FDD MODE: DSKCHG2
This pin is for Extension FDD A and B; this function of this pin is
the same as the
internally.
pin of FDC. It is pulled high
DSKCHG
26
24
I/O24t
PRINTER MODE: PD5
PD5
PD6
Parallel port data bus bit 5. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
-
-
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
I/O24t
PRINTER MODE: PD6
Parallel port data bus bit 6. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION. 2FDD MODE: MOA2
OD24
This pin is for Extension FDD A; its function is the same as the
MOA pin of FDC.
23
I/O24t
PRINTER MODE: PD7
PD7
Parallel port data bus bit 7. Refer to description of the parallel
port for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: DSA2
-
OD24
This pin is for Extension FDD A; its function is the same as the
DSA pin of FDC.
Publication Release Date: March 1998
-15 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.6 FDC Interface
SYMBOL
DRVDEN0
DRVDEN1
PIN
2
3
I/O
FUNCTION
OD24 Drive Density Select bit 0.
OD24 Drive Density Select bit 1.
GP10
(IRQIN1)
Alternate Function 1: General purpose I/O port 1, bit 0. It can be
configured as an interrupt channel.
P12
Alternate Function 2: Keyboard P12 I/O port.
DSRC
Alternate Function 3: DSR input of UART C [W83977AF only]
Head select. This open drain output determines which disk drive
head is active.
5
OD24
HEAD
Logic 1 = side 0; Logic 0 = side 1
Write enable. An open drain output.
9
OD24
OD24
WE
WD
Write data. This logic low open drain writes precompensation serial
data to the selected FDD. An open drain output.
10
Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
11
12
13
OD24
OD24
STEP
DIR
Direction of the head step motor. An open drain output.
Logic 1 = outward motion; Logic 0 = inward motion
OD24 Motor B On. When set to 0, this pin enables disk drive 1. This is an
open drain output.
MOB
Drive Select A. When set to 0, this pin enables disk drive A. This is
an open drain output.
14
15
OD24
DSA
DSB
OD24 Drive Select B. When set to 0, this pin enables disk drive B. This is
an open drain output.
Motor A On. When set to 0, this pin enables disk drive 0. This is an
open drain output.
16
4
OD24
MOA
Diskette change. This signal is active low at power on and when the
diskette is removed. This input pin is pulled up internally by a 1 KW
resistor, which can can be disabled by bit 7 of L0-CRF0
(FIPURDWN).
INcs
DSKCHG
The read data input signal from the FDD. This input pin is pulled up
internally by a 1 KW resistor, which can be disabled by bit 7 of L0-
CRF0 (FIPURDWN).
6
7
INcs
INcs
RDATA
WP
Write protected. This active low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is pulled
up internally by a 1 KW resistor, which can be disabled by bit 7 of L0-
CRF0 (FIPURDWN).
Track 0. This Schmitt-triggered input from the disk drive is active low
when the head is positioned over the outermost track. This input pin
is pulled up internally by a 1 KW resistor, which can be disabled by bit
7 of L0-CRF0 (FIPURDWN).
8
INcs
TRAK0
Publication Release Date: March 1998
-16-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.6 FDC Interface, continued
SYMBOL
PIN
I/O
FUNCTION
This Schmitt-triggered input from the disk drive is active low when the
head is positioned over the beginning of a track marked by an index
hole. This input pin is pulled up internally by a 1 KW resistor, which
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
17
INcs
INDEX
1.7 KBC Interface
SYMBOL
KDATA
MDATA
KCLK
PIN
59
I/O
FUNCTION
I/OD16u Keyboard Data
I/OD16u PS2 Mouse Data
I/OD16u Keyboard Clock
I/OD16u PS2 Mouse Clock
60
67
68
56
MCLK
GA20
OUT12t
I/O12t
CR2A bit6= 0 (default): Keyboard GATE A20 (P21) Output.
GP11
(IRQIN2)
CR2A bit6= 1: General purpose I/O port 1, bit 1. It can be
configured as an interrupt channel.
KBRST
57
58
OUT12t
I/O12t
CR2A bit7= 0 (default): Keyboard Reset (P20) Output.
GP12
(WDTO,
IRRX)
CR2A bit7= 1: General purpose I/O port 1, bit 2. It can be
configured as watchdog timer output or IRRX (SINC if UART C is
used as a simple serial port [W83977AF only] ) input.
KBLOCK
IN16tu
CR2B bit0= 0 (default): Keyboard KINH (P17) Input.
GP13
(PLEDO,
IRTX)
I/O16tu
CR2B bit0= 1: General purpose I/O port 1, bit 3. It can be
configured as watchdog timer output or IRTX (SOUTC if UART C
is used as a simple serial port [W83977AF only] ) output.
1.8 RTC Interface
SYMBOL
VBAT
PIN
64
I/O
FUNCTION
RTC battery voltage input
XTAL1
XTAL2
63
INC
O8t
RTC 32.768Khz Clock Input
RTC 32.768Khz Clock Output
61
1.9 POWER PINS
VCC
20,55,
+5V power supply for the digital circuitry
Ground
85,115
25,62,
90,120
GND
Publication Release Date: March 1998
-17 - Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2. FDC FUNCTIONAL DESCRIPTION
2.1 W83977F/ AF FDC
The floppy disk controller of the W83977F/ AF integrates all of the logic required for floppy disk
control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to
compatible values. The FIFO provides better system performance in multi-master systems. The
digital data separator supports up to 2 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
2.1.1 AT interface
The interface consists of the standard asynchronous signals: RD , WR, A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
and DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors.
The following tables give several examples of the delays with a FIFO. The data are based upon the
following formula:
THRESHOLD # ´ (1/DATA/RATE) *8 - 1.5 mS = DELAY
Data Rate
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 500K BPS
1 Byte
1 ´ 16 mS - 1.5 mS = 14.5 mS
2 ´ 16 mS - 1.5 mS = 30.5 mS
8 ´ 16 mS - 1.5 mS = 6.5 mS
15 ´ 16 mS - 1.5 mS = 238.5 mS
2 Byte
8 Byte
15 Byte
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
1 ´ 8 mS - 1.5 mS = 6.5 mS
2 ´ 8 mS - 1.5 mS = 14.5 mS
8 ´ 8 mS - 1.5 mS = 62.5 mS
15 ´ 8 mS - 1.5 mS = 118.5 mS
Publication Release Date: March 1998
-18-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating
the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only on DACK . This mode is only available when the FDC has been configured
into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.¡ @
2.1.3 Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is provided with a clock which is synchronized to the
read data. The synchronized clock, called the Data Window, is used to internally sample the serial
data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel
conversion logic separates the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on
speed. A digital integrator is used to keep track of the speed changes in the input data stream.
2.1.4 Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.
2.1.5 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented
vertically. This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
Publication Release Date: March 1998
-19 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2.1.6 FDC Core
The W83977F/ AF FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information is provided
to the microprocessor.
2.1.7 FDC Commands
Command Symbol Descriptions:
C:
Cylinder number 0 - 256
Data Pattern
D:
DIR:
Step Direction
DIR = 0, step out
DIR = 1, step in
DS0:
DS1:
DTL:
EC:
Disk Drive Select 0
Disk Drive Select 1
Data Length
Enable Count
EOT:
EFIFO:
EIS:
End of Track
Enable FIFO
Enable Implied Seek
End of track
EOT:
FIFOTHR:
GAP:
GPL:
H:
FIFO Threshold
Gap length selection
Gap Length
Head number
HDS:
HLT:
HUT:
LOCK:
MFM:
MT:
Head number select
Head Load Time
Head Unload Time
Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM or FM Mode
Multitrack
N:
The number of data bytes written in a sector
New Cylinder Number
Non-DMA Mode
NCN:
ND:
OW:
Overwritten
Publication Release Date: March 1998
-20- Revision 0.58
PCN:
Present Cylinder Number
W83977F/ W83977AF
PRELIMINARY
POLL:
PRETRK:
R:
Polling Disable
Precompensation Start Track Number
Record
RCN:
R/W:
SC:
Relative Cylinder Number
Read/Write
Sector/per cylinder
SK:
Skip deleted data address mark
Step Rate Time
SRT:
ST0:
ST1:
ST2:
ST3:
WG:
Status Register 0
Status Register 1
Status Register 2
Status Register 3
Write gate alters timing of WE
Publication Release Date: March 1998
-21 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(1) Read Data
PHASE
R/W
W
D7
D6 D5 D4
D3
0
D2 D1 D0
REMARKS
Command
MT MFM SK
0
0
1
1
0
Command codes
W
0
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
R
R
R
R
Sector ID information after
command execution
Publication Release Date: March 1998
-22-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(2) Read Deleted Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM SK
0
0
1
0
1
0
0
Command codes
W
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: March 1998
-23 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(3) Read A Track
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
W
W
W
W
W
W
W
0
0
MFM
0
0
0
0
0
0
0
0
1
0
Command codes
HDS DS1 DS0
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
Execution
Result
Data transfer between the
FDD and system; FDD
reads contents of all
cylinders from index hole to
EOT
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
Status information after
command execution
R
R
-------------------- ST2 -----------------------
---------------------- C ------------------------
Sector ID information after
command execution
R
R
R
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Publication Release Date: March 1998
-24-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(4) Read ID
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
MFM
0
0
0
0
0
1
0
0
1
0
Command codes
W
HDS DS1 DS0
Execution
Result
The first correct ID
information on the cylinder
is stored in Data Register
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
R
Disk status after the
command has been
completed
R
R
(5) Verify
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM SK
EC
1
0
0
0
1
1
0
Command codes
W
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL/SC -------------------
Sector ID information prior
to command execution
W
W
W
W
W
Execution
Result
No data transfer takes
place
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: March 1998
-25 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(6) Version
PHASE
Command
Result
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command code
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
R
Enhanced controller
(7) Write Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM
0
0
0
0
0
0
1
0
1
Command codes
W
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to Command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
Command execution
Sector ID information after
Command execution
Publication Release Date: March 1998
-26-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(8) Write Deleted Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM
0
0
0
0
1
0
0
1
Command codes
W
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: March 1998
-27 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(9) Format A Track
PHASE
R/W
W
W
W
W
W
W
W
W
W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
MFM
0
0
0
0
0
1
0
1
0
1
Command codes
HDS DS1 DS0
---------------------- N ------------------------
--------------------- SC -----------------------
--------------------- GPL ---------------------
---------------------- D ------------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
Bytes/Sector
Sectors/Cylinder
Gap 3
Filler Byte
Execution
for Each
Sector
Input Sector Parameters
Repeat:
Result
Status information after
command execution
R
R
R
R
R
R
(10) Recalibrate
PHASE
R/W D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
0
0
0
0
0
0
0
0
0
1
1
1
Command codes
0
0
DS1 DS0
Execution
Head retracted to Track 0
Interrupt
(11) Sense Interrupt Status
PHASE
Command
Result
R/W D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
W
R
0
0
0
0
1
0
0
0
Command code
---------------- ST0 -------------------------
---------------- PCN -------------------------
Status information at the end
of each seek operation
R
Publication Release Date: March 1998
-28- Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(12) Specify
PHASE
R/W D7
D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
Command
W
W
W
0
0
0
0
0
0
1
1
| ---------SRT ----------- | --------- HUT ---------- |
|------------ HLT ----------------------------------| ND
(13) Seek
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command codes
Command
0
0
0
0
0
0
0
0
1
0
1
1
1
W
HDS DS1 DS0
W
-------------------- NCN -----------------------
Execution
R
Head positioned over proper
cylinder on diskette
(14) Configure
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
Configure information
W
0
W
EIS EFIFO POLL | ------ FIFOTHR ----|
W
| --------------------PRETRK ----------------------- |
Execution
Internal registers written
(15) Relative Seek
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
1
0
DIR
0
0
0
0
0
1
0
1
1
1
Command codes
W
HDS DS1 DS0
W
| -------------------- RCN ---------------------------- |
Publication Release Date: March 1998
-29 - Revision 0.58
W83977F/ W83977AF
PRELIMINARY
(16) Dumpreg
PHASE
Command
Result
R/W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
0
0
0
0
1
1
1
0
Registers placed in FIFO
----------------------- PCN-Drive 0--------------------
----------------------- PCN-Drive 1 -------------------
----------------------- PCN-Drive 2--------------------
----------------------- PCN-Drive 3 -------------------
--------SRT ------------------ | --------- HUT --------
----------- HLT -----------------------------------| ND
------------------------ SC/EOT ----------------------
LOCK 0 D3 D2 D1 D0 GAP WG
0 EIS EFIFO POLL | ------ FIFOTHR --------
-----------------------PRETRK -------------------------
R
R
R
R
R
R
R
R
R
(17) Perpendicular Mode
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
1
0
0
1
0
Command Code
W
OW
0
D3
D2 D1 D0 GAP WG
(18) Lock
PHASE
Command
Result
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
LOCK 0
0
0
1
0
0
1
0
0
0
0
Command Code
R
0
0
LOCK
0
(19) Sense Drive Status
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
0
0
0
0
0
0
1
0
0
Command Code
W
0
HDS DS1 DS0
Result
R
---------------- ST3 -------------------------
Status information about
disk drive
(20) Invalid
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
------------- Invalid Codes -----------------
Invalid codes (no
operation- FDC goes to
standby state)
Result
R
-------------------- ST0 ----------------------
ST0 = 80H
Publication Release Date: March 1998
-30- Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2.2 Register Descriptions
There are several status, data, and control registers in W83977F/ AF. These registers are defined
below:
ADDRESS
REGISTER
OFFSET
READ
WRITE
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
SA REGISTER
SB REGISTER
DO REGISTER
TD REGISTER
TD REGISTER
MS REGISTER
DR REGISTER
DT (FIFO) REGISTER
DI REGISTER
DT (FIFO) REGISTER
CC REGISTER
2.2.1 Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR
WP
INDEX
HEAD
TRAK0
STEP
DRV2
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2 (Bit 6):
0
1
A second drive has been installed
A second drive has not been installed
STEP (Bit 5):
This bit indicates the complement of STEP output.
TRAK0 (Bit 4):
This bit indicates the value of TRAK0 input.
Publication Release Date: March 1998
-31 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
HEAD (Bit 3):
This bit indicates the complement of HEAD output.
0
1
side 0
side 1
INDEX (Bit 2):
This bit indicates the value of INDEX output.
WP
0
(Bit 1):
disk is write-protected
disk is not write-protected
1
DIR (Bit 0)
This bit indicates the direction of head movement.
0
1
outward direction
inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR
WP
INDEX
HEAD
TRAK0
STEP F/F
DRQ
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRQ (Bit 6):
This bit indicates the value of DRQ output pin.
STEP F/F (Bit 5):
This bit indicates the complement of latched STEP output.
TRAK0 (Bit 4):
This bit indicates the complement of TRAK0 input.
HEAD (Bit 3):
Publication Release Date: March 1998
-32-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
This bit indicates the value of HEAD output.
0
1
side 1
side 0
INDEX (Bit 2):
This bit indicates the complement of INDEX output.
WP (Bit 1):
0
1
disk is not write-protected
disk is write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
1
inward direction
outward direction
Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2
mode, the bit definitions for this register are as follows:
2
1
7
1
6
5
4
3
0
1
MOT EN A
MOT EN B
WE
RDATA Toggle
WDATA Toggle
Drive SEL0
Drive SEL0 (Bit 5):
This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).
WDATA Toggle (Bit 4):
This bit changes state at every rising edge of the WD output pin.
RDATA Toggle (Bit 3):
This bit changes state at every rising edge of the RDATA output pin.
WE (Bit 2):
This bit indicates the complement of the WE output pin.
MOT EN B (Bit 1)
This bit indicates the complement of the MOB output pin.
Publication Release Date: March 1998
-33 - Revision 0.58
W83977F/ W83977AF
PRELIMINARY
MOT EN A (Bit 0)
This bit indicates the complement of the MOA output pin.
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DSC
DSD
WE F/F
RDATA F/F
WD F/F
DSA
DSB
DRV2
DRV2 (Bit 7):
0
1
A second drive has been installed
A second drive has not been installed
DSB (Bit 6):
This bit indicates the status of DSB output pin.
DSA (Bit 5):
This bit indicates the status of DSA output pin.
WD F/F(Bit 4):
This bit indicates the complement of the latched WD output pin at every rising edge of the WD
output pin.
RDATA F/F(Bit 3):
This bit indicates the complement of the latched RDATA output pin .
WE F/F (Bit 2):
This bit indicates the complement of latched WE output pin.
DSD (Bit 1):
0
1
Drive D has been selected
Drive D has not been selected
DSC (Bit 0):
0
1
Drive C has been selected
Drive C has not been selected
Publication Release Date: March 1998
-34- Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2.2.3 Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ
enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions
are as follows:
7
6
3
1-0
5
4
2
Drive Select: 00 select drive A
01 select drive B
10 select drive C
11 select drive D
Floppy Disk Controller Reset
Active low resets FDC
DMA and INT Enable
Active high enable DRQ/IRQ
Motor Enable A. Motor A on when active high
Motor Enable B. Motor B on when active high
Motor Enable C. Motor C on when active high
Motor Enable D. Motor D on when active high
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information of the
floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are
as follows:
2
1
7
6
5
4
3
0
X
X
X
X
X
X
Tape sel 0
Tape sel 1
If three mode FDD function is enabled (EN3MODE = 1 in Logical Device 0 CRF0 bit:0), the bit
definitions are as follows:
2
1
7
6
5
4
3
0
Tape Sel 0
Tape Sel 1
Floppy boot drive 0
Floppy boot drive 1
Drive type ID0
Drive type ID1
Media ID0
Media ID1
Publication Release Date: March 1998
-35 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Media ID1 Media ID0 (Bit 7, 6):
These two bits are read only. These two bits reflect the value of Logical Device 0 CRF1 bit 4,5.
Drive type ID1 Drive type ID0 (Bit 5, 4):
These two bits reflect two of the bits of Logical Device 0 CRF2. Which two bits are reflected depends
on the last drive selected in the DO REGISTER.
Floppy Boot drive 1, 0 (Bit 3, 2):
These two bits reflect the value of Logical Device 0 CRF1 bit 7,6.
Tape Sel 1, Tape Sel 0 (Bit 1, 0):
These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved as the floppy disk boot drive.
TAPE SEL 1
TAPE SEL 0
DRIVE SELECTED
0
0
None
0
1
1
1
0
1
1
2
3
2.2.5 Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
6
4
0
7
5
3
2
1
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.
FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.
FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
2.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of
the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and
not by the DR REGISTER. The real data rate is determined by the most recent write to either of the
DR REGISTER or CC REGISTER.
Publication Release Date: March 1998
-36-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1
7
6
5
0
4
3
2
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
1
FDC in normal mode
FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
PRECOMP
PRECOMPENSATION DELAY
2
1
0
250K - 1 Mbps
2 Mbps Tape drive
Default Delays
20.8 nS
0
0
0
Default Delays
41.67 nS
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
83.34 nS
41.17 nS
125.00 nS
62.5nS
166.67 nS
83.3 nS
208.33 nS
104.2 nS
250.00 nS
125.00 nS
0.00 nS (disabled)
0.00 nS (disabled)
Publication Release Date: March 1998
-37 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
DEFAULT PRECOMPENSATION DELAYS
125 nS
125 nS
125 nS
41.67nS
20.8 nS
2 MB/S
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1
01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0
10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0
11 1 MB/S (MFM), Illegal (FM), RWC = 1
The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits
in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for
individual data rates setting.
2.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the
data bus at a time. This register stores data, commands, and parameters and provides diskette-drive
status information. Data bytes are passed through the data register to program or obtain results after
a command. In the W83977F/ AF, this register defaults to FIFO disabled mode after reset. The FIFO
can change its value and enable its operation through the CONFIGURE command.
Publication Release Date: March 1998
-38-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Status Register 0 (ST0)
7-6
5
3
2
1-0
4
US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command executio
Status Register 1 (ST1)
7
6
5
4
3
2
1
0
Missing Address Mark. 1 When the FDC cannot detect the data address mark
or the data address mark has been deleted.
NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during
execution of write data.
ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data.
Not used. This bit is always 0.
OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.
DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.
Not used. This bit is always 0.
EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7
1
0
4
3
2
6
5
MD (Missing Address Mark in Data Field).
1 If the FDC cannot find a data address mark
(or the address mark has been deleted)
when reading data from the media
0 No error
BC (Bad Cylinder)
1 Bad Cylinder
0 No error
SN (Scan Not satisfied)
1 During execution of the Scan command
0 No error
SH (Scan Equal Hit)
1 During execution of the Scan command, if the equal condition is satisfied
0 No error
WC (Wrong Cylinder)
1 Indicates wrong Cylinder
DD (Data error in the Data field)
1 If the FDC detects a CRC error in the data field
0 No error
CM (Control Mark)
1 During execution of the read data or scan command
0 No error
Not used. This bit is always 0
Publication Release Date: March 1998
-39 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Status Register 3 (ST3)
6
4
2
1
0
7
5
3
US0 Unit Select 0
US1 Unit Select 1
HD Head Address
TS Two-Side
TO Track 0
RY Ready
WP Write Protected
FT Fault
2.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or
AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of
DSKCHG , while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7
6
5
4
3
2
1
0
x x x
x x x
x
Reserved for the hard disk controller
x
During a read of this register, these bits are in tri-state
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
7
6
1
5
4
3
1
2
0
1
1
1
HIGH DENS
DRATE0
DRATE1
DSKCHG
DSKCHG (Bit 7):
This bit indicates the complement of the DSKCHG input.
Bit 6-3: These bits are always a logic 1 during a read.
Publication Release Date: March 1998
-40-
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings
corresponding to the individual data rates.
HIGH DENS (Bit 0):
0
1
500 KB/S or 1 MB/S data rate (high density FDD)
250 KB/S or 300 KB/S data rate
In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
0
5
0
4
3
2
0
1
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG
DSKCHG (Bit 7):
This bit indicates the status of DSKCHG input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
Publication Release Date: March 1998
-41 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
4
2
1
3
6
5
7
0
x
x
x
x
x
x
DRATE0
DRATE1
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
2
1
7
6
5
4
3
0
X
X
X
X
X
DRATE0
DRATE1
NOPREC
X: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
Publication Release Date: March 1998
-42- Revision 0.58
W83977F/ W83977AF
PRELIMINARY
3.
UART PORT
Universal Asynchronous Receiver/Transmitter (UART A, UART B)
3.1
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use
this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore,
the UARTs also include complete modem control capability and a processor interrupt system that
may be software trailed to the computing time required to handle the communication link. The
UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART,
there are 16-byte FIFOs for both receive and transmit mode.
3.2
Register Address
3.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
5
4
2
6
7
3
0
1
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
format) from the divisor latches of the baudrate generator during a read or write operation.
When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the
Interrupt Control Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
Publication Release Date: January 1997
- 43 - Revision 0.50
W83977F/ W83977AF
PRELIMINARY
TABLE 3-1 UART Register Bit Map
Bit Number
Register Address Base
0
1
2
3
4
5
6
7
+ 0
Receiver
Buffer
Register
RBR
TBR
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data
Bit 5
RX Data
Bit 6
RX Data
Bit 7
BDLAB = 0
(Read Only)
+ 0
Transmitter
Buffer Register
(Write Only)
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
BDLAB = 0
+ 1
Interrupt Control ICR
Register
RBR Data
Ready
Interrupt
Enable
TBR
Empty
Interrupt
Enable
USR
Interrupt
Enable
HSR
Interrupt
Enable
0
0
0
0
BDLAB = 0
(EUSRI)
(EHSRI)
(ERDRI)
(ETBREI)
+ 2
+ 2
Interrupt Status
Register
(Read Only)
ISR
"0" if
Interrupt
Pending
Interrupt
Status
Interrupt
Status
Interrupt
Status
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
Bit (0)
Bit (1)
Bit (2)**
UART FIFO
Control
Register
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
Reversed
RX
Interrupt
Active Level Active Level
RX
Interrupt
(Write Only)
(LSB)
(MSB)
+ 3
UART Control
Register
UCR
Data
Length
Select
Bit 0
Data
Length
Select
Bit 1
Multiple
Stop Bits
Enable
Parity
Bit
Enable
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Silence
Enable
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
(MSBE)
(PBE)
(EPE)
PBFE)
(SSE)
(DLS0)
(DLS1)
+ 4
+ 5
Handshake
Control
Register
HCR
USR
Data
Terminal
Ready
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
(DTR)
UART Status
Register
RBR Data
Ready
Overrun
Error
Parity Bit
Error
No Stop
Bit
Silent
Byte
TBR
Empty
TSR
Empty
RX FIFO
Error
Error
(NSER)
Detected
(SBD)
Indication
(RFEI) **
(RDR)
(OER)
(PBER)
(TBRE)
(TSRE)
+ 6
+ 7
Handshake
Status Register
HSR
UDR
CTS
Toggling
DSR
Toggling
RI Falling
Edge
DCD
Toggling
Clear
to Send
Data Set
Ready
Ring
Indicator
Data Carrier
Detect
(DCD)
(TCTS)
Bit 0
(TDSR)
Bit 1
(FERI)
Bit 2
(TDCD)
Bit 3
(CTS)
Bit 4
(DSR)
Bit 5
(RI)
User Defined
Register
Bit 6
Bit 7
Bit 7
+ 0
Baudrate Divisor BLL
Latch Low
Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
BDLAB = 1
+ 1
Baudrate
Divisor Latch
High
BHL
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
BDLAB = 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Publication Release Date: January 1997
-44 - Revision 0.50
W83977F/ W83977AF
PRELIMINARY
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit
3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT
will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
TABLE 3-2 WORD LENGTH DEFINITION
DLS1
DLS0
DATA LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
3.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
2
7
6
4
3
1
0
5
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic
1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO.
In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left
in the FIFO.
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PRELIMINARY
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
thanthese two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be
set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU
to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO
is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit
to a logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
3.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
2
7
0
5
4
3
1
0
6
0
0
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the
TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
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PRELIMINARY
(bit 0 of HCR) ® DSR, RTS ( bit 1 of HCR) ® CTS, Loopback RI input ( bit 2 of HCR) ®
RI and IRQ enable ( bit 3 of HCR) ® DCD.
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
bit is internally connected to the modem control input DCD .
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
connected to the modem control input RI .
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR.
3.2.4
Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
7
6
5
4
3
2
1
0
toggling (TCTS)
toggling (TDSR)
CTS
DSR
RI falling edge (FERI)
toggling (TDCD)
DCD
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback
mode.
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback
mode.
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback
mode.
Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the
CPU.
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read
by the CPU.
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
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2
1
7
6
5
4
3
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
TABLE 3-3 FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
1
1
0
1
0
1
01
04
08
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1
before other bits of UFR are programmed.
3.2.6
Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
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7
6
5
0
4
0
3
2
1
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
out interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has
occurred, this bit will be set to a logical 0.
TABLE 3-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit
3
Bit
2
Bit
1
Bit Interrupt
Interrupt Type
-
Interrupt Source
Clear Interrupt
0
priority
0
0
0
1
0
1
1
0
-
No Interrupt pending
-
First
UART Receive
Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
Read USR
0
1
0
0
Second
RBR Data Ready
1. RBR data ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
1
0
1
0
0
1
0
0
Second
Third
FIFO Data Timeout
TBR Empty
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
3.2.7
Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output
signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the
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PRELIMINARY
Interrupt
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PRELIMINARY
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
5
6
0
3
0
4
0
2
7
0
1
0
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
16
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table in the next page illustrates the use of the baud generator with a frequency of
1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable
baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-
speed mode, the data transmission rate can be as high as 1.5M bps.
3.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
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TABLE 3-5 BAUD RATE TABLE
BAUD RATE FROM DIFFERENT PRE-DIVIDER
Pre-Div:1.625 Pre-Div: 1.0 Decimal divisor used Error Percentage between
Pre-Div: 13
1.8461M Hz
to generate 16X
clock
desired and actual
14.769M Hz
24M Hz
50
75
400
600
650
975
**
2304
1536
1047
857
768
384
192
96
**
110
880
1430
0.18%
134.5
150
1076
1478.5
1950
0.099%
1200
**
**
300
2400
3900
600
4800
7800
**
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
9600
15600
23400
26000
31200
46800
62400
93600
124800
249600
499200
748800
1497600
**
14400
16000
19200
28800
38400
57600
76800
153600
307200
460800
921600
**
64
0.53%
**
58
48
**
32
**
24
**
16
**
12
**
6
**
3
**
2
**
1
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
Note. Pre-Divisor is determined by CRF0 of UART A and B.
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PRELIMINARY
4. INFRARED (IR) PORT
The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless
communication which can operate under various transmission protocols including IrDA 1.0 SIR, IrDA
1.1 MIR (1.152 Mbps), IrDA 1.1 FIR (4 Mbps), SHARP ASK-IR, and remote control (NEC, RC-5,
advanced RC-5, and RECS-80 protocol).
4.1 IR Register Description
When bank select enable bit (ENBNKSEL, the bit 0 in CRF0 of logic device 6) is set, legacy IR will be
switched to Advanced IR, and eight Register Sets can then be accessible. These Register Sets
control enhanced IR, SIR, MIR, or FIR. Also a superior traditional SIR function can be used with
enhanced features such as 32-byte transmitter/receiver FIFOs, non-encoding IRQ identify status
register, and automatic flow control. The MIR/FIR and remote control registers are also defined in
these Register Sets. Structure of these Register Sets is shown as follows.
Reg 7
Reg 6
Reg 5
Reg 4
BDL/ SSR
All in one Reg
to Select SSR
Reg 2
Reg 1
Reg 0
Set 0
Set 1
Set 2
Set 3
Set 4
Set 5
Set 6
Set 7
*Set 0, 1 are legacy/Advanced UART Registers
*Set 2~7 are Advanced UART Registers
Each of these register sets has a common register, namely Sets Select Register (SSR), in order to
switch to another register set. The summary description of these Sets is shown in the following.
Set
Sets Description
0
1
2
3
4
5
6
7
Legacy/Advanced IR Control and Status Registers.
Legacy Baud Rate Divisor Register.
Advanced IR Control and Status Registers.
Version ID and Mapped Control Registers.
Transmitter/Receiver/Timer Counter Registers and IR Control Registers.
Flow Control and IR Control and Frame Status FIFO Registers.
IR Physical Layer Control Registers
Remote Control and IR front-end Module Selection Registers.
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PRELIMINARY
4.2 Set0-Legacy/Advanced IR Control and Status Registers
Address Offset Register Name
Register Description
Receiver/Transmitter Buffer Registers
Interrupt Control Register
Interrupt Status or IR FIFO Control Register
IR Control or Sets Select Register
Handshake Control Register
IR Status Register
Handshake Status Register
User Defined Register
0
1
2
3
4
5
6
7
RBR/TBR
ICR
ISR/UFR
UCR/SSR
HCR
USR
HSR
UDR/ESCR
4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write)
Receiver Buffer Register is read only and Transmitter Buffer Register is write only. When operate in
the PIO mode, the port is used to Receive/Transmit 8-bit data.
When function as a legacy IR, this port only supports PIO mode. If set in the advanced IR mode and
configured as MIR/FIR/Remote IR, this port can support DMA transmission. Two DMA channels can
be used simultaneously, one for TX DMA and the other for RX DMA. Therefore, single DMA channel
is also supported when set the bit of D_CHSW (DMA Channel Swap, in Set2.Reg2.Bit3) and the
TX/RX DMA channel is swapped. Note that two DMA channel can be defined in configure register
CR2A which selects DMA channel or disables DMA channel. If only RX DMA channel is enabled
while TX DMA channel is disabled, then the single DMA channel will be selected.
4.2.2 Set0.Reg1 - Interrupt Control Register (ICR)
Mode
B7
B6
B5
B4
B3
B2
B1
B0
Legacy IR
Advanced IR ETMRI
0
0
0
0
0
0
EUSRI
EUSRI/
TXURI
ETBREI ERDRI
ETBREI ERBRI
EFSFI
ETXTHI
EDMAI
The advanced IR functions including Advanced SIR/ASK-IR, MIR, FIR, or Remote IR are described
as follows.
Bit 7:
Legacy IR Mode:
Not used. A read will return 0.
Advanced IR Mode:
ETMRI - Enable Timer Interrupt
A write to 1 will enable timer interrupt.
Legacy IR Mode:
Bit 6:
Not used. A read will return 0.
MIR, FIR mode:
EFSFI - Enable Frame Status FIFO Interrupt
A write to 1 will enable frame status FIFO interrupt.
Advanced SIR/ASK-IR, Remote IR:
Not used.
Bit 5:
Legacy IR Mode:
Not used. A read will return 0.
Advanced SIR/ASK-IR, MIR, FIR, Remote IR:
ETXTHI - Enable Transmitter Threshold Interrupt
A write to 1 will enable transmitter threshold interrupt.
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Bit 4:
Legacy IR Mode:
Not used. A read will return 0.
MIR, FIR, Remote IR:
EDMAI - Enable DMA Interrupt.
A write to 1 will enable DMA interrupt.
Reserved. A read will return 0.
Legacy IR Mode:
Bit 3:
Bit 2:
EUSRI - Enable USR (IR Status Register) Interrupt
A write to 1 will enable IR status register interrupt.
Advanced SIR/ASK-IR:
EUSRI - Enable USR (IR Status Register) Interrupt
A write to 1 will enable IR status register interrupt.
MIR, FIR, Remote Controller:
EHSRI/ETXURI - Enable USR Interrupt or Enable Transmitter Underrun Interrupt
A write to 1 will enable USR interrupt or enable transmitter underrun interrupt.
ETBREI - Enable TBR (Transmitter Buffer Register) Empty Interrupt
A write to 1 will enable the transmitter buffer register empty interrupt.
ERBRI - Enable RBR (Receiver Buffer Register) Interrupt
A write to 1 will enable receiver buffer register interrupt.
Bit 1:
Bit 0:
4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)
4.2.3.1 Interrupt Status Register (Read Only)
Mode
B7
B6
B5
B4
B3
B2
B1
B0
Legacy IR FIFO Enable FIFO Enable
0
0
IID2
IID1
IID0
IP
Advanced
IR
TMR_I
0
FSF_I
0
TXTH_I DMA_I HS_I
USR_I/ TXEMP_I RXTH_I
FEND_I
Reset Value
1
0
0
0
1
0
Legacy IR:
This register reflects the Legacy IR interrupt status, which is encoded by different interrupt sources
into 3 bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logical 0.
Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical
1 when a time-out interrupt is pending.
Bit 2, 1: These bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has
occurred, this bit will be set to logical 0.
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PRELIMINARY
TABLE: INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit
3
Bit
2
Bit
1
Bit Interrupt
Interrupt Type
Interrupt Source
Clear Interrupt
0
priority
0
0
0
1
0
1
1
0
-
-
No Interrupt pending
-
First
IR Receive Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
1. RBR data ready
Read USR
0
1
0
0
Second
RBR Data Ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
1
0
1
0
0
1
0
0
Second
Third
FIFO Data Time-out
TBR Empty
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
Advanced IR:
Bit 7:
TMR_I - Timer Interrupt.
Set to 1 when timer count to logical 0. This bit is valid when: (1) the timer registers are
defined in Set4.Reg0 and Set4.Reg1; (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0) is
set to 1; (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) is set to 1.
MIR, FIR modes:
Bit 6:
FSF_I - Frame Status FIFO Interrupt.
Set to 1 when Frame Status FIFO is equal or larger than the threshold level or Frame
Status FIFO time-out occurs. Cleared to 0 when Frame Status FIFO is below the
threshold level.
Advanced SIR/ASK-IR, Remote IR modes: Not used.
Bit 5:
Bit 4:
TXTH_I - Transmitter Threshold Interrupt.
Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level.
Cleared to 0 if the TBR (Transmitter Buffer Register) FIFO is above the threshold level.
MIR, FIR, Remote IR Modes:
DMA_I - DMA Interrupt.
Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which
might be a Transmitter TC or a Receiver TC. Cleared to 0 when this register is read.
HS_I - Handshake Status Interrupt.
Set to 1 when the Handshake Status Register has a toggle. Cleared to 0 when
Handshake Status Register (HSR) is read. Note that in all IR modes including SIR, ASK-
IR, MIR, FIR, and Remote Control IR, this bit defaults to be inactive unless IR Handshake
Status Enable (IRHS_EN) is set to 1.
Bit 3:
Bit 2:
Advanced SIR/ASK-IR modes:
USR_I - IR Status Interrupt.
Set to 1 when overrun error, parity error, stop bit error, or silent byte error detected and
registered in the IR Status Register (USR). Cleared to 0 when USR is read.
MIR, FIR modes:
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is
defined in the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been
detected during receiving valid data. Cleared to 0 when this register is read.
Remote Controller Mode: Not used.
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PRELIMINARY
Bit 1:
Bit 0:
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this
register is read.
RXTH_I - Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold
level; or (2) RBR time-out occurs if the receiver buffer register has valid data and below
the threshold level. Cleared to 0 when RBR is less than threshold level after reading
RBR.
4.2.3.2 IR FIFO Control Register (UFR):
Mode
Legacy IR RXFTL1 RXFTL0
(MSB) (LSB)
Advanced RXFTL1 RXFTL0 TXFTL1 TXFTL0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
TXF_RST RXF_RST EN_FIFO
0
0
TXF_RST RXF_RST EN_FIFO
IR
(MSB)
(LSB)
(MSB)
(LSB)
Reset Value
0
0
0
0
0
0
0
Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example,
if the interrupt active level is set as 4 bytes and there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
TABLE: FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
1
1
0
1
0
1
01
04
08
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be
cleared to logical 0 by itself after being set to logical 1.
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be
cleared to a logical 0 by itself after being set to logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before
other bits of UFR can be programmed.
Publication Release Date: March 1998
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PRELIMINARY
Advanced IR:
Bit 7, 6:
RXFTL1, 0 - Receiver FIFO Threshold Level
Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO
Threshold Level is equal or larger than the defined value shown as follow.
RXFTL1, 0
RX FIFO Threshold Level RX FIFO Threshold Level
(Bit 7, 6)
(FIFO Size: 16-byte)
(FIFO Size: 32-byte)
1
4
8
1
4
16
26
00
01
10
11
14
Note that the FIFO Size is selectable in SET2.Reg4.
Bit 5, 4:
TXFTL1, 0 - Transmitter FIFO Threshold Level
TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter
Threshold Level is less than the programmed value shown as follows.
TXFTL1, 0
TX FIFO Threshold Level TX FIFO Threshold Level
(Bit 5, 4)
(FIFO Size: 16-byte)
(FIFO Size: 32-byte)
1
3
9
1
7
17
25
00
01
10
11
13
Bit 3 ~0
Same as in Legacy IR Mode
4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR):
These two registers share the same address. In all Register Sets, Set Select Register (SSR) can be
programmed to select a desired Set but IR Control Register can only be programmed in Set 0 and Set
1. In other words, writing to Reg3 in Sets other than Set 0 and Set 1 will not affect IR Control
Register. The mapping of entry Set and programming value is shown as follows.
SSR Bits
Selected
Set
7
6
5
4
3
2
1
0
Hex
Value
¡ Ð
¡ Ñ
¡ Ñ
¡ Ñ
¡ Ñ
¡ Ñ
¡ Ñ
¡ Ñ
0
1
1
1
1
1
1
1
Set 0
Set1
¡ Ð
Any combination except those used in SET 2~7
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
Set 2
Set 3
Set 4
Set 5
Set 6
Set 7
Publication Release Date: March 1998
Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
4.2.5 Set0.Reg4 - Handshake Control Register (HCR)
Mode
B7
B6
B5
B4
B3
B2
B1
B0
Legacy IR
0
0
0
XLOOP
EN_IRQ
0
EN_DMA
0
0
0
0
0
0
0
Advanced IR AD_MD2 AD_MD1 AD_MD0 SIR_PLS TX_WT
Reset Value
0
1
1
0
0
Legacy IR Register:
This register controls the pins of IR used for handshaking with peripherals such as modem, and
controls the diagnostic mode of IR.
Bit 4: When this bit is set to logical 1, the legacy IR enters diagnostic mode by an internal loopback:
IRTX is forced to logical 0, and IRRX is isolated from the communication link instead of the
TSR.
Bit 3: The legacy IR interrupt output is enabled by setting this bit to logic 1.
Advanced IR Register:
Bit 7~5 Advanced SIR/ASK-IR, MIR, FIR, Remote Controller Modes:
AD_MD2~0 - Advanced IR/Infrared Mode Select.
These registers are active when Advanced IR Select (ADV_SL, in Set2.Reg2.Bit0) is set
to 1. Operational mode selection is defined as follows. When backward operation
occurs, these registers will be reset to 0 and fall back to legacy IR mode.
AD_MD2~0
Selected Mode
(Bit 7, 6, 5)
000
001
010
011
100
101
110
111
Reserved
Low speed MIR (0.576M bps)
Advanced ASK-IR
Advanced SIR
High Speed MIR (1.152M bps)
FIR (4M bps)
Consumer IR
Reserved
Bit 4:
Bit 3:
MIR, FIR Modes:
SIR_PLS - Send Infrared Pulse
Writing 1 to this bit will send a 2 m s long infrared pulse after physical frame end. This is
to signal to SIR that the high speed infrared is still in. This bit will be auto cleared by
hardware.
Other Modes: Not used.
MIR, FIR modes:
TX_WT - Transmission Waiting
If this bit is set to 1, the transmitter will wait for TX FIFO reaching threshold level or
transmitter time-out before it begins to transmit data which prevents short queues of data
bytes from transmitting prematurely. This is to avoid Underrun.
Other Modes: Not used.
Publication Release Date: March 1998
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W83977F/ W83977AF
PRELIMINARY
Bit 2:
MIR, FIR modes:
EN_DMA - Enable DMA
Enable DMA function for transmitting or receiving. Before using this, the DMA channel
should be selected first. If only RX DMA channel is set and TX DMA channel is disabled,
then the single DMA channel is used. In the single channel system, the bit of D_CHSW
(DMA channel swap, in Set 2.Reg2.Bit3) will determine if it is RX_DMA or TX_DMA
channel.
Other modes: Not used.
Bit 1, 0:
RTS, DTR
Functional definitions is the same as in legacy IR mode.
4.2.6 Set0.Reg5 - IR Status Register (USR)
Mode
B7
B6
B5
B4
B3
B2
B1
B0
Legacy IR
Advanced IR LB_INFR TSRE
Reset Value
RFEI
TSRE
TBRE
TBRE
0
SBD
NSER
PBER
OER
RDR
RDR
0
MX_LEX PHY_ERR CRC_ERR OER
0
0
0
0
0
0
Legacy IR Register: These registers are defined the same as previous description.
Advanced IR Register:
Bit 7:
MIR, FIR Modes:
LB_INFR - Last Byte In Frame End
Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame
from another when RX FIFO has more than one frame.
Same as legacy IR description.
Bit 6, 5:
Bit 4:
MIR, FIR modes:
MX_LEX - Maximum Frame Length Exceed
Set to 1 when the length of a frame from the receiver has exceeded the programmed
frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not
receive any data to RX FIFO.
Bit 3:
MIR, FIR modes:
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in
physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will
be aborted and a frame end signal is set to 1.
Bit 2:
MIR, FIR Modes:
CRC_ERR - CRC Error
Set to 1 when an attached CRC is erroneous.
Bit 1, 0:
OER - Overrun Error, RDR - RBR Data Ready
Definitions are the same as legacy IR.
4.2.7 Set0.Reg6 - Reserved
4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Legacy IR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
LB_SF
Bit 0
RX_TO
Advanced FLC_ACT UNDRN RX_BSY/ LST_FE/ S_FEND
IR
RX_IP
RX_PD
Reset Value
0
0
0
0
0
0
0
0
Publication Release Date: March 1998
Revision 0.58
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PRELIMINARY
Legacy IR Register:
This is a temporary register that can be accessed and defined by the user.
Advanced IR Register:
Bit 7
MIR, FIR Modes:
FLC_ACT - Flow Control Active
Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that
this will be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR
mode or MIR/FIR mode operated in DMA function switches to SIR mode.
Bit 6
Bit 5
MIR, FIR Modes:
UNDRN - Underrun
Set to 1 when transmitter is empty and S_FEND (bit 3 of this register) is not set in PIO
mode or no TC (Terminal Count) in DMA mode. Cleared to 0 after a write to 1.
MIR, FIR Modes:
RX_BSY - Receiver Busy
Set to 1 when receiver is busy or active in process.
Remote IR mode:
RX_IP - Receiver in Process
Set to 1 when receiver is in process.
Bit 4:
MIR, FIR modes:
LST_FE - Lost Frame End
Set to 1 when a frame end in a entire frame is lost. Cleared to 0 when this register is
read.
Remote IR Modes:
RX_PD - Receiver Pulse Detected
Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register is
read.
Bit 3
MIR, FIR Modes:
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure of PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
This bit should be set to 1, if use in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Bit 2:
Bit 1:
Reserved.
MIR, FIR Modes:
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends still stay in receiver FIFO.
MIR, FIR, Remote IR Modes:
Bit 0:
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
4.3 Set1 - Legacy Baud Rate Divisor Register
Address Offset Register Name
Register Description
Baud Rate Divisor Latch (Low Byte)
0
1
2
3
4
5
6
7
BLL
BHL
ISR/UFR
UCR/SSR
HCR
USR
HSR
UDR/ESCR
Baud Rate Divisor Latch (High Byte)
Interrupt Status or IR FIFO Control Register
IR Control or Sets Select Register
Handshake Control Register
IR Status Register
Handshake Status Register
User Defined Register
Publication Release Date: March 1998
Revision 0.58
- 60 -
W83977F/ W83977AF
PRELIMINARY
4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
Set & Register
Advanced Mode
Legacy Mode
DIS_BACK=0
¡ Ñ
DIS_BACK=
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
Bit 7~5
Bit 0, 5, 7
Bit 2, 3
-
Bit 5, 7
-
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any
register which is meaningful in legacy SIR/ASK-IR.
4.3.2 Set1.Reg 2~7
These registers are defined as the same as Set 0 registers.
4.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes.
Address Offset Register Name
Register Description
Advanced Baud Rate Divisor Latch (Low Byte)
Advanced Baud Rate Divisor Latch (High Byte)
Advanced IR Control Register 1
Sets Select Register
Advanced IR Control Register 2
-
Transmitter FIFO Depth
0
1
2
3
4
5
6
7
ABLL
ABHL
ADCR1
SSR
ADCR2
Reserved
TXFDTH
RXFDTH
Receiver FIFO Depth
4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced
SIR/ASK-IR mode, user should program these registers to set baud rate. This is to prevent backward
operation from occurring.
4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR BR_OUT
-
0
EN_LOUT ALOOP D_CHSW DMATHL DMA_F ADV_SL
Reset Value
0
0
0
0
0
0
0
Bit 7:
BR_OUT - Baud Rate Clock Output
When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is
only used to test baud rate divisor.
Bit 6:
Bit 5:
Reserved, write 0.
EN_LOUT - Enable Loopback Output
A write to 1 will enable transmitter to output data to IRTX pin when loopback operation.
Internal data can be verified through an output pin by setting this bit.
Publication Release Date: March 1998
- 61 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Bit 4:
Bit 3:
ALOOP - All Mode Loopback
A write to 1 will enable loopback in all modes.
D_CHSW - DMA TX/RX Channel Swap
If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be
swapped.
D_CHSW
DMA Channel Selected
Receiver (Default)
Transmitter
0
1
A write to 1 will enable output data when ALOOP=1.
DMATHL - DMA Threshold Level
Bit 2:
Set DMA threshold level as shown in the following table.
DMATHL
TX FIFO Threshold
RX FIFO Threshold
16-Byte
32-Byte
(16/32-Byte)
13
23
13
7
4
10
0
1
Bit 1:
Bit 0:
DMA_F - DMA Fairness
DMA_F
Function Description
DMA request (DREQ) is forced inactive after 10.5us
No effect DMA request.
0
1
ADV_SL - Advanced Mode Select
A write to 1 selects advanced mode.
4.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E0H. Writing a value selects Register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Refault Value
SSR7
1
SSR6
1
SSR5
1
SSR4
0
SSR3
0
SSR2
0
SRR1
0
SRR0
0
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR DIS_BACK
-
0
PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
Reset Value
0
0
0
0
0
0
0
Bit 7:
DIS_BACK - Disable Backward Operation
A write to 1 disables backward legacy IR mode. When operate in legacy SIR/ASK-IR
mode, this bit should be set to 1 to avoid backward operation.
Reserved, write 0.
Bit 6:
Bit 5, 4:
PR_DIV1~0 - Pre-Divisor 1~0.
These bits select pre-divisor for external input clock 24M Hz. The clock goes through the
pre-divisor then input to baud rate divisor of IR.
PR_DIV1~0
Pre-divisor
Max. Baud Rate
115.2K bps
921.6K bps
230.4K bps
1.5M bps
13.0
1.625
6.5
00
01
10
11
1
Publication Release Date: March 1998
Revision 0.58
- 62 -
W83977F/ W83977AF
PRELIMINARY
Bit 3, 2:
RX_FSZ1~0 - Receiver FIFO Size 1~0
These bits setup receiver FIFO size when FIFO is enable.
RX_FSZ1~0
RX FIFO Size
00
01
1X
16-Byte
32-Byte
Reserved
Bit 1, 0:
TX_FSZ1~0 - Transmitter FIFO Size 1~0
These bits setup transmitter FIFO size when FIFO is enable.
TX_FSZ1~0
TX FIFO Size
00
01
1X
16-Byte
32-Byte
Reserved
TABLE: SIR Baud Rate
Pre-Div: 13
BAUD RATE FROM DIFFERENT PRE-DIVIDER
Pre-Div:1.625
Pre-Div:
1.0
Decimal divisor used Error Percentage between
to generate 16X clock
desired and actual
1.8461M Hz
14.769M Hz
24M Hz
650
50
75
400
600
**
2304
1536
1047
857
768
384
192
96
975
**
110
880
1430
0.18%
134.5
150
1076
1478.5
1950
0.099%
1200
**
**
300
2400
3900
600
4800
7800
**
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
9600
15600
23400
26000
31200
46800
62400
93600
124800
249600
499200
748800
1497600
**
14400
16000
19200
28800
38400
57600
76800
153600
307200
460800
921600
**
64
0.53%
**
58
48
**
32
**
24
**
16
**
12
**
6
**
3
**
2
**
1
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
Publication Release Date: March 1998
Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR
Reset Value
0
0
0
0
TXFD5
0
TXFD4
0
TXFD3
0
TXFD2
0
TXFD1
0
TXFD1
0
Bit 7~6:
Bit 5~0:
Reserved, Read 0.
Reading these bits returns the current transmitter FIFO depth, that is, the number of
bytes left in the transmitter FIFO.
4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR
Reset Value
0
0
0
0
RXFD5
0
RXFD4
0
RXFD3
0
RXFD2
0
RXFD1 RXFD1
0
0
Bit 7~6:
Bit 5~0:
Reserved, Read 0.
Reading these bits returns the current receiver FIFO depth, that is, the number of bytes
left in the receiver FIFO.
4.5 Set3 - Version ID and Mapped Control Registers
Address Offset Register Name Register Description
Advanced IR ID
Mapped IR Control Register
Mapped IR FIFO Control Register
Sets Select Register
0
1
2
3
4
5
6
7
AUID
MP_UCR
MP_UFR
SSR
Reversed
Reserved
Reserved
Reserved
-
-
-
-
4.5.1 Reg0 - Advanced IR ID (AUID)
This register is read only. It stores advanced IR version ID. Reading it returns 1XH.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
SSR7
0
SSR6
0
SSR5
0
SSR4
1
SSR3
X
SSR2
X
SRR1
X
SRR0
X
4.5.2 Reg1 - Mapped IR Control Register (MP_UCR)
This register is read only. Reading this register returns IR Control Register value of Set 0.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
SSR7
0
SSR6
0
SSR5
0
SSR4
0
SSR3
0
SSR2
0
SRR1
0
SRR0
0
Publication Release Date: March 1998
Revision 0.58
- 64 -
W83977F/ W83977AF
PRELIMINARY
4.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR)
This register is read only. Reading this register returns IR FIFO Control Register (UFR) value of SET
0.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
SSR7
0
SSR6
0
SSR5
0
SSR4
0
SSR3
0
SSR2
0
SRR1
0
SRR0
0
4.5.4 Reg3 - Sets Select Register (SSR)
Reading this register returns E4H. Writing a value selects a Register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
SSR7
1
SSR6
1
SSR5
1
SSR4
0
SSR3
0
SSR2
1
SRR1
0
SRR0
0
4.6 Set4 - TX/RX/Timer counter registers and IR control registers.
Address Offset Register Name Register Description
Timer Value Low Byte
0
1
2
3
4
5
6
7
TMRL
TMRH
IR_MSL
SSR
TFRLL
TFRLH
RFRLL
RFRLH
Timer Value High Byte
Infrared Mode Select
Sets Select Register
Transmitter Frame Length Low Byte
Transmitter Frame Length High Byte
Receiver Frame Length Low Byte
Receiver Frame Length High Byte
4.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)
This is a 12-bit timer whose resolution is 1ms, that is, the maximum programmable time is 212-1 ms.
The timer is a down-counter and starts counting down when EN_TMR (Enable Timer) of Set4.Reg2 is
set to 1. When the timer counts down to zero and EN_TMR=1, the TMR_I is set to 1 and a new initial
value will be loaded into counter.
4.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL)
Mode
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR
Reset Value
-
0
-
0
-
0
-
0
IR_MSL1
0
IR_MSL0
0
TMR_TST
0
EN_TMR
0
Bit 7~4:
Bit 3, 2:
Reserved, write to 0.
IR_MSL1, 0 - Infrared Mode Select
Select legacy IR, SIR, or ASK-IR mode. Note that in legacy SIR/ASK-IR user should set
DIS_BACK=1 to avoid backward when programming baud rate.
IR_MSL1, 0
Operation Mode Selected
00
01
10
11
Legacy IR
CIR
Legacy ASK-IR
Legacy SIR
Publication Release Date: March 1998
Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
Bit 1:
Bit 0:
TMR_TST - Timer Test
When set to 1, reading the TMRL/TMRH returns the programmed values of TMRL/TMRH
instead of the value of down counter. This bit is for testing timer register.
EN_TMR - Enable Timer
A write to 1 will enable the timer.
4.6.3 Set4.Reg3 - Set Select Register (SSR)
Reading this register returns E8H. Writing this register selects Register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
SSR7
1
SSR6
1
SSR5
1
SSR4
1
SSR3
1
SSR2
0
SRR1
0
SRR0
0
4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TFRLL
bit 7
0
-
bit 6
0
-
bit 5
0
-
bit 4
0
bit 12
0
bit3
0
bit 11
0
bit 2
0
bit 10
0
bit 1
0
bit 9
0
bit 0
0
bit 8
0
Reset Value
TFRLH
Reset Value
-
-
-
These are combined to be a 13-bit register. Writing these registers programs the transmitter frame
length of a package. These registers are only valid when APM=1 (automatic package mode,
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame
length if the transmitted data is larger than the programmed frame length. When these registers are
read, they will return the number of bytes which is not transmitted from a frame length programmed.
4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFRLL
bit 7
0
-
bit 6
0
-
bit 5
0
-
bit 4
0
bit 12
0
bit 3
0
bit 11
0
bit 2
0
bit 10
0
bit 1
0
bit 9
0
bit 0
0
bit 8
0
Reset Value
RFRLH
Reset Value
-
-
-
These are combined to be a 13-bit registers and up counter. The length of receiver frame will be
limited to the programmed frame length. If the received frame length is larger than the programmed
receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously,
the receiver will not receive any more data to RX FIFO until the next start flag of the next frame,
which is defined in the physical layer IrDA 1.1. Reading these registers returns the number of
received data bytes of a frame from the receiver.
Publication Release Date: March 1998
- 66 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.7 Set 5 - Flow control and IR control and Frame Status FIFO registers
Address Offset Register Name
Register Description
Flow Control Baud Rate Divisor Latch Register (Low Byte)
Flow Control Baud Rate Divisor Latch Register (High Byte)
Flow Control Mode Operation
Sets Select Register
Infrared Configure Register
Frame Status FIFO Register
Receiver Frame Length FIFO Low Byte
Receiver Frame Length FIFO High Byte
0
1
2
3
4
5
6
7
FCBLL
FCBHL
FC_MD
SSR
IRCFG1
FS_FO
RFRLFL
RFRLFH
4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)
These registers control flow control mode operation as shown in the following table.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FC_MD FC_MD2 FC_MD1 FC_MD0
-
0
FC_DSW EN_FD EN_BRFC EN_FC
Reset Value
0
0
0
0
0
0
0
Bit 7~5
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced
HSR (Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Reserved, write 0.
Bit 4:
Bit 3:
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allow user to swap DMA channel for transmitter or receiver when flow control
is enforced.
FC_DSW
Next Mode After Flow Control Occurred
Receiver Channel
0
1
Transmitter Channel
Bit 2:
Bit 1:
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
Bit 0:
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
Publication Release Date: March 1998
- 67 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.7.3 Set5.Reg3 - Sets Select Register (SSR)
Writing this register selects Register Set. Reading this register returns ECH.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
SSR7
1
SSR6
1
SSR5
1
SSR4
0
SSR3
1
SSR2
1
SRR1
0
SRR0
0
4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRCFG1
Reset Value
-
0
FSF_TH FEND_M AUX_RX
-
0
-
0
IRHSSL IR_FULL
0
0
0
0
0
Bit 7:
Bit 6:
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the
FSF_I. The threshold level values are defined as follows.
FSF_TH
Status FIFO Threshold Level
2
4
0
1
Bit 5:
Bit 4:
FEND_MD - Frame End Mode
A write to 1 enables hardware to split data stream into equal length frame automatically
as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved, write 0.
IRHSSL - Infrared Handshake Status Select
Bit 3~2:
Bit 1:
When set to 0, the HSR (Handshake Status Register) operates as same as defined in IR
mode. A write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
Bit 0:
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate
in full duplex.
4.7.5Set5.Reg5 - Frame Status FIFO Register (FS_FO)
This register shows the bottom byte of frame status FIFO.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS_FO
Reset Value
FSFDR
0
LST_FR
0
-
0
MX_LEX PHY_ERR CRC_ERR RX_OV FSF_OV
0
0
0
0
0
Bit 7:
Bit 6:
Bit 5:
FSFDR - Frame Status FIFO Data Ready
Indicate that a data byte is valid in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more frames have been lost.
Reserved.
Publication Release Date: March 1998
Revision 0.58
- 68 -
W83977F/ W83977AF
PRELIMINARY
Bit 4:
Bit 3:
Bit 2:
MX_LEX - Maximum Frame Length Exceed
Set to 1 when incoming data exceeds programmed maximum frame length defined in
Set4.Reg6 and Set4.Reg7. This bit is in frame status FIFO bottom and is valid only when
FSFDR=1 (Frame Status FIFO Data Ready).
PHY_ERR - Physical Error
When receiving data, any physical layer error as defined in IrDA 1.1 will set this bit to 1.
This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status
FIFO Data Ready).
CRC_ERR - CRC Error
Set to 1 when receive a bad CRC in a frame. This CRC belongs to physical layer as
defined in IrDA 1.1. This bit is in frame status FIFO bottom and is valid only when
FSFDR=1 (Frame Status FIFO Data Ready).
Bit 1:
Bit 0:
RX_OV - Received Data Overrun
Set to 1 when receiver FIFO overruns.
FSF_OV - Frame Status FIFO Overrun
Set to 1 When frame status FIFO overruns.
4.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number
(LST_NU)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFLFL/ LST_NU
Bit 7
0
-
Bit 6
0
-
Bit 5
0
-
Bit 4
0
Bit 12
0
Bit 3
0
Bit 11
0
Bit 2
0
Bit 10
0
Bit 1
0
Bit 9
0
Bit 0
0
Bit 8
0
Reset Value
RFLFH
Reset Value
0
0
0
Receiver Frame Length FIFO (RFLFL/RFLFH):
These are combined to be a 13-bit register. Reading these registers returns received byte count for
the frame. When read, the register of RFLFH will pop-up another frame status and frame length if
FSFDR=1 (Set5.Reg4.Bit7).
Lost Frame Number (LST_NU):
When LST_FR=1 (Set5.Reg4.Bit6), Reg6 stands for LST_NU which is a 8-bit register holding the
number of frames lost in succession.
4.8 Set6 - IR Physical Layer Control Registers
Address Offset Register Name
Register Description
Infrared Configure Register 2
0
1
2
3
4
5
6
7
IR_CFG2
MIR_PW
SIR_PW
SSR
MIR (1.152M bps or 0.576M bps) Pulse Width
SIR Pulse Width
Sets Select Register
High Speed Infrared Flag Number
HIR_FNU
Reserved
Reserved
Reserved
-
-
-
Publication Release Date: March 1998
Revision 0.58
- 69 -
W83977F/ W83977AF
PRELIMINARY
4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)
This register controls ASK-IR, MIR, FIR operations.
Reg. Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IR_CFG2 SHMD_N SHDM_N FIR_CRC MIR_CRC
-
INV_CRC DIS_CRC
-
Reset Value
0
0
1
0
0
0
0
0
Bit 7:
Bit 6:
Bit 5:
SHMD_N - ASK-IR Modulation Disable
SHMD_N
Modulation Mode
0
1
IRTX modulate 500K Hz Square Wave
Re-rout IRTX
SHDM_N - ASK-IR Demodulation Disable
SHDM_N
Demodulation Mode
Demodulation 500K Hz
Re-rout IRRX
0
1
FIR_CRC - FIR (4M bps) CRC Type
FIR_CRC
CRC Type
16-bit CRC
32-bit CRC
0
1
Note that the 16/32-bit CRC are defined in IrDA 1.1 physical layer.
Bit 4:
MIR_CRC - MIR (1.152M/0.576M bps) CRC Type
MIR_CRC
CRC Type
16-bit CRC
32-bit CRC
0
1
Bit 2:
Bit 1:
Bit 0:
INV_CRC - Inverting CRC
When set to 1, the CRC is inversely output in physical layer.
DIS_CRC - Disable CRC
When set to 1, the transmitter does not transmit CRC in physical layer.
Reserved, write 1.
4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MIR_PW
Reset Value
-
0
-
0
-
0
M_PW4 M_PW3 M_PW2 M_PW1 M_PW0
0
1
0
1
0
This 5-bit register sets MIR output pulse width.
M_PW4~0
MIR Pulse Width (1.152M bps)
MIR Output Width (0.576M bps)
00000
00001
00010
...
0 ns
0 ns
20.83 ns
41.66 ns
41.66 (==20.83*2) ns
83.32 (==41.66*2) ns
...
20.83*k10 ns
...
...
41.66*k10 ns
...
k10
...
11111
645 ns
1290 ns
Publication Release Date: March 1998
Revision 0.58
- 70 -
W83977F/ W83977AF
PRELIMINARY
4.8.3 Set6.Reg2 - SIR Pulse Width
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIR_PW
-
-
-
S_PW4 S_PW3 S_PW2 S_PW1 S_PW0
Reset Value
0
0
0
0
0
0
0
0
This 5-bit register sets SIR output pulse width.
S_PW4~0
00000
SIR Output Pulse Width
3/16 bit time of IR
1.6 us
01101
Others
1.6 us
4.8.4 Set6.Reg3 - Set Select Register
Select Register Set by writing a set number to this register. Reading this register returns F0H.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
SSR7
1
SSR6
1
SSR5
1
SSR4
1
SSR3
0
SSR2
0
SRR1
0
SRR0
0
4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HIR_FNU
Reset Value
M_FG3 M_FG2
M_FG1 M_FG0
F_FL3
1
F_FL2
0
F_FL1
1
F_FL0
0
0
0
1
0
Bit 7~4:
M_FG3~0 - MIR beginning Flag Number
These bits define the number of transmitter Start Flag of MIR. Note that the number of
MIR start flag should be equal or more than two which is defined in IrDA 1.1 physical
layer. The default value is 2.
M_FG3~0
Beginning Flag Number
M_FG3~0
1000
Beginning Flag Number
Reserved
10
12
16
20
24
0000
0001
0010
0011
0100
0101
0110
0111
1
1001
1010
1011
1100
1101
1110
1111
2 (Default)
3
4
5
6
8
28
32
Reserved
Publication Release Date: March 1998
Revision 0.58
- 71 -
W83977F/ W83977AF
PRELIMINARY
Bit 3~0:
F_FG3~0 - FIR Beginning Flag Number
These bits define the number of transmitter Preamble Flag in FIR. Note that the number
of FIR start flag should be equal to sixteen which is defined in IrDA 1.1 physical layer.
The default value is 16.
M_FG3~0
Beginning Flag Number
M_FG3~0
1000
Beginning Flag Number
Reserved
10
12
0000
0001
0010
0011
0100
0101
0110
0111
1
2
3
4
5
6
8
1001
1010
1011
1100
1101
1110
1111
16 (Default)
20
24
28
32
Reserved
4.9 Set7 - Remote control and IR module selection registers
Address Offset Register Name Register Description
Remote Infrared Receiver Control
0
1
2
3
4
5
6
7
RIR_RXC
RIR_TXC
RIR_CFG
SSR
Remote Infrared Transmitter Control
Remote Infrared Config Register
Sets Select Register
Infrared Module (Front End) Select 1
Infrared Module Select 2
IRM_SL1
IRM_SL2
IRM_SL3
IRM_CR
Infrared Module Select 3
Infrared Module Control Register
4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RIR_RXC
Default Value
RX_FR2 RX_FR1 RX_FR0 RX_FSL4 RX_FSL3 RX_FSL2 RX_FSL1 RX_FSL0
0
0
1
0
1
0
0
1
This register defines frequency range of receiver of remote IR.
Bit 7~5:
RX_FR2~0 - Receiver Frequency Range 2~0.
These bits select the input frequency range of the receiver. It is implemented through a
band pass filter, i.e., only the input signals whose frequency lies in the range defined in
this register will be received.
Bit 4~0:
RX_FSL4~0 - Receiver Frequency Select 4~0.
Select the operation frequency of receiver.
Publication Release Date: March 1998
- 72 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Table: Low Frequency range select of receiver.
RX_FR2~0 (Low Frequency)
010
001
011
RX_FSL4~0
Min.
26.1
28.2
29.4
30.0
31.4
32.1
32.8
33.6*
34.4
36.2
37.2
38.2
40.3
41.5
42.8
44.1
45.5
48.7
50.4
54.3
Max.
29.6
32.0
33.3
34.0
35.6
36.4
37.2
38.1*
39.0
41.0
42.1
43.2
45.7
47.1
48.5
50.0
51.6
55.2
57.1
61.5
Min.
24.7
26.7
27.8
28.4
29.6
30.3
31.0
31.7
32.5
34.2
35.1
36.0
38.1
39.2
40.4
41.7
43.0
46.0
47.6
51.3
Max.
31.7
34.3
35.7
36.5
38.1
39.0
39.8
40.8
41.8
44.0
45.1
46.3
49.0
50.4
51.9
53.6
55.3
59.1
61.2
65.9
Min.
23.4
25.3
26.3
26.9
28.1
28.7
29.4
30.1
30.8
32.4
33.2
34.1
36.1
37.2
38.3
39.5
40.7
43.6
45.1
48.6
Max.
34.2
36.9
38.4
39.3
41.0
42.0
42.9
44.0
45.0
47.3
48.6
49.9
52n.7
54.3
56.0
57.7
59.6
63.7
65.9
71.0
00010
00011
00100
00101
00110
00111
01000
01001
01011
01100
01101
01111
10000
10010
10011
10101
10111
11010
11011
11101
Note that those unassigned combinations are reserved.
Table: High Frequency range select of receiver
RX_FR2~0 (High Frequency)
001
Min.
Max.
RX_FSL4~0
355.6
380.1
410.3
457.1
489.8
527.4
00011
01000
01011
Note that those unassigned combinations are reserved.
Table: SHARP ASK-IR receiver frequency range select.
RX_FSL4~0 (SHARP ASK-IR)
011 100
RX_FR2~0
001
010
101
110
-
480.0* 533.3* 457.1 564.7 436.4 600.0 417.4 640.0 400.0 685.6 384.0 738.5
Note that those unassigned combinations are reserved.
Publication Release Date: March 1998
Revision 0.58
- 73 -
W83977F/ W83977AF
PRELIMINARY
4.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC)
Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
RIR_TXC TX_PW2 TX_PW1 TX_PW0 TX_FSL4 TX_FSL3 TX_FSL2 TX_FSL1 TX_FSL0
Default Value
0
1
1
0
1
0
0
1
This Register defines the transmitter frequency and pulse width of remote IR.
Bit 7~5:
TX_PW2~0 - Transmitter Pulse Width 2~ 0.
Select the transmission pulse width.
TX_PW2~0
010
Low Frequency
6 m s
High Frequency
0.7 m s
011
7 m s
0.8 m s
100
9 m s
0.9 m s
101
10.6 m s
1.0 m s
Note that those unassigned combinations are reserved.
Bit 4~0:
TX_FSL4~0 - Transmitter Frequency Select 4~0.
Select the transmission frequency.
Table: Low frequency selected.
TX_FSL4~0
00011
00100
...
Low Frequency
30K Hz
31K HZ
...
56K Hz
11101
Note that those unassigned combinations are reserved.
Table: High frequency selected.
TX_FSL4~0
00011
High Frequency
400K Hz
450K Hz
480K Hz
01000
01011
Note that those unassigned combinations are reserved.
4.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RIR_CFG
Default Value
P_PNB
0
SMP_M RXCFS
-
0
TX_CFS RX_DM TX_MM1 TX_MM0
0
0
0
0
0
0
Publication Release Date: March 1998
Revision 0.58
- 74 -
W83977F/ W83977AF
PRELIMINARY
Bit 7:
P_PNB: Programming Pulse Number Coding.
Write a 1 to select programming pulse number coding. The code format is defined as
follows.
(Number of bits) - 1
B7 B6 B5 B4 B3 B2 B1 B0
Bit value
If the bit value is set to 0, the high pulse will be transmitted/received. If the bit value is
set to 1, then no energy will be transmitted/received.
SMP_M - Sampling Mode.
To select receiver sampling mode.
When set to 0 then uses T-period sampling, that the T-period is programmed IR baud
rate.
Bit 6:
Bit 5:
When set to 1, programmed baud rate will be used to do oversampling.
RXCFS - Receiver Carry Frequency Select
RXCFS
Selected Frequency
30K ~ 56K Hz
0
1
400K ~ 480K Hz
Bit 4:
Bit 3:
Reserved, write 0.
TX_CFS - Transmitter Carry Frequency Select.
Select low speed or high speed transmitter carry frequency.
TX_FCS
Selected Frequency
30K ~ 56K Hz
0
400K ~ 480K Hz
1
Bit 2:
RX_DM - Receiver Demodulation Mode.
RX_DM
Demodulation Mode
Enable internal decoder
Disable internal decoder
0
1
Bit 1~0:
TX_MM1~0 - Transmitter Modulation Mode 1~0
TX_MM1~0
TX Modulation Mode
Continuously send pulse for logic 0
8 pulses for logic 0 and no pulse for logic 1.
6 pulses for logic 0 and no pulse for logic 1
Reserved.
00
01
10
11
4.9.4 Set7.Reg3 - Sets Select Register (SSR)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
Default Value
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
0
Bit 2
1
Bit 1
0
Bit 0
0
Reading this register returns F4H. Select Register Set by writing a set number to this register.
Publication Release Date: March 1998
Revision 0.58
- 75 -
W83977F/ W83977AF
PRELIMINARY
4.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRM_SL1
Default Value
IR_MSP SIR_SL2 SIR_SL1 SIR_SL0
-
0
AIR_SL2 AIR_SL1 AIR_SL0
0
0
0
0
0
0
0
Bit 7:
IR_MSP - IR Mode Select Pulse
When set to 1, the transmitter (IRTX) will send a 64 ms pulse to setup a special IR front-
end operational mode. When IR front-end module uses mode select pin (MD) and
transmitter IR pulse (IRTX) to switch between high speed IR (such as FIR or MIR) and
low speed IR (SIR or ASK-IR), this bit should be used.
Bit 6~4:
SIR_SL2~0 - SIR (Serial IR) mode select.
These bits are used to program the operational mode of the SIR front-end module.
These values of SIR_SL2~0 will be automatically loaded to pins of IR_SL2~0,
respectively, when (1) AM_FMT=1 (Automatic Format, in Set7.Reg7.Bit7); (2) the mode
of Advanced IR is set to SIR (AD_MD2~0, in Set0.Reg4.Bit7~0).
Reserved, write 0.
Bit 3:
Bit 2~0:
AIR_SL2~0 - ASK-IR Mode Select.
These bits setup the operational mode of ASK-IR front-end module when AM_FMT=1
and AD_MD2~0 are configured to ASK-IR mode. These values will be automatically
loaded to IR_SL2~0, respectively.
4.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRM_SL2
Default Value
-
0
FIR_SL2 FIR_SL1 FIR_SL0
-
0
MIR_SL2 MIR_SL1 MIR_SL0
0
0
0
0
0
0
Bit 7:
Bit 6~4:
Reserved, write 0.
FIR_SL2~0 - FIR mode select.
These bits setup the operational mode of FIR front-end module when AM_FMT=1 and
AD_MD2~0 are configured to FIR mode. These values will be automatically loaded to
IR_SL2~0, respectively.
Bit 3:
Reserved, write 0.
Bit 2~0:
MIR_SL2~0 - MIR Mode Select.
These bits setup the MIR operational mode when AM_FMT=1 and AD_MD2~0 are
configured to MIR mode. These values will be automatically loaded to IR_SL2~0,
respectively.
4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRM_SL3
Default Value
-
0
LRC_SL2 LRC_SL1 LRC_SL0
-
0
HRC_SL2 HRC_SL1 HRC_SL0
0
0
0
0
0
0
Bit 7:
Bit 6~4:
Reserved, write 0.
LRC_SL2~0 - Low Speed Remote IR mode select.
These bits setup the operational mode of low speed remote IR front-end module when
AM_FMT=1 and AD_MD2~0 are configured to Remote IR mode. These values will be
automatically loaded to IR_SL2~0, respectively.
Publication Release Date: March 1998
- 76 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Bit 3:
Reserved, write 0.
Bit 2~0:
HRC_SL2~0 - High Speed Remote IR Mode Select.
These bits setup the operational mode of high speed remote IR front-end module when
AM_FMT=1 and .AD_MD2~0 are configured to Remote IR mode. These values will be
automatically loaded to IR_SL2~0, respectively.
4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRM_CR
Default Value
AM_FMT IRX_MSL IRSL0D
RXINV
0
TXINV
0
-
0
-
0
-
0
0
0
0
Bit 7:
AM_FMT - Automatic Format
A write to 1 will enable automatic format IR front-end module. These bit will affect the
output of IR_SL2~0 which is referred by IR front-end module selection (Set7.Reg4~6)
IRX_MSL - IR Receiver Module Select
Bit 6:
Select the receiver input path from the IR front end module if IR module has the
separated high speed and low speed receiver path. If the IR module has only one
receiving path, then this bit should be set to 0.
IRX_MSL
Receiver Pin selected
IRRX (Low/High Speed)
IRRXH (High Speed)
0
1
Bit 5:
IRSL0D - Direction of IRSL0 Pin
Select function for IRRXH or IRSL0 because they share common pin and have different
input/output direction.
IRSL0_D
Function
IRRXH (I/P)
IRSL0 (O/P)
0
1
Table: IR receiver input pin selection
IRSL0D
IRX_MSL
AUX_RX
High Speed IR
Selected IR Pin
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
X
X
0
1
X
X
X
X
0
1
X
X
0
1
IRRX
IRRXH
IRRX
IRRXH
IRRX
Reserved
IRRX
Reserved
Note: that (1) AUX_RX is defined in Set5.Reg4.Bit4, (2) high speed IR includes MIR (1.152M or 0.576M bps) and FIR (4M bps), (3)
IRRX is the input of the low speed or high speed IR receiver, IRRXH is the input of the high speed IR receiver.
Bit 4:
RXINV - Receiving Signal Invert
A write to 1 will Invert the receiving signal.
TXINV - Transmitting Signal Invert
A write to 1 will Invert the transmitting signal.
Reserved, write 0.
Bit 3:
Bit 2~0:
Publication Release Date: March 1998
Revision 0.58
- 77 -
W83977F/ W83977AF
PRELIMINARY
5. PARALLEL PORT
5.1 Printer Interface Logic
The parallel port of the W83977F/ AF makes possible the attachment of various devices that accept
eight bits of parallel data at standard TTL level. The W83977F/ AF supports an IBM XT/AT
compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP),
Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode
(EXT2FDD) on the parallel port. Refer to the configuration registers for more information on
disabling, power-down, and on selecting the mode of operation.
Table 5-1 shows the pin definitions for different modes of the parallel port.
TABLE 5-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
HOST
PIN NUMBER
PIN
SPP
EPP
ECP
CONNECTOR
OF W83977F/ AF
ATTRIBUTE
2
1
36
O
I/O
I
nSTB
PD<0:7>
nACK
BUSY
PE
nWrite
PD<0:7>
Intr
nSTB, HostClk
2-9
10
11
12
13
14
15
16
17
31-26, 24-23
PD<0:7>
2
22
21
19
18
35
34
33
32
nACK, PeriphClk
2
I
nWait
PE
BUSY, PeriphAck
2
I
PEerror, nAckReverse
2
I
SLCT
nAFD
nERR
nINIT
nSLIN
Select
nDStrb
nError
nInit
SLCT, Xflag
2
O
I
nAFD, HostAck
1
2
nFault , nPeriphRequest
1
2
O
O
nINIT , nReverseRqst
1
2
nAStrb
nSLIN , ECPMode
Notes:
n<name > : Active Low
1. Compatible Mode
2. High Speed Mode
3. For more information, refer to the IEEE 1284 standard.
TABLE 5-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
HOST
CONNECTOR
PIN NUMBER OF
W83977F/ AF
PIN
ATTRIBUTE
SPP
PIN
ATTRIBUTE
EXT2FDD
PIN
ATTRIBUTE
EXTFDD
1
2
36
31
O
nSTB
PD0
---
I
---
---
I
---
I/O
INDEX2
TRAK02
WP2
INDEX2
TRAK02
WP2
3
4
5
6
7
30
29
28
27
26
I/O
I/O
I/O
I/O
I/O
PD1
PD2
PD3
PD4
PD5
I
I
I
I
I
I
RDATA2
RDATA2
I
I
DSKCHG2
---
DSKCHG2
---
---
---
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PRELIMINARY
TABLE 5-1-2, continued
HOST
PIN NUMBER OF
PIN
SPP
PIN
EXT2FDD
PIN
EXTFDD
CONNECTOR
W83977F/ AF
ATTRIBUTE
ATTRIBUTE
ATTRIBUTE
8
24
23
22
21
19
18
35
34
I/O
PD6
PD7
OD
OD
OD
OD
OD
OD
OD
OD
---
---
---
MOA2
DSA2
DSB2
MOB2
WD2
9
I/O
---
10
11
12
13
14
15
I
I
nACK
BUSY
PE
OD
OD
OD
OD
OD
OD
DSB2
MOB2
WD2
I
I
SLCT
nAFD
nERR
WE2
WE2
O
I
RWC2
HEAD2
DIR2
RWC2
HEAD2
DIR2
16
17
33
32
O
O
nINIT
OD
OD
OD
OD
nSLIN
STEP2
STEP2
5.2 Enhanced Parallel Port (EPP)
TABLE 5-2 PRINTER MODE AND EPP REGISTER ADDRESS
A2
0
A1
0
A0
0
REGISTER
NOTE
Data port (R/W)
1
1
1
1
2
2
2
2
2
0
0
1
Printer status buffer (Read)
Printer control latch (Write)
Printer control swapper (Read)
EPP address port (R/W)
EPP data port 0 (R/W)
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
EPP data port 1 (R/W)
1
1
0
EPP data port 2 (R/W)
1
1
1
EPP data port 2 (R/W)
Notes:
1. These registers are available in all modes.
2. These registers are available only in EPP mode.
5.2.1 Data Swapper
The system microprocessor can read the contents of the printer's data latch by reading the data
swapper.
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PRELIMINARY
5.2.2 Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the printer status
buffer. The bit definitions are as follows:
7
6
5
4
3
2
1
1
1
0
TMOUT
ERROR
SLCT
PE
ACK
BUSY
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print
head is changing position, or during an error state. When this signal is active, the printer is
busy and cannot accept data.
Bit 6: This bit represents the current state of the printer's
signal. A 0 means the printer has
ACK
received a character and is ready to accept another. Normally, this signal will be active for
approximately 5 microseconds before BUSY stops.
Bit 5: Logical 1 means the printer has detected the end of paper.
Bit 4: Logical 1 means the printer is selected.
Bit 3: Logical 0 means the printer has encountered an error condition.
Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.
Bit 0: This bit is valid in EPP mode only. It indicates that a 10 mS time-out has occurred on the EPP
bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error
has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0
has no effect.
5.2.3 Printer Control Latch and Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the printer
control swapper. Bit definitions are as follows:
7
1
6
1
5
4
3
2
1
0
STROBE
AUTO FD
INIT
SLCT IN
IRQ ENABLE
DIR
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Bit 7, 6: These two bits are a logic one during a read. They can be written.
Bit 5: Direction control bit
When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the
parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit
is invalid and fixed at zero.
Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low to high.
Bit 3: A 1 in this bit position selects the printer.
Bit 2: A 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A 1 causes the printer to line-feed after a line is printed.
Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microseconds before and after the strobe pulse.
5.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW causes an EPP address write cycle to be performed, and the
trailing edge of IOW latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
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PRELIMINARY
5.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-
inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes
an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the
duration of the EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read
cycle to be performed and the data to be output to the host CPU.
5.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
3
2
PD2
1
1
PD1
1
0
Data Port (R/W)
PD7
PD6
PD5
PE
PD4
SLCT
PD3
PD0
Status Buffer (Read)
TMOUT
BUSY
ACK
ERROR
SLIN
Control Swapper (Read)
Control Latch (Write)
1
1
1
1
1
IRQEN
IRQ
INIT
AUTOFD
STROBE
DIR
SLIN
INIT
PD2
AUTOFD
PD1
STROBE
PD0
EPP Address Port R/W)
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
PD7
PD7
PD7
PD7
PD7
PD6
PD6
PD6
PD6
PD6
PD5
PD5
PD5
PD5
PD5
PD4
PD4
PD4
PD4
PD4
PD3
PD3
PD3
PD3
PD3
PD2
PD2
PD2
PD2
PD1
PD1
PD1
PD1
PD0
PD0
PD0
PD0
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PRELIMINARY
5.2.7 EPP Pin Descriptions
EPP NAME
nWrite
TYPE
EPP DESCRIPTION
O
I/O
I
Denotes an address or data read or write operation.
Bi-directional EPP address and data bus.
PD<0:7>
Intr
Used by peripheral device to interrupt the host.
nWait
I
Inactive to acknowledge that data transfer is completed. Active to
indicate that the device is ready for the next transfer.
PE
I
I
Paper end; same as SPP mode.
Select
nDStrb
nError
nInits
Printer selected status; same as SPP mode.
This signal is active low. It denotes a data read or write operation.
Error; same as SPP mode.
O
I
O
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
nAStrb
O
This signal is active low. It denotes an address read or write operation.
5.2.8 EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP
Control Port and the direction is controlled by DIR of the Control Port.
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 mS
have elapsed from the start of the EPP cycle to the time
is deasserted. The current EPP cycle
WAIT
is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.
5.2.8.1 EPP Operation
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address
Read, and Data Read. All operations on the EPP device are performed asynchronously.
5.2.8.2 EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or
write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds
normally and will be completed when nWait goes inactive high.
b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to
active low, at which time it will start as described above.
5.2.8.3 EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive
high.
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PRELIMINARY
5.3 Extended Capabilities Parallel (ECP) Port
This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel
that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host)
directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for
the standard parallel port to improve compatibility mode transfer speed.
The ECP port supports run-length-encoded (RLE) decompression (required) in hardware.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates
how many times the next byte is to be repeated. Hardware support for compression is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and
ISA Interface Standard.
5.3.1 ECP Register and Mode Definitions
NAME
data
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
R/W
R/W
R
ECP MODES
FUNCTION
Data Register
000-001
011
All
ecpAFifo
dsr
ECP FIFO (Address)
Status Register
dcr
R/W
R/W
R/W
R/W
R
All
Control Register
cFifo
010
011
110
111
111
All
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Configuration Register A
Configuration Register B
Extended Control Register
R/W
R/W
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE
000
001
010
011
100
101
110
111
DESCRIPTION
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
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5.3.2 Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input. The contents of this register are output to the PD0-PD7 ports. During a read operation,
ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this
register is defined only for the forward direction. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Address or RLE
Address/RLE
5.3.3 Device Status Register (DSR)
These bits are at low level during a read of the Printer Status Register. The bits of this status register
are defined as follows:
7
6
5
4
3
2
1
0
1
1
1
nFault
Select
PError
nAck
nBusy
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Bit 7: This bit reflects the complement of the Busy input.
Bit 6: This bit reflects the nAck input.
Bit 5: This bit reflects the PError input.
Bit 4: This bit reflects the Select input.
Bit 3: This bit reflects the nFault input.
Bit 2-0: These three bits are not implemented and are always logic one during a read.
5.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7
6
5
4
3
2
1
0
1
1
strobe
autofd
nInit
SelectIn
ackIntEn
Direction
Bit 6, 7: These two bits are logic one during a read and cannot be written.
Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is
valid in all other modes.
0
1
the parallel port is in output mode.
the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt
requests from the parallel port to the CPU due to a low to high transition on the ACK input.
Bit 3: This bit is inverted and output to the SLIN output.
0
1
The printer is not selected.
The printer is selected.
Bit 2: This bit is output to the INIT output.
Bit 1: This bit is inverted and output to the AFD output.
Bit 0: This bit is inverted and output to the STB output.
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5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this
FIFO. Transfers to the FIFO are byte aligned.
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to
the system.
5.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data
in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be
displayed on the parallel port data lines.
5.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
5.3.9 cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows:
7
6
5
4
3
2
1
1
0
1
1
IRQx 0
IRQx 1
IRQx 2
intrValue
compress
Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support
hardware RLE compression.
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
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PRELIMINARY
Bit 5-3: Reflect the IRQ resource assigned for ECP port.
cnfgB[5:3]
000
IRQ resource
reflect other IRQ resources selected by PnP register (default)
001
IRQ7
010
IRQ9
011
100
101
110
IRQ10
IRQ11
IRQ14
IRQ15
IRQ5
111
Bit 2-0: These five bits are at high level during a read and can be written.
5.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7
6
5
4
3
2
1
0
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Bit 7-5: These bits are read/write and select the mode.
000
001
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be
used to tri-state the data lines and reading the data register returns the value on the
data lines and not the value in the data register.
010
011
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
auto transmitted to the peripheral using ECP Protocol. When the direction is 1
(reverse direction), bytes are moved from the ECP parallel port and packed into
bytes in the ecpDFifo.
100
101
110
Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
111
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
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Bit 4: Read/Write (Valid only in ECP Mode)
1
0
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
0
Enables DMA.
Disables DMA unconditionally.
Bit 2: Read/Write
1
0
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr
Threshold or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr
Threshold or more valid bytes to be read from the FIFO.
Bit 1: Read only
0
1
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
1
The FIFO contains at least 1 byte of data.
The FIFO is completely empty.
5.3.11Bit Map of ECP Port Registers
D7
PD7
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
D0
PD0
NOTE
data
Addr/RLE
nBusy
1
Address or RLE field
2
1
1
2
2
2
ecpAFifo
dsr
nAck
1
PError
Select
nFault
1
1
1
Directio
ackIntEn
SelectIn
nInit
autofd
strobe
dcr
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
cFifo
ecpDFifo
tFifo
0
0
0
1
1
1
0
1
0
1
0
1
0
1
cnfgA
cnfgB
ecr
compress
intrValue
MODE
nErrIntrEn
dmaEn
serviceIntr
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
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PRELIMINARY
5.3.12 ECP Pin Descriptions
NAME
TYPE
DESCRIPTION
nStrobe (HostClk)
O
The nStrobe registers data or address into the slave on the
asserting edge during write operations. This signal handshakes
with Busy.
PD<7:0>
I/O
I
These signals contains address or data or RLE data.
nAck (PeriphClk)
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
Busy (PeriphAck)
I
This signal deasserts to indicate that the peripheral can accept
data. It indicates whether the data lines contain ECP command
information or data in the reverse direction. When in reverse
direction, normal data are transferred when Busy (PeriphAck)
is high and an 8-bit command is transferred when it is low.
PError (nAckReverse)
I
This signal is used to acknowledge a change in the direction of
the transfer (asserted = forward). The peripheral drives this
signal low to acknowledge nReverseRequest. The host relies
upon nAckReverse to determine when it is permitted to drive
the data bus.
Select (Xflag)
I
Indicates printer on line.
nAutoFd (HostAck)
O
Requests a byte of data from the peripheral when it is asserted.
This signal indicates whether the data lines contain ECP
address or data in the forward direction. When in forward
direction, normal data are transferred when nAutoFd (HostAck)
is high and an 8-bit command is transferred when it is low.
nFault (nPeriphRequest)
I
Generates an error interrupt when it is asserted. This signal is
valid only in the forward direction. The peripheral is permitted
(but not required) to drive this pin low to request a reverse
transfer during ECP Mode.
nInit (nReverseRequest)
nSelectIn (ECPMode)
O
O
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the
channel in the reverse direction.
This signal is always deasserted in ECP mode.
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5.3.13 ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol
before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The
following are required:
(a) Set direction = 0, enabling the drivers.
(b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
(c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
(d) Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo,
respectively.
5.3.13.1 Mode Switching
Software will execute P1284 negotiation and all operations prior to a data transfer phase under
programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake,
moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001
it can only be switched into mode 000 or 001. The direction can be changed only in mode 001.
When in extended forward mode, the software should wait for the FIFO to be empty before switching
back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the
FIFO before changing back to mode 000 or 001.
5.3.13.2 Command/Data
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction,
normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck
is low. The most significant bits of the command indicate whether it is a run-length count (for
compression) or a channel address.
In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
5.3.13.3 Data Compression
The W83977F/ AF supports run length encoded (RLE) decompression in hardware and can transfer
compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported.
In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data
byte is written to the ecpDFifo.
5.3.14 FIFO Operation
The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO
is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO
is disabled.
Publication Release Date:March 1998
- 91 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
5.3.15 DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC
DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the
DMA.
5.3.16 Programmed I/O (NON-DMA) Mode
The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo
located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and
serviceIntr = 0 in the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The
programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
5.4 Extension FDD Mode (EXTFDD)
In this mode, the W83977F/ AF changes the printer interface pins to FDC input/output pins, allowing
the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin
assignments for the FDC input/output pins are shown in Table 5-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOB and DSB will be forced to inactive state.
(2) Pins DSKCHG, RDATA, WP, TRAK0, INDEX will be logically ORed with pins PD4-PD0 to serve
as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
5.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83977F/ AF changes the printer interface pins to FDC input/output pins, allowing
the user to install two external floppy disk drives through the DB-25 printer connector to replace
internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in
Table5-1.
After the printer interface is set to EXTFDD mode, the following occur:
(1) Pins MOA , DSA, MOB, and DSB will be forced to inactive state.
(2) Pins DSKCHG, RDATA, WP, TRAK0, and INDEX will be logically ORed with pins PD4-PD0 to
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
Publication Release Date: January 1997
- 92 -
Revision 0.50
W83977F/ W83977AF
PRELIMINARY
6. REAL-TIME CLOCK (RTC) AND "ON-NOW" CONTROL
The RTC with 242 bytes of RAM is a low-power device that provides a time-of-day clock in various
formats, and a calendar with century register. It has two alarms and three programmable interrupts.
It is also equipped with external battery backup capability for keeping time and saving RAM data
under power-failure situation.
The RTC software is compatible with the MC146818 Clock chip.
The "On-Now" Control enables PC to be powered on by several trigger events, a telephone ring for
example. Also, it allows a safely controlled power-off procedure executed in an orderly fashion.
6.1 REGISTER ADDRESS MAP
Table 6.1.1, table 6.1.2, and table 6.1.3 show the register map of RTC and "On-Now". These
registers are separated into three banks: Bank 0, Bank 1, and Bank 2. Bank 0 contains 10 bytes of
time, calendar, and alarm A data, four bytes of control/status registers, and 114 bytes of general
purpose user RAM.
TABLE 6.1.1 - REAL TIME CLOCK ADDRESS MAP BANK 0
ADDRESS
00h
REGISTER TYPE
REGISTER FUNCTION
Register 00h : Seconds
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
01h
Register 01h : Seconds Alarm A
Register 02h : Minutes
02h
03h
Register 03h : Minutes Alarm A
Register 04h : Hours
04h
05h
Register 05h : Hours Alarm A
Register 06h : Day of Week
Register 07h : Date of Month
Register 08h: Month
06h
07h
08h
09h
Register 09h : Year
0Ah
Register 0Ah : Control Register
Register 0Bh : Control Register (Bit 0 is Read only)
Register 0Ch : Status Register
Register 0Dh : Status Register
Register 0Eh-7Fh : User RAM
0Bh
0Ch
0Dh
R
0Eh-7Fh
R/W
Publication Release Date:March 1998
- 93 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
In Bank 1, there are 128 bytes of general purpose user RAM, as shown in table 6.1.2.
TABLE 6.1.2 - REAL TIME CLOCK ADDRESS MAP BANK 1
ADDRESS
REGISTER TYPE
REGISTER FUNCTION
Register 0h-7Fh : user RAM
00h-7Fh
R/W
Bank 2 has 13 registers, 1 Century register, 8 Alarm B registers and 4 control/status registers for "On-
Now" function.
TABLE 6.1.3 - REAL TIME CLOCK "ON-NOW" ADDRESS MAP BANK 2
ADDRESS
40h
REGISTER TYPE
REGISTER FUNCTION
Register 40h : Centuries
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
41h
Register 41h : Seconds Alarm B
42h
Register 42h : Minutes Alarm B
43h
Register 43h : Hours Alarm B
44h
Register 44h : Day of Week Alarm B
Register 45h : Date of Month Alarm B
Register 46h : Month Alarm B
45h
46h
47h
Register 47h : Year Alarm B
48h
Register 48h : Century Alarm B
49h
Register 49h : "On-Now" Control Register 1
Register 4Ah : "On-Now" Control Register 2
Register 4Bh : "On-Now" Status Register 3
Register 4Ch : "On-Now" Control/Status Register 4
4Ah
4Bh
4Ch
R/W
Time, Calendar, Alarm A, and Alarm B data Modes
REGISTER
LOCATION
FUNCTION
RANGE(DATA MODE)
BINARY BCD
00h-3Bh 00h-59h
EXAMPLE
BINARY
BCD
30h
30h
30h
30h
08h
Register 00h Seconds
Register 01h Sec. Alarm A
Register 02h Minutes
Register 03h Min. Alarm A
Register 04h Hours
1Eh
1Eh
1Eh
1Eh
08h
00h-3Bh
00h-59h
00h-3Bh
00h-59h
00h-3Bh
00h-59h
01h-0Ch(AM)
01h-12h(AM)
81h-92h(PM)
00h-23h
(12-Hour Mode) 81h-8Ch(PM)
(24-Hour Mode) 00h-17h
08h
08h
Publication Release Date: January 1997
Revision 0.50
- 94 -
W83977F/ W83977AF
PRELIMINARY
Time, Calendar, Alarm A, and Alarm B data Modes continued
REGISTER
LOCATION
FUNCTION
RANGE(DATA MODE)
EXAMPLE
BINARY
BINARY
BCD
01h-12h(AM)
81h-92h(PM)
00h-23h
BCD
08h
Register 05h Hours Alarm A 01h-0Ch(AM)
(12-Hour Mode) 81h-8Ch(PM)
08h
(24-Hour Mode) 00h-17h
08h
02h
04h
07h
97h
19h
30h
30h
08h
08h
02h
04h
07h
61h
13h
1Eh
1Eh
08h
Register 06h Day of Week
01h-07h
01h-07h
Register 07h Date of Month 01h-1Fh
01h-31h
Register 08h Month
01h-0Ch
00h-63h
00h-63h
00h-3Bh
00h-3Bh
01h-12h
Register 09h Year
00h-99h
Register 40h Century
Register 41h Sec. Alarm B
Register 42h Min. Alarm B
00h-99h
00h-59h
00h-59h
Register 43h Hours Alarm B 01h-0Ch(AM)
(12-Hour Mode) 81h-8Ch(PM)
01h-12h(AM)
81h-92h(PM)
00h-23h
(24-Hour Mode) 00h-17h
08h
02h
08h
02h
Register 44h Day of Week
Alarm B
01h-07h
01h-07h
Register 45h Date of Month 01h-1Fh
Alarm B
01h-31h
04h
04h
Register 46h Month Alarm B 01h-0Ch
01h-12h
00h-99h
00h-99h
07h
61h
13h
07h
97h
19h
Register 47h Year Alarm B
00h-63h
Register 48h Century Alarm 00h-63h
B
6.2 Update Cycle
The RTC executes an update cycle once per second. It is in an update cycle when RTC updates the
contents of the clock and calendar registers. In the meantime, RTC also compares each alarm byte
with corresponding timer byte and generates an alarm flag if a match or a don't care condition (0C0h)
is present in the alarm register.
The update-in-progress bit (UIP) in register A pulses high once per second. The update cycle occurs
244mS after the UIP bit goes high. This bit is cleared and the update-ended flag (UF) is set in the end
of an update cycle.
Publication Release Date:March 1998
- 95 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
UPDATE CYCLE TIME TABLE
UIP BIT
UPDATE CYCLE TIME (TUC
)
BEFORE UPDATE CYCLE TIME (TBUC MIN)
1
0
-
1984mS
-
244mS
Update Period and UIP Timing
Update Period(1 Second)
BUC
UC
t
t
6.3 REGISTERS
The RTC has four control/status registers. They are accessible at all times.
6.3.1 Register 0Ah
· All bits are unaffected by RESET.
· Register A is a read/write register except bit 7 (UIP is read only).
BIT
7
6
5
4
3
2
1
0
NAME
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
UIP : (read only)
When UIP is 1, an update cycle is in progress. The UIP is cleared in the end of an update cycle and
when the SET bit in register B is 1.
Publication Release Date: January 1997
- 96 -
Revision 0.50
W83977F/ W83977AF
PRELIMINARY
DV[2:0] : Divider Control
These three bits are used to control divider and 32KHz oscillator.
TIME-BASE
DV2
DV1
DV0
OPERATION MODE
DIVIDER RESET
FREQUENCY
32.768KHZ
32.768KHZ
32.768KHZ
32.768KHZ
32.768KHZ
0
0
0
1
1
0
1
1
0
1
X
0
NO
YES
NO
NO
NO
-
-
1
-
-
X
X
YES
RS[3:0] : Periodic Interrupt Rate
PERIODIC INTERRUPT RATE TABLE
RS[3:0]
TIME BASE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
None
3.90625mS / 256Hz
7.8125mS / 128Hz
122.070mS / 8.192KHz
244.141mS / 4.096KHz
488.281mS / 2.048KHz
976.562mS / 1.024KHz
1.953125mS / 512Hz
3.90625mS / 256Hz
7.8125mS / 128Hz
15.625ms / 64Hz
31.25ms / 32Hz
62.5ms / 16Hz
125ms / 8Hz
250ms / 4Hz
500ms / 2Hz
Publication Release Date:March 1998
Revision 0.58
- 97 -
W83977F/ W83977AF
PRELIMINARY
6.3.2 Register 0Bh (Read/Write)
BIT
7
6
5
4
3
2
1
0
NAME
SET
PE
AE
UE
Reserved
DM
12/24
DSE
SET
When the SET bit is set, any occurring update cycle is aborted and registers (Register 00h~09h,
Register (40h~48h) may be modified without entering an update cycle. When this bit is cleared, the
update cycle function occurs once per second. This bit is not affected by any other internal functions
or by a RESET.
PE
A "1" on the periodic interrupt enable bit enables the periodic interrupt flag (PF) bit in Register 0Ch to
assert an interrupt.
A "0" on this bit blocks the IRQ output from being driven by a periodic interrupt. This bit can not be
modified by any internal function, but it may be cleared by a RESET.
AE
A "1" on the enable bit of alarm A enables the alarm A flag (AF) bit in Register 0Ch to assert an
interrupt.
A "0" on this bit prohibits alarm A interrupt. The RESET signal clears AE to "0". This bit can not be
modified by any internal function.
UE
A "1" on this bit enables the update-ended flag (UF) bit in register C to assert an interrupt.
A "0" on this bit prohibits update-ended interrupt. The UE bit is cleared by setting the SET bit or by a
RESET.
DM
The data mode bit determines whether time and calendar updates are in binary format or in binary-
coded-decimal (BCD) format.
A "1" on this bit means binary format.
A "0" on this bit means BCD format. This bit can not be modified by a RESET or any internal
function.
24/12
A "1" on this bit selects 24-hour mode for the time-of-day function.
A "0" on this bit selects 12-hour mode. This bit can not be modified by a RESET or any internal
function.
DSE
A "1" on this bit allows two special updates:
· On the last Sunday of April, the time increments from 1:59:59 AM to 3:00:00 AM.
· On the last Sunday of October, the time decrements from 1:59:59 AM to 1:00:00 AM.
A "0" on this bit disables these special updates. DSE can not be changed by any internal operation or
a RESET.
(Note: RTC IRQ is ultimately controlled by Logical Device 4-CR70 and Logical Device 4-CR71. These two registers must be set
properly if RTC IRQ is needed)
Publication Release Date: January 1997
- 98 -
Revision 0.50
W83977F/ W83977AF
PRELIMINARY
6.3.3 Register 0Ch (Read only)
BIT
7
6
5
4
3
0
2
0
1
0
0
0
NAME
IRQF
PF
AF
UF
IRQF
The interrupt request flag is set to a "1" if one or more of following cases are true:
PF*PE = "1"
AF*AE = "1"
UF*UE = "1"
(i.e., IRQF = PF*PE + AF*AE + UF*UE)
Any time the IRQF bit is a "1", the IRQ is asserted (provided LD4-CR70 and LD4-CR71 are set
properly). All flags are cleared by reading the register or by a RESET.
PF
The periodic interrupt flag is set to "1" when a rising edge is detected on the selected tap of the
divider chain(RS[3:0] of register A). PF is set to a "1" regardless of the state of PE bit. This bit is
cleared by a RESET or when this register is read.
AF
A "1" on this bit indicates that the current time has reached the alarm time setting (alarm A). A
RESET or a read of this register clears this bit.
UF
The update-ended interrupt flag bit is set after the end of each update cycle. This bit is cleared by a
RESET or when this bit is read.
Bit 3 - Bit 0
These bits are reserved and all read "0".
6.3.4 Register D (Read only)
BIT
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
NAME
VRT
VRT
The valid RAM and time bit. A "0" appears on this bit when the external battery is removed or at low-
voltage during power-failure situation, indicating the data integrity of the real time clock, "On-Now"
logic, and storage registers is not guaranteed. This bit can only be set by reading this register, and is
not affected by a RESET.
Publication Release Date:March 1998
- 99 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
6.4 "On-Now" Control
The "On-Now" Control function is built in RTC. It enables the PC to be powered on automatically
from triggers of various events, and to be powered off in an orderly controlled fashion.
The "On-Now" works at all times even when the system power is switch-off or disconnected. It
detects several external events to control system power supply On/Off properly (e.g. telephone ring,
panel switch-off). It also controls the signal (PSCTRL ) to turn the power supply on or off.
6.5 Power-On Events
The "On-Now" Control turns on power supply when one of the following events occurs:
· Panel Switch "turned on"
· Telephone is ringing
· Ring-In detection signal comes from a modem
· Keyboard/Mouse is stroked/moved
· Power-wake-up input goes from high to low.
· PSCTRL active when power returns after a power-failure occurs.
(Note: Panel-Switch has a debounce circuit which is clocked by RTC 32.768KHz oscillator. The "On-Now" control will not function
properly if this oscillator fails to work and PC can not be powered-on consequently)
6.6 Power-Off Events
· Panel Switch "turned off"
· Power-off under software control
· Power-failure event
· Override Power off: Panel switch is pushed for at least 4 seconds, then the system will be forced
to turn off immediately
Publication Release Date: January 1997
- 100 -
Revision 0.50
W83977F/ W83977AF
PRELIMINARY
6.7 Registers
6.7.1 On-Now Register 1 (Bank2 Register 49h)
7
6
5
4
3
2
1
0
BIT
PF
CLPOST SPOFC
DPSCA CLRSMI SMIMD PHRIDM DPODTM
NAME
PF (Power Failure)
The PF is set when a power-failure occurs. This bit is cleared by writing a "1" to it.
CLPOST (Clear Panel-switch-off-Save Timer)
This bit is self-cleared after writing an "1" to it. If it is set, Panel-switch-off-Save timer is stopped and
cleared.
SPOFC (Software Power-Off Command)
This bit is self-cleared after writing an "1" to it. If it is set, the PSCTRL goes inactive immediately.
DPSCA (Disable Power Supply Control Activation)
This bit is set as long as PF is set. When set, it disables all PSCTRL activation events except Panel-
Switch- On event.
CLSMI (Clear SMI )
This bit is self-cleared after writing an "1" to it. If it is set, SMI is cleared to its inactive state. This bit
is used to clear SMI when SMIMD is set.
SMIMD ( SMI Mode)
If it is set, SMI is level-sensitive. Once SMI goes active, it keeps active until CLSMI is set.
Writing a "0" to this bit sets SMI to be edge-triggered.
PHRIDM (PHRI Detection Mode)
A "1" on this bit sets PHRI detection mode to be on falling edge.
A "0" on this bit sets PHRI detection mode to be on a pulse train of frequency greater than 11Hz and
lasts for 0.2 second.
DPODTM (Disable Power Off Delay Timer )
If set, Panel Switch Power-Off Delay Timer is stopped.
If reset, Panel Switch Power-Off Delay Timer counts down continuously.
Publication Release Date:March 1998
- 101 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
6.7.2 On-Now Register 2 (Bank2 Register 4Ah)
7
6
5
4
3
2
1
0
BIT
MCLKE
KCLKE
RIBE
RIAE
PHRIE
PWAKI2E PWAKI1E
NAME
ALARMBE
MCLKE (Mouse Clock Enable)
Logical 1 on this bit, a falling edge transition on MCLK asserts PSCTRL .
KCLKE (Keyboard Clock Enable)
Logical 1 on this bit, a falling edge transition on KCLK asserts PSCTRL .
RIBE (RI B Enable)
Logical 1 on this bit, a falling edge transition on RIB asserts PSCTRL .
RIAE (RI A Enable)
Logical 1 on this bit, a falling edge transition on RIA asserts PSCTRL .
PHRIE (PHRI Enable)
Logical 1 on this bit, a falling edge transition on PHRI asserts PSCTRL .
PWAKI2E (Power Wake-up Input 2 Enable)
Logical 1 on this bit, a falling edge transition on PWAKIN2 asserts PSCTRL .
PWAKI1E (Power Wake-up Input 1 Enable)
Logical 1 on this bit, a falling edge transition on PWAKIN1 asserts PSCTRL .
ALARMBE (Alarm B Enable)
Logical 1 on this bit, the alarm B reaches its predetermined time asserts PSCTRL .
Publication Release Date: January 1997
Revision 0.50
- 102 -
W83977F/ W83977AF
PRELIMINARY
6.7.3 "On-Now" Register 3 (Bank2 Register 4Bh)
7
6
5
4
3
2
1
0
BIT
PHRIST Reserved PSPOFD PSPOFTD RIBD
RIAD
PHRID
ALMBD
NAME
This register is read only except bit 5.
PHRIST (PHRI Status)
This bit holds the current value of PHRI.
PSPOFD (Panel Switch Power-Off Detect)
Logical 1 on this bit, a Panel-Switch-Off event is detected.
Logical 0 on this bit, there is no Panel-Switch-Off event.
PSOFTD (Panel Switch Power-Off Delay Timer Detect)
This bit is set when Panel Switch Power-Off Delay Timer reaches its terminal count. This bit is
cleared by reading this register.
RIBD (RI B Detect)
A falling edge transition on RIB asserts this bit. This bit is cleared by reading this register.
RIAD (RI A Detect)
A falling edge transition on RIA asserts this bit. This bit is cleared by reading this register.
PHRID (PHRI Detect)
A falling edge transition on PHRI asserts this bit. This bit is cleared by reading this register.
ALMBD (Alarm B Detect)
Logical 1 on this bit, the alarm B when reaching its preset time asserts this bit. This bit is cleared by
reading this register.
Publication Release Date:March 1998
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Revision 0.58
W83977F/ W83977AF
PRELIMINARY
6.7.4 "On-Now" Register 4 (Bank2 Register 4Ch)
7
6
5
4
3
2
1
0
BIT
PSOFDS1 PSOFDS0 INVSMI Reserved MCLKD
KCLKD PWAKI2D PWAKI1D
NAME
This register is read only except bits 5, 6 and 7.
PSOFDS1, PSOFDS0
These two bits decide the delay time between panel switch power off event and power supply off.
00 : 0 second.
01 : 5 seconds.
10 : 13 seconds.
11 : 21 seconds.
INVSMI
Logical 1 on this bit, nSMI is active low and goes high-Z when dis-asserted.
Logical 0 on this bit, nSMI is active high and goes high-Z when dis-asserted.
MCLKD (MCLK Detect)
A falling edge transition on MCLK asserts this bit. This bit is cleared by reading this register.
KCLKD (KCLK Detect)
A falling edge transition on KCLK asserts this bit. This bit is cleared by reading this register.
PWAKI2D (PWAKIN2 Detect)
A falling edge transition on PWAKIN2 asserts this bit. This bit is cleared by reading this register.
PWAKI1D (PWAKIN1 Detect)
A falling edge transition on PWAKIN1 asserts this bit. This bit is cleared by reading this register.
Publication Release Date: January 1997
- 104 -
Revision 0.50
W83977F/ W83977AF
PRELIMINARY
7. KEYBOARD CONTROLLER
The KBC (8042 with licensed KB BIOS) circuit of W83977F/ AF is designed to provide the functions
needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBMÒ-
compatible personal computers or PS/2-based systems. The controller receives serial data from the
keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte
of data in its output buffer. Then, the controller will assert an interrupt to the system when data are
placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data
transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge
is received for the previous data byte.
P24
P25
P21
P20
KIRQ
MIRQ
GATEA20
KBRST
KINH
P17
KDAT
KCLK
P27
P10
P26
8042
T0
GP I/O PINS
Multiplex I/O PINS
MCLK
MDAT
P23
T1
P12~P16
P22
P11
Keyboard and Mouse Interface
Publication Release Date:March 1998
Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
7.1 Output Buffer
The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O
address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan
code received from the keyboard and data bytes required by commands to the system. The output
buffer can only be read when the output buffer full bit in the register is "1".
7.2 Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable
I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag
to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written
to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte)
through the controller's input buffer only if the input buffer full bit in the status register is 0 .
7.3 Status Register
The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O
address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller
and interface. It may be read at any time.
BIT
BIT FUNCTION
DESCRIPTION
0: Output buffer empty
0
Output Buffer Full
1: Output buffer full
1
2
Input Buffer Full
System Flag
0: Input buffer empty
1: Input buffer full
This bit may be set to 0 or 1 by writing to the system flag
bit in the command byte of the keyboard controller. It
defaults to 0 after a power-on reset.
3
4
5
6
7
Command/Data
Inhibit Switch
0: Data byte
1: Command byte
0: Keyboard is inhibited
1: Keyboard is not inhibited
Auxiliary Device Output 0: Auxiliary device output buffer empty
Buffer
1: Auxiliary device output buffer full
General Purpose Time-
out
0: No time-out error
1: Time-out error
Parity Error
0: Odd parity
1: Even parity (error)
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Revision 0.50
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PRELIMINARY
7.4 Commands
COMMAND
20h
FUNCTION
Read Command Byte of Keyboard Controller
Write Command Byte of Keyboard Controller
60h
BIT
BIT DEFINITION
7
6
Reserved
IBM Keyboard Translate Mode
Disable Auxiliary Device
5
4
3
2
1
Disable Keyboard
Reserve
System Flag
Enable Auxiliary Interrupt
Enable Keyboard Interrupt
0
Test Password
A4h
Returns 0Fah if Password is loaded
Returns 0F1h if Password is not loaded
Load Password
A5h
A6h
Load Password until a "0" is received from the system
Enable Password
Enable the checking of keystrokes for a match with the password
Disable Auxiliary Device Interface
A7h
A8h
A9h
Enable Auxiliary Device Interface
Interface Test
BIT
BIT DEFINITION
No Error Detected
00
01
Auxiliary Device "Clock" line is stuck low
Auxiliary Device "Clock" line is stuck high
Auxiliary Device "Data" line is stuck low
02
03
04
Auxiliary Device "Data" line is stuck low
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Revision 0.58
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PRELIMINARY
7.4 Commands, continued
COMMAND
FUNCTION
AAh
Self-test
Returns 055h if self test succeeds
ABh
Interface Test
BIT DEFINITION
No Error Detected
BIT
00
01
Keyboard "Clock" line is stuck low
02
03
04
Keyboard "Clock" line is stuck high
Keyboard "Data" line is stuck low
Keyboard "Data" line is stuck high
ADh
AEh
C0h
C1h
C2h
D0h
D1h
D2h
D3h
D4h
E0h
FXh
Disable Keyboard Interface
Enable Keyboard Interface
Read Input Port(P1) and send data to the system
Continuously puts the lower four bits of Port1 into STATUS register
Continuously puts the upper four bits of Port1 into STATUS register
Send Port2 value to the system
Only set/reset GateA20 line based on the system data bit 1
Send data back to the system as if it came from Keyboard
Send data back to the system as if it came from Auxiliary Device
Output next received byte of data from system to Auxiliary Device
Reports the status of the test inputs
Pulse only RC(the reset line) low for 6mS if Command byte is even
Publication Release Date: January 1997
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Revision 0.50
W83977F/ W83977AF
PRELIMINARY
7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC
The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control
logic is controlled by LD5-CRF0 as follows:
7.5.1 KB Control Register (Logic Device 5, CR-F0)
BIT
7
6
5
4
3
2
1
0
NAME
KCLKS1 KCLKS0 Reserved Reserved Reserved P92EN
HGA20 HKBRST
KCLKS1, KCLKS0
This 2 bits are for the KBC clock rate selection.
= 0 0 KBC clock input is 6 Mhz
= 0 1 KBC clock input is 8 Mhz
= 1 0 KBC clock input is 12 Mhz
= 1 1 KBC clock input is 16 Mhz
P92EN (Port 92 Enable)
A "1" on this bit enables Port 92 to control GATEA20 and KBRESET.
A "0" on this bit disables Port 92 functions.
HGA20 (Hardware GATE A20)
A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal.
A "0" on this bit disables hardware GATEA20 control logic function.
HKBRST (Hardware Keyboard Reset)
A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal.
A "0" on this bit disables hardware KB RESET control logic function.
When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears
GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears
KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the
KBRESET is pulse low for 6mS(Min.) with 14mS(Min.) delay.
GATEA20 and KBRESET are controlled by either the software control or the hardware control logic
and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92
when P92EN bit is set.
7.5.2 Port 92 Control Register (Default Value = 0x24)
7
6
5
4
3
2
1
0
BIT
Res. (0) Res. (0) Res. (1) Res. (0)
Res. (0) Res. (1)
SGA20 PLKBRST
NAME
SGA20 (Special GATE A20 Control)
A "1" on this bit drives GATE A20 signal to high.
A "0" on this bit drives GATE A20 signal to low.
PLKBRST (Pull-Low KBRESET)
A "1" on this bit causes KBRESET to drive low for 6mS(Min.) with 14mS(Min.) delay. Before issuing
another keyboard reset command, the bit must be cleared.
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Revision 0.58
W83977F/ W83977AF
PRELIMINARY
8. GENERAL PURPOSE I/O
W83977F/ AF provides 14 Input/Output ports that can be individually configured to perform a simple
basic I/O function or a pre-defined alternate function. Those 14 GP I/O ports are divided into two
groups, the first group contains 8 ports, and the other group contains only 6 ports. Each port in the
first group corresponds to a configuration register in logical device 7. Each port in the second group
corresponds to a configuration register in logical device 8. Users can select those I/O ports functions
by independently programming the configuration registers. Figure 8.1 and 8.2 respectively show the
GP I/O port' s structure of logical device 7 and device 8. Right after Power-on reset, those ports
perform basic I/O functions.
Figure 8.1
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PRELIMINARY
Figure 8.2
8.1 Basic I/O functions
The Basic I/O functions of W83977F/ AF provide several I/O operations including driving a logic
value to output port, latching a logic value from input port, inverting the input/output logic value, and
steering Common Interrupt (only available in the second group of the GP I/O port). Common
Interrupt is the ORed function of all interrupt channels in the second group of the GP I/O ports, and it
also connects to a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There
are two 8-bit registers, GP1 and GP2, which are directly connected to both groups of GP I/O ports.
Each GP I/O port is represented as a bit in one of two 8-bit registers. Only 6 bits of GP2 are
implemented. Table 11.1.1 shows their combinations of Basic I/O functions, and Table 11.1.2 shows
the register bit assignments of GP1 and GP2.
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PRELIMINARY
Table 8.1.1
I/O BIT
ENABLE INT BIT
POLARITY BIT
BASIC I/O OPERATIONS
0 = OUTPUT
0 = DISABLE
0 = NON INVERT
1 = INPUT
1 = ENABLE
1 = INVERT
0
0
0
0
0
1
0
1
0
Basic non-inverting output
Basic inverting output
Non-inverted output bit value of GP2
drive to Common Interrupt
0
1
1
Inverted output bit value of GP2 drive
to Common Interrupt
1
1
1
0
0
1
0
1
0
Basic non-inverting input
Basic inverting input
Non-inverted input drive to Common
Interrupt
1
1
1
Inverted input drive to Common
Interrupt
Table 8.1.2
GP I/O PORT ACCESSED
REGISTER
REGISTER BIT
ASSIGNMENT
GP I/O PORT
BIT 0
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
GP1
GP2
Publication Release Date: March 1998
Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
8.2 Alternate I/O Functions
W83977F/ AF provides several alternate functions which are scattered among the GP I/O ports.
Table 8.2.1 shows their assignments. Polarity bit can also be set to alter their polarity of alternate
functions.
Table 8.2.1
GP I/O PORT
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
ALTERNATE FUNCTION
Interrupt Steering
Interrupt Steering
Watching Dog Timer Output/IRRX input
Power LED output/ IRTX output [W83977AF only]
General Purpose Address Decoder/ Keyboard Inhibit(P17)
General Purpose Write Strobe/ 8042 P12
Watching Dog Timer Output
Power LED output
Keyboard Reset (8042 P20)
8042 P13
8042 P14
8042 P15
8042 P16
GATE A20 (8042 P21)
8.2.1 Interrupt Steering
GP10 and GP11 can be programmed to map their own interrupt channels. The selection of IRQ
channel can be done in configure registers CR70 and CR72 of logical device 7. Each interrupt
channel also has its own 1 ms debounce filter that is used to reject any noise which is equal to or less
than 1 ms wide.
8.2.2 Watch Dog Timer Output
Watch Dog Timer contains a one minutes resolution down counter, CRF2 of Logical Device 8, and
two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down
counter can be programmed within the range from 1 to 255 minutes. Writing any new non-zero value
to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains
non-zero value) will cause the Watch Dog Timer to reload and start to count down from the new
value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of
WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable
in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is
enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1.
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PRELIMINARY
8.2.3 Power LED
The Power LED function provides 1 Hertz rate toggle pulse output with 50 percent duty cycle. Table
8.2.2 shows how to enable Power LED.
Table 8.2.2
WDT_CTRL1 BIT[1]
WDT_CTRL0 BIT[3]
WDT_CTRL1 BIT[0]
POWER LED STATE
1 Hertz Toggle pulse
Continuous high or low *
Continuous high or low *
1 Hertz Toggle pulse
1
0
0
0
X
0
1
1
X
X
0
1
* Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers.
8.2.4 General Purpose Address Decoder
General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The
address base is stored at CR62, CR63 of logical device 7. The decode output is normally active low.
Users can alter its polarity through the polarity bit of the GP14' s configuration register.
8.2.5 General Purpose Write Strobe
General Purpose Write Strobe is an address decoder that performs like General Purpose Address
Decoder, but it has to be qualified by IOW and AEN. Its output is normally active low. Users can
alter its polarity through the polarity bit of the GP15' s configuration register.
9. PLUG AND PLAY CONFIGURATION
The W83977F/ AF provides many configuration registers for setting up different types of
configurations. There are two approaches to entering the configuration state and accessing these
configuration registers, Comply PnP and Compatible PnP. The Comply PnP protocol is based on the
Plug and Play ISA Specification. The Compatible PnP protocol is similar to previous Winbond I/O' s
protocol. The Power-On-Setting upon the Pin 51 (DTRB) decides the method of entering the
configuration mode. In W83977F/ AF, there are nine Logical Devices (from Logical Device 0 to
Logical Device 8) which correspond to nine individual functions: FDC, PRT, UART1, UART2, RTC,
KBC, IR, GPIO1, GPIO2 in listed order. Each Logical Device has its own configuration registers
(above CR30). Host can access those registers only after entering configuration mode.
Publication Release Date: March 1998
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W83977F/ W83977AF
PRELIMINARY
9.1 Comply PnP
The protocol of Comply PnP is 100% compatible with the Plug and Play ISA Specification.
W83977F/ AF provides built-in Plug and Play state machine to control the configuration flow. The
state machine supports four states: Wait for Key state, Sleep state, Isolation state, and Configure
State. According to Plug and Play ISA Specification, users can transit the four states by accessing
the configuration registers, CR00 - CR07.
9.1.1 Wait for Key State
All cards enter this state after power-up reset or in response to the Reset and Wait for Key
commands. No command is active in this state until the initiation key is detected on the ISA bus. The
initiation key is a sequence of 32 hexadecimal number which will be shifted into LFSR (linear
feedback shift register) built in W83977F/ AF. The Wait for Key state is the default state for Plug and
Play cards during normal system operation. After configuration and activation, software should return
all cards to this state.
9.1.2 Sleep State
In this state, Plug and Play wait for a Wake[CSN] command. This command will selectively enable
one or more cards to enter either the Isolation or Configure states based on the write data and the
value of the CSN on each card. If the write data for the Wake[CSN] command is zero then all cards
that have not been assigned a CSN will enter the Isolation state. If the write data for the Wake[CSN]
command is not zero then the one card whose assigned CSN matches the parameter of the
Wake[CSN] command will enter the Configure state.
9.1.3 Isolation State
In this state, Plug and Play cards respond to reads of the Serial Isolation registers according to
Isolation protocol. An unique CSN is assigned after the card is isolated
9.1.4 Configure State
A card in the Configure state responds to all configuration commands including reading the card' s
resource configure information and programming the card' s resource selections. Only one card may
be in this state at a time.
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W83977F/ W83977AF
PRELIMINARY
9.2 Compatible PnP
9.2.1 Extended Function Registers
In Compatible PnP, there are two ways to enter Extended Function mode (which is same as
Configure State in Comply PnP) and read or write the configuration registers. HEFRAS (CR26 bit 6)
can be used to select one out of these two methods of entering the Extended Function mode as
follows:
HEFRAS
address and value
write 87h to the location 3F0h twice
write 87h to the location 370h twice
0
1
After Power-on reset, the value on RTSA (pin 43) is latched by HEFRAS of CR26. In Compatible
PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port
address 3F0h or 370h). Secondly, an index value (02h, 07h-FEh) must be written to the Extended
Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable
Register) to identify which configuration register is to be accessed. The designer can then access the
desired configuration register through the Extended Functions Data Register (I/O port address 3F1h
or 371h).
After programming of the configuration register is finished, an additional value(AAh) should be written
to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration
registers against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
9.2.2 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83977F/ AF enters the default operating mode. Before the W83977F/
AF enters the extended function mode, a specific value must be programmed into the Extended
Function Enable Register (EFER) so that the extended function register can be accessed. The
Extended Function Enable Registers are write-only registers. On a PC/AT system, their port
addresses are 3F0h or 370h (as described in previous section).
9.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as
described in section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address
3F1h or 371h (as described in section 9.2.1) on PC/AT systems.
Publication Release Date: March 1998
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Revision 0.58
W83977F/ W83977AF
PRELIMINARY
10. CONFIGURATION REGISTER
10.1 Chip (Global) Control Register
CR00 (only available in comply PnP mode)
Bit 7-0 : IORDPRA9 - IORDPRA2 --> Set RD_DATA Port A9-A2
CR01 (only available in comply PnP mode)
Bit7-0 : SISO 7-0 --> Serial Isolation
CR02 (Default 0x00)
Bit 7-3 : Reserved.
Bit 2: RSTCSN --> Reset CSN to 0. Only available in comply PnP mode.
Bit 1: RTUWAIT -- > Return to Wait for Key state. Only available in comply PnP mode.
Bit 0 : SWRST --> Soft Reset.
CR03 (only available in comply PnP mode)
Bit 7-0 : WAKCSN7 - WAKCSN0 --> Wake CSN
CR04 (only available in comply PnP mode)
Bit 7-0 : RSODAT7 - RSODAT 0 --> Resource Data
CR05 (only available in comply PnP mode)
Bit 7-1 : Reserved
Bit 0 : RSOSTAT -- > resource status bit
CR06 (only available in comply PnP mode)
Bit 7-0 : CSN7 -CSN0 --> Card Select Number 7 - 0
CR07
Bit 7-0 : LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0
CR20
Bit 7-0 : DEVIDB7 - DEBIDB0 -- > Device ID Bit 7 - Bit 0 = 0x97 (read only).
CR21
Bit 7-0 : DEVREVB7 - DEBREVB0 -- > Device Rev Bit 7 - Bit 0 = 0x71 (read only).
CR22 (Default 0xff)
Bit 7-6 : Reserved.
Bit 5 : URBPWD
= 0 Power down
= 1 No Power down
Bit 4 : URAPWD
= 0 Power down
= 1 No Power down
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Revision 0.58
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PRELIMINARY
Bit 3 : PRTPWD
= 0 Power down
= 1 No Power down
Bit 2 : IRPWD
= 0 Power down
= 1 No Power down
Bit 1 : Reserved.
Bit 0 : FDCPWD
= 0 Power down
= 1 No Power down
CR23 (Default 0x00)
Bit7-6 : Reserved
Bit 5-3 : APDTMS2 APDTMS1 APDTMS0
= 000 4 seconds count-down time of the APD mode.
= 001 8 seconds count-down time of the APD mode.
= 010 16 seconds count-down time of the APD mode.
= 011 32 seconds count-down time of the APD mode.
= 100 1 minute count-down time of the APD mode.
= 101 2 minutes count-down time of the APD mode.
= 110 4 minutes count-down time of the APD mode.
= 111 16 minutes count-down time of the APD mode.
Bit 2-0 : OSCS2, OSCS1, OSCS0.
= 000 Default power-on state after power on reset.
= 1xx Stop Clock supply to whole chip, but PLL circuit still in operation.
= 001 Stop Clock supply to whole chip and PLL circuit.
= 010 Standby for automatic power-down(APD).
= 011 Automatic power-down(APD) has been happened.
CR24 (Default 0b1ss00sss)
Bit 7 : EN16SA
= 0 12 bit Address Qualification
= 1 16 bit Address Qualification
Bit 6-5 : CLKSEL, ENPLL
= 00 The clock input on Pin 1 should be 14.31818 Mhz.
= 01 The clock input on Pin 1 should be 24 Mhz.
= 11 The clock input on Pin 1 should be 48 Mhz.
Bit 4 : RWPNPREG
= 0 Disable read/write PnP mode config registers by using the method of non-PnP mode
= 1 Enable read/write PnP mode config registers by using the method of non-PnP mode
Bit 3 : Reserved
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W83977F/ W83977AF
PRELIMINARY
Bit 2 : ENKBRTC
= 0 KBC and RTC are disabled after hardware reset.
= 1 KBC and RTC are active after hardware reset.
This bit is read only, and set/reset by hardware setting.
Bit 1 : ENPNP
= 0 Disable Comply PnP
= 1 Enable Comply PnP
Bit 0 : PNPCSV
= 0 The Compatible and Comply PnP has default value
= 1 The Compatible and Comply PnP has no default value
CR25 (Default 0x00)
Bit 7-6 : Reserved
Bit 5 : URBTRI
Bit 4 : URATRI
Bit 3 : PRTTRI
Bit 2 : IRTRI [W83977AF only]
Bit 1 : Reserved.
Bit 0 : FDCTRI.
CR26 (Default 0b0s000000)
Bit 7 : SEL4FDD
= 0 Select two FDD mode.
= 1 Select four FDD mode.
Bit 6 : HEFRAS
These two bits define how to enable Configuration mode.
HEFRAS Address and Value
= 0 Write 87h to the location 3F0h twice.
= 1 Write 87h to the location 370h twice.
Bit 5 : LOCKREG
= 0 Enable R/W Configuration Registers.
= 1 Disable R/W Configuration Registers.
Bit 4 : DSIRLGRQ [W83977AF only]
= 0 Enable IR legacy mode on IRQ and DRQ selection, then MCR register bit 3 is effective
in selecting IRQ and DRQ.
= 1 Disable IR legacy mode on IRQ and DRQ selection, then MCR register bit 3 is not
effective in selecting IRQ and DRQ.
Bit 3 : DSFDLGRQ
= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective
in selecting IRQ
= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
effective in selecting IRQ
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W83977F/ W83977AF
PRELIMINARY
Bit 2 : DSPRLGRQ
= 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
selecting IRQ
= 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
on selecting IRQ
Bit 1 : DSUALGRQ
= 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
Bit 0 : DSUBLGRQ
= 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
CR28 (Default 0x00)
Bit 7-5: Reserved.
Bit 4 : IRQ Sharing selection.
= 0
= 1
Disable IRQ Sharing
Enable IRQ Sharing
Bit 3 :Reserved
Bit 2-0 : PRTMODS2 - PRTMODS0
= 0xx Parallel Port Mode
= 100 Reserved
= 101 External FDC Mode
= 110 Reserved
= 111 External two FDC Mode
CR29 [W83977AF only]
Bit 7-0 : CPSIDB7 - CPSIDB0 --> Comply PnP Serial ID Bit 7 - Bit 0.
CR2A (Default 0x00)
Bit 7 : PIN57S
= 0 KBRST
= 1 GP12
Bit 6 : PIN56S
= 0 GA20
= 1 GP11
Bit 5-4 : PIN40S1, PIN40S0
= 00 CIRRX [W83977AF only]
= 01 GP24
= 10 8042 P13
= 11 Reserved
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Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
Bit 3-2 : PIN39S1, PIN39S0
= 00 IRRXH [W83977AF only]
= 01 IRSL0 [W83977AF only]
= 10 GP25
= 11 CTSC [W83977AF only]
Bit 1-0 : PIN3S1, PIN3S0
= 00 DRVDEN1
= 01 GP10
= 10 8042 P12
= 11 nDSRC
CR2B (Default 0x00)
Bit 7-6 : PIN73S1, PIN73S0
= 00 PANSW
= 01 GP23
= 10 Reserved
= 11 DCDC [W83977AF only]
Bit 5 : PIN72S
= 0 PSCTRL
= 1 GP22
Bit 4-3 : PIN70S1, PIN70S0
= 00 SMI
= 01 GP21
= 10 8042 P16
= 11 RIC [W83977AF only]
Bit 2-1 : PIN69S1, PIN69S0
= 00 PHRI
= 01 GP20
= 10 Reserved
= 11 Reserved
Bit 0 : PIN58S
= 0 KBLOCK
= 1 GP13
CR2C (Default 0x00)
Bit 7-6 : PIN121S1, PIN121S0
= 00 DRQ0
= 01 GP17
= 10 8042 P14
= 11 nDTRC [W83977AF only]
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Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
Bit 5-4 : PIN119S1, PIN119S0
= 00 NDACK0
= 01 GP16
= 10 8042 P15
= 11 nRTSC
Bit 3-2 : PIN104S1, PIN104S0
= 00 IRQ15
= 01 GP15
= 10 WDTO
= 11 IRSL2 [W83977AF only]
Bit 1-0 : PIN103S1, PIN103S0
= 00 IRQ14
= 01 GP14
= 10 PLEDO
= 11 IRSL1 [W83977AF only]
CR2D (Default 0x00)
Test Modes: Reserved for Winbond.
CR2E (Default 0x00)
Test Modes: Reserved for Winbond.
CR2F (Default 0x00)
Test Modes: Reserved for Winbond.
10.2 Logical Device 0 (FDC)
CR30 (Default 0x01)
Bit 7-1 : Reserved.
Bit 0 : = 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x03, 0xf0)
These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundaries.
CR70 (Default 0x06)
Bit 7-4 : Reserved.
Bit 3-0 : These bits select IRQ resource for FDC.
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CR71 (Default 0x02, read only)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
CR74 (Default 0x02)
Bit 7-3 : Reserved.
Bit 2-0 : These bits select DRQ resource for FDC.
= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04-0x07 No DMA active
CRF0 (Default 0x0E)
FDD Mode Register
Bit 7 : FIPURDWN
This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0,
DSKCHG, and WP.
= 0 The internal pull-up resistors of FDC are turned on.(Default)
= 1 The internal pull-up resistors of FDC are turned off.
Bit 6 : INTVERTZ
This bit determines the polarity of all FDD interface signals.
= 0 FDD interface signals are active low.
= 1 FDD interface signals are active high.
Bit 5 : DRV2EN (PS2 mode only)
When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.
Bit 4 : Swap Drive 0, 1 Mode
= 0 No Swap (Default)
= 1 Drive and Motor sel 0 and 1 are swapped.
Bit 3-2 Interface Mode
= 11 AT Mode (Default)
= 10 (Reserved)
= 01 PS/2
= 00 Model 30
Bit 1 : FDC DMA Mode
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (Default)
Bit 0 : Floppy Mode
= 0 Normal Floppy Mode (Default)
= 1 Enhanced 3-Mode FDD
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CRF1 (Default 0x00)
Bit 7-6 : Boot Floppy
= 00 FDD A
= 01 FDD B
= 10 FDD C
= 11 FDD D
Bit 5 : Media ID1 Polarity
= 0 Non-Inverse
= 1 Inverse
Bit 4 : Media ID0 Polarity
= 0 Non-Inverse
= 1 Inverse
Bit 3-2 : Density Select
= 00 Normal (Default)
= 01 Normal
= 10 1 ( Forced to logic 1)
= 11 0 ( Forced to logic 0)
Bit 1 : DISFDDWR
= 0 Enable FDD write.
= 1 Disable FDD write(forces pins WE, WD to stay high).
Bit 0 : SWWP
= 0 Normal, use WP to determine whether the FDD is write protected or not.
= 1 FDD is always write-protected.
CRF2 (Default 0xFF)
Bit 7-6 : FDD D Drive Type
Bit 5-4 : FDD C Drive Type
Bit 3-2 : FDD B Drive Type
Bit 1:0 : FDD A Drive Type
When FDD is in enhanced 3-mode(CRF0.bit0=1),these bits determine SELDEN value in TABLE A
of CRF4 and CRF5 as follows.
DTYPE1
DPYTE0
DRATE1
DRATE0
SELDEN
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
1
X
X
0
1
0
1
0
X
X
1
1
1
0
0
0
1
0
Note: X means don't care.
CRF4 (Default 0x00)
FDD0 Selection:
Bit 7 : Reserved.
Bit 6 : Precomp. Disable.
= 1 Disable FDC Precompensation.
= 0 Enable FDC Precompensation.
Bit 5 : Reserved.
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Bit 4-3 : DRTS1, DRTS0 : Data Rate Table select (Refer to TABLE A).
= 00 Select Regular drives and 2.88 format
= 01 Specifical application
= 10 2 Meg Tape
= 11 Reserved
Bit 2 : Reserved.
Bit 1:0 : DMOD0, DMOD1 : Drive Model select (Refer to TABLE B).
CRF5 (Default 0x00)
FDD1 Selection : Same as FDD0 of CRF4.
TABLE A
Drive Rate Table
Select
Data Rate
Selected Data Rate
SELDEN
DRTS1
DRTS0
DRATE1
DRATE0
MFM
1Meg
500K
300K
250K
1Meg
500K
500K
250K
1Meg
500K
2Meg
250K
FM
---
CRF0 bit 0=0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
250K
150K
125K
---
0
1
1
0
250K
250K
125K
---
250K
---
125K
Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1.
TABLE B
DMOD0
DMOD1
DRVDEN0(pin 2)
DRVDEN1(pin 3)
DRIVE TYPE
0
0
SELDEN
DRATE0
4/2/1 MB 3.5
2/1 MB 5.25
2/1.6/1 MB 3.5 (3-MODE)
0
1
1
0
DRATE1
DRATE0
DRATE0
SELDEN
DRATE0
1
1
DRATE1
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10.3 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 when PNPCSV=0 at POR)
Bit 7-1 : Reserved.
Bit 0 :
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x03, 0x78 at PNPCSV=0)
These two registers select Parallel Port I/O base address.
[0x100:0xFFC] on 4 byte boundaries(EPP not supported) or
[0x100:0xFF8] on 8 byte boundaries(all modes supported, EPP is only available when the base
address is on an 8byte boundary).
CR70 (Default 0x07 when PNPCSV=0 at POR)
Bit 7-4 : Reserved.
Bit [3:0] : These bits select IRQ resource for Parallel Port.
CR71 (Default 0x02, read only)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
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CR74 (Default 0x04)
Bit 7-3 : Reserved.
Bit 2-0 : These bits select DRQ resource for Parallel Port.
0x00=DMA0
0x01=DMA1
0x02=DMA2
0x03=DMA3
0x04-0x07= No DMA active
CRF0 (Default 0x3F)
Bit 7 : PP Interrupt Type:
Not valid when the parallel port is in the printer Mode (100) or the standard & Bi-directional
Mode (000).
= 1 Pulsed Low, released to high-Z .
= 0 IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP.
Bit [6:3] : ECP FIFO Threshold.
Bit 2-0 Parallel Port Mode (CR F1 PRTMODS2= logical 1)
= 100 Printer Mode (Default)
= 000 Standard and Bi-direction (SPP) mode
= 001 EPP-1.9 and SPP mode
= 101 EPP-1.7 and SPP mode
= 010 ECP mode
= 011 ECP and EPP-1.9 mode
= 111 ECP and EPP-1.7 mode.
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¢)
10.4 Logical Device 2 (UART A)
CR30 (Default 0x01 when PNPCSV=0 at POR)
Bit 7-1 : Reserved.
Bit 0 :
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x03, 0xF8 when PNPCSV=0 at POR )
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundaries.
CR70 (Default 0x04 when PNPCSV=0 at POR)
Bit 7-4 : Reserved.
Bit [3:0] : These bits select IRQ resource for Serial Port 1.
CR71(Default 0x02, read only)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
CRF0 (Default 0x00)
Bit 7-2 : Reserved.
Bit 1-0 : SUACLKB1, SUACLKB0
= 00 UART A clock source is 1.8462 Mhz (24MHz/13)
= 01 UART A clock source is 2 Mhz (24MHz/12)
= 10 UART A clock source is 24 Mhz (24MHz/1)
= 11 UART A clock source is 14.769 Mhz (24MHz/1.625)
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10.5 Logical Device 3 (UART B)
CR30 (Default 0x01 when PNPCSV=0 at POR)
Bit 7-1 : Reserved.
Bit 0 :
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x02, 0xF8 when PNPCSV=0 at POR)
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundaries.
CR70 (Default 0x03 when PNPCSV=0 at POR)
Bit 7-4 : Reserved.
Bit [3:0] : These bits select IRQ resource for Serial Port 2.
CR71 (Default 0x02, read only)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; 0: Edge trigger
CRF0 (Default 0x00)
Bit 7-2 : Reserved.
Bit 1-0 : SUBCLKB1, SUBCLKB0
= 00 UART B clock source is 1.8462 Mhz (24MHz/13)
= 01 UART B clock source is 2 Mhz (24MHz/12)
= 10 UART B clock source is 24 Mhz (24MHz/1)
= 11 UART B clock source is 14.769 Mhz (24MHz/1.625)
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10.6 Logical Device 4 (Real Time Clock)
CR30 (Default 0x01 when PENKRC=1 at POR)
Bit 7-1 : Reserved.
Bit 0 :
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x00, 0x70 when PENKRC=1 at POR)
These two registers select Real Time Clock I/O base address [0x100:0xFFE] on 2 byte
boundaries.
CR70 (Default 0x08 when PENKRC=1 at POR)
Bit 7-4 : Reserved.
Bit [3:0] : These bits select IRQ resource for RTC.
CR71 (Default 0x00, read/write)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
CRF0 (Default 0x00)
RTC Mode Register
Bit 7-6 :
= 00 Select BANK0 of RAM
= 01 Select BANK1 of RAM
= 10 Select BANK2 of RAM
Bit 5-4 : Reserved.
Bit 3 : = 1 Lock CMOS RAM E0-FFh
Bit 2 : = 1 Lock CMOS RAM C0-DFh
Bit 1 : = 1 Lock CMOS RAM A0-BFh
Bit 0 : = 1 Lock CMOS RAM 80-9Fh
Note : Once set, bit[3:0] can not be cleared by a write; bit[3:0] is cleared only on Power-On Reset or upon a Hard Reset.
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10.7 Logical Device 5 (KBC)
CR30 (Default 0x01 when PENKRC=1 at POR)
Bit 7-1 : Reserved.
Bit 0 :
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enables I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x00, 0x60 when PENKRC=1 at POR)
These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundaries.
CR62, CR 63 (Default 0x00, 0x64 when PENKRC=1 at POR)
These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundaries.
CR70 (Default 0x01 when PENKRC=1 at POR)
Bit 7-4 : Reserved.
Bit [3:0] : These bits select IRQ resource for KINT(keyboard).
CR71 (Default 0x02, Read only)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
CR72 (Default 0x0C when PENKRC=1 at POR)
Bit 7-4 : Reserved.
Bit [3:0] : These bits select IRQ resource for MINT(PS2 Mouse)
CR73 (Default 0x02)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
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CRF0 (Default 0x40)
Bit 7-6 : KBC clock rate selection
= 00 Select 6MHz as KBC clock input.
= 01 Select 8MHz as KBC clock input.
= 10 Select 12Mhz as KBC clock input.
= 11 Select 16Mhz as KBC clock input.
Bit 5-3 : Reserved.
Bit 2 : = 0 Port 92 disable.
= 1 Port 92 enable.
Bit 1 : = 0 Gate20 software control.
= 1 Gate20 hardware speed up.
Bit 0 : = 0 KBRST software control.
= 1 KBRST hardware speed up.
10.8 Logical Device 6 (IR)
CR30 (Default 0x00)
Bit 7-1 : Reserved.
Bit 0 : = 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x00, 0x00)
These two registers select IR I/O base address [0x100:0xFF8] on 8 byte boundaries.
CR70 (Default 0x00)
Bit 7-4 : Reserved.
Bit [3:0] : These bits select IRQ resource for IR.
CR71 (Default 0x02, read only)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
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CR74 (Default 0x04)
Bit 7-3 : Reserved.
Bit 2-0 : These bits select DRQ resource for RX of UART C.
= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04-0x07 No DMA active
CR75 (Default 0x04)
Bit 7-3 : Reserved.
Bit 2-0 : These bits select DRQ resource for TX of UART C.
= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04-0x07 No DMA active
CRF0 (Default 0x00)
Bit 7-4 : Reserved.
Bit 3 : RXW4C
= 0 No reception delay when SIR is changed from TX mode to RX mode.
= 1 Reception delays 4 characters-time(40 bit-time) when SIR is changed from TX mode
to RX mode.
Bit 2 : TXW4C
= 0 No transmission delay when SIR is changed from RX mode to TX mode.
= 1 Transmission delays 4 characters-time(40 bit-time) when SIR is changed from RX
to TX mode.
mode
Bit 1 : APEDCRC
= 0 No append hardware CRC value as data in FIR/MIR mode.
= 1 Append hardware CRC value as data in FIR/MIR mode.
Bit 0 : ENBNKSEL; Bank select enable
= 0 Disable IR Bank selection.
= 1 Enable IR Bank selection.
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10.9 Logical Device 7 (Auxiliary I/O Part I)
CR30 (Default 0x00)
Bit 7-1 : Reserved.
Bit 0 : = 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP1 I/O base address [0x100:0xFFF] on 1 byte boundaries.
CR62, CR 63 (Default 0x00, 0x00)
These two registers select GP14 alternate function Primary I/O base address [0x100:0xFFE] on 2
byte boundaries; They are available as you setting GP14 to be an alternate function (General
Purpose Address Decode).
CR64, CR 65 (Default 0x00, 0x00)
These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFF] on 1
byte boundaries; They are available as you setting GP15 to be an alternate function (General
Purpose Write Decode).
CR70 (Default 0x00)
Bit 7-4 : Reserved.
Bit 3-0 : These bits select IRQ resource for GP10 as you setting GP10 to be an alternate function
(Interrupt Steering).
CR71 (Default 0x02, read only)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
CR72 (Default 0x00)
Bit 7-4 : Reserved.
Bit 3-0 : These bits select IRQ resource for GP11 as you setting GP10 to be an alternate function
(Interrupt Steering).
CR73 (Default 0x02)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
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CRE0 (GP10, Default 0x01)
Bit 7-5 : Reserved.
Bit 4 : IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 3 : Select Function.
= 1 Select Alternate Function : Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2 : Reserved.
Bit 1 : Polarity.
= 1 Invert.
= 0 No Invert.
Bit 0 : In/Out selection.
= 1 Input.
= 0 Output.
CRE1 (GP11, Default 0x01)
Bit 7-5 : Reserved.
Bit 4 : IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 3 : Select Function.
= 1 Select Alternate Function : Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2 : Reserved.
Bit 1 : Polarity.
= 1 Invert.
= 0 No Invert.
Bit 0 : In/Out selection.
= 1 Input.
= 0 Output.
CRE2 (GP12, Default 0x01)
Bit 7-5 : Reserved
Bit 4-3 : Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function : Watching Dog Timer Output.
= 10 Reserved
= 11 Reserved
Bit 2 : Reserved.
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
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CRE3 (GP13, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function : Power LED output.
= 10 Reserved
= 11 Reserved
Bit 2 : Reserved.
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
CRE4 (GP14, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function : General Purpose Address Decoder(Active Low when
Bit 1 = 0, Decode two byte address).
= 10 Select 2nd alternate function : Keyboard Inhibit(P17).
= 11 Reserved
Bit 2 : Reserved.
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
CRE5 (GP15, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function.
= 01 General Purpose Write Strobe(Active Low when Bit 1 = 0).
= 10 8042 P12.
= 11 Reserved
Bit 2 : Reserved.
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
CRE6 (GP16, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function : Watching Dog Timer Output.
= 1x Reserved
Bit 2 : Reserved.
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
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CRE7 (GP17, Default 0x01)
Bit 7-4 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function : Power LED output. Please refer to TABLE C
= 1x Reserved
Bit 2 : Reserved.
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
TABLE C
WDT_CTRL1* BIT[1]*
WDT_CTRL0* BIT[3] WDT_CTRL1 BIT[0] POWER LED STATE
1
0
0
0
X
0
1
1
X
X
0
1
1 Hertz Toggle pulse
Continuous high or low*
Continuous high or low*
1 Hertz Toggle pulse
*Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8.
2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers.
CRF1 ( Default 0x00)
General Purpose Read/Write Enable*
Bit 7-2 : Reserved
Bit 1 :
= 1 Enable General Purpose Write Strobe
= 0 Disable General Purpose Write Strobe
Bit 0 :
= 1 Enable General Purpose Address Decode
= 0 Disable General Purpose Address Decode
*Note : If the logical device s activate bit is not set then bit 0 and 1 have no effect.
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10.10 Logical Device 8 (Auxiliary I/O Part II)
CR30 (Default 0x00)
Bit 7-1 : Reserved.
Bit 0 : = 1 Activates the logical device.
= 0 Logical device is inactive.
CR31
Bit 7-2 : Reserved.
Bit 1 : ENRNGCK -- > Enable I/O Range check
Bit 0 : FORIORD --> Forces LDN to respond I/O read
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE] on 2 byte
boundaries. I/O base address + 1 : Watch Dog I/O base address.
CR70 (Default 0x00)
Bit 7-4 : Reserved.
Bit 3-0 : These bits select IRQ resource for Common IRQ of GP20~GP25 at Logic Device 9.
CR71 (Default 0x02)
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; 0: Edge trigger
CR72 (Default 0x00)
Bit 7-4 : Reserved.
Bit 3-0 : These bits select IRQ resource for Watch Dog.
CR73
Bit 7-2 : Reserved.
Bit 1 : IRQLEV -- > IRQ Level
= 1: High; = 0: Low
Bit 0 : IRQTYPE --> IRQ Type
= 1: Level trigger; = 0: Edge trigger
CRE8 (GP20, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select basic I/O function
= 01 Reserved
= 10 Select alternate function : Keyboard Reset (connected to KBC P20)
= 11 Reserved
Bit 2 : Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
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CRE9 (GP21, Default 0x01)
Bit 7-5 : Reserved
Bit 4-3 : Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function : Keyboard P13 I/O
= 11 Reserved
Bit 2 : Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
CREA (GP22, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function.
= 01 Reserved
= 10 Select 2nd alternate function : Keyboard P14 I/O.
= 11 Reserved
Bit 2 : Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
¡ @¡ @
Bit 0 : In/Out : 1 : Input, 0 : Output
CREB (GP23, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function : Keyboard P15 I/O
= 11 Reserved
Bit 2 : Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
¡ @
Bit 0 : In/Out : 1 : Input, 0 : Output
Publication Release Date: March 1998
Revision 0.58
- 139 -
W83977F/ W83977AF
PRELIMINARY
CREC (GP24, Default 0x01)
Bit 7-5 : Reserved.
Bit 4-3 : Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function : Keyboard P16 I/O
= 11 Reserved
Bit 2 : Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
CRED (GP25, Default 0x01)
Bit 7-4 : Reserved.
Bit 3 : Select Function.
= 1 Select alternate function: GATE A20(Connect to KBC P21).
= 0 Select basic I/O function
Bit 2 : Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert
Bit 0 : In/Out : 1 : Input, 0 : Output
CRF0 (Default 0x00)
Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter
can reject a pulse with 1ms width or less.
Bit 7-4 : Reserved
Bit 3 : GP Common IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 2-0 : Reserved
CRF1 (Reserved)
Publication Release Date: March 1998
- 140 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
CRF2 (Default 0x00)
Watching Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to
load the value to Watching Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any
Mouse Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to
Watching Dog Counter and count down. Read this register can not access Watching Dog Timer
Time-out value, but can access the current value in Watching Dog Counter.
Bit 7-0 :
= 0x00 Time-out Disable
= 0x01 Time-out occurs after 1 minute
= 0x02 Time-out occurs after 2 minutes
= 0x03 Time-out occurs after 3 minutes
................................................
= 0xFF Time-out occurs after 255 minutes
CRF3 (WDT_CTRL0, Default 0x00)
Watching Dog Timer Control Register #0
Bit 7-4 : Reserved
Bit 3 : When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output.
= 1 Enable
= 0 Disable
Bit 2 : Mouse interrupt reset Enable or Disable
= 1 Watching Dog Timer is reset upon a Mouse interrupt
= 0 Watching Dog Timer is not affected by Mouse interrupt
Bit 1 : Keyboard interrupt reset Enable or Disable
= 1 Watching Dog Timer is reset upon a Keyboard interrupt
= 0 Watching Dog Timer is not affected by Keyboard interrupt
Bit 0 : Reserved.
CRF4 (WDT_CTRL1, Default 0x00)
Watching Dog Timer Control Register #1
Bit 7-4 : Reserved
Bit 3 : Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
= 1 Enable
= 0 Disable
Bit 2 : Force Watching Dog Timer Time-out, Write only*
= 1 Force Watching Dog Timer time-out event; this bit is self-clearing.
Bit 1 : Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W
= 1 Enable
= 0 Disable
Bit 0 : Watching Dog Timer Status, R/W
= 1 Watching Dog Timer time-out occurred.
= 0 Watching Dog Timer counting
*Note : 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then
connect to set the Bit 0(Watching Dog Timer Status). The ORed signal is self-clearing.
Publication Release Date: March 1998
- 141 -
Revision 0.58
W83977F/ W83977AF
PRELIMINARY
11. SPECIFICATIONS
11.1 Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage
Input Voltage
-0.5 to 7.0
-0.5 to VDD+0.5
4.0 to 1.8
V
V
RTC Battery Voltage VBAT
Operating Temperature
Storage Temperature
V
0 to +70
° C
° C
-55 to +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
11.2 DC CHARACTERISTICS
(Ta = 0
°C to 70°C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER
SYM. MIN.
TYP.
MAX.
UNIT
CONDITIONS
VBAT = 2.5 V
RTC Battery Quiescent
Current
IBAT
2.4
uA
ACPI Stand-by Power
Supply Quiescent Current
IBAT
2.0
mA
VSB = 5.0 V, All ACPI pins are
not connected.
I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
2.0
2.4
0.4
V
IOL = 8 mA
IOH = - 8 mA
VIN = VDD
VIN = 0V
V
+10
-10
mA
mA
I/O6t - TTL level bi-directional pin with source-sink capability of 6 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
2.0
2.4
0.4
V
IOL = 6 mA
IOH = - 6 mA
VIN = VDD
VIN = 0V
V
+10
-10
mA
mA
Publication Release Date: March 1998
Revision 0.58
- 142 -
W83977F/ W83977AF
PRELIMINARY
11.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O8 - CMOS level bi-directional pin with source-sink capability of 8 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
0.4
V
V
0.7xVDD
3.5
V
IOL = 8 mA
V
IOH = - 8 mA
VIN = VDD
VIN = 0V
+ 10
- 10
mA
mA
I/O12 - CMOS level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
V
V
0.7xVDD
3.5
0.4
V
IOL = 12 mA
IOH = - 12 mA
VIN = VDD
V
+ 10
- 10
mA
mA
VIN = 0V
I/O16u - CMOS level bi-directional pin with source-sink capability of 16 mA, with internal pull-up
resistor
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
V
V
0.7xVDD
3.5
0.4
V
IOL = 16 mA
IOH = - 16 mA
VIN = VDD
V
+ 10
- 10
mA
mA
VIN = 0V
I/OD16u - CMOS level Open-Drain pin with source-sink capability of 16 mA, with internal pull-up
resistor
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.3xVDD
V
V
0.7xVDD
3.5
0.4
V
IOL = 16 mA
IOH = - 16 mA
VIN = VDD
V
+ 10
- 10
mA
mA
VIN = 0V
Publication Release Date: March 1998
Revision 0.58
- 143 -
W83977F/ W83977AF
PRELIMINARY
11.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
0.4
V
V
2.0
2.4
V
IOL = 12 mA
V
IOH = - 12 mA
VIN = VDD
VIN = 0V
+ 10
- 10
mA
mA
I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
VOL
VOH
ILIH
ILIL
0.8
V
V
2.0
2.4
0.4
V
IOL = 24 mA
IOH = - 24 mA
VIN = VDD
V
+ 10
- 10
mA
mA
VIN = 0V
OUT8t - TTL level output pin with source-sink capability of 8 mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 8 mA
2.4
IOH = - 8 mA
OUT12t - TTL level output pin with source-sink capability of 12 mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
V
V
IOL = 12 mA
IOH = -12 mA
2.4
OD12 - Open-drain output pin with sink capability of 12 mA
Output Low Voltage 0.4
OD24 - Open-drain output pin with sink capability of 24 mA
VOL
V
V
IOL = 12 mA
IOL = 24 mA
Output Low Voltage
VOL
0.4
INt - TTL level input pin
Input Low Voltage
VIL
VIH
ILIH
ILIL
0.8
V
V
Input High Voltage
Input High Leakage
Input Low Leakage
2.0
+10
-10
VIN = VDD
VIN = 0 V
mA
mA
Publication Release Date: March 1998
Revision 0.58
- 144 -
W83977F/ W83977AF
PRELIMINARY
11.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
INc - CMOS level input pin
Input Low Voltage
VIL
VIH
ILIH
ILIL
V
V
0.3´ VDD
Input High Voltage
0.7´ VDD
Input High Leakage
Input Low Leakage
+10
-10
VIN = VDD
VIN = 0 V
mA
mA
INcs - CMOS level Schmitt-triggered input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Vt-
Vt+
1.3
3.2
1.5
1.5
3.5
2
1.7
3.8
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0 V
VTH
ILIH
ILIL
V
Input High Leakage
Input Low Leakage
+10
-10
mA
mA
INcu - CMOS level input pin with internal pull-up resistor
Input Low Voltage
Input High Voltage
Input High Leakage
Input Low Leakage
VIL
VIH
ILIH
ILIL
0.7xVDD
V
V
0.7xVDD
+10
-10
VIN = VDD
VIN = 0 V
mA
mA
INts - TTL level Schmitt-triggered input pin
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0 V
VTH
ILIH
ILIL
V
Input High Leakage
Input Low Leakage
+10
-10
mA
mA
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
Vt-
Vt+
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VIN = VDD
VIN = 0 V
VTH
ILIH
ILIL
V
Input High Leakage
Input Low Leakage
+10
-10
mA
mA
Publication Release Date: March 1998
Revision 0.58
- 145 -
W83977F/ W83977AF
PRELIMINARY
11.3 AC Characteristics
11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec.
PARAMETER
SA9-SA0, AEN, DACK ,
SYM.
TEST
CONDITIONS
MIN.
TYP.
(NOTE 1)
MAX.
UNIT
TAR
25
nS
¡ õ
CS, setup time to IOR
TAR
0
nS
SA9-SA0, AEN, DACK ,
¡ ô
hold time for IOR
IOR width
TRR
TFD
80
nS
nS
CL = 100 pf
Data access time from
¡ õ
80
50
IOR
Data hold from IOR
¡ ô
CL = 100 pf
CL = 100 pf
TDH
TDF
TRI
10
10
nS
nS
nS
¡ õ
SD to from IOR
IRQ delay from IOR
360/570
/675
¡ ô
TAW
TWA
25
0
nS
nS
SA9-SA0, AEN, DACK ,
¡ õ
setup time to IOW
SA9-SA0, AEN, DACK ,
¡ ô
hold time for IOW
TWW
TDW
TWD
60
60
0
nS
nS
nS
IOW width
¡ ô
Data setup time to IOW
Data hold time from
¡ ô
IOW
TWI
360/570
/675
nS
¡ ô
IRQ delay from IOW
DRQ cycle time
TMCY
TAM
TMA
TAA
27
0
mS
50
nS
¡ õ
DRQ delay time DACK
DRQ to DACK delay
DACK width
nS
nS
260/430
/510
TMR
0
0
nS
nS
IOR delay from DRQ
IOW delay from DRQ
TMW
Publication Release Date: March 1998
Revision 0.58
- 146 -
W83977F/ W83977AF
PRELIMINARY
11.3.1 AC Characteristics, FDC continued
PARAMETER
SYM.
TEST
CONDITIONS
MIN.
TYP.
(NOTE 1)
MAX.
UNIT
mS
TMRW
6/12
/20/24
IOW or IOR response time
from DRQ
TC width
TTC
TRST
TIDX
TDST
135/220
/260
nS
RESET width
1.8/3/3.
5
mS
0.5/0.9
/1.0
mS
INDEX width
1.0/1.6
/2.0
mS
DIR setup time to STEP
TSTD
TSTP
24/40/48
mS
mS
DIR hold time from STEP
STEP pulse width
6.8/11.5
/13.8
7/11.7
/14
7.2/11.9
/14.2
TSC
Note 2
Note 2
Note 2
mS
mS
STEP cycle width
WD pulse width
TWDD
100/185
/225
125/210
/250
150/235
/275
Write precompensation
TWPC
100/138
/225
125/210
/250
150/235
/275
mS
Notes:
1. Typical values for T = 25° C and normal supply voltage.
2. Programmable from 2 mS through 32 mS in 2 mS increments.
Publication Release Date: March 1998
Revision 0.58
- 147 -
W83977F/ W83977AF
PRELIMINARY
11.3.2 UART/Parallel Port
PARAMETER
SYMBOL
TEST
MIN.
MAX.
UNIT
CONDITIONS
Delay from Stop to Set Interrupt
Delay from IOR Reset Interrupt
TSINT
9/16
Baud
Rate
TRINT
TIRS
100 pf Loading
100 pf Loading
1
mS
Delay from Initial IRQ Reset to
Transmit Start
1/16
9/16
8/16
Baud
Rate
THR
TSI
175
nS
Delay from IOW to Reset interrupt
Delay from Initial IOW to interrupt
16/16
Baud
Rate
Delay from Stop to Set Interrupt
TSTI
1/2
Baud
Rate
TIR
TMWO
TSIM
100 pF Loading
100 pF Loading
250
200
250
nS
nS
nS
Delay from IOR to Reset Interrupt
Delay from IOR to Output
Set Interrupt Delay from Modem
Input
TRIM
TIAD
250
nS
Reset Interrupt Delay from IOR
Interrupt Active Delay
Interrupt Inactive Delay
Baud Divisor
100 pF Loading
100 pF Loading
100 pF Loading
25
30
216-1
nS
nS
TIID
N
11.3.3 Parallel Port Mode Parameters
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
t1
100
nS
PD0-7, INDEX, STROBE, AUTOFD Delay from
IOW
t2
t3
t4
t5
60
nS
nS
nS
nS
IRQ Delay from ACK, nFAULT
105
300
105
IRQ Delay from IOW
IRQ Active Low in ECP and EPP Modes
200
ERROR Active to IRQ Active
Publication Release Date: March 1998
Revision 0.58
- 148 -
W83977F/ W83977AF
PRELIMINARY
11.3.4 EPP Data or Address Read Cycle Timing Parameters
PARAMETER
Ax Valid to IOR Asserted
SYM.
MIN.
MAX.
UNIT
t1
t2
t3
t4
t5
40
0
nS
nS
nS
IOCHRDY Deasserted to IOR Deasserted
IOR Deasserted to Ax Valid
10
40
0
10
24
IOR Deasserted to
or IOR Asserted
IOW
nS
IOR Asserted to IOCHRDY Asserted
PD Valid to SD Valid
t6
t7
0
0
75
40
nS
mS
nS
nS
IOR Deasserted to SD Hi-Z (Hold Time)
SD Valid to IOCHRDY Deasserted
t8
t9
0
85
60
160
WAIT Deasserted to IOCHRDY Deasserted
PD Hi-Z to PDBIR Set
t10
t13
t14
t15
t16
t17
t18
t19
t20
t21
0
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
WRITE Deasserted to IOR Asserted
WAIT Asserted to WRITE Deasserted
Deasserted to WRITE Modified
IOR Asserted to PD Hi-Z
0
185
190
50
60
0
60
0
180
WAIT Asserted to PD Hi-Z
Command Asserted to PD Valid
Command Deasserted to PD Hi-Z
0
60
1
190
WAIT Deasserted to PD Drive
WRITE Deasserted to Command
PBDIR Set to Command
t22
t23
t24
t25
0
0
20
30
nS
nS
nS
nS
PD Hi-Z to Command Asserted
Asserted to Command Asserted
0
195
180
60
WAIT Deasserted to Command Deasserted
Time out
t26
t27
10
0
12
nS
nS
PD Valid to WAIT Deasserted
PD Hi-Z to WAIT Deasserted
t28
0
mS
Publication Release Date: March 1998
Revision 0.58
- 149 -
W83977F/ W83977AF
PRELIMINARY
11.3.5 EPP Data or Address Write Cycle Timing Parameters
PARAMETER
Ax Valid to IOW Asserted
SYM.
MIN.
MAX.
UNIT
t1
t2
40
10
10
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SD Valid to Asserted
t3
IOW Deasserted to Ax Invalid
t4
WAIT Deasserted to IOCHRDY Deasserted
Command Asserted to WAIT Deasserted
IOW Deasserted to IOW or IOR Asserted
IOCHRDY Deasserted to IOW Deasserted
WAIT Asserted to Command Asserted
IOW Asserted to WAIT Asserted
PBDIR Low to WRITE Asserted
t5
10
40
0
t6
t7
24
160
70
t8
60
0
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
0
60
60
0
185
185
50
WAIT Asserted to WRITE Asserted
WAIT Asserted to WRITE Change
IOW Asserted to PD Valid
0
WAIT Asserted to PD Invalid
PD Invalid to Command Asserted
10
5
35
210
190
10
IOW to Command Asserted
60
60
0
WAIT Asserted to Command Asserted
WAIT Deasserted to Command Deasserted
mS
Command Asserted to WAIT Deasserted
Time out
10
0
12
mS
nS
Command Deasserted to WAIT Asserted
0
nS
IOW Deasserted to WRITE Deasserted and PD
invalid
Publication Release Date: March 1998
Revision 0.58
- 150 -
W83977F/ W83977AF
PRELIMINARY
11.3.6 Parallel Port FIFO Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
DATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
DATA Hold from nSTROBE Inactive
BUSY Inactive to PD Inactive
t1
t2
t3
t4
t5
t6
600
600
450
80
nS
nS
nS
nS
nS
nS
BUSY Inactive to nSTROBE Active
nSTROBE Active to BUSY Active
680
500
11.3.7 ECP Parallel Port Forward Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
nAUTOFD Valid to nSTROBE Asserted
PD Valid to nSTROBE Asserted
t1
t2
t3
t4
t5
t6
t7
t8
0
0
60
60
nS
nS
nS
nS
nS
nS
nS
nS
BUSY Deasserted to nAUTOFD Changed
BUSY Deasserted to PD Changed
80
80
0
180
180
nSTROBE Deasserted to BUSY Deasserted
BUSY Deasserted to nSTROBE Asserted
nSTROBE Asserted to BUSY Asserted
BUSY Asserted to nSTROBE Deasserted
80
0
200
180
80
11.3.8 ECP Parallel Port Reverse Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
PD Valid to nACK Asserted
t1
t2
t3
t4
t5
t6
0
0
nS
nS
nS
nS
nS
nS
nAUTOFD Deasserted to PD Changed
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK Deasserted
nACK Deasserted to nAUTOFD Asserted
PD Changed to nAUTOFD Deasserted
0
0
80
80
200
200
Publication Release Date: March 1998
Revision 0.58
- 151 -
W83977F/ W83977AF
PRELIMINARY
11.3.9 KBC Timing Parameters
NO.
DESCRIPTION
MIN.
MAX.
UNIT
T1
T2
Address Setup Time from WRB
Address Setup Time from RDB
WRB Strobe Width
0
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
mS
mS
mS
mS
mS
mS
mS
mS
mS
nS
mS
mS
mS
T3
20
20
0
T4
RDB Strobe Width
T5
Address Hold Time from WRB
Address Hold Time from RDB
Data Setup Time
T6
0
T7
50
0
T8
Data Hold Time
T9
Gate Delay Time from WRB
RDB to Drive Data Delay
RDB to Floating Data Delay
Data Valid After Clock Falling (SEND)
K/B Clock Period
10
30
40
20
4
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
0
20
10
4
K/B Clock Pulse Width
Data Valid Before Clock Falling (RECEIVE)
K/B ACK After Finish Receiving
RC Fast Reset Pulse Delay (8 Mhz)
RC Pulse Width (8 Mhz)
Transmit Timeout
20
2
3
2
6
Data Valid Hold Time
0
83
30
30
5
167
50
Input Clock Period (6- 12 Mhz)
Duration of CLK inactive
Duration of CLK active
50
Time from inactive CLK transition, used to time when
the auxiliary device sample DATA
25
T25
T26
T27
T28
T29
Time of inhibit mode
100
5
300
T28-5
50
mS
mS
mS
mS
mS
Time from rising edge of CLK to DATA transition
Duration of CLK inactive
30
30
5
Duration of CLK active
50
Time from DATA transition to falling edge of CLK
25
Publication Release Date: March 1998
Revision 0.58
- 152 -
W83977F/ W83977AF
PRELIMINARY
11.3.10 GPIO, ACPI, ROM Interface Timing Parameters
SYMBOL
tWGO
PARAMETER
Write data to GPIO update
MIN.
MAX.
UNIT
ns
300(Note 1)
tSWP
SWITCH pulse width
16
14
msec
msec
tSWE
16
Delay from SWITCH events to PSCTRL , and from
SWITCH Off event to SMI
tPORW
tPOWR
30
-
90
25
ms
SMI pulse width (edge mode)
nsec
Delay from APCI Reg.1 write to SMI inactive
(level mode)
tRIO
-
25
nsec
Delay from RIA,B KCLK, MCLK, PWAKIN1,
PWAKIN2 to PSCTRL
tRPO
tRTO
tRINW
-
25
0.190
-
sec
sec
ns
Delay from PHRI pulse to PSCTRL
Delay from PHRI pulse train to PSCTRL
PHRI width (high and low time)
0.125
10
Note : Refer to Microprocessor Interface Timing for Read Timing.
Publication Release Date: March 1998
Revision 0.58
- 153 -
W83977F/ W83977AF
PRELIMINARY
12. TIMING WAVEFORMS
12.1 FDC
Write Date
Processor Read Operation
WD
SA0-SA9
AEN
TWDD
CS
TAR
TRA
DACK
TRR
IOR
TDH
Index
TFD
TDF
D0-D7
IRQ
INDEX
TR
TIDX
TIDX
Processor Write Operation
Terminal Count
SA0-SA9
AEN
TC
TAW
TWA
DACK
IOW
TTC
TWW
TWD
Reset
TDW
D0-D7
IRQ
RESET
TWI
TRST
DMA Operation
Drive Seek operation
TAM
DRQ
DIR
TMCY
TAA
DACK
TMA
TSTP
TSTD
TDST
TMRW
IOW or
IOR
STEP
TMW (IOW)
TMR (IOR)
TSC
Publication Release Date: March 1998
Revision 0.58
- 154 -
W83977F/ W83977AF
PRELIMINARY
12.2 UART/Parallel
Receiver Timing
SIN
(RECEIVER
STAR
INPUT DATA)
DATA BITS
(5-8)
PARITY
STOP
TSINT
IRQ3 or IRQ4
IOR
TRINT
(READ RECEIVER
BUFFER REGISTER)
Transmitter Timing
SERIAL OUT
(SOUT)
STAR
STAR
DATA
(5-8)
PARITY
STOP
(1-2)
THRS
THR
TSTI
IRQ3 or IRQ4
THR
IOW
TSI
(WRITE THR)
TIR
IOR
(READ TIR)
Publication Release Date: March 1998
Revision 0.58
- 155 -
W83977F/ W83977AF
PRELIMINARY
12.2.1 Modem Control Timing
MODEM Control Timing
IOW
¢x
¢x
¢x
¢x
(WRITE MCR)
¢x
¢x
¢x
¢x
TMWO
¢
¢
¡÷
TMWO
¡÷ ¡ö
¢¡x ö
¢x
¢x
¢x
RTS,DTR
¢x
¢x
¢x
¢
¢x
¢
¢x
¢x
¢x
¢x
CTS,DSR
DCD
¢x
¢x
¢
¢
¢x
¡÷
¢
TSIM
TSIM
¢¡x ö
¡ö
¡÷
¢x
¢x
¢x
¢x
¢x
¢x
IRQ3 or
IRQ4
¢x
¢x
¢x
¢x
¢x
¢
¢x
¢
¢x
¢x
¢x
¢x
¢x
¢
¢
¢
¢
¢x
¡öTRIM
TRIM
¢x
¡ö
¡÷
¡÷
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
IOR
(READ MSR)
¢
TSIM
¡÷
¡ö
¢x
¢x
¢
¢x
¢x
¢x
¢x
¢x
¢x
¢
RI
Printer Interrupt Timing
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢
¢
ACK
¢x
TLAD
TLID
¢x
¡÷
¡ö
¡÷
¢x¡ö
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢
¢
IRQ7
Publication Release Date: March 1998
Revision 0.58
- 156 -
W83977F/ W83977AF
PRELIMINARY
12.3 Parallel Port
12.3.1 Parallel Port Timing
IOW
t1
INIT, STROBE
AUTOFD, SLCTIN
PD<0:7>
ACK
t2
IRQ (SPP)
IRQ
t3
t4
(EPP or ECP)
nFAULT
(ECP)
ERROR
(ECP)
t5
t2
t4
IRQ
Publication Release Date: March 1998
Revision 0.58
- 157 -
W83977F/ W83977AF
PRELIMINARY
12.3.2
EPP Data or Address Read Cycle (EPP Version 1.9)
t3
A<0:10>
IOR
t1
t2
t4
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE
t16
t18
t19
t20
t17
t21
PD<0:7>
t22
t23
t25
t24
ADDRSTB
DATASTB
t27
t28
t26
WAIT
Publication Release Date: March 1998
Revision 0.58
- 158 -
W83977F/ W83977AF
PRELIMINARY
12.3.3
EPP Data or Address Write Cycle (EPP Version 1.9)
t3
t4
A10-A0
SD<0:7>
t5
t1
t6
t2
IOW
IOCHRDY
t7
t8
t9
t10
t11
t12
t14
WRITE
t13
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t21
t20
WAIT
t22
PBDIR
Publication Release Date: March 1998
Revision 0.58
- 159 -
W83977F/ W83977AF
PRELIMINARY
12.3.4
EPP Data or Address Read Cycle (EPP Version 1.7)
t3
A<0:10>
IOR
t1
t2
t4
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE
t16
t18
t19
t20
t17
t21
PD<0:7>
t22
t23
t25
ADDRSTB
DATASTB
t24
t26
t28
t27
WAIT
Publication Release Date: March 1998
Revision 0.58
- 160 -
W83977F/ W83977AF
PRELIMINARY
12.3.5
EPP Data or Address Write Cycle (EPP Version 1.7)
t3
t4
A10-A0
SD<0:7>
t5
t1
t6
t2
IOW
t7
t8
IOCHRDY
t9
t10
t11
t22
t22
WRITE
t13
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t20
WAIT
12.3.6
Parallel Port FIFO Timing
t4
>|
>|
t3
PD<0:7>
t1
t2
t5
>|
>
>|
nSTROBE
BUSY
t6
>|
Publication Release Date: March 1998
Revision 0.58
- 161 -
W83977F/ W83977AF
PRELIMINARY
12.3.7
ECP Parallel Port Forward Timing
t3
t4
nAUTOFD
PD<0:7>
t1
t2
t6
t8
nSTROBE
t5
t5
t7
BUSY
12.3.8
ECP Parallel Port Reverse Timing
t2
PD<0:7>
t1
t3
t4
nACK
t5
t5
t6
nAUTOFD
Publication Release Date: March 1998
Revision 0.58
- 162 -
W83977F/ W83977AF
PRELIMINARY
12.4 KBC
12.4.1
Write Cycle Timing
A2, CSB
WRB
T1
T5
T3
ACTIVE
T7
T8
D0~D7
DATA IN
T9
GA20
OUTPUT PORT
T17
T18
FAST RESET PULSE RC
FE COMMAND
12.4.2
Read Cycle Timing
A2,CSB
AEN
T2
T6
T4
RDB
ACTIVE
T10
T11
D0-D7
DATA OUT
12.4.3
Send Data to K/B
CLOCK
(KCLK)
T12
T13
D4
T16
T14
SERIAL DATA
D5
D1
START
D2
D3
D0
D6
D7
P
STOP
(KDAT)
T19
Publication Release Date: March 1998
Revision 0.58
- 163 -
W83977F/ W83977AF
PRELIMINARY
12.4.4
Receive Data from K/B
CLOCK
(KCLK)
T14
T13
T15
SERIAL DATA
D5
START
D1
D2
D3
D4
D0
D6
D7
P
STOP
(T1)
T20
12.4.5
12.4.6
Input Clock
CLCOLCOKCK
T21
Send Data to Mouse
MCLK
T25
T23
T24
T22
MDAT
START
Bit
D5
D1
D2
D3
D4
D0
D6
D7
P
STOP
Bit
12.4.7
Receive Data from Mouse
MCLK
T29
T26
D1
T27
T28
D3
MDAT
D5
START
D2
D4
D0
D6
D7
P
STOP
Bit
Publication Release Date: March 1998
Revision 0.58
- 164 -
W83977F/ W83977AF
PRELIMINARY
12.5 GPIO Write Timing Diagram
VALID
VALID
A0-A15
IOW
D0-7
GPIO10-17
GPIO20-25
PREVIOUS STATE
VALID
tWGO
12.6 Master Reset (MR) Timing
Vcc
MR
tVMR
12.7 ACPI
12.7.1
PANSW Trigger and PSCTRL Timing
V
V
tSWP
tSWP
tSWE
OH
OL
PANSW
tSWE
HI-Z
OL
PSCTRL
SMI
V
edge:
tPORW
V
HI-Z/
OH
V
OL
V
V
OH
OL
WR
Level:
tPRL
Publication Release Date: March 1998
Revision 0.58
- 165 -
W83977F/ W83977AF
PRELIMINARY
RIA RIB
,
PSCTRL
12.7.2
, KLCK, MCLK, PWAKIN1, PWAKIN2 Trigger and
Timing
RIA, RIB
KCLK, MCLK
PWAKIN1, PWAKIN2
V
V
OH
OL
tRIO
HI-Z
PSCTRL
V
OL
12.7.3
PHRI Trigger and PSCTRL Timing
V
V
OH
OL
PHRI
tRINW
tRINW
tRPO
tRTO
HI-Z
PSCTRL
V
OL
13. APPLICATION CIRCUITS
13.1 Parallel Port Extension FDD
JP13
13
WE2/SLCT
25
12
JP 13A
WD2/PE
24
11
23
10
DCH2
34
33
31
29
27
25
23
21
19
17
15
13
11
9
MOB2/BUSY
HEAD2
RDD2
WP2
32
30
28
26
24
22
20
18
16
14
12
10
8
DSB2/ACK
22
TRK02
WE2
9
21
8
20
7
19
6
PD7
WD2
PD6
STEP2
DIR2
PD5
MOB2
DCH2/PD4
DSB2
IDX2
18
RDD2/PD3
5
17
4
16
3
15
2
14
1
7
5
3
1
STEP2/SLIN
WP2/PD2
6
4
2
RWC2
DIR2/INIT
TRK02/PD1
EXT FDC
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
Publication Release Date: March 1998
Revision 0.58
- 166 -
W83977F/ W83977AF
PRELIMINARY
13.2 Parallel Port Extension 2FDD
JP13
13
25
12
WE2/SLCT
JP 13A
WD2/PE
DCH2
24
11
23
10
22
9
21
8
20
7
19
6
18
5
34
32
30
28
26
24
22
20
18
16
14
12
10
8
33
31
29
27
25
23
21
19
17
15
13
11
9
MOB2/BUSY
HEAD2
RDD2
WP2
DSB2/ACK
TRK02
DSA2/PD7
MOA2/PD6
WE2
WD2
STEP2
DIR2
PD5
MOB2
DSA2
DSB2
MOA2
IDX2
DCH2/PD4
RDD2/PD3
7
5
3
1
17
4
16
3
STEP2/SLIN
WP2/PD2
6
4
2
DIR2/INIT
RWC2
TRK02/PD1
15
2
14
1
EXT FDC
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
13.3 Four FDD Mode
74LS139
G1
7407(2)
W83977F
1Y0
1Y1
DSA
DSB
DSC
DSD
MOA
DSA
DSB
A1
B1
1Y2
1Y3
2Y0
2Y1
MOA
MOB
MOB
MOC
MOD
G2
2Y2
2Y3
A2
B2
Publication Release Date: March 1998
Revision 0.58
- 167 -
W83977F/ W83977AF
PRELIMINARY
14. ORDERING INFORMATION
PART NO.
W83977F-P
KBC FIRMWARE
Phoenix MultiKey/42TM
AMIKEY-2TM
Phoenix MultiKey/42TM
AMIKEY-2TM
REMARKS
without FIR, 3rd UART
without FIR, 3rd UART
with FIR, 3rd UART
with FIR, 3rd UART
W83977F-A
W83977AF-P
W83977AF-A
15. HOW TO READ THE TOP MARKING
Example: The top marking of W83977F-A
inbond
W83977TF-A
ã AM. MEGA. 87-96
719AB27039520
1st line: Winbond logo
2nd line: the type number: W83977F-A
3rd line: the source of KBC F/W -- American Megatrends IncorporatedTM
4th line: Tracking code 709 A B 2 6519520
709: packages made in '97, week 09
A: assembly house ID; A means ASE, S means SPIL
B: IC revision; B means version B, C means version C
2: wafers manufactured in Winbond FAB 2
6519520: wafer production series lot number
Publication Release Date: March 1998
Revision 0.58
- 168 -
W83977F/ W83977AF
PRELIMINARY
16. PACKAGE DIMENSIONS
(128-pin QFP)
Dimension in mm
Dimension in inch
H E
E
Symbol
Min
0.25
2.57
Nom
0.35
Max
0.45
2.87
Min Nom Max
65
102
0.010
0.101
0.014
0.107
0.018
0.113
1
A
2.72
A2
64
103
0.004
0.004
0.547
0.008
0.006
0.551
0.012
0.008
0.555
0.791
0.10
0.10
0.20
0.15
0.30
0.20
b
c
13.90
14.00
14.10
20.10
D
E
e
19.90
20.00
0.50
0.783 0.787
0.020
HD
D
H
D
17.20
23.20
0.669
0.905
0.677
0.913
0.685
0.921
17.40
23.40
0.95
17.00
23.00
HE
L
0.80
1.60
0.025
0.031
0.063
0.037
0.65
39
128
1
L
0.08
7
y
0.003
7
1
38
e
b
0
0
0
c
Note:
A
1.Dimension D & E do not include interlead
flash.
2
1
A
2.Dimension b does not include dambar
protrusion/intrusion
.
3.Controlling dimension : Millimeter
4.General appearance spec. should be based
on final visual inspection spec.
See Detail F
Seating Plane
A
L
y
L 1
Detail F
5. PCB layout please use the "mm".
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
FAX: 1-408-9436668
www: http://www.winbond.com.tw/
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without
notice. All the trade marks of products and companies mentioned in this data
sheet belong to their respective owners.
Publication Release Date: March 1998
- 169 -
Revision 0.58
相关型号:
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W83C17P
Processor Specific Clock Generator, 80MHz, CMOS, PDSO14, 0.150 INCH, PLASTIC, SOP-14
WINBOND
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