W83977TF [WINBOND]
WINBOND I/O; WINBOND I / O
| 型号： | W83977TF |
| 厂家： | 
WINBOND |
| 描述： | WINBOND I/O |
| 文件： | 总160页 (文件大小：989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W83977TF
WINBOND I/O
W83977TF Data Sheet Revision History
Pages
Dates
Versi Version
Main Contents
on
on Web
1
2
n.a.
05/20/97
07/01/97
0.50
0.51
First published.
IV,V,6,7,14,49,5
5,69-80,87-96,
103,113, 117,
118,122, 128,
149
Typo correction and data calibrated
3
III,3,68,134,
07/20/97
0.60
Explanation of OnNow/ security wake-up
functions; Repagenating
146,148; 64-67
4
5
P101,101.1,102 11/18/97
0.61
0.62
Register correction
P1,3,49,62,64,
67,71,73,74,
100,117,119,
120,129
03/19/98
Typo correction and data calibrated
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
W83977TF
TABLE OF CONTENTS
GENERAL DESCRIPTION ....................................................................................................... 1
FEATURES.................................................................................................................................... 2
PIN CONFIGURATION ............................................................................................................. 4
1. PIN DESCRIPTION................................................................................................................ 5
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
HOST INTERFACE.....................................................................................................................................5
GENERAL PURPOSE I/O PORT...............................................................................................................7
SERIAL PORT INTERFACE......................................................................................................................8
INFRARED INTERFACE...........................................................................................................................9
MULTI-MODE PARALLEL PORT ...........................................................................................................9
FDC INTERFACE......................................................................................................................................14
KBC INTERFACE......................................................................................................................................15
POWER PINS .............................................................................................................................................16
ACPI INTERFACE.....................................................................................................................................16
2. FDC FUNCTIONAL DESCRIPTION................................................................................17
2.1
W83977TF FDC .........................................................................................................................................17
2.1.1 AT INTERFACE.............................................................................................................................17
2.1.2 FIFO (DATA)..................................................................................................................................17
2.1.3 DATA SEPARATOR.....................................................................................................................18
2.1.4 WRITE PRECOMPENSATION ...................................................................................................18
2.1.5 PERPENDICULAR RECORDING MODE.................................................................................18
2.1.6 FDC CORE......................................................................................................................................19
2.1.7 FDC COMMANDS ........................................................................................................................19
REGISTER DESCRIPTIONS ...................................................................................................................29
2.2.1 STATUS REGISTER A (SA REGISTER) (READ BASE ADDRESS + 0).............................29
2.2.2 STATUS REGISTER B (SB REGISTER) (READ BASE ADDRESS + 1) .............................31
2.2.3 DIGITAL OUTPUT REGISTER (DO REGISTER) (WRITE BASE ADDRESS + 2)............33
2.2.4 TAPE DRIVE REGISTER (TD REGISTER) (READ BASE ADDRESS + 3) ........................33
2.2.5 MAIN STATUS REGISTER (MS REGISTER) (READ BASE ADDRESS + 4)....................34
2.2
Publication Release Date: March 1998
- I -
Revision 0.62
W83977TF
2.2.6 DATA RATE REGISTER (DR REGISTER) (WRITE BASE ADDRESS + 4).......................34
2.2.7 FIFO REGISTER (R/W BASE ADDRESS + 5)..........................................................................36
2.2.8 DIGITAL INPUT REGISTER (DI REGISTER) (READ BASE ADDRESS + 7)....................38
2.2.9 CONFIGURATION CONTROL REGISTER (CC REGISTER)
(WRITE BASE ADDRESS + 7)...................................................................................................39
3. UART PORT............................................................................................................................40
3.1
3.2
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)..................40
REGISTER ADDRESS..............................................................................................................................40
3.2.1 UART CONTROL REGISTER (UCR) (READ/WRITE)...........................................................40
3.2.2 UART STATUS REGISTER (USR) (READ/WRITE)...............................................................42
3.2.3 HANDSHAKE CONTROL REGISTER (HCR) (READ/WRITE) ............................................43
3.2.4 HANDSHAKE STATUS REGISTER (HSR) (READ/WRITE).................................................44
3.2.5 UART FIFO CONTROL REGISTER (UFR) (WRITE ONLY).................................................45
3.2.6 INTERRUPT STATUS REGISTER (ISR) (READ ONLY).......................................................46
3.2.7 INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE).................................................47
3.2.8 PROGRAMMABLE BAUD GENERATOR (BLL/BHL) (READ/WRITE) .............................47
3.2.9 USER-DEFINED REGISTER (UDR) (READ/WRITE).............................................................48
4. INFRARED (IR) PORT.........................................................................................................49
5. PARALLEL PORT ...............................................................................................................49
5.1
5.2
PRINTER INTERFACE LOGIC...............................................................................................................49
ENHANCED PARALLEL PORT (EPP)..................................................................................................50
5.2.1 DATA SWAPPER ..........................................................................................................................51
5.2.2 PRINTER STATUS BUFFER.......................................................................................................51
5.2.3 PRINTER CONTROL LATCH AND PRINTER CONTROL SWAPPER...............................52
5.2.4 EPP ADDRESS PORT...................................................................................................................52
5.2.5 EPP DATA PORT 0-3....................................................................................................................53
5.2.6 BIT MAP OF PARALLEL PORT AND EPP REGISTERS .......................................................53
5.2.7 EPP PIN DESCRIPTIONS ............................................................................................................54
5.2.8 EPP OPERATION..........................................................................................................................54
EXTENDED CAPABILITIES PARALLEL (ECP) PORT.....................................................................55
5.3.1 ECP REGISTER AND MODE DEFINITIONS...........................................................................55
5.3.2 DATA AND ECPAFIFO PORT....................................................................................................56
5.3.3 DEVICE STATUS REGISTER (DSR).........................................................................................56
5.3.4 DEVICE CONTROL REGISTER (DCR) ....................................................................................57
5.3
Publication Release Date: March 1998
- II -
Revision 0.62
W83977TF
5.3.5 CFIFO (PARALLEL PORT DATA FIFO) MODE = 010...........................................................58
5.3.6 ECPDFIFO (ECP DATA FIFO) MODE = 011............................................................................58
5.3.7 TFIFO (TEST FIFO MODE) MODE = 110.................................................................................58
5.3.8 CNFGA (CONFIGURATION REGISTER A) MODE = 111 ....................................................58
5.3.9 CNFGB (CONFIGURATION REGISTER B) MODE = 111.....................................................58
5.3.10 ECR (EXTENDED CONTROL REGISTER) MODE = ALL....................................................59
5.3.11 BIT MAP OF ECP PORT REGISTERS.......................................................................................60
5.3.12 ECP PIN DESCRIPTIONS............................................................................................................61
5.3.13 ECP OPERATION..........................................................................................................................62
5.3.14 FIFO OPERATION ........................................................................................................................62
5.3.15 DMA TRANSFERS........................................................................................................................63
5.3.16 PROGRAMMED I/O (NON-DMA) MODE................................................................................63
EXTENSION FDD MODE (EXTFDD)...................................................................................................63
EXTENSION 2FDD MODE (EXT2FDD) ..............................................................................................63
5.4
5.5
6. KEYBOARD CONTROLLER.............................................................................................64
6.1
6.2
6.3
6.4
6.5
OUTPUT BUFFER ....................................................................................................................................64
INPUT BUFFER.........................................................................................................................................64
STATUS REGISTER.................................................................................................................................65
COMMANDS .............................................................................................................................................65
HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC .................................................67
6.5.1 KB CONTROL REGISTER (LOGIC DEVICE 5, CR-F0).........................................................67
6.5.2 PORT 92 CONTROL REGISTER (DEFAULT VALUE = 0X24)............................................67
ONNOW / SECURITY KEYBOARD AND MOUSE WAKE-UP ......................................................68
6.4
7. GENERAL PURPOSE I/O....................................................................................................69
7.1
7.2
BASIC I/O FUNCTIONS...........................................................................................................................71
ALTERNATE I/O FUNCTIONS ..............................................................................................................73
7.2.1 INTERRUPT STEERING..............................................................................................................73
7.2.2 WATCH DOG TIMER OUTPUT.................................................................................................74
7.2.3 POWER LED...................................................................................................................................74
7.2.4 GENERAL PURPOSE ADDRESS DECODER..........................................................................74
7.2.5 GENERAL PURPOSE WRITE STROBE....................................................................................74
8. PLUG AND PLAY CONFIGURATION ............................................................................75
8.1
COMPATIBLE PNP...................................................................................................................................75
8.1.1 EXTENDED FUNCTION REGISTERS......................................................................................75
Publication Release Date: March 1998
- III -
Revision 0.62
W83977TF
8.1.2 EXTENDED FUNCTIONS ENABLE REGISTERS (EFERS) .................................................76
8.1.3 EXTENDED FUNCTION INDEX REGISTERS (EFIRS), EXTENDED FUNCTION
DATA REGISTERS(EFDRS) .......................................................................................................76
9. ACPI REGISTERS FEATURES .........................................................................................77
9.1
9.2
9.3
SMI TO SCI/SCI TO SMI AND BUS MASTER ....................................................................................78
POWER MANAGEMENT TIMER..........................................................................................................79
ACPI REGISTERS (ACPIRS)...................................................................................................................80
9.3.1 POWER MANAGEMENT 1 STATUS REGISTER 1 (PM1STS1)..........................................80
9.3.2 POWER MANAGEMENT 1 STATUS REGISTER 2 (PM1STS2)..........................................81
9.3.3 POWER MANAGEMENT 1 ENABLE REGISTER 1(PM1EN1) ............................................82
9.3.4 POWER MANAGEMENT 1 ENABLE REGISTER 2 (PM1EN2) ...........................................82
9.3.5 POWER MANAGEMENT 1 CONTROL REGISTER 1 (PM1CTL1)......................................83
9.3.6 POWER MANAGEMENT 1 CONTROL REGISTER 2 (PM1CTL2)......................................83
9.3.7 POWER MANAGEMENT 1 CONTROL REGISTER 3 (PM1CTL3)......................................84
9.3.8 POWER MANAGEMENT 1 CONTROL REGISTER 4 (PM1CTL4)......................................84
9.3.9 POWER MANAGEMENT 1 TIMER 1 (PM1TMR1) ................................................................85
9.3.10 POWER MANAGEMENT 1 TIMER 2 (PM1TMR2) ................................................................85
9.3.11 POWER MANAGEMENT 1 TIMER 3 (PM1TMR3) ................................................................86
9.3.12 POWER MANAGEMENT 1 TIMER 4 (PM1TMR4) ................................................................87
9.3.13 GENERAL PURPOSE EVENT 0 STATUS REGISTER 1 (GP0STS1)...................................87
9.3.14 GENERAL PURPOSE EVENT 0 STATUS REGISTER 2 (GP0STS2)...................................88
9.3.15 GENERAL PURPOSE EVENT 0 ENABLE REGISTER 1 (GP0EN1)....................................89
9.3.16 GENERAL PURPOSE EVENT 0 ENABLE REGISTER 2 (GP0EN2)....................................89
9.3.17 GENERAL PURPOSE EVENT 1 STATUS REGISTER 1 (GP1STS1)...................................90
9.3.18 GENERAL PURPOSE EVENT 1 STATUS REGISTER 2 (GP1STS2)...................................90
9.3.19 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 1 (GP1EN1)....................................91
9.3.20 GENERAL PURPOSE EVENT 1 ENABLE REGISTER 2 (GP1EN2)....................................91
9.3.21 BIT MAP CONFIGURATION REGISTERS...............................................................................92
10. SERIAL IRQ .........................................................................................................................93
10.1 START FRAME .........................................................................................................................................94
10.2 IRQ/DATA FRAME...................................................................................................................................94
10.3 STOP FRAME ............................................................................................................................................94
10.4 RESET AND INITIALIZATION..............................................................................................................95
11. CONFIGURATION REGISTER.......................................................................................96
Publication Release Date: March 1998
- IV -
Revision 0.62
W83977TF
11.1 CHIP (GLOBAL) CONTROL REGISTER..............................................................................................96
11.2 LOGICAL DEVICE 0 (FDC)...................................................................................................................100
11.3 LOGICAL DEVICE 1 (PARALLEL PORT)..........................................................................................103
11.4 LOGICAL DEVICE 2 (UART A)¢) ........................................................................................................104
11.5 LOGICAL DEVICE 3 (UART B) ...........................................................................................................104
11.6 LOGICAL DEVICE 5 (KBC) ..................................................................................................................106
11.7 LOGICAL DEVICE 7 (GP I/O PORT I).................................................................................................107
11.8 LOGICAL DEVICE 8 (GP I/O PORT II) ...............................................................................................110
11.9 LOGICAL DEVICE 9 (GP I/O PORT III)..............................................................................................114
11.10 LOGICAL DEVICE A (ACPI) ................................................................................................................117
12. SPECIFICATIONS............................................................................................................123
12.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................123
12.2 DC CHARACTERISTICS.......................................................................................................................123
12.3 AC CHARACTERISTICS .......................................................................................................................127
12.3.1 FDC: DATA RATE = 1 MB, 500 KB, 300 KB, 250 KB/SEC...............................................127
12.3.2 UART/PARALLEL PORT........................................................................................................129
12.3.3 PARALLEL PORT MODE PARAMETERS..........................................................................129
12.3.4 EPP DATA OR ADDRESS READ CYCLE TIMING PARAMETERS..............................130
12.3.5 EPP DATA OR ADDRESS WRITE CYCLE TIMING PARAMETERS ............................131
12.3.6 PARALLEL PORT FIFO TIMING PARAMETERS..............................................................132
12.3.7 ECP PARALLEL PORT FORWARD TIMING PARAMETERS.........................................132
12.3.8 ECP PARALLEL PORT REVERSE TIMING PARAMETERS...........................................132
12.3.9 KBC TIMING PARAMETERS................................................................................................133
12.3.10 GPIO TIMING PARAMETERS................................................................................................134
13. TIMING WAVEFORMS ..................................................................................................135
13.1 FDC............................................................................................................................................................135
13.2 UART/PARALLEL...................................................................................................................................136
13.2.1 MODEM CONTROL TIMING ................................................................................................137
13.3 PARALLEL PORT ...................................................................................................................................138
13.3.1 PARALLEL PORT TIMING.....................................................................................................138
13.3.2 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.9)......................................139
13.3.3 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.9) ....................................140
13.3.4 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.7)......................................141
13.3.5 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.7) ....................................142
13.3.6 PARALLEL PORT FIFO TIMING...........................................................................................142
Publication Release Date: March 1998
- V -
Revision 0.62
W83977TF
13.3.7 ECP PARALLEL PORT FORWARD TIMING......................................................................143
13.3.8 ECP PARALLEL PORT REVERSE TIMING........................................................................143
13.4 KBC............................................................................................................................................................144
13.4.1 WRITE CYCLE TIMING..........................................................................................................144
13.4.2 READ CYCLE TIMING...........................................................................................................144
13.4.3 SEND DATA TO K/B...............................................................................................................144
13.4.4 RECEIVE DATA FROM K/B ..................................................................................................145
13.4.5 INPUT CLOCK..........................................................................................................................145
13.4.6 SEND DATA TO MOUSE.......................................................................................................145
13.4.7 RECEIVE DATA FROM MOUSE ..........................................................................................145
13.5 GPIO WRITE TIMING DIAGRAM .......................................................................................................146
13.6 MASTER RESET (MR) TIMING...........................................................................................................146
14. APPLICATION CIRCUITS.............................................................................................147
14.1 PARALLEL PORT EXTENSION FDD.................................................................................................147
14.2 PARALLEL PORT EXTENSION 2FDD...............................................................................................147
14.3 FOUR FDD MODE..................................................................................................................................148
15. ORDERING INFORMATION.........................................................................................148
16. HOW TO READ THE TOP MARKING .......................................................................148
17. PACKAGE DIMENSIONS...............................................................................................149
Publication Release Date: March 1998
- VI -
Revision 0.62
W83977TF
WINBOND I/O
GENERAL DESCRIPTION
'
The W83977TF is an evolving product from Winbond s most popular I/O chip W83877F --- which
integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plug-and-
ACPI
play registers for the whole chip --- plus additional powerful features:
, 8042 keyboard controller
with PS/2 mouse support, 23 general purpose I/O ports, full 16-bit address decoding, OnNow keyboard
wake-up, OnNow mouse wake-up.
The disk drive adapter functions of W83977TF include a floppy disk drive controller compatible with the
industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate
selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of
functions integrated into the W83977TF greatly reduces the number of components required for
interfacing with floppy disk drives. The W83977TF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M
disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The W83977TF provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system. Both
UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates
230k 460k
, or
921k bps
which support higher speed modems.
of
,
The W83977TF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two
external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95TM, which makes system resource allocation more efficient than ever.
ACPI Advanced Configuration and Power Interface
W83977TF provides functions that comply with
(
),
SMI
SCI
function pins.
which includes support of legacy and ACPI power management through
or
W83977TF also has auto power management to reduce power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM
and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEYTM 2, Phoenix
-
MultiKey/42TM, or customer code.
The W83977TF provides a set of flexible I/O control functions to the system designer through a set of
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a predefined alternate function.
Microsoft PC97 Hardware Design Guide
. IRQs, DMAs, and
W83977TF is made to fully comply with
I/O space resource are flexible to adjust to meet ISA PnP requirement. Moreover W83977TF is made to
'
ACPI
DPM
and (Device
meet the specification of PC97 s requirement in the power management:
Power Management).
Another benifit is that W83977TF has the same pin assignment as W83977AF, W83977F, W83977ATF.
This makes the design very flexible.
Publication Release Date: April 1998
-1-
Preliminary Revision 0.62
W83977TF
PRELIMINARY
FEATURES
General
·
Plug & Play 1.0A compatible
· Support 13 IRQs, 4 DMA channels, full 16-bit address decoding
·
·
·
Capable of ISA Bus IRQ Sharing
Microsoft PC97
Compliant with
DPM
Hardware Design Guide
ACPI
Support
(Device Power Management),
·
SCI
signal issued from any of the 13 IQRs pins or GPIO xx
Report ACPI status interrupt by
· Programmable configuration settings
·
Single 24/48 Mhz clock input
FDC
·
·
Compatible with IBM PC AT disk drive systems
Variable write pre-compensation with track selectable capability
· Support vertical recording format
·
·
·
·
·
·
DMA enable logic
16-byte data FIFOs
Support floppy disk drives and tape drives
Detects all overrun and underrun conditions
Built-in address mark detection circuit to simplify the read electronics
FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was
forced to be inactive)
·
·
·
·
Support up to four 3.5-inch or 5.25-inch floppy disk drives
Completely compatible with industry standard 82077
360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
3-mode FDD, and its Win95 driver
Support
UART
·
·
·
Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
MIDI compatible
Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
Internal diagnostic capabilities:
·
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (216-1)
·
921k bps
Maximum baud rate up to
for 14.769 Mhz and 1.5M bps for 24 Mhz
Publication Release Date: April 1998
Revision 0.62
-2-
W83977TF
PRELIMINARY
Infrared
·
Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
·
Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
· Support S/W driver for Windows95TM and Windows98TM (MemphisTM
)
Parallel Port
·
·
·
·
·
Compatible with IBM parallel port
Support PS/2 compatible bi-directional parallel port
-
Support Enhanced Parallel Port (EPP) Compatible with IEEE 1284 specification
-
Support Extended Capabilities Port (ECP) Compatible with IEEE 1284 specification
Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B
through parallel port
·
Enhanced printer port back-drive current protection
Keyboard Controller
8042 based with optional F/W from AMIKKEYTM-2, Phoenix MultiKey/42TM or customer code
·
with 2K bytes of programmable ROM, and 256 bytes of RAM
·
·
·
·
Asynchronous Access to Two Data Registers and One status Register
Software compatibility with the 8042 and PC87911 microcontrollers
Support PS/2 mouse
Support port 92
· Support both interrupt and polling modes
·
·
·
Fast Gate A20 and Hardware Keyboard Reset
8 Bit Timer/ Counter
Support binary and BCD arithmetic
· 6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
General Purpose I/O Ports
·
·
23 programmable general purpose I/O ports; 3 dedicate, 20 optional
General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer
output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins
OnNow Funtions
·
·
Keyboard wake-up by programmable keys
Mouse wake-up by programmable buttons
Package
·
128-pin PQFP
Publication Release Date: April 1998
Revision 0.62
-3 -
W83977TF
PRELIMINARY
PIN CONFIGURATION
/
/
P
A
N
P
A
N
S
S
W
O
U
/
W
I
,
S
M
N T
,
I
,
I
I I
R R R I
I I I I I I I
G
G
P
2
G
/
K
G
P
2
M
C
L
/
Q Q Q R R R R R R R R
1 1 1 Q Q Q Q Q Q Q Q
2 1 0 1 3 4 5 6 7 8 9
A V A A A
A
V
S
B
A
P P
V
R
C
R
I
1
S 1 1 1
1 A A A A A A A A A
A
1 C
S 4 3 2 1 C 0 9 8 7 6 5 4 3 2 1
2
2
2
L I
5
3
0
0
B
1
K
K
A
1
9 9
9
8 8
7 7
7 7
7 6
6
6
1
1
9
9
8 8
9 8
8
7
8 8
8 7 7
7
7
6
6
5
9
9 9 9 9
8
8
7
6
0
8 7
1
6 5
7 6
4 3
0 9
0
0 9
6 5 4 3 2
0
3 2 1 0 9 8
5
2 1
8 7
4
2 1 0
64
103
104
IRQ14/GP14
IRQ15/GP15
IOR
VBAT
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
XTAL1
VSS
105
106
107
108
109
110
111
112
XTAL2
IOW
MDATA
AEN
KDATA
IOCHRDY
KBLOCK/GP13
KBRST/GP12
GA20/GP11
VCC
D0
D1
D2
D3
DCDB
SOUTB/PEN48
113
D4
D5
114
115
116
117
118
119
120
121
122
SINB
VCC
D6
DTRB
RTSB
D7
MR
DSRB
CTSB
DACK0/GP16
VSS
DCDA
SCI/DRQ0/GP17
SOUTA/PENKBC
SINA
DACK1
123
124
125
126
127
DRQ1
DTRA/PNPCSV
RTSA/HEFRAS
DSRA
DACK2
DRQ2
CTSA
DACK3
DRQ3
TC
GP24
128
GP25
2
3
1
1 1
2 2
2 2 2 2 2
3 3
3
3
1
1
1 1
2
1
2
3
1
1 1
3
3
8
3
7
4
/
7
3
1 2 3
5
9 0
8
6
8 9
4 5 6 7 8
2 3 4 5 6 7
9 0 1 2
5
4
6
0 1 2 3
P
V
P
D
0
D
R
V
D
E
N
/
/
P
D
1
/
I
R
I
D
R
V
D
/
/
/
/
S
L
/
P P
P
P P
/
/ /
/
/
/
V
C
L
K
I
/
/
/
W
/
/
B
U
S
Y
P
E
C
M
O
B
I
D
S I
R
T
X
W
S D
T I
M
O
A
A D
D D D D
E A
S
W
D
D
S
A
S
D H R
T
D
S
B
N
D
E
X
L
E
C
T
C
C 7 6
4
3 2
N R F T R
S 5
S E P R
D
E
R
I
I
K
K
R D B X
A
A
K
0
A
T
A
T
N
N E
N
P
C
H
G
D
1
0
,
G
P
1
0
,
/
S
C
I
Publication Release Date: April 1998
Revision 0.62
-4-
W83977TF
PRELIMINARY
1. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O - TTL level bi-directional pin with 6 mA source-sink capability
6t
I/O - TTL level bi-directional pin with 8 mA source-sink capability
8t
I/O - CMOS level bi-directional pin with 8 mA source-sink capability
8
I/O
- TTL level bi-directional pin with 12 mA source-sink capability
12t
I/O - CMOS level bi-directional pin with 12 mA source-sink capability
12
I/O
- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
16u
I/OD
- CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor
16u
I/O
- TTL level bi-directional pin with 24 mA source-sink capability
24t
OUT - TTL level output pin with 8 mA source-sink capability
8t
OUT
- TTL level output pin with 12 mA source-sink capability
12t
OD - Open-drain output pin with 12 mA sink capability
12
OD - Open-drain output pin with 24 mA sink capability
24
IN - TTL level input pin
t
IN - CMOS level input pin
c
IN - CMOS level input pin with internal pull-up resitor
cu
IN - CMOS level Schmitt-triggered input pin
cs
IN - TTL level Schmitt-triggered input pin
ts
IN
- TTL level Schmitt-triggered input pin with internal pull-up resistor
tsu
1.1 Host Interface
SYMBOL
PIN
74-84
86-89
91
I/O
INt
FUNCTION
System address bus bits 0-10
-
A0 A10
A11-A14
A15
INt
System address bus bits 11-14
System address bus bit 15
System data bus bits 0-5
INt
109-
114
I/O12t
-
D0 D5
116-
117
I/O12t
System data bus bits 6-7
-
D6 D7
105
106
INts
INts
CPU I/O read signal
IOR
CPU I/O write signal
IOW
AEN
107
108
INts
System address bus enable
IOCHRDY
OD24
In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
MR
118
INts
Master Reset; Active high; MR is low during normal operations.
Publication Release Date: April 1998
-5 -
Revision 0.62
W83977TF
PRELIMINARY
1.1 Host Interface, continued
SYMBOL
PIN
I/O
FUNCTION
119
INtsu
DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00, default)
DACK0
GP16
(WDTO)
I/O12t
General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)
Alternate function from GP16: Watch dog timer output
KBC P15 I/O port. (CR2C bit 5_4 = 10)
P15
I/O12t
DRQ0
121
OUT12t DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)
GP17
I/O12t
General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)
Alternate Function from GP17: Power LED output.
KBC P14 I/O port (CR2C bit 7_6 = 10)
(PLEDO)
P14
SCI
I/O12t
OUT12t System Control Interrupt (CR2C bit 7_6 = 11)
INts DMA Channel 1 Acknowledge signal
OUT12t DMA Channel 1 request signal
INts DMA Channel 2 Acknowledge signal
OUT12t DMA Channel 2 request signal
INts DMA Channel 3 Acknowledge signal
OUT12t DMA Channel 3 request signal
INts Terminal Count. When active, this pin indicates termination of a
122
DACK1
DRQ1
123
124
DACK2
DRQ2
125
126
DACK3
DRQ3
TC
127
128
DMA transfer.
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
99
98
OUT12t Interrupt request 1
OUT12t Interrupt request 3
OUT12t Interrupt request 4
OUT12t Interrupt request 5
OUT12t Interrupt request 6
OUT12t Interrupt request 7
OUT12t Interrupt request 8
OUT12t Interrupt request 9
OUT12t Interrupt request 10
OUT12t Interrupt request 11
OUT12t Interrupt request 12
97
96
95
94
93
92
100
101
102
Publication Release Date: April 1998
Revision 0.62
-6-
W83977TF
PRELIMINARY
1.1 Host Interface, continued
SYMBOL
IRQ14
PIN
I/O
FUNCTION
103
OUT12t Interrupt request 14. (CR2C bit 1_0 = 00, default)
GP14
I/O12t
General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01)
Alternate Function 1 from GP14: General purpose address
decode output.
GPACS
(
)
(P17)
Alternate Function 2 from GP14: KBC P17 I/O port.
PLEDO
OUT12t Power LED output. (CR2C bit 1_0 = 10)
IRQ15
GP15
104
OUT12t Interrupt request 15.(CR2C bit 3_2 = 00, default)
I/O12t
General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01)
GPAWE
(
)
Alternate Function 1 from GP15: General purpose address write
enable output.
(P12)
Alternate Function 2 from GP15: KBC P12 I/O port.
WDT
OUT12t Watch-Dog timer output. (CR2C bit 3_2 = 10)
CLKIN
1
INt
24 or 48 MHz clock input, selectable through bit 5 of CR24.
1.2 General Purpose I/O Port
SYMBOL
GP20
PIN
I/O
FUNCTION
69
I/O12t
General purpose I/O port 2 bit 0.
(KBRST)
Alternate Function from GP20: Keyboard reset (KBC P20)
70
OUT12t
SMI
SMI
For the power management, the
is active low by the power
SCI
management events, that generate and
(CR2B bit 4_3 = 00, default)
in ACPI mode.
GP21
(P13)
P16
I/O12t
I/O12t
General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01)
Alternate Function from GP21: KBC P13 I/O port.
KBC P16 I/O port. (CR2B bit 4_3 = 10)
72
73
OUT12t Panel Switch output. (CR2B bit 5 = 0, default)
PANSWOUT
GP22
I/O12t
General purpose I/O port 2 bit 2. (CR2B bit 5 = 1)
Alternate Function from GP22: KBC P14 I/O port.
(P14)
IN12t
Panel Switch input. (CR2B bit 7_6 = 00, default)
PANSWIN
GP23
I/O12t
General purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01)
(P15)
Alternate Function from GP23: KBC P15 I/O port
GP24
(P16)
40
39
I/O12t
General purpose I/O port 2 bit 4 (CR2A bit 5_4 = 01)
Alternate Function from GP24: KBC P16 I/O port
P13
I/O12t
I/O12
KBC P13 I/O port. (CR2A bit 5_4 = 10)
GP25
General purpose I/O port 2 bit 5.
(GA20)
Alternate Function from GP25: GATE A20 (KBC P21)
Publication Release Date: April 1998
Revision 0.62
-7 -
W83977TF
PRELIMINARY
1.3 Serial Port Interface
SYMBOL
PIN
41
I/O
FUNCTION
INt
Clear To Send is the modem control input.
CTSA
CTSB
48
The function of these pins can be tested by reading Bit 4 of the
handshake status register.
42
49
INt
Data Set Ready. An active low signal indicates the modem or data
set is ready to establish a communication link and transfer data to
the UART.
DSRA
DSRB
43
I/O8t
UART A Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
RTSA
During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for CR26
HEFRAS
W
bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up.
(select 370H as configuration I/O port¢s address)
50
44
I/O8t
I/O8t
UART B Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
RTSB
UART A Data Terminal Ready. An active low signal informs the
modem or data set that the controller is ready to communicate.
DTRA
During power-on reset, this pin is pulled down internally and is
PNPCSV
PNPCSV
defined as
, which provides the power-on value for CR24
PNPCSV
bit 0 (
). A 4.7 kW is recommended if intends to pull up.
(clear the default value of FDC, UARTs, and PRT)
51
I/O8t
UART B Data Terminal Ready. An active low signal informs the
modem or data set that controller is ready to communicate.
DTRB
45, 52
46
INt
SINA
SINB
Serial Input. Used to receive serial data through the
communication link.
I/O8t
UART A Serial Output. Used to transmit serial data out to the
communication link.
SOUTA
During power-on reset, this pin is pulled down internally and is
defined as PENKBC, which provides the power-on value for CR24
bit 2 (ENKBC). A 4.7 kW resistor is recommended if intends to pull
up. (enable KBC)
PENKBC
SOUTB
PEN48
53
I/O8t
INt
UART B Serial Output. During power-on reset, this pin is pulled
down internally and is defined as PEN48, which provides the
W
power-on value for CR24 bit 6 (EN48). A 4.7 k resistor is
recommended if intends to pull up.
47
54
Data Carrier Detect. An active low signal indicates the modem or
data set has detected a data carrier.
DCDA
DCDB
Publication Release Date: April 1998
-8-
Revision 0.62
W83977TF
PRELIMINARY
1.3 Serial Port Interface, continued
SYMBOL
RIA
RIB
PIN
65
I/O
FUNCTION
INt
Ring Indicator. An active low signal indicates that a ring signal is
being received from the modem or data set.
66
1.4 Infrared Interface
SYMBOL
IRRX
IRTX
PIN
37
I/O
FUNCTION
INcs
Infrared Receiver input.
38
OUT12t Infrared Transmitter Output.
1.5 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SYMBOL
SLCT
PIN
I/O
FUNCTION
PRINTER MODE: SLCT
18
INt
An active high input on this pin indicates that the printer is selected.
This pin is pulled high internally. Refer to description of the
parallel port for definition of this pin in ECP and EPP mode.
OD12
OD12
INt
WE2
EXTENSION FDD MODE:
This pin is for Extension FDD B; its function is the same as the WE
pin of FDC.
WE2
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; it function is the same as
WE
the
pin of FDC.
PRINTER MODE: PE
PE
19
An active high input on this pin indicates that the printer has
detected the end of the paper. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
OD12
OD12
WD2
EXTENSION FDD MODE:
This pin is for Extension FDD B; its function is the same as the
WD
pin of FDC.
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; its function is the same as
WD2
WD
the
pin of FDC.
Publication Release Date: April 1998
Revision 0.62
-9 -
W83977TF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
BUSY
PIN
I/O
FUNCTION
21
INt
PRINTER MODE: BUSY
An active high input indicates that the printer is not ready to receive
data. This pin is pulled high internally. Refer to description of the
parallel port for definition of this pin in ECP and EPP mode.
MOB2
EXTENSION FDD MODE:
This pin is for Extension FDD B; the function of this pin is the same
MOB
OD12
OD12
as the
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; the function of this pin is the
pin of FDC.
MOB2
MOB
same as the
pin of FDC.
22
INt
ACK
PRINTER MODE:
ACK
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. This pin is pulled
high internally. Refer to description of the parallel port for
definition of this pin in ECP and EPP mode.
DSB2
EXTENSION FDD MODE:
This pin is for the Extension FDD B; its functions is the same as the
DSB
OD12
OD12
pin of FDC.
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; it functions is the same as
DSB
DSB2
the
pin of FDC.
ERR
34
INt
PRINTER MODE:
ERR
An active low input on this pin indicates that the printer has
encountered an error condition. This pin is pulled high internally.
Refer to description of the parallel port for definition of this pin in
ECP and EPP mode.
HEAD2
EXTENSION FDD MODE:
This pin is for Extension FDD B; its function is the same as the
HEAD
OD12
OD12
pin of FDC.
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; its function is the same as
HEAD2
HEAD
the
pin of FDC.
Publication Release Date: April 1998
Revision 0.62
-10-
W83977TF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PIN
I/O
FUNCTION
32
OD12
SLIN
PRINTER MODE:
SLIN
Output line for detection of printer selection. This pin is pulled high
internally. Refer to description of the parallel port for definition of
this pin in ECP and EPP mode.
STEP2
EXTENSION FDD MODE:
This pin is for Extension FDD B; its function is the same as the
STEP
OD12
pin of FDC.
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; its function is the same as
STEP
STEP2
OD12
OD12
the
pin of FDC.
INIT
33
PRINTER MODE:
INIT
Output line for the printer initialization. This pin is pulled high
internally. Refer to description of the parallel port for definition of
this pin in ECP and EPP mode.
DIR2
EXTENSION FDD MODE:
OD12
DIR
This pin is for Extension FDD B; its function is the same as the
pin of FDC.
DIR2
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; its function is the same as
DIR
OD12
OD12
the
pin of FDC.
AFD
35
PRINTER MODE:
AFD
An active low output from this pin causes the printer to auto feed a
line after a line is printed. This pin is pulled high internally. Refer
to description of the parallel port for definition of this pin in ECP and
EPP mode.
EXTENSION FDD MODE: DRVDEN0
OD12
OD12
This pin is for Extension FDD B; its function is the same as the
DRVDEN0 pin of FDC.
EXTENSION 2FDD MODE: DRVDEN0
This pin is for Extension FDD A and B; its function is the same as
the DRVDEN0 pin of FDC.
Publication Release Date: April 1998
-11 -
Revision 0.62
W83977TF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
STB
PIN
I/O
FUNCTION
36
OD12
STB
PRINTER MODE:
An active low output is used to latch the parallel data into the
printer. This pin is pulled high internally. Refer to description of the
parallel port for definition of this pin in ECP and EPP mode.
-
-
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
PRINTER MODE: PD0
31
30
29
I/O24t
PD0
PD1
PD2
Parallel port data bus bit 0. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
INt
INt
INDEX2
EXTENSION FDD MODE:
This pin is for Extension FDD B; the function of this pin is the same
INDEX
as the
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; the function of this pin is the
INDEX
pin of FDC. It is pulled high internally.
INDEX2
same as the
pin of FDC. It is pulled high internally.
I/O24t
INt
PRINTER MODE: PD1
Parallel port data bus bit 1. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
TRAK02
EXTENSION FDD MODE:
This pin is for Extension FDD B; the function of this pin is the same
TRAK0
as the
EXTENSION. 2FDD MODE:
This pin is for Extension FDD A and B; the function of this pin is the
TRAK0
pin of FDC. It is pulled high internally.
INt
TRAK02
same as the
pin of FDC. It is pulled high internally.
I/O24t
INt
PRINTER MODE: PD2
Parallel port data bus bit 2. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
WP2
EXTENSION FDD MODE:
This pin is for Extension FDD B; the function of this pin is the same
as the WP pin of FDC. It is pulled high internally.
INt
WP2
EXTENSION. 2FDD MODE:
This pin is for Extension FDD A and B; the function of this pin is the
WP
same as the
pin of FDC. It is pulled high internally.
Publication Release Date: April 1998
Revision 0.62
-12-
W83977TF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PD3
PIN
I/O
FUNCTION
28
I/O24t
PRINTER MODE: PD3
Parallel port data bus bit 3. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
INt
INt
RDATA2
EXTENSION FDD MODE:
This pin is for Extension FDD B; the function of this pin is the same
RDATA
as the
EXTENSION 2FDD MODE:
This pin is for Extension FDD A and B; this function of this pin is the
RDATA
pin of FDC. It is pulled high internally.
RDATA2
same as the
pin of FDC. It is pulled high internally.
27
I/O24t
INt
PRINTER MODE: PD4
PD4
Parallel port data bus bit 4. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
DSKCHG2
EXTENSION FDD MODE:
This pin is for Extension FDD B; the function of this pin is the same
DSKCHG
as the
pin of FDC. It is pulled high internally.
DSKCHG2
EXTENSION 2FDD MODE:
INt
This pin is for Extension FDD A and B; this function of this pin is the
same as the DSKCHG pin of FDC. It is pulled high internally.
PRINTER MODE: PD5
26
24
I/O24t
PD5
PD6
Parallel port data bus bit 5. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
EXTENSION 2FDD MODE: This pin is a tri-state output.
-
-
I/O24t
PRINTER MODE: PD6
Parallel port data bus bit 6. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
-
EXTENSION FDD MODE: This pin is a tri-state output.
MOA2
EXTENSION. 2FDD MODE:
OD24
This pin is for Extension FDD A; its function is the same as the
MOA
pin of FDC.
Publication Release Date: April 1998
Revision 0.62
-13 -
W83977TF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL
PD7
PIN
I/O
FUNCTION
23
I/O24t
PRINTER MODE: PD7
Parallel port data bus bit 7. Refer to description of the parallel port
for definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: This pin is a tri-state output.
-
DSA2
EXTENSION 2FDD MODE:
This pin is for Extension FDD A; its function is the same as the
DSA
OD24
pin of FDC.
1.6 FDC Interface
SYMBOL
DRVDEN0
DRVDEN1
GP10
PIN
2
I/O
FUNCTION
OD24
OD24
IO24t
Drive Density Select bit 0.
3
Drive Density Select bit 1. (CR2A bit 1_0 = 00, default)
General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01)
Alternate Function from GP10: Interrupt channel input.
KBC P12 I/O port. (CR2A bit 1_0 = 10)
(IRQIN1)
P12
IO24t
OUT12t System Control Interrupt (CR2A bit 1_0 = 11)
SCI
5
OD24
Head select. This open drain output determines which disk drive
head is active.
HEAD
Logic 1 = side 0
Logic 0 = side 1
9
OD24
OD24
Write enable. An open drain output.
WE
WD
10
Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.
11
12
OD24
OD24
Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
STEP
DIR
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
13
14
15
OD24
OD24
OD24
Motor B On. When set to 0, this pin enables disk drive 1. This is
an open drain output.
MOB
DSA
DSB
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open drain output.
Drive Select B. When set to 0, this pin enables disk drive B. This
is an open drain output.
Publication Release Date: April 1998
-14-
Revision 0.62
W83977TF
PRELIMINARY
1.6 FDC Interface, continued
SYMBOL
PIN
I/O
FUNCTION
16
OD24
Motor A On. When set to 0, this pin enables disk drive 0. This is
an open drain output.
MOA
4
INcs
Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
DSKCHG
W
internally by a 1 K resistor. The resistor can be disabled by bit 7
of L0-CRF0 (FIPURDWN).
6
7
INcs
INcs
The read data input signal from the FDD. This input pin is pulled
RDATA
WP
W
up internally by a 1 K resistor. The resistor can be disabled by
bit 7 of L0-CRF0 (FIPURDWN).
Write protected. This active low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
W
pulled up internally by a 1 K resistor. The resistor can be
disabled by bit 7 of L0-CRF0 (FIPURDWN).
8
INcs
INcs
Track 0. This Schmitt-triggered input from the disk drive is active
TRAK0
INDEX
low when the head is positioned over the outermost track.
This
W
input pin is pulled up internally by a 1 K resistor. The resistor
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
17
This Schmitt-triggered input from the disk drive is active low when
the head is positioned over the beginning of a track marked by an
W
index hole. This input pin is pulled up internally by a 1 K resistor.
The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
1.7 KBC Interface
SYMBOL
KDATA
MDATA
KCLK
PIN
59
I/O
FUNCTION
I/OD16u Keyboard Data
I/OD16u PS2 Mouse Data
I/OD16u Keyboard Clock
I/OD16u PS2 Mouse Clock
60
67
68
56
MCLK
GA20
I/O12t
I/O12t
KBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default)
GP11
General purpose I/O port 1 bit 1. (CR2A bit 6 = 1)
(IRQIN2)
Alternate Function from GP11: Interrupt channel input.
KBRST
GP12
57
I/O12t
I/O12t
W83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default)
General purpose I/O port 1 bit 2. (CR2A bit 7 = 1)
(WDTO)
Alternate Function 1 from GP12 : Watchdog timer output.
Publication Release Date: April 1998
-15 -
Revision 0.62
W83977TF
PRELIMINARY
1.7 KBC Interface, continued
SYMBOL
KBLOCK
GP13
PIN
58
I/O
INts
FUNCTION
W83C45 KINH (P17) Input. (CR2B bit 0 = 0, default)
General purpose I/O port 1 bit 3. (CR2B bit 0 = 1)
I/O16t
1.8 POWER PINS
SYMBOL
PIN
FUNCTION
VCC
20, 55, 85,
115
+5V power supply for the digital circuitry
VSB
71
+5V stand-by power supply for the digital circuitry
Ground
GND
25, 62, 90,
120
1.9 ACPI Interface
SYMBOL
VBAT
PIN
64
I/O
NA
INC
O8t
FUNCTION
battery voltage input
XTAL1
XTAL2
63
32.768Khz Clock Input
61
32.768Khz Clock Output
Publication Release Date: April 1998
Revision 0.62
-16-
W83977TF
PRELIMINARY
2. FDC FUNCTIONAL DESCRIPTION
2.1 W83977TF FDC
The floppy disk controller of the W83977TF integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to 2 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
2.1.1 AT interface
RD WR
, A0-A3, IRQ, DMA control, and
The interface consists of the standard asynchronous signals:
,
a data bus. The address lines select between the configuration registers, the FIFO and control/status
registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2
register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following formula:
´
m
THRESHOLD # (1/DATA/RATE) *8 - 1.5 S = DELAY
FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
1 Byte
2 Byte
8 Byte
15 Byte
´
´
´
m m m
16 S - 1.5 S = 14.5 S
1
2
8
m
m
m
16 S - 1.5 S = 30.5 S
m
m
m
16 S - 1.5 S = 6.5 S
´
m
m
m
15 16 S - 1.5 S = 238.5 S
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
FIFO THRESHOLD
1 Byte
2 Byte
8 Byte
15 Byte
´
´
´
m m m
8 S - 1.5 S = 6.5 S
1
2
8
m
m
m
8 S - 1.5 S = 14.5 S
m
m
m
8 S - 1.5 S = 62.5 S
´
m
m
m
15 8 S - 1.5 S = 118.5 S
Publication Release Date: April 1998
Revision 0.62
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W83977TF
PRELIMINARY
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the
DACK
DRQ pin during a data transfer command. The FIFO is enabled directly by asserting
addresses need not be valid.
and
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by
DACK
the FDC based only on
. This mode is only available when the FDC has been configured into byte
mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is
performed by using the new VERIFY command. No DMA operation is needed.
2.1.3 Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved
the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The
synchronized clock, called the Data Window, is used to internally sample the serial data portion of the
bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates
the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and
then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every
pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A
digital integrator is used to keep track of the speed changes in the input data stream.
2.1.4 Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk
drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media
and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known. Depending upon the pattern, the bit is shifted either early or late
relative to the surrounding bits.
2.1.5 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically.
This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the
FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
Publication Release Date: April 1998
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Revision 0.62
W83977TF
PRELIMINARY
2.1.6 FDC Core
The W83977TF FDC is capable of performing twenty commands. Each command is initiated by a multi-
byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information is provided to
the microprocessor.
2.1.7 FDC Commands
Command Symbol Descriptions:
C:
D:
Cylinder number 0 - 256
Data Pattern
DIR:
Step Direction
DIR = 0, step out
DIR = 1, step in
Disk Drive Select 0
Disk Drive Select 1
Data Length
DS0:
DS1:
DTL:
EC:
Enable Count
EOT:
EFIFO:
EIS:
End of Track
Enable FIFO
Enable Implied Seek
End of track
EOT:
FIFOTHR: FIFO Threshold
GAP:
GPL:
H:
Gap length selection
Gap Length
Head number
HDS:
HLT:
HUT:
LOCK:
MFM:
MT:
Head number select
Head Load Time
Head Unload Time
Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM or FM Mode
Multitrack
N:
NCN:
ND:
The number of data bytes written in a sector
New Cylinder Number
Non-DMA Mode
OW:
PCN:
POLL:
Overwritten
Present Cylinder Number
Polling Disable
PRETRK: Precompensation Start Track Number
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Revision 0.62
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PRELIMINARY
R:
Record
RCN:
R/W:
SC:
Relative Cylinder Number
Read/Write
Sector/per cylinder
Skip deleted data address mark
Step Rate Time
Status Register 0
Status Register 1
Status Register 2
Status Register 3
SK:
SRT:
ST0:
ST1:
ST2:
ST3:
WG:
Write gate alters timing of WE
(1) Read Data
PHASE
R/W
W
D7
D6 D5 D4
D3
D2 D1 D0
REMARKS
Command
MT MFM SK
0
0
1
1
0
Command codes
W
0
0
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
R
R
R
R
Sector ID information after
command execution
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Revision 0.62
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W83977TF
PRELIMINARY
(2) Read Deleted Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM SK
0
0
1
0
1
0
0
Command codes
W
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
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Revision 0.62
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PRELIMINARY
(3) Read A Track
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
W
W
W
W
W
W
W
0
0
MFM
0
0
0
0
0
0
0
0
1
0
Command codes
HDS DS1 DS0
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior to
command execution
Execution
Result
Data transfer between the
FDD and system; FDD reads
contents of all cylinders from
index hole to EOT
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
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PRELIMINARY
(4) Read ID
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
MFM
0
0
0
0
0
1
0
0
1
0
Command codes
W
HDS DS1 DS0
Execution
Result
The first correct ID
information on the cylinder
is stored in Data Register
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
R
R
Disk status after the
command has been
completed
R
R
(5) Verify
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM SK
EC
1
0
0
0
1
1
0
Command codes
W
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL/SC -------------------
Sector ID information prior
to command execution
W
W
W
W
W
Execution
Result
No data transfer takes
place
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
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PRELIMINARY
(6) Version
PHASE
Command
Result
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Command code
R
Enhanced controller
(7) Write Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
MT MFM
REMARKS
Command
0
0
0
1
0
1
Command codes
W
0
0
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to Command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
Command execution
Sector ID information after
Command execution
Publication Release Date: April 1998
Revision 0.62
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PRELIMINARY
(8) Write Deleted Data
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
MT MFM
0
0
1
0
0
0
1
Command codes
W
0
0
0
0
HDS DS1 DS0
W
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- EOT -----------------------
-------------------- GPL -----------------------
-------------------- DTL -----------------------
Sector ID information prior
to command execution
W
W
W
W
W
W
Execution
Result
Data transfer between the
FDD and system
R
R
R
R
R
R
R
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
Status information after
command execution
Sector ID information after
command execution
Publication Release Date: April 1998
Revision 0.62
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W83977TF
PRELIMINARY
(9) Format A Track
PHASE
R/W
W
W
W
W
W
W
W
W
W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
MFM
0
0
0
0
0
1
0
1
0
1
Command codes
HDS DS1 DS0
---------------------- N ------------------------
--------------------- SC -----------------------
--------------------- GPL ---------------------
---------------------- D ------------------------
---------------------- C ------------------------
---------------------- H ------------------------
---------------------- R ------------------------
---------------------- N ------------------------
-------------------- ST0 -----------------------
-------------------- ST1 -----------------------
-------------------- ST2 -----------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
---------------- Undefined -------------------
Bytes/Sector
Sectors/Cylinder
Gap 3
Filler Byte
Execution
for Each
Sector
Input Sector Parameters
Repeat:
Result
Status information after
command execution
R
R
R
R
R
R
(10) Recalibrate
PHASE
R/W D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
0
0
0
0
0
0
0
0
0
1
1
1
Command codes
0
0
DS1 DS0
Execution
Head retracted to Track 0
Interrupt
(11) Sense Interrupt Status
PHASE
Command
Result
R/W D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
W
R
0
0
0
0
1
0
0
0
Command code
---------------- ST0 -------------------------
---------------- PCN -------------------------
Status information at the end
of each seek operation
R
Publication Release Date: April 1998
Revision 0.62
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W83977TF
PRELIMINARY
(12) Specify
PHASE
R/W D7
D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
W
W
0
0
0
0
0
0
1
1
Command codes
| ---------SRT ----------- | --------- HUT ---------- |
|------------ HLT ----------------------------------| ND
(13) Seek
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
0
0
0
0
0
1
0
1
1
1
Command codes
W
HDS DS1 DS0
W
-------------------- NCN -----------------------
Execution
R
Head positioned over proper
cylinder on diskette
(14) Configure
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
Configure information
W
0
W
0
EIS EFIFO POLL | ------ FIFOTHR ----|
W
| --------------------PRETRK ----------------------- |
Execution
Internal registers written
(15) Relative Seek
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
1
0
DIR
0
0
0
0
0
1
0
1
1
1
Command codes
W
HDS DS1 DS0
W
| -------------------- RCN ---------------------------- |
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Revision 0.62
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W83977TF
PRELIMINARY
(16) Dumpreg
PHASE
Command
Result
R/W
W
R
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
0
0
0
0
1
1
1
0
Registers placed in FIFO
----------------------- PCN-Drive 0--------------------
----------------------- PCN-Drive 1 -------------------
----------------------- PCN-Drive 2--------------------
----------------------- PCN-Drive 3 -------------------
--------SRT ------------------ | --------- HUT --------
----------- HLT -----------------------------------| ND
------------------------ SC/EOT ----------------------
LOCK 0 D3 D2 D1 D0 GAP WG
0 EIS EFIFO POLL | ------ FIFOTHR --------
-----------------------PRETRK -------------------------
R
R
R
R
R
R
R
R
R
(17) Perpendicular Mode
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
1
0
0
1
0
Command Code
W
OW
0
D3
D2 D1 D0 GAP WG
(18) Lock
PHASE
Command
Result
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
LOCK 0
0
0
1
0
0
1
0
0
0
0
Command Code
R
0
0
LOCK
0
(19) Sense Drive Status
PHASE
R/W
W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
0
0
0
0
0
0
0
0
0
1
0
0
Command Code
W
0
HDS DS1 DS0
Result
R
---------------- ST3 -------------------------
Status information about
disk drive
(20) Invalid
PHASE
R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command
W
------------- Invalid Codes -----------------
Invalid codes (no operation-
FDC goes to standby state)
Result
R
-------------------- ST0 ----------------------
ST0 = 80H
Publication Release Date: April 1998
Revision 0.62
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PRELIMINARY
2.2 Register Descriptions
There are several status, data, and control registers in W83977TF. These registers are defined below:
ADDRESS
REGISTER
OFFSET
READ
WRITE
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
SA REGISTER
SB REGISTER
DO REGISTER
TD REGISTER
TD REGISTER
MS REGISTER
DT (FIFO) REGISTER
DI REGISTER
DR REGISTER
DT (FIFO) REGISTER
CC REGISTER
2.2.1 Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode,
the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR
WP
INDEX
HEAD
TRAK0
STEP
DRV2
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2
(Bit 6):
0
1
A second drive has been installed
A second drive has not been installed
STEP (Bit 5):
STEP
This bit indicates the complement of
output.
TRAK0
(Bit 4):
TRAK0
This bit indicates the value of
HEAD (Bit 3):
input.
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PRELIMINARY
HEAD
output.
This bit indicates the complement of
output.
0
1
side 0
side 1
INDEX
(Bit 2):
INDEX
This bit indicates the value of
WP
(Bit 1):
0disk is write-protected
1disk is not write-protected
DIR (Bit 0)
This bit indicates the direction of head movement.
0
1
outward direction
inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
2
1
7
6
5
4
3
0
DIR
WP
INDEX
HEAD
TRAK0
STEP F/F
DRQ
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRQ (Bit 6):
This bit indicates the value of DRQ output pin.
STEP F/F (Bit 5):
STEP
This bit indicates the complement of latched
output.
TRAK0 (Bit 4):
TRAK0
output.
This bit indicates the complement of
input.
HEAD
(Bit 3):
HEAD
This bit indicates the value of
0
1
side 1
side 0
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PRELIMINARY
INDEX (Bit 2):
INDEX
This bit indicates the complement of
output.
WP (Bit 1):
0
1
disk is not write-protected
disk is write-protected
DIR
(Bit 0)
This bit indicates the direction of head movement.
0
1
inward direction
outward direction
2.2.2 Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode,
the bit definitions for this register are as follows:
2
1
7
1
6
5
4
3
0
1
MOT EN A
MOT EN B
WE
RDATA Toggle
WDATA Toggle
Drive SEL0
Drive SEL0 (Bit 5):
This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).
WDATA Toggle (Bit 4):
WD
This bit changes state at every rising edge of the
output pin.
RDATA Toggle (Bit 3):
RDATA
This bit changes state at every rising edge of the
output pin.
WE (Bit 2):
WE
This bit indicates the complement of the
output pin.
MOT EN B (Bit 1)
MOB
MOA
This bit indicates the complement of the
output pin.
output pin.
MOT EN A (Bit 0)
This bit indicates the complement of the
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
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PRELIMINARY
2
1
7
6
5
4
3
0
DSC
DSD
WE F/F
RDATA F/F
WD F/F
DSA
DSB
DRV2
DRV2
(Bit 7):
0
1
A second drive has been installed
A second drive has not been installed
DSB
(Bit 6):
DSB
DSA
This bit indicates the status of
output pin.
output pin.
DSA
(Bit 5):
This bit indicates the status of
WD F/F(Bit 4):
WD
WD
output
This bit indicates the complement of the latched
pin.
output pin at every rising edge of the
RDATA F/F(Bit 3):
RDATA
This bit indicates the complement of the latched
output pin .
WE F/F (Bit 2):
WE
This bit indicates the complement of latched
output pin.
DSD
(Bit 1):
0
1
Drive D has been selected
Drive D has not been selected
DSC
(Bit 0):
0
1
Drive C has been selected
Drive C has not been selected
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PRELIMINARY
2.2.3 Digital Output Register (DO Register) (Write base address + 2)
The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ
enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are
as follows:
7
6
3
1-0
5
4
2
Drive Select: 00 select drive A
01 select drive B
10 select drive C
11 select drive D
Floppy Disk Controller Reset
Active low resets FDC
DMA and INT Enable
Active high enable DRQ/IRQ
Motor Enable A. Motor A on when active high
Motor Enable B. Motor B on when active high
Motor Enable C. Motor C on when active high
Motor Enable D. Motor D on when active high
2.2.4 Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data
separator. This register also holds the media ID, drive type, and floppy boot drive information of the
floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as
follows:
2
1
7
6
5
4
3
0
X
X
X
X
X
X
Tape sel 0
Tape sel 1
If three mode FDD function is enabled (EN3MODE = 1 in Logical Device 0 CRF0 bit:0), the bit definitions
are as follows:
2
1
7
6
5
4
3
0
Tape Sel 0
Tape Sel 1
Floppy boot drive 0
Floppy boot drive 1
Drive type ID0
Drive type ID1
Media ID0
Media ID1
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PRELIMINARY
Media ID1 Media ID0 (Bit 7, 6):
These two bits are read only. These two bits reflect the value of Logical Device 0 CRF1 bit 4,5.
Drive type ID1 Drive type ID0 (Bit 5, 4):
These two bits reflect two of the bits of Logical Device 0 CRF2. Which two bits are reflected depends on
the last drive selected in the DO REGISTER.
Floppy Boot drive 1, 0 (Bit 3, 2):
These two bits reflect the value of Logical Device 0 CRF1 bit 7,6.
Tape Sel 1, Tape Sel 0 (Bit 1, 0):
These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive
and is reserved as the floppy disk boot drive.
TAPE SEL 1
TAPE SEL 0
DRIVE SELECTED
0
0
1
1
0
1
0
1
None
1
2
3
2.2.5 Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
6
0
7
5
4
3
2
1
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.
FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.
FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
If DIO = LOW then transfer is from processor to Data Register.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
2.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the
FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by
the DR REGISTER. The real data rate is determined by the most recent write to either of the DR
REGISTER or CC REGISTER.
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1
7
6
5
0
4
3
2
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
1
FDC in normal mode
FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
PRECOMP
PRECOMPENSATION DELAY
2
1
0
250K - 1 Mbps
Default Delays
41.67 nS
2 Mbps Tape drive
Default Delays
20.8 nS
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
83.34 nS
41.17 nS
125.00 nS
62.5nS
166.67 nS
83.3 nS
208.33 nS
104.2 nS
250.00 nS
125.00 nS
0.00 nS (disabled)
0.00 nS (disabled)
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DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
DEFAULT PRECOMPENSATION DELAYS
125 nS
125 nS
125 nS
41.67nS
20.8 nS
2 MB/S
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
RWC
RWC
RWC
= 1
00 500 KB/S (MFM), 250 KB/S (FM),
01 300 KB/S (MFM), 150 KB/S (FM),
10 250 KB/S (MFM), 125 KB/S (FM),
= 1
= 0
= 0
RWC
11 1 MB/S (MFM), Illegal (FM),
The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in
logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for
individual data rates setting.
2.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the data
bus at a time. This register stores data, commands, and parameters and provides diskette-drive status
information. Data bytes are passed through the data register to program or obtain results after a
command. In the W83977TF, this register defaults to FIFO disabled mode after reset. The FIFO can
change its value and enable its operation through the CONFIGURE command.
Status Register 0 (ST0)
7-6
5
3
2
1-0
4
US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command execution
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Status Register 1 (ST1)
7
6
5
4
3
2
1
0
Missing Address Mark. 1 When the FDC cannot detect the data address mark
or the data address mark has been deleted.
NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during
execution of write data.
ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data.
Not used. This bit is always 0.
OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer.
DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.
Not used. This bit is always 0.
EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7
1
0
4
3
2
6
5
MD (Missing Address Mark in Data Field).
1 If the FDC cannot find a data address mark
(or the address mark has been deleted)
when reading data from the media
0 No error
BC (Bad Cylinder)
1 Bad Cylinder
0 No error
SN (Scan Not satisfied)
1 During execution of the Scan command
0 No error
SH (Scan Equal Hit)
1 During execution of the Scan command, if the equal condition is satisfied
0 No error
WC (Wrong Cylinder)
1 Indicates wrong Cylinder
DD (Data error in the Data field)
1 If the FDC detects a CRC error in the data field
0 No error
CM (Control Mark)
1 During execution of the read data or scan command
0 No error
Not used. This bit is always 0
Status Register 3 (ST3)
6
4
2
1
0
7
5
3
US0 Unit Select 0
US1 Unit Select 1
HD Head Address
TS Two-Side
TO Track 0
RY Ready
WP Write Protected
FT Fault
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2.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT
,
DSKCHG
only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of
while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7
6
5
4
3
2
1
0
x x x
x x x
x
Reserved for the hard disk controller
x
During a read of this register, these bits are in tri-state
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
7
6
1
5
4
3
1
2
0
1
1
1
HIGH DENS
DRATE0
DRATE1
DSKCHG
DSKCHG (Bit 7):
This bit indicates the complement of the
DSKCHG
input.
Bit 6-3: These bits are always a logic 1 during a read.
DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings
corresponding to the individual data rates.
HIGH DENS
(Bit 0):
0
1
500 KB/S or 1 MB/S data rate (high density FDD)
250 KB/S or 300 KB/S data rate
In the PS/2 Model 30 mode, the bit definitions are as follows:
7
6
0
5
0
4
3
2
0
1
0
DRATE0
DRATE1
NOPREC
DMAEN
DSKCHG
DSKCHG (Bit 7):
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DSKCHG
This bit indicates the status of
input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
2.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
4
2
3
1
6
5
0
7
x
x
x
x
x
x
DRATE0
DRATE1
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
2
1
7
6
5
4
3
0
X
X
X
X
X
DRATE0
DRATE1
NOPREC
:
X Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
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3. UART PORT
3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit
format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing
a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to
drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also
include complete modem control capability and a processor interrupt system that may be software
trailed to the computing time required to handle the communication link. The UARTs have a FIFO
mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs
for both receive and transmit mode.
3.2 Register Address
3.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
5
4
2
6
7
3
0
1
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format)
from the divisor latches of the baudrate generator during a read or write operation. When this bit
is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control
Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
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TABLE 3-1 UART Register Bit Map
Bit Number
Register Address Base
0
1
2
3
4
5
6
7
RX Data
Bit 0
RX Data
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data
Bit 5
RX Data
Bit 6
RX Data
Bit 7
+ 0
Receiver
Buffer
Register
(Read Only)
RBR
BDLAB = 0
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
+ 0
Transmitter
Buffer Register
(Write Only)
TBR
ICR
BDLAB = 0
RBR Data
Ready
Interrupt
Enable
TBR
Empty
Interrupt
Enable
USR
Interrupt
Enable
HSR
Interrupt
Enable
0
0
0
0
+ 1
Interrupt
Control
Register
BDLAB = 0
(EUSRI)
(EHSRI)
(ERDRI)
(ETBREI)
"0" if Interrupt
Pending
Interrupt
Status
Interrupt
Status
Interrupt
Status
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
+ 2
+ 2
Interrupt Status ISR
Register
(Read Only)
Bit (0)
Bit (1)
Bit (2)**
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved
Reversed
RX
Interrupt
Active Level Active Level
(LSB)
RX
Interrupt
UART FIFO
Control
Register
UFR
UCR
(MSB)
(Write Only)
Data
Length
Select
Bit 0
Data
Length
Select
Bit 1
Multiple
Stop Bits
Enable
Parity
Bit
Enable
Even
Parity
Enable
Parity
Bit Fixed
Enable
Set
Silence
Enable
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
+ 3
UART Control
Register
(MSBE)
(PBE)
(EPE)
PBFE)
(SSE)
(DLS0)
(DLS1)
Data
Terminal
Ready
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
+ 4
+ 5
Handshake
Control
Register
HCR
USR
HSR
(DTR)
RBR Data
Ready
Overrun
Error
Parity Bit
Error
No Stop
Bit
Error
Silent
Byte
Detected
(SBD)
TBR
Empty
TSR
Empty
RX FIFO
Error
Indication
(RFEI) **
UART Status
Register
(RDR)
(OER)
(PBER)
(TBRE)
(TSRE)
(NSER)
CTS
Toggling
DSR
Toggling
RI Falling
Edge
DCD
Toggling
Clear
to Send
Data Set
Ready
Ring
Indicator
Data Carrier
Detect
(DCD)
+ 6
+ 7
Handshake
Status Register
(TCTS)
Bit 0
(TDSR)
Bit 1
(FERI)
Bit 2
(TDCD)
Bit 3
(CTS)
Bit 4
(DSR)
Bit 5
(RI)
Bit 6
Bit 7
Bit 7
User Defined
Register
UDR
BLL
Bit 0
Bit 8
Bit 1
Bit 9
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
+ 0
Baudrate
Divisor Latch
Low
BDLAB = 1
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
+ 1
Baudrate
Divisor Latch
High
BHL
BDLAB = 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is
programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit
is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be
stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as
the transmitter will be detected.
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
checked.
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
checked.
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
each serial character.
TABLE 3-2 WORD LENGTH DEFINITION
DLS1
DLS0
DATA LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
3.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
2
7
6
4
3
1
0
5
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1
when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In
16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in
the FIFO.
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Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
thanthese two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to
a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write
the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It
will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word
time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same
condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a
logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR,
it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR,
it will clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same condition
instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the
RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
3.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
2
7
0
5
0
4
3
1
0
6
0
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
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Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the
TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
® DSR
® CTS
®
, Loopback RI input ( bit 2 of HCR)
(bit 0 of HCR)
, RTS ( bit 1 of HCR)
RI
® DCD
.
and IRQ enable ( bit 3 of HCR)
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit
DCD
is internally connected to the modem control input
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected
RI
.
to the modem control input
.
RTS
DTR
RTS
DTR
Bit 1: This bit controls the
Bit 0: This bit controls the
output. The value of this bit is inverted and output to
output. The value of this bit is inverted and output to
.
.
3.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
7
6
5
4
3
2
1
0
toggling (TCTS)
toggling (TDSR)
CTS
DSR
RI falling edge (FERI)
toggling (TDCD)
DCD
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
DCD
Bit 7: This bit is the opposite of the
input. This bit is equivalent to bit 3 of HCR in loopback mode.
RI
Bit 6: This bit is the opposite of the
Bit 5: This bit is the opposite of the
Bit 4: This bit is the opposite of the
Bit 3: TDCD. This bit indicates that the
input. This bit is equivalent to bit 2 of HCR in loopback mode.
DSR
CTS
input. This bit is equivalent to bit 0 of HCR in loopback mode.
input. This bit is equivalent to bit 1 of HCR in loopback mode.
DCD
pin has changed state after HSR was read by the CPU.
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RI
Bit 2: FERI. This bit indicates that the
by the CPU.
pin has changed from low to high state after HSR was read
DSR
Bit 1: TDSR. This bit indicates that the
pin has changed state after HSR was read by the CPU.
pin has changed state after HSR was read.
CTS
Bit 0: TCTS. This bit indicates that the
3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
2
1
7
6
5
4
3
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the
interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver
FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
TABLE 3-3 FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
1
1
0
1
0
1
01
04
08
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a
logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a
logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
other bits of UFR are programmed.
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3.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
7
6
5
0
4
3
2
1
0
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out
interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
TABLE 3-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit
3
Bit Bit
Bit Interrupt
Interrupt Type
Interrupt Source
Clear Interrupt
2
1
0
priority
0
0
0
1
0
1
1
0
-
-
No Interrupt pending
-
First
UART Receive
Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
1. RBR data ready
Read USR
0
1
0
0
Second
RBR Data Ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
1
0
1
0
0
1
0
0
Second
Third
FIFO Data Timeout
TBR Empty
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
Read RBR
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
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Revision 0.62
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PRELIMINARY
3.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
5
3
6
0
0
4
0
2
7
0
1
0
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
16
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table in the next page illustrates the use of the baud generator with a frequency of
1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud
generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode,
the data transmission rate can be as high as 1.5M bps.
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PRELIMINARY
3.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
TABLE 3-5 BAUD RATE TABLE
BAUD RATE FROM DIFFERENT PRE-DIVIDER
Pre-Div: 13
1.8461M Hz
50
Pre-Div:1.625
14.769M Hz
400
Pre-Div: 1.0
24M Hz
650
Decimal divisor used
to generate 16X clock
Error Percentage between
desired and actual
2304
1536
1047
857
768
384
192
96
**
75
600
975
**
110
880
1430
0.18%
134.5
150
1076
1478.5
1950
0.099%
1200
**
**
300
2400
3900
600
4800
7800
**
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
9600
15600
23400
26000
31200
46800
62400
93600
124800
249600
499200
748800
1497600
**
14400
16000
19200
28800
38400
57600
76800
153600
307200
460800
921600
64
**
58
0.53%
**
48
32
**
24
**
16
**
12
**
6
**
3
**
2
**
1
**
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
Note. Pre-Divisor is determined by CRF0 of UART A and B.
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PRELIMINARY
4. INFRARED (IR) PORT
The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless
communication which can operate under various transmission protocols including IrDA 1.0 SIR,
SHARP ASK-IR. IR port shares the same port with UART B port in W83977TF. Please refer to
section 11.5 for configuration information.
5. PARALLEL PORT
5.1 Printer Interface Logic
The parallel port of the W83977TF makes possible the attachment of various devices that accept
eight bits of parallel data at standard TTL level. The W83977TF supports an IBM XT/AT compatible
parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended
Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode
(EXT2FDD) on the parallel port. Refer to the configuration registers for more information on
disabling, power-down, and on selecting the mode of operation.
Table 5-1 shows the pin definitions for different modes of the parallel port.
PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
TABLE 5-1-1
HOST
CONNECTOR
PIN NUMBER
OF W83977TF
PIN
ATTRIBUTE
SPP
EPP
ECP
2
1
36
O
I/O
I
nSTB
PD<0:7>
nACK
BUSY
PE
nWrite
PD<0:7>
Intr
nSTB, HostClk
2-9
10
11
12
13
14
15
16
17
31-26, 24-23
PD<0:7>
2
22
21
19
18
35
34
33
32
nACK, PeriphClk
2
I
nWait
PE
BUSY, PeriphAck
2
I
PEerror, nAckReverse
2
I
SLCT
nAFD
nERR
nINIT
nSLIN
Select
nDStrb
nError
nInit
SLCT, Xflag
2
O
I
nAFD, HostAck
1
2
nFault , nPeriphRequest
1
2
O
O
nINIT , nReverseRqst
1
2
nAStrb
nSLIN , ECPMode
Notes:
n<name > : Active Low
1. Compatible Mode
2. High Speed Mode
3. For more information, refer to the IEEE 1284 standard.
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PARALLEL PORT CONNECTOR AND PIN DEFINITIONS
TABLE 5-1-2
HOST
CONNECTOR
PIN NUMBER OF
W83977TF
PIN
ATTRIBUTE
SPP
PIN
ATTRIBUTE
EXT2FDD
PIN
ATTRIBUTE
EXTFDD
1
2
36
31
O
nSTB
PD0
---
I
---
---
I
---
I/O
INDEX2
TRAK02
WP2
INDEX2
TRAK02
WP2
3
4
5
6
30
29
28
27
I/O
I/O
I/O
I/O
PD1
PD2
PD3
PD4
I
I
I
I
I
I
I
I
RDATA2
RDATA2
DSKCHG2
---
DSKCHG2
---
7
8
26
24
I/O
I/O
PD5
PD6
---
---
---
OD
---
---
MOA2
DSA2
DSB2
MOB2
WD2
9
23
22
21
19
18
35
34
33
32
I/O
I
PD7
nACK
BUSY
PE
OD
OD
OD
OD
OD
OD
OD
OD
OD
---
10
11
12
13
14
15
16
17
OD
OD
OD
OD
OD
OD
OD
OD
DSB2
MOB2
WD2
I
I
I
SLCT
nAFD
nERR
nINIT
nSLIN
WE2
WE2
O
I
RWC2
HEAD2
DIR2
RWC2
HEAD2
DIR2
O
O
STEP2
STEP2
5.2 Enhanced Parallel Port (EPP)
TABLE 5-2
PRINTER MODE AND EPP REGISTER ADDRESS
A2
A1
0
A0
0
REGISTER
NOTE
0
Data port (R/W)
1
1
1
1
2
2
2
2
2
0
0
1
Printer status buffer (Read)
Printer control latch (Write)
Printer control swapper (Read)
EPP address port (R/W)
EPP data port 0 (R/W)
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
EPP data port 1 (R/W)
1
1
1
0
EPP data port 2 (R/W)
1
1
EPP data port 2 (R/W)
Notes:
1. These registers are available in all modes.
2. These registers are available only in EPP mode.
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PRELIMINARY
5.2.1 Data Swapper
The system microprocessor can read the contents of the printer's data latch by reading the data
swapper.
5.2.2 Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the printer status
buffer. The bit definitions are as follows:
7
6
5
4
3
2
1
1
1
0
TMOUT
ERROR
SLCT
PE
ACK
BUSY
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print
head is changing position, or during an error state. When this signal is active, the printer is
busy and cannot accept data.
Bit 6: This bit represents the current state of the printer's ACK signal. A 0 means the printer has
received a character and is ready to accept another. Normally, this signal will be active for
BUSY
approximately 5 microseconds before
stops.
Bit 5: Logical 1 means the printer has detected the end of paper.
Bit 4: Logical 1 means the printer is selected.
Bit 3: Logical 0 means the printer has encountered an error condition.
Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.
m
Bit 0: This bit is valid in EPP mode only. It indicates that a 10 S time-out has occurred on the EPP
bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error
has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0
has no effect.
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PRELIMINARY
5.2.3 Printer Control Latch and Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the printer
control swapper. Bit definitions are as follows:
7
1
6
1
5
4
3
2
1
0
STROBE
AUTO FD
INIT
SLCT IN
IRQ ENABLE
DIR
Bit 7, 6: These two bits are a logic one during a read. They can be written.
Bit 5: Direction control bit
When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the
parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit
is invalid and fixed at zero.
ACK
Bit 4: A 1 in this position allows an interrupt to occur when
Bit 3: A 1 in this bit position selects the printer.
changes from low to high.
Bit 2: A 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A 1 causes the printer to line-feed after a line is printed.
Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microseconds before and after the strobe pulse.
5.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
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The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
IOW
c
operation. The leading edge of
auses an EPP address write cycle to be performed, and the
IOW
trailing edge of
latches the data for the duration of the EPP write cycle.
IOR
PD0-PD7 ports are read during a read operation. The leading edge of
read cycle to be performed and the data to be output to the host CPU.
causes an EPP address
5.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-
IOW
inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of
causes
IOW
an EPP data write cycle to be performed, and the trailing edge of
duration of the EPP write cycle.
latches the data for the
IOR
During a read operation, ports PD0-PD7 are read, and the leading edge of
cycle to be performed and the data to be output to the host CPU.
causes an EPP read
5.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
3
2
1
0
Data Port (R/W)
PD7
PD6
PD
5
PD4
PD3
PD2
PD1
PD0
Status Buffer (Read)
PE
SLCT
1
1
TMOUT
BUSY
ACK
1
ERROR
SLIN
Control Swapper (Read)
Control Latch (Write)
1
1
1
IRQEN
IRQ
INIT
AUTOFD
STROBE
1
DIR
SLIN
INIT
PD2
AUTOFD
PD1
STROBE
PD0
EPP Address Port R/W)
PD7
PD6
PD
5
PD4
PD3
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
PD7
PD7
PD6
PD6
PD
5
PD4
PD4
PD3
PD3
PD2
PD2
PD1
PD1
PD0
PD0
PD
5
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EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
PD7
PD7
PD6
PD6
PD
5
PD4
PD4
PD3
PD3
PD2
PD2
PD1
PD1
PD0
PD0
PD
5
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5.2.7 EPP Pin Descriptions
EPP NAME
nWrite
TYPE
EPP DESCRIPTION
Denotes an address or data read or write operation.
Bi-directional EPP address and data bus.
O
I/O
I
PD<0:7>
Intr
Used by peripheral device to interrupt the host.
nWait
I
Inactive to acknowledge that data transfer is completed. Active to
indicate that the device is ready for the next transfer.
PE
I
I
Paper end; same as SPP mode.
Select
nDStrb
nError
nInits
Printer selected status; same as SPP mode.
This signal is active low. It denotes a data read or write operation.
Error; same as SPP mode.
O
I
O
This signal is active low. When it is active, the EPP device is reset to its
initial operating mode.
nAStrb
O
This signal is active low. It denotes an address read or write operation.
5.2.8 EPP Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or
address cycle is currently being executed. In this condition all output signals are set by the SPP
Control Port and the direction is controlled by DIR of the Control Port.
m
S
A watchdog timer is required to prevent system lockup. The timer indicates that more than 10
have elapsed from the start of the EPP cycle to the time WAIT is deasserted. The current EPP cycle
is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0.
5.2.8.1 EPP Operation
The EPP operates on a two-phase cycle. First, the host selects the register within the device for
subsequent operations. Second, the host performs a series of read and/or write byte operations to the
selected register. Four operations are supported on the EPP: Address Write, Data Write, Address
Read, and Data Read. All operations on the EPP device are performed asynchronously.
5.2.8.2 EPP Version 1.9 Operation
The EPP read/write operation can be completed under the following conditions:
a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or
write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds
normally and will be completed when nWait goes inactive high.
b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to
active low, at which time it will start as described above.
5.2.8.3 EPP Version 1.7 Operation
The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the
read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive
high.
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PRELIMINARY
5.3 Extended Capabilities Parallel (ECP) Port
This
port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel
that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host)
directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for
the standard parallel port to improve compatibility mode transfer speed.
The ECP port supports run-length-encoded (RLE) decompression (required) in hardware.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates
how many times the next byte is to be repeated. Hardware support for compression is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and
ISA Interface Standard.
5.3.1 ECP Register and Mode Definitions
NAME
data
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
R/W
R/W
R
ECP MODES
FUNCTION
Data Register
000-001
011
All
ecpAFifo
dsr
ECP FIFO (Address)
Status Register
dcr
R/W
R/W
R/W
R/W
R
All
Control Register
cFifo
ecpDFifo
tFifo
010
011
110
111
111
All
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
cnfgA
cnfgB
ecr
Configuration Register A
Configuration Register B
Extended Control Register
R/W
R/W
Note: The base addresses are specified by CR60 and 61, which are determined by configuration register or hardware setting.
MODE
000
001
010
011
100
101
110
111
DESCRIPTION
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
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Revision 0.62
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PRELIMINARY
5.3.2 Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input. The contents of this register are output to the PD0-PD7 ports. During a read operation,
ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this
register is defined only for the forward direction. The bit definitions are as follows:
7
6
5
4
3
2
1
0
Address or RLE
Address/RLE
5.3.3 Device Status Register (DSR)
These bits are at low level during a read of the Printer Status Register. The bits of this status register
are defined as follows:
7
6
5
4
3
2
1
0
1
1
1
nFault
Select
PError
nAck
nBusy
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Bit 7: This bit reflects the complement of the Busy input.
Bit 6: This bit reflects the nAck input.
Bit 5: This bit reflects the PError input.
Bit 4: This bit reflects the Select input.
Bit 3: This bit reflects the nFault input.
Bit 2-0: These three bits are not implemented and are always logic one during a read.
5.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7
6
5
4
3
2
1
0
1
1
strobe
autofd
nInit
SelectIn
ackIntEn
Direction
Bit 6, 7: These two bits are logic one during a read and cannot be written.
Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is
valid in all other modes.
0
1
the parallel port is in output mode.
the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt
ACK
requests from the parallel port to the CPU due to a low to high transition on the
input.
SLIN
Bit 3: This bit is inverted and output to the
output.
0
1
The printer is not selected.
The printer is selected.
INIT
Bit 2: This bit is output to the
output.
AFD
STB
Bit 1: This bit is inverted and output to the
Bit 0: This bit is inverted and output to the
output.
output.
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5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this
FIFO. Transfers to the FIFO are byte aligned.
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware
handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to
the system.
5.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data
in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be
displayed on the parallel port data lines.
5.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read-only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
5.3.9 cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows:
7
6
5
4
3
2
1
1
0
1
1
IRQx 0
IRQx 1
IRQx 2
intrValue
compress
Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support
hardware RLE compression.
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
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PRELIMINARY
Bit 5-3: Reflect the IRQ resource assigned for ECP port.
cnfgB[5:3]
000
IRQ resource
reflect other IRQ resources selected by PnP register (default)
001
IRQ7
010
IRQ9
011
100
101
110
IRQ10
IRQ11
IRQ14
IRQ15
IRQ5
111
.
Bit 2-0: These five bits are at high level during a read and can be written
5.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7
6
5
4
3
2
1
0
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Bit 7-5: These bits are read/write and select the mode.
000
001
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be
used to tri-state the data lines and reading the data register returns the value on the
data lines and not the value in the data register.
010
011
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
auto transmitted to the peripheral using ECP Protocol. When the direction is 1
(reverse direction), bytes are moved from the ECP parallel port and packed into
bytes in the ecpDFifo.
100
101
110
Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
111
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
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Bit 4: Read/Write (Valid only in ECP Mode)
1
0
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
0
Enables DMA.
Disables DMA unconditionally.
Bit 2: Read/Write
1
0
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr
Threshold or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr
Threshold or more valid bytes to be read from the FIFO.
Bit 1: Read only
0
1
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
1
The FIFO contains at least 1 byte of data.
The FIFO is completely empty.
5.3.11 Bit Map of ECP Port Registers
D7
PD7
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
D0
PD0
NOTE
data
Addr/RLE
nBusy
1
Address or RLE field
2
1
1
2
2
2
ecpAFifo
dsr
nAck
1
PError
Select
nFault
1
1
1
Directio
ackIntEn
SelectIn
nInit
autofd
strobe
dcr
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
cFifo
ecpDFifo
tFifo
0
0
0
1
1
1
0
1
0
1
0
1
0
1
cnfgA
cnfgB
ecr
compress
intrValue
MODE
nErrIntrEn
dmaEn
serviceIntr
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
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5.3.12
ECP Pin Descriptions
NAME TYPE DESCRIPTION
nStrobe (HostClk)
O
The nStrobe registers data or address into the slave on the
asserting edge during write operations. This signal handshakes
with Busy.
PD<7:0>
I/O
I
These signals contains address or data or RLE data.
nAck (PeriphClk)
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
Busy (PeriphAck)
I
This signal deasserts to indicate that the peripheral can accept
data. It indicates whether the data lines contain ECP command
information or data in the reverse direction. When in reverse
direction, normal data are transferred when Busy (PeriphAck)
is high and an 8-bit command is transferred when it is low.
PError (nAckReverse)
I
This signal is used to acknowledge a change in the direction of
the transfer (asserted = forward). The peripheral drives this
signal low to acknowledge nReverseRequest. The host relies
upon nAckReverse to determine when it is permitted to drive
the data bus.
Select (Xflag)
I
Indicates printer on line.
nAutoFd (HostAck)
O
Requests a byte of data from the peripheral when it is asserted.
This signal indicates whether the data lines contain ECP
address or data in the forward direction. When in forward
direction, normal data are transferred when nAutoFd (HostAck)
is high and an 8-bit command is transferred when it is low.
nFault (nPeriphRequest)
I
Generates an error interrupt when it is asserted. This signal is
valid only in the forward direction. The peripheral is permitted
(but not required) to drive this pin low to request a reverse
transfer during ECP Mode.
nInit (nReverseRequest)
nSelectIn (ECPMode)
O
O
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the
channel in the reverse direction.
This signal is always deasserted in ECP mode.
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5.3.13
ECP Operation
The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol
before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The
following are required:
(a) Set direction = 0, enabling the drivers.
(b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
(c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
(d) Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo,
respectively.
5.3.13.1 Mode Switching
Software will execute P1284 negotiation and all operations prior to a data transfer phase under
programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake,
moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001
it can only be switched into mode 000 or 001. The direction can be changed only in mode 001.
When in extended forward mode, the software should wait for the FIFO to be empty before switching
back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the
FIFO before changing back to mode 000 or 001.
5.3.13.2 Command/Data
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction,
normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck
is low. The most significant bits of the command indicate whether it is a run-length count (for
compression) or a channel address.
In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
5.3.13.3 Data Compression
The W83977TF supports run length encoded (RLE) decompression in hardware and can transfer
compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported.
In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data
byte is written to the ecpDFifo.
5.3.14 FIFO Operation
The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO
is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO
is disabled.
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5.3.15
DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC
DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the
DMA.
5.3.16 Programmed I/O (NON-DMA) Mode
The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo
located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and
serviceIntr = 0 in the programmed I/O transfers.
The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The
programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
5.4 Extension FDD Mode (EXTFDD)
In this mode, the W83977TF changes the printer interface pins to FDC input/output pins, allowing the
user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin
assignments for the FDC input/output pins are shown in Table 5-1.
After the printer interface is set to EXTFDD mode, the following occur:
MOB
DSB
(1) Pins
(2) Pins
and
will be forced to inactive state.
DSKCHG RDATA WP TRAK0 INDEX
,
,
,
,
will be logically ORed with pins PD4-PD0 to serve
as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
5.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83977TF changes the printer interface pins to FDC input/output pins, allowing the
user to install two external floppy disk drives through the DB-25 printer connector to replace internal
floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table5-1.
After the printer interface is set to EXTFDD mode, the following occur:
MOA DSA MOB
DSB
(1) Pins
,
,
, and
will be forced to inactive state.
INDEX
will be logically ORed with pins PD4-PD0 to
DSKCHG RDATA WP TRAK0
(2) Pins
,
,
,
, and
serve as input signals to the FDC.
(3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for
FDD open drain/collector output.
(4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating
system, a warm reset is needed to enable the system to recognize the extension floppy drive.
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PRELIMINARY
6. KEYBOARD CONTROLLER
The KBC (8042 with licensed KB BIOS) circuit of W83977TF is designed to provide the functions
needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBMÒ-
compatible personal computers or PS/2-based systems. The controller receives serial data from the
keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte
of data in its output buffer. Then, the controller will assert an interrupt to the system when data are
placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data
transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge
is received for the previous data byte.
P24
P25
P21
P20
KIRQ
MIRQ
GATEA20
KBRST
KINH
P17
KDAT
KCLK
P27
P10
P26
8042
T0
GP I/O PINS
Multiplex I/O PINS
MCLK
MDAT
P23
T1
P12~P16
P22
P11
Keyboard and Mouse Interface
6.1 Output Buffer
The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O
address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan
code received from the keyboard and data bytes required by commands to the system. The output
buffer can only be read when the output buffer full bit in the register is "1".
6.2 Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable
I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag
to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written
to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte)
through the controller's input buffer only if the input buffer full bit in the status register is 0 .
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6.3 Status Register
The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O
address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller
and interface. It may be read at any time.
BIT
0
BIT FUNCTION
DESCRIPTION
0: Output buffer empty
Output Buffer Full
1: Output buffer full
1
2
Input Buffer Full
System Flag
0: Input buffer empty
1: Input buffer full
This bit may be set to 0 or 1 by writing to the system flag
bit in the command byte of the keyboard controller. It
defaults to 0 after a power-on reset.
3
4
5
6
7
Command/Data
Inhibit Switch
0: Data byte
1: Command byte
0: Keyboard is inhibited
1: Keyboard is not inhibited
Auxiliary Device Output 0: Auxiliary device output buffer empty
Buffer
1: Auxiliary device output buffer full
General Purpose Time-
out
0: No time-out error
1: Time-out error
Parity Error
0: Odd parity
1: Even parity (error)
6.4 Commands
COMMAND
20h
FUNCTION
Read Command Byte of Keyboard Controller
Write Command Byte of Keyboard Controller
60h
BIT
BIT DEFINITION
Reserved
7
6
IBM Keyboard Translate Mode
Disable Auxiliary Device
Disable Keyboard
5
4
3
2
1
Reserve
System Flag
Enable Auxiliary Interrupt
Enable Keyboard Interrupt
0
A4h
Test Password
Returns 0Fah if Password is loaded
Returns 0F1h if Password is not loaded
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6.4 Commands, continued
COMMAND
A5h
FUNCTION
Load Password
Load Password until a "0" is received from the system
Enable Password
A6h
Enable the checking of keystrokes for a match with the password
Disable Auxiliary Device Interface
Enable Auxiliary Device Interface
Interface Test
A7h
A8h
A9h
BIT
BIT DEFINITION
No Error Detected
00
01
Auxiliary Device "Clock" line is stuck low
Auxiliary Device "Clock" line is stuck high
Auxiliary Device "Data" line is stuck low
02
03
04
Auxiliary Device "Data" line is stuck low
AAh
ABh
Self-test
Returns 055h if self test succeeds
Interface Test
BIT DEFINITION
BIT
00
No Error Detected
01
Keyboard "Clock" line is stuck low
02
03
04
Keyboard "Clock" line is stuck high
Keyboard "Data" line is stuck low
Keyboard "Data" line is stuck high
ADh
AEh
C0h
C1h
C2h
D0h
D1h
D2h
D3h
D4h
E0h
FXh
Disable Keyboard Interface
Enable Keyboard Interface
Read Input Port(P1) and send data to the system
Continuously puts the lower four bits of Port1 into STATUS register
Continuously puts the upper four bits of Port1 into STATUS register
Send Port2 value to the system
Only set/reset GateA20 line based on the system data bit 1
Send data back to the system as if it came from Keyboard
Send data back to the system as if it came from Auxiliary Device
Output next received byte of data from system to Auxiliary Device
Reports the status of the test inputs
m
Pulse only RC(the reset line) low for 6 S if Command byte is even
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6.5 Hardware GATEA20/Keyboard Reset Control Logic
The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control
logic is controlled by LD5-CRF0 as follows:
6.5.1 KB Control Register (Logic Device 5, CR-F0)
BIT
7
6
5
4
3
2
1
0
NAME
KCLKS1 KCLKS0 Reserved Reserved Reserved P92EN
HGA20 HKBRST
KCLKS1, KCLKS0
This 2 bits are for the KBC clock rate selection.
= 0 0 KBC clock input is 6 Mhz
= 0 1 KBC clock input is 8 Mhz
= 1 0 KBC clock input is 12 Mhz
= 1 1 KBC clock input is 16 Mhz
P92EN
(Port 92 Enable)
A "1" on this bit enables Port 92 to control GATEA20 and KBRESET.
A "0" on this bit disables Port 92 functions.
HGA20
(Hardware GATE A20)
A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal.
A "0" on this bit disables hardware GATEA20 control logic function.
HKBRST
(Hardware Keyboard Reset)
A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal.
A "0" on this bit disables hardware KB RESET control logic function.
When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears
GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears
KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the
m
m
KBRESET is pulse low for 6 S(Min.) with 14 S(Min.) delay.
GATEA20 and KBRESET are controlled by either the software control or the hardware control logic
and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92
when P92EN bit is set.
6.5.2 Port 92 Control Register (Default Value = 0x24)
BIT
7
6
5
4
3
2
1
0
NAME
Res. (0) Res. (0)
Res. (1) Res. (0)
Res. (0)
Res. (1)
SGA20 PLKBRST
SGA20
(Special GATE A20 Control)
A "1" on this bit drives GATE A20 signal to high.
A "0" on this bit drives GATE A20 signal to low.
PLKBRST
(Pull-Low KBRESET)
m
m
A "1" on this bit causes KBRESET to drive low for 6 S(Min.) with 14 S(Min.) delay. Before issuing
another keyboard reset command, the bit must be cleared.
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6.6 OnNow / Security Keyboard and Mouse Wake-Up
---- Programmable Keyboard / Mouse Wake-Up Functions
Winbond's unique programmable keyboard/ mouse wake-up functions provide the system diversified
methods for either OnNow wake-up application, or security control application. The keyboard or
mouse can wake up the system by producing a panel switch low pulse on PANSWOUT pin, and connect
it to chipset (for example IntelTM chipset TX, LX PIIX4) panel switch input. The wake-up conditions
can be programmed as pre-determined or any keys/buttons. To implement this function, a
32.768KHz crystal must be installed between XTAL1 and XTAL2, or a 32.768KHz clock to be
SB
SB
connected to XTAL1 and leave XTAL2 open. The V pin must be connected to +5V V of ATX
BAT
power supply, and an external battery should be installed on V
pin to store the data (the
passwords and wake-up status which had been set already) when power fails.
6.6.1 Keyboard Wake-Up Function
The keyboard wake-up function is enable by setting LD-0A CR-E0 bit 6. The pre-determined keys
data are stored in registers, and they can be access by an indirection method. At first, write their
index address to LD-0A CR-E1, then access them by reading/writing LD-0A CR-E2. A zero data is
written to the register means the comparison of this register will be ignored. The pre-programmed
keys may be 1 to 5 keys with various combinations. If LD-0A CR-E0 bit 0 is set, the system will be
waken up after any key struck.
6.6.2 Keyboard Password Wake-Up Function
To implement this function, the bit 7 of LD-0A CR-E0 must be set, and panel switch input is
connected to
pin. Thus
is blocked to PANSWOUT , by setting LD-0A CR-E0 properly
PANSWIN
PANSWIN
and make only keyboard can wake up the system with preset keys (password).
6.6.3 Mouse Wake-Up Function
The mouse wake-up function is activated by setting bit 5 of LD-0A CR-E0. If bit 1 of LD-0A CR-E0 is
set, any movement or button clicking will make up the system. Otherwise, the mouse can wake up
the system only by clicking its button twice successively with the mouse unmoved. The bit 4 of LD-
0A CR-E0 determines which button (left or right) to perform wake-up function.
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PRELIMINARY
7. GENERAL PURPOSE I/O
W83977TF provides 23 Input/Output ports that can be individually configured to perform a simple
basic I/O function or a pre-defined alternate function. Those 23 GP I/O ports are divided into three
groups, the first group contains 8 ports, the second group contains only 7 ports, and the third group
contains 8 ports. Each port in first group corresponds to a configuration register in logical device 7,
the second group in logical device 8, and the third group in logical device 9. Users can select those
I/O ports functions by independently programming those configuration registers. Figure 7.1, 7.2, and
7.3 respectively show the GP I/O port's structure of logical device 7, 8, and 9. Right after Power-on
reset, those ports default to perform basic I/O functions.
Figure 7.1
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Figure 7.2
Figure 7.3
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7.1 Basic I/O functions
The Basic I/O functions of W83977TF provide several I/O operations including driving a logic value to
output port, latching a logic value from input port, inverting the input/output logic value, and steering
Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the
ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects
to a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There are three 8-bit
registers (GP1, GP2, and GP3) which are directly connected to those GP I/O ports. Each GP I/O port
is represented as a bit in one of three 8-bit registers. Only 6 bits of GP2 are implemented. Table
7.1.1 shows their combinations of Basic I/O functions, and Table 7.1.2 shows the register bit
assignments of GP1, GP2, and GP3.
Table 7.1.1
I/O BIT
ENABLE INT BIT
POLARITY BIT
BASIC I/O OPERATIONS
0 = OUTPUT
0 = DISABLE
0 = NON INVERT
1 = INPUT
1 = ENABLE
1 = INVERT
0
0
0
0
0
1
0
1
0
Basic non-inverting output
Basic inverting output
Non-inverted output bit value of GP2
drive to Common Interrupt
0
1
1
Inverted output bit value of GP2 drive
to Common Interrupt
1
1
1
0
0
1
0
1
0
Basic non-inverting input
Basic inverting input
Non-inverted input drive to Common
Interrupt
1
1
1
Inverted input drive to Common
Interrupt
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Table 7.1.2
GP I/O PORT ACCESSED
REGISTER
REGISTER BIT
ASSIGNMENT
GP I/O PORT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
GP26
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
GP1
GP2
GP3
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7.2 Alternate I/O Functions
W83977TF provides several alternate functions which are scattered among the GP I/O ports. Table
7.2.1 shows their assignments. Polarity bit can also be set to alter their polarity.
Table 7.2.1
GP I/O PORT
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
GP30
GP31
GP32
GP33
GP34
ALTERNATE FUNCTION
Interrupt Steering
Interrupt Steering
Watch Dog Timer Output/IRRX input
Power LED output/IRTX output
General Purpose Address Decoder/Keyboard Inhibit(P17)
General Purpose Write Strobe/ 8042 P12
Watch Dog Timer Output
Power LED output
Keyboard Reset (8042 P20)
8042 P13
8042 P14
8042 P15
8042 P16
GATE A20 (8042 P21)
Interrupt Steering
Interrupt Steering
General Purpose Address Decoder
General Purpose Address Decoder
Watch Dog Timer Output
7.2.1 Interrupt Steering
GP10, GP11, GP30, and GP31 can be programmed to map their own interrupt channels. The
selection of IRQ channel can be done in configuration registers CR70 and CR72 of logical device 7
and logical device 9. Each interrupt channel also has its own 1 ms debounce filter that is used to
reject any noise whose width is equal to or less than 1 ms.
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7.2.2 Watch Dog Timer Output
Watch Dog Timer contains a one minute resolution down counter, CRF2 of Logical Device 8, and two
watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down counter
can be programmed within the range from 1 to 255 minutes. Writing any new non-zero value to
CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains non-
zero value) will cause the Watch Dog Timer to reload and start to count down from the new value. As
the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of WDT_CTRL1 will be
set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable in CR72 of logical
device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is enabled.
WDT_CTRL1 also can be accessed through GP2 I/O base address + 1.
7.2.3 Power LED
The Power LED function provides 1 Hertz rate toggle pulse output with 50 percent duty cycle. Table
7.2.2 shows how to enable Power LED.
Table 7.2.2
WDT_CTRL1 BIT[1]
WDT_CTRL0 BIT[3]
WDT_CTRL1 BIT[0]
POWER LED STATE
1 Hertz Toggle pulse
Continuous high or low *
Continuous high or low *
1 Hertz Toggle pulse
1
0
0
0
X
0
1
1
X
X
0
1
* Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configuration registers.
7.2.4 General Purpose Address Decoder
General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The
address base is stored at CR62, CR63 of logical device 7 for GP14 and at CR62-65 of logical device
9 for GP32 and GP33. The decoding output is normally active low. Users can alter its polarity
through the polarity bit of the GP14, GP32, and GP33's configuration register.
7.2.5 General Purpose Write Strobe
General Purpose Write Strobe is an address decoder that performs like General Purpose Address
IOW
Decoder, but it has to be qualified by
and AEN. Its output is normally active low. Users can
alter its polarity through the polarity bit of the GP15's configuration register.
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8. PLUG AND PLAY CONFIGURATION
The W83977TF uses Compatible PNP protocol to access configuration registers for setting up
different types of configurations. In W83977TF, there are nine Logical Devices (from Logical Device
0 to Logical Device A with the exception of logical device 4 and 6 for compatibility) which correspond
to nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2),
UART2 (logical device 3), KBC (logical device 5), GPIO1 (logical device 7), GPIO2 (logical device 8),
GPIO3 (logical device 9), and ACPI ((logical device A). Each Logical Device has its own
configuration registers (above CR30). Host can access those registers by writing an appropriate
logical device number into logical device select register at CR7.
8.1 Compatible PnP
8.1.1 Extended Function Registers
In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration
registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the
Extended Function mode as follows:
HEFRAS
address and value
write 87h to the location 3F0h twice
write 87h to the location 370h twice
0
1
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RTSA
After Power-on reset, the value on
(pin 43) is latched by HEFRAS of CR26. In Compatible
PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port
address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended
Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable
Register) to identify which configuration register is to be accessed. The designer can then access the
desired configuration register through the Extended Functions Data Register (I/O port address 3F1h
or 371h).
After programming of the configuration register is finished, an additional value (AAh) should be
written to EFERs to exit the Extended Function mode to prevent unintentional access to those
configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the
configuration registers against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
8.1.2 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83977TF enters the default operating mode. Before the W83977TF
enters the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are
3F0h or 370h (as described in previous section).
8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as
described in section 8.1.1) on PC/AT systems; the EFDRs are read/write registers with port address
3F1h or 371h (as described in section 8.1.1) on PC/AT systems.
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9. ACPI REGISTERS FEATURES
W83977TF supports both ACPI and legacy power managements. The switch logic of the power
SMI SCI
managment block generates an
mode. For the legacy mode, the SMI_EN bit is used. If it is set, it routes the power management
SMI
interrupt in the legacy mode and an
interrupt in the ACPI
events to the
interrupt logic. For the ACPI mode, the SCI_EN bit is used. If it is set, it route the
SCI
power management events to the
interrupt logic. The SMI_EN bit is located in the configuration
register block of Device A and the SCI_EN bit is located in the PM1 register block. See the following
figure for illustration.
SMI_EN
IRQs
from SCI to SMI
SMI Logic
SMI output
SMI
Logic
0
IRQs
PM Timer
1
SCI output
Logic
SCI
SCI_EN
from SMI to SCI
Bus Master SCI
SCI Logic
WAK_STS
IRQs
Sleep/Wake
State machine
Clock
Control
Device Idle
Timers
Device Trap
Global STBY
Timer
SMI
SMI
SMI
, which is dedicated for the interrupt output. Another way
The
interrupt is routed to pin
SMI
to output the
interrupt is to route to pin IRQSER, which is the signal pin in the Serial IRQ mode.
SCI
SCI
SCI
, which is dedicated for the function. Or it can be
The
interrupt can be routed to pin
routed to one interrupt request pin, which is selected through CR70.bit3 - 0 of logical device 9.
SCI
Another way is to output the
interrupt to pin IRQSER if serial IRQ mode is enabled.
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9.1 SMI to SCI/SCI to SMI and Bus Master
SMI
SCI
SCI
or from to
The following figure illustrates the process of generating an interrupt from
to
SMI
.
clear
set
GBL_STS
from SMI to SCI
BIOS_RLS
To SCI Logic
GBL_EN
clear
set
BIOS_STS
from SCI to SMI
GBL_RLS
BIOS_EN
To SMI Logic
clear
set
BM_STS
BUS Master SCI
BM_CNTPL
BM_RLD
To SCI Logic
: Status bit
: Enable bit
For the BIOS software to raise an event to the ACPI software, BIOS_RLS, GBL_EN, and GBL_STS
bits are involved. GBL_EN is the enable bit and the GBL_STS is the status bit. Both are controlled
by the ACPI software. If BIOS_RLS is set by the BIOS software and GBL_EN is set by the ACPI
SCI
software, an
interrupt is raised. Writing a 1 to BIOS_RLS sets it to logic 1 and also sets
GBL_STS to logic 1. Writing a 0 to BIOS_RLS has no effect. Wrinting a 1 to GBL_STS clears it to
logic 0 and also clears BIOS_RLS to logic 0. Writing a 0 to GBL_STS has no effect.
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For the ACPI software to raise an event to the BIOS software, GBL_RLS, BIOS_EN, and BIOS_STS
bits are involved. BIOS_EN is the enable bit and the BIOS_STS is the status bit. Both are controlled
by the BIOS software. If GBL_RLS is set by the ACPI software and BIOS_EN is set by the BIOS
SMI
software, an
is raised. Writing a 1 to GBL_RLS sets it to logic 1 and also sets BIOS_STS to
logic 1. Writing a 0 to GBL_RLS has no effect. Wrinting a 1 to BIOS_STS clears it to logic 0 and
also clears GBL_RLS to logic 0. Writing a 0 to BIOS_STS has no effect.
For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits
are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set
SCI
by the BIOS software and BM_RLD is set by the ACPI software, an
interrupt is raised. Writing a
1 to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1. Writing a 0 to BM_CNTRL has no
effect. Wrinting a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0. Writing a 0
to BM_STS has no effect.
9.2 Power Management Timer
In the ACPI specification, it requires a power management timer. The power management timer is a
24-bit fixed rate free running up-count timer that runs off a 3.579545MHZ clock. The power
management timer corresponds to status bit (TMR_STS) and enable bit (TMR_EN). The TMR_STS
bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the TMR_EN bit
SCI
is set, the setting of the TMR_STS bit will generate an
interrupt. Three registers are used to
read the timer value which are located in the PM1 register block. The power management timer has
one enabel bit (TMR_ON) to turn ii on or off. The TMR_ON is located in GPE register block. If it is
cleared to 0, the power management timer function would not work. There are no timer reset
requirements, except that the timer should function after power-up. See the following figure for
illustration.
TMR_STS
TMR_EN
TMR_ON
24 bit
counter
To SCI Logic
Bits (23-0)
3.579545 MHz
24
TMR_VAL
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9.3 ACPI Registers (ACPIRs)
The ACPI register model consists of the fixed register blocks that perform the ACPI functuions. A
register block may be a event register block which deals with ACPI events or a control register block
which deals with control features. The order in the event register block is a status register followed by
an enable register.
Each event register, if implemented, contains two two register: a status register and an enable
register, of 16 bits wide each. The status register indicates which event triggers the ACPI System
SCI
Control Interrupt (
However, the corresponding enable bit is also required to be set before an
raised. If the enable bit is not set, the software can examine the state of the hardware event by
SCI
). When the hardware event occurs, the corresponding status bit will be set.
SCI
interrupt could be
reading the status bit without generating an
interrupt.
Any status bit, unless otherwise noted, can only be set by specific hardware event. It is cleared by
writing a 1 to its bit position and writing a 0 has no effect. Except some special status bits, every
status bit has the corresponding enable bit on the same bit position in the enable register. Those
status bits which have no corresponding enable bit are read for special purpose. Reverved or
unimplemented enable bits always return zero, and writing to these bits should has no effect.
The control bit in the control register provides some special control function over the hardware event,
SCI
or some special control over
event. Reserved or unimplemented control bits always return zero,
and writing to those bits should has no effect.
Table 9-1 (sec. 9.3.21) lists the PM1 register block and its registers. The base address of PM1
register block is named as PM1a_EVT_BLK in the ACPI specification and is specified in CR60, 61 of
logical device A.
Table 9-2 (sec. 9.3.21) lists the GPE register block and its registers. The base address of general-
purpose event block GPE0 is named as GPE0_BLK in the ACPI specification and is specified in
CR62, 63 of logical device A. The base address of general-purpose event block GPE1 is named as
GPE1_BLK in the ACPI specification and is specified in CR64, 65 of logical device A.
9.3.1 Power Management 1 Status Register 1 (PM1STS1)
Register Location:
Default Value:
Attribute:
<CR60, 61> System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
TMR_STS
Reserved
Reserved
Reserved
BM_STS
GBL_STS
Reserved
Reserved
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Bit
Name
Description
0
TMR_STS
This bit is the timer carry status bit. This bit is set anytime the bit 23 of the
24-bit counter changes (whenever the MSB changes from low to high or high
to low). When TMR_EN and TMR_STS are set, a power magement event is
raised. This bit is only set by hardware and can only be cleared by writing a
1 to this bit position. Writing a 0 has no effect.
1-3
4
Reserved
BM_STS
Reserved.
This is the bus master status bit. Writing a 1 to BM_CNTRL also sets
BM_STS. Writing a 1 clears this bit and also clears BM_CNTRL. Writing a
0 has no effect.
5
GBL_STS
Reserved
This is the global status bit. This bit is set when the BIOS wants the
SCI
attention of the
handler. BIOS sets this bit by setting BIOS_RLS and
can only be cleared by writing a 1 to this bit position. Writing a 1 to this bit
position also clears BIOS_RLS. Writing a 0 has no effect.
6-7
Reserved. These bits always return zeros.
9.3.2 Power Management 1 Status Register 2 (PM1STS2)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 1H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WAK_STS
Bit
0-6
7
Name
Reserved
WAK_STS
Description
Reserved.
This bit is set when the system is in the sleeping state and an enabled resume
event occurs. Upon setting this bit, the sleeping/working state machine will
transition the system to the working state. This bit is only set by hardware and
is cleared by writing a 1 to this bit position or by the sleeping/working state
machine automatically when the global standby timer expires. Writing a 0 has
no effect. When the WAK_STS is cleared and all devices are in sleeping
state, the whole chip enters the sleeping state.
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9.3.3 Power Management 1 Enable Register 1(PM1EN1)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 2H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
TMR_EN
Reserved
Reserved
Reserved
GBL_EN
Reserved
Reserved
Reserved
Bit
Name
Description
0
TMR_EN
SCI
This is the timer carry interrupt enable bit. When this bit is set then an
event is generated whenever the TMR_STS bit is set. When this bit is reset
then no interrupt is generated even when the TMR_STS bit is set.
1-4
5
Reserved
GBL_EN
Reserved. These bits always return a value of zero.
The global enable bit. When both the GBL_EN bit and the GBL_STS bit are
SCI
set, an
interrupt is raised.
6-7
Reserved
Reserved.
9.3.4 Power Management 1 Enable Register 2 (PM1EN2)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 3H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0-7
Reserved
Reserved. These bits always return zeros.
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9.3.5 Power Management 1 Control Register 1 (PM1CTL1)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 4H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
SCI_EN
BM_RLD
GBL_RLD
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0
SCI_EN
SCI
SMI
or an
Select whether the power management event triggers an
interrupt. When this bit is set, then the power management events will
SCI
generate an
the power management events will generate an
This is the bus master reload enable bit. If this bit is set and BM_CNTRL is
SCI
interrupt. When this bit is reset and SMI_EN bit is set, then
SMI
interrupt.
1
2
BM_RLD
set, an
interrupt is raised.
GBL_RLS
The global release bit. This bit is used by the ACPI software to raise an event
to the BIOS software. The BIOS software has a corresponding enable and
status bit to control its ability to receive the ACPI event. Setting GBL_RLS
SMI
sets BIOS_STS, and it generates an
interrupt if BIOS_EN is also set.
3-7
Reserved
Reserved. These bits always return zeros.
9.3.6 Power Management 1 Control Register 2 (PM1CTL2)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 5H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0-7
Reserved
Reserved. These bits always return zeros.
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9.3.7 Power Management 1 Control Register 3 (PM1CTL3)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 6H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0-7
Reserved
Reserved. These bits always return zeros.
9.3.8 Power Management 1 Control Register 4 (PM1CTL4)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 7H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0-7
Reserved
Reserved. These bits always return zeros.
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9.3.9 Power Management 1 Timer 1 (PM1TMR1)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 8H System I/O Space
00h
Read only
Size:
8 bits
2
1
7
6
5
4
3
0
TMR_VAL0
TMR_VAL1
TMR_VAL2
TMR_VAL3
TMR_VAL4
TMR_VAL5
TMR_VAL6
TMR_VAL7
Bit
Name
Description
0-7
TMR_VAL
This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in
the working state. The timer is reset and then continues counting until the
CLKIN input the the chip is stopped. If the clock is restarted without a MR
reset, then the counter will resume counting from where it stopped. The
TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1
or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will
SCI
generate an
interrupt.
9.3.10 Power Management 1 Timer 2 (PM1TMR2)
Register Location:
Default Value:
Attribute:
<CR60, 61> + 9H System I/O Space
00h
Read only
Size:
8 bits
2
1
7
6
5
4
3
0
TMR_VAL8
TMR_VAL9
TMR_VAL10
TMR_VAL11
TMR_VAL12
TMR_VAL13
TMR_VAL14
TMR_VAL15
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Bit
0-7
Name
Description
TMR_VAL
This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in
the working state. The timer is reset and then continues counting until the
CLKIN input the the chip is stopped. If the clock is restarted without a MR
reset, then the counter will resume counting from where it stopped. The
TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1
or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will
SCI
generate an
interrupt.
9.3.11 Power Management 1 Timer 3 (PM1TMR3)
Register Location:
Default Value:
Attribute:
<CR60, 61> + AH System I/O Space
00h
Read only
Size:
8 bits
2
1
7
6
5
4
3
0
TMR_VAL16
TMR_VAL17
TMR_VAL18
TMR_VAL19
TMR_VAL20
TMR_VAL21
TMR_VAL22
TMR_VAL23
Bit
Name
Description
0-7
TMR_VAL
This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts in
the working state. The timer is reset and then continues counting until the
CLKIN input the the chip is stopped. If the clock is restarted without a MR
reset, then the counter will resume counting from where it stopped. The
TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1
or from 1 to 0. If the TMR_EN bit is set, the setting of the TMR_STS bit will
SCI
generate an
interrupt.
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9.3.12 Power Management 1 Timer 4 (PM1TMR4)
Register Location:
Default Value:
Attribute:
<CR60, 61> + BH System I/O Space
00h
Read only
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
Reserved. These bits always return zeros.
0-7
Reserved
9.3.13 General Purpose Event 0 Status Register 1 (GP0STS1)
Register Location:
Default Value:
Attribute:
<CR62, 63> System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
URBSCISTS
URASCISTS
FDCSCISTS
PRTSCISTS
KBCSCISTS
MOUSCISTS
Reserved
Reserved
SCI
These bits indicate the status of the
SCI
input, which is set when the device's IRQ is raised. If the
SCI
interrupt is
corresponding enable bit in the
interrupt enable register (in GP0EN1) is set, an
raised and routed to the output pin. Wrinting a 1 clears the bit, and wrinting a 0 has no effect. If the
SCI
SCI
interrupt will be raised.
bit is not cleared, new IRQ to the
logic input is ignored and no
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Bit
Name
Description
0
URBSCISTS
SCI
SCI
UART B
UART A
status, which is set by the UART B IRQ.
status, which is set by the UART A IRQ.
1
URASCISTS
FDCSCISTS
PRTSCISTS
KBCSCISTS
MOUSCISTS
Reserved
2
SCI
FDC
PRT
KBC
status, which is set by the FDC IRQ.
status, which is set by the printer port IRQ.
status, which is set by the KBC IRQ.
3
SCI
SCI
4
5
SCI
MOUSE
status, which is set by the MOUSE IRQ.
6-7
Reserved.
9.3.14 General Purpose Event 0 Status Register 2 (GP0STS2)
Register Location:
Default Value:
Attribute:
<CR62, 63> + 1H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0-7
Reserved
Reserved. These bits always return zeros.
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9.3.15 General Purpose Event 0 Enable Register 1 (GP0EN1)
Register Location:
Default Value:
Attribute:
<CR62, 63> + 2H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
URBSCIEN
URASCIEN
FDCSCIEN
PRTSCIEN
KBCSCIEN
MOUSCIEN
Reserved
Reserved
SCI
SCI
logic output for
These bits are used to enable the device's IRQ sources into the
the IRQs is as follows:
logic. The
SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN
and FDCSCISTS) or (PRTSCIEN and PRTSCISTS) or (KBCSCIEN and KBCSCISTS) or
(MOUSCIEN and MOUSCISTS)
Bit
Name
Description
0
URBSCIEN
SCI
SCI
UART B
UART A
enable, which controls the UART B IRQ.
enable, which controls the UART A IRQ.
1
URASCIEN
FDCSCIEN
PRTSCIEN
KBCSCIEN
MOUSCIEN
Reserved
2
SCI
FDC
enable, which controls the FDC IRQ.
SCI
3
printer port
enable, which controls the printer port IRQ.
4
SCI
KBC
enable, which controls the KBC IRQ.
5
SCI
MOUSE
enable, which controls the MOUSE IRQ.
6-7
Reserved.
9.3.16 General Purpose Event 0 Enable Register 2 (GP0EN2)
Register Location:
Default Value:
Attribute:
<CR62, 63> + 3H System I/O Space
00h
Read/write
Size:
8 bits
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2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return zeros.
Reserved
9.3.17 General Purpose Event 1 Status Register 1 (GP1STS1)
Register Location:
Default Value:
Attribute:
<CR64, 65> System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
BIOS_STS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0
BIOS_STS
The BIOS status bit. This bit is set when GBL_RLS is set. If BIOS_EN is set,
SMI
setting GBL_RLS will raise an
event. Writing a 1 to its bit location clears
BIOS_STS and also clears GBL_RLS. Writing a 0 has no effect.
1-7
Reserved
Reserved.
9.3.18 General Purpose Event 1 Status Register 2 (GP1STS2)
Register Location:
Default Value:
Attribute:
<CR64, 65> + 1H System I/O Space
00h
Read/write
Size:
8 bits
Publication Release Date:March 1998
Revision 0.62
-90 -
W83977TF
PRELIMINARY
2
1
7
6
5
4
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
0-7
Name
Description
Reserved. These bits always return zeros.
Reserved
9.3.19 General Purpose Event 1 Enable Register 1 (GP1EN1)
Register Location:
Default Value:
Attribute:
<CR64, 65> + 2H System I/O Space
00h
Read/write
Size:
8 bits
2
1
7
6
5
4
3
0
BIOS_EN
TMR_ON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
event. When this bit is set and the ACPI software
0
BIOS_EN
SMI
This bit is raise the
SMI
SMI
logic
writes a 1 to the GBL_RLS bit, an
output.
event is raised on the
1
TMR_ON
Reserved
This bit is used to turn on the power management timer.
1 = timer on; 0 = timer off.
Reserved.
2-7
9.3.20 General Purpose Event 1 Enable Register 2 (GP1EN2)
Register Location:
Default Value:
Attribute:
<CR64, 65> + 3H System I/O Space
00h
Read/write
8 bits
Size:
Publication Release Date:March 1998
Revision 0.62
-91 -
W83977TF
PRELIMINARY
2
1
7
6
5
4
3
0
BIOS_RLS
BM_CNTRL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit
Name
Description
0
BIOS_RLS
The BIOS release bit. This bit is used by the BIOS software to raise an event
to the ACPI software. The ACPI software has a corresponding enable and
status bit to control its ability to receive the ACPI event. Setting BIOS_RLS
SCI
sets GBL_STS, and it generates an
interrupt if GBL_EN is also set.
Writing a 1 to its bit position sets this bit and also sets the BM_STS bit.
Writing a 0 has no effect. This bit is cleared by writing a 1 to the GBL_STS
bit.
1
BM_CNTRL
This bit is used to set the BM_STS bit and if the BM_RLD bit is also set, then
an SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets
BM_STS. Writing a 0 has no effect. Wrinting a 1 to BM_STS clears
BM_STS and also clears BM_CNTRL.
2-7 Reserved
Reserved.
9.3.21 Bit Map Configuration Registers
Table 9-1: Bit Map of PM1 Register Block
Register
Address
Power-On
Reset
D7
D6
D5
D4
D3
D2
D1
D0
Value
PM1STS1 <CR60,61>
PM1STS2 <CR60,61>
+1H
0000 0000
0000 0000
0
0
0
GBL_STS
0
BM_STS
0
0
0
0
0
0
0
TMR_STS
0
WAK_STS
PM1EN1
<CR60,61>
+2H
<CR60,61>
+3H
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0
0
GBL_EN
0
0
0
0
TMR_EN
PM1EN2
0
0
0
0
0
0
0
0
PM1CTL1 <CR60,61>
0
0
0
0
0
GBL_RLS
BM_RLD
SCI_EN
+4H
PM1CTL2 <CR60,61>
0
0
0
0
0
0
0
0
+5H
PM1CTL3 <CR60,61>
0
0
0
0
0
0
0
0
0
+6H
PM1CTL4 <CR60,61>
0
0
0
0
0
0
0
+7H
PM1TMR1 <CR60,61>
TMR_VAL7
TMR_VAL6
TMR_VAL5
TMR_VAL4
TMR_VAL3
TMR_VAL2
TMR_VAL1
TMR_VAL9
TMR_VAL0
TMR_VAL8
TMR_VAL16
0
+8H
PM1TMR2 <CR60,61>
+9H
PM1TMR3 <CR60,61>
+AH
TMR_VAL15 TMR_VAL14 TMR_VAL13 TMR_VAL12 TMR_VAL11 TMR_VAL10
TMR_VAL23 TMR_VAL22 TMR_VAL21 TMR_VAL20 TMR_VAL19 TMR_VAL18 TMR_VAL17
PM1TMR4 <CR60,61>
+BH
0
0
0
0
0
0
Publication Release Date:March 1998
Revision 0.62
-92 -
W83977TF
PRELIMINARY
Table 9-2: Bit Map of GPE Register Block
Register
Address
Power-On
Reset Value
0000 0000
D7
D6
D5
D4
D3
D2
D1
D0
GP0STS1 <CR62,63>
0
0
0
0
MOUSCISTS
0
KBCSCISTS
0
PRTSCISTS
0
FDCSCISTS
0
URASCISTS
0
URBSCISTS
0
GP0STS2 <CR62,63>
+1H
0000 0000
GP0EN1
<CR62,63>
+2H
0000 0000
0000 0000
0
0
0
0
MOUSCIEN
0
KBCSCIEN
0
PRTSCIEN
0
FDCSCIEN
0
URASCIEN
0
URBSCIEN
0
GP0EN2
<CR62,63>
+3H
GP1STS1 <CR64,65>
0000 0000
0000 0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIOS_STS
0
GP1STS2 <CR64,65>
+1H
GP1EN1
<CR64,65>
+2H
0000 0000
0000 0000
0
0
0
0
0
0
0
0
0
0
0
0
TMR_ON
BIOS_EN
GP1EN2
<CR64,65>
+3H
BM_CNTRL
BIOS_RLS
10. SERIAL IRQ
W83977TF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA
interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
Serial IRQ
IRQ/Data frame, and one Stop frame. The serial interrupt scheme adheres to the
Specification for PCI System, Version 6.0.
Timing Diagrams For IRQSER Cycle
Start Frame timing with source sampled a low pulse on IRQ1
START FRAME
IRQ0 FRAME
IRQ1 FRAME
IRQ2 FRAME
R T
SL
or
H
H
R
T
S
R
T
S
R
T
S
PCICLK
IRQSER
1
START
Drive Source
Host Controller
SL=Slave Control
None
IRQ1
T=Turn-around
None
IRQ1
H=Host Control
R=Recovery
S=Sample
1. Start Frame pulse can be 4-8 clocks wide.
Publication Release Date:March 1998
Revision 0.62
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W83977TF
PRELIMINARY
Stop Frame Timing with Host using 17 IRQSER sampling period
IRQ14
FRAME
IRQ15
FRAME
IOCHCK
FRAME
STOP FRAME
H
NEXT CYCLE
2
S
R
T
S
R
T
S
R
T
I
R
T
PCICLK
IRQSER
1
3
STOP
START
Drive
None
IRQ15
None
Host Controller
S=Sample
H=Host Control
R=Recovery
T=Turn-around
I=Idle
1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
2. There may be none, one or more Idle states during the Stop Frame.
3. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stip Frame.
10.1 Start Frame
There are two modes of operation for the IRQSER Start frame: Quiet mode and Continuous mode.
In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tri-
states it. This brings all the states machines of the peripherals from idle to active states. The host
controller will then take over driving IRQSER signal low in the next clock and will continue driving the
IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4
to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock
and then tri-states it.
In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line
information. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset,
the IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start
frame.
10.2 IRQ/Data Frame
Once the start frame has been initiated, all the peripherals must start counting frames based on the
rsing edge of the start pulse. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase,
and Turn-around phase.
During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the
corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the
peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left
the IRQSER tri-stated.
The IRQ/Data Frame has a number of specific order, as shown in Table 10-1.
10.3 Stop Frame
After all IRQ/Data Frames have completed, the host controller will terminate IRQSER by a Stop
frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If
the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the
Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode.
Publication Release Date:March 1998
-94 -
Revision 0.62
W83977TF
PRELIMINARY
Table 10-1 IRQSER Sampling periods
IRQ/Data Frame
Signal Sampled
# of clocks past Start
1
2
3
IRQ0
IRQ1
2
5
8
SMI
IRQ3
4
5
11
14
17
20
23
26
29
32
35
38
41
44
47
50
IRQ4
6
IRQ5
7
IRQ6
8
IRQ7
9
IRQ8
10
11
12
13
14
15
16
17
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IOCHCK
INTA
18
19
53
56
59
62
95
INTB
20
INTC
21
INTD
32:22
Unassigned
10.4 Reset and Initialization
After MR reset, IRQSER Slaves are put into the Continuous(Idle) mode. The Host Controller is
responsible for starting the initial IRQSER Cycle to collect system's IRQ/Data default values. The
system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent IRQSER cycles. It's the Host Controller's responsibility to provide the default values to
8259's and other system logic before the first IRQSER cycle is performed. For IRQSER system
suspend, insertion, or removal application, the Host controller should be programmed into
Continuous(Idle) mode first. This is to guarantee IRQSER bus in the Idle state before the system
configuration changes.
Publication Release Date:March 1998
-95 -
Revision 0.62
W83977TF
PRELIMINARY
11. CONFIGURATION REGISTER
11.1 Chip (Global) Control Register
CR02 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: SWRST --> Soft Reset.
CR07
Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0
CR20
Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x97 (read only).
CR21
Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x73 (read only).
CR22 (Default 0xff)
Bit 7 - 6: Reserved.
Bit 5: URBPWD
= 0 Power down
= 1 No Power down
Bit 4: URAPWD
= 0 Power down
= 1 No Power down
Bit 3: PRTPWD
= 0 Power down
= 1 No Power down
Bit 2, 1: Reserved.
Bit 0: FDCPWD
= 0 Power down
= 1 No Power down
CR23 (Default 0xFE)
Bit 7 - 1: Reserved.
Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down
mode immediately.
CR24 (Default 0b1s000s0s)
Bit 7: EN16SA
= 0 12 bit Address Qualification
= 1 16 bit Address Qualification
Bit 6: EN48
= 0 The clock input on Pin 1 should be 24 Mhz.
= 1 The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 53).
Publication Release Date: March 1998
-96 -
Revision 0.62
W83977TF
PRELIMINARY
Bit 5 - 3: Reserved.
Bit 2: ENKBC
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
setting pin is SOUTA (pin 46).
Bit 1: Reserved
PNPCSV
Bit 0:
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.
PNPCSV
When trying to make a change to this bit, new value of
must be complementary
PNPCSV
PNPCSV
to the old one to make an effective change. For example, the user must set
to 0
is 1.
first and then reset it to 1 to reset these PnP registers if the present value of
The corresponding power-on setting pin is NDTRA (pin 44).
CR25 (Default 0x00)
Bit 7 - 6: Reserved
Bit 5: URBTRI
Bit 4: URATRI
Bit 3: PRTTRI
Bit 2 - 1 : Reserved
Bit 0: FDCTRI.
CR26 (Default 0b0s000000)
Bit 7: SEL4FDD
= 0 Select two FDD mode.
= 1 Select four FDD mode.
Bit 6: HEFRAS
These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is NRTSA (pin 43).
HEFRAS Address and Value
= 0 Write 87h to the location 3F0h twice.
= 1 Write 87h to the location 370h twice.
Bit 5: LOCKREG
= 0 Enable R/W Configuration Registers.
= 1 Disable R/W Configuration Registers.
Bit 4: Reserved.
Bit 3: DSFDLGRQ
= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective
on selecting IRQ
= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
effective on selecting IRQ
Publication Release Date: March 1998
-97 -
Revision 0.62
W83977TF
PRELIMINARY
Bit 2: DSPRLGRQ
= 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
selecting IRQ
= 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
on selecting IRQ
Bit 1: DSUALGRQ
= 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
Bit 0: DSUBLGRQ
= 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
= 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
CR28 (Default 0x00)
Bit 7 - 5: Reserved.
Bit 4: IRQ Sharing selection.
= 0
= 1
Disable IRQ Sharing
Enable IRQ Sharing
Bit 3:Reserved
Bit 2 - 0: PRTMODS2 - PRTMODS0
= 0xx Parallel Port Mode
= 100 Reserved
= 101 External FDC Mode
= 110 Reserved
= 111 External two FDC Mode
CR2A (Default 0x00)
Bit 7: PIN57S
= 0 KBRST
= 1 GP12
Bit 6: PIN56S
= 0 GA20
= 1 GP11
Bit 5 - 4: PIN40S1, PIN40S0
= 00 Reserved
= 01 GP24
= 10 8042 P13
= 11 Reserved
Bit 3 - 2: Reserved.
Bit 1 - 0: PIN3S1, PIN3S0
= 00 DRVDEN1
= 01 GP10
= 10 8042 P12
SCI
= 11
Publication Release Date: March 1998
Revision 0.62
-98 -
W83977TF
PRELIMINARY
CR2B (Default 0x00)
Bit 7 - 6: PIN73S1, PIN73S0
PANSWIN
= 00
= 01 GP23
= 10 Reserved
= 11 Reserved
Bit 5: PIN72S
PANSWOUT
= 0
= 1 GP22
Bit 4 - 3: PIN70S1, PIN70S0
SMI
= 00
= 01 GP21
= 10 8042 P16
= 11 Reserved
Bit 2 - 1: Reserved.
Bit 0: PIN58S
= 0 KBLOCK
= 1 GP13
CR2C (Default 0x00)
Bit 7 - 6: PIN121S1, PIN121S0
= 00 DRQ0
= 01 GP17
= 10 8042 P14
SCI
= 11
Bit 5 - 4: PIN119S1, PIN119S0
= 00 NDACK0
= 01 GP16
= 10 8042 P15
= 11 Reserved
Bit 3 - 2: PIN104S1, PIN104S0
= 00 IRQ15
= 01 GP15
= 10 WDTO
= 11 Reserved
Bit 1 - 0: PIN103S1, PIN103S0
= 00 IRQ14
= 01 GP14
= 10 PLEDO
= 11 Reserved
CR2D (Default 0x00)
Test Modes: Reserved for Winbond.
CR2E (Default 0x00)
Test Modes: Reserved for Winbond.
CR2F (Default 0x00)
Test Modes: Reserved for Winbond.
Publication Release Date: March 1998
Revision 0.62
-99 -
W83977TF
PRELIMINARY
11.2 Logical Device 0 (FDC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
PNPCSV
CR60, CR 61 (Default 0x03, 0xf0 if
= 0 during POR, default 0x00, 0x00 otherwise)
These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for FDC.
CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise)
Bit 7 - 3: Reserved.
Bit 2 - 0: These bits select DRQ resource for FDC.
= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04 - 0x07 No DMA active
CRF0 (Default 0x0E)
FDD Mode Register
Bit 7: FIPURDWN
This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0,
DSKCHG, and WP.
= 0 The internal pull-up resistors of FDC are turned on.(Default)
= 1 The internal pull-up resistors of FDC are turned off.
Bit 6: INTVERTZ
This bit determines the polarity of all FDD interface signals.
= 0 FDD interface signals are active low.
= 1 FDD interface signals are active high.
Bit 5: DRV2EN (PS2 mode only)
When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status
register A.
Bit 4: Swap Drive 0, 1 Mode
= 0 No Swap (Default)
= 1 Drive and Motor sel 0 and 1 are swapped.
Bit 3 - 2 Interface Mode
= 11 AT Mode (Default)
= 10 (Reserved)
= 01 PS/2
= 00 Model 30
Bit 1: FDC DMA Mode
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (Default)
Publication Release Date: March 1998
-100 -
Revision 0.62
W83977TF
PRELIMINARY
Bit 0: Floppy Mode
= 0 Normal Floppy Mode (Default)
= 1 Enhanced 3-mode FDD
CRF1 (Default 0x00)
Bit 7 - 6: Boot Floppy
= 00 FDD A
= 01 FDD B
= 10 FDD C
= 11 FDD D
Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6.
Bit 3 - 2: Density Select
= 00 Normal (Default)
= 01 Normal
= 10 1 ( Forced to logic 1)
= 11 0 ( Forced to logic 0)
Bit 1: DISFDDWR
= 0 Enable FDD write.
= 1 Disable FDD write(forces pins WE, WD stay high).
Bit 0: SWWP
= 0 Normal, use WP to determine whether the FDD is write protected or not.
= 1 FDD is always write-protected.
CRF2 (Default 0xFF)
Bit 7 - 6: FDD D Drive Type
Bit 5 - 4: FDD C Drive Type
Bit 3 - 2: FDD B Drive Type
Bit 1:0: FDD A Drive Type
When FDD is in enhanced 3-mode(CRF0.bit0=1),these bits determine SELDEN value in TABLE A
of CRF4 and CRF5 as follows.
DTYPE1
DPYTE0
DRATE1
DRATE0
SELDEN
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
1
X
X
0
1
0
1
0
X
X
1
1
1
0
0
0
1
0
Note: X means don't care.
Publication Release Date: March 1998
Revision 0.62
-101 -
W83977TF
PRELIMINARY
CRF4 (Default 0x00)
FDD0 Selection:
Bit 7: Reserved.
Bit 6: Precomp. Disable.
= 1 Disable FDC Precompensation.
= 0 Enable FDC Precompensation.
Bit 5: Reserved.
Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A).
= 00 Select Regular drives and 2.88 format
= 01 Specifical application
= 10 2 Meg Tape
= 11 Reserved
Bit 2: Reserved.
Bit 1:0: DMOD0, DMOD1 : Drive Model select (Refer to TABLE B).
CRF5 (Default 0x00)
FDD1 Selection: Same as FDD0 of CRF4.
Publication Release Date: July 1997
Revision 0.61
-101.1 -
W83977TF
PRELIMINARY
TABLE A
Drive Rate Table
Data Rate
Selected Data Rate
SELDEN
Select
DRTS1
DRTS0
DRATE1
DRATE0
MFM
1Meg
500K
300K
250K
1Meg
500K
500K
250K
1Meg
500K
2Meg
250K
FM
---
CRF0 bit 0=0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
250K
150K
125K
---
1
0
250K
250K
125K
---
250K
---
125K
Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1.
TABLE B
DMOD0
DMOD1
DRVDEN0(pin 2)
DRVDEN1(pin 3)
DRIVE TYPE
0
0
SELDEN
DRATE0
4/2/1 MB 3.5” “
2/1 MB 5.25”
2/1.6/1 MB 3.5” (3-MODE)
0
1
1
0
DRATE1
DRATE0
DRATE0
SELDEN
DRATE0
1
1
DRATE1
Publication Release Date: March 1998
Revision 0.62
-102-
W83977TF
PRELIMINARY
11.3 Logical Device 1 (Parallel Port)
PNPCSV
CR30 (Default 0x01 if
Bit 7 - 1: Reserved.
Bit 0:
= 0 during POR, default 0x00 otherwise)
= 1 Activates the logical device.
= 0 Logical device is inactive.
PNPCSV
CR60, CR 61 (Default 0x03, 0x78 if
= 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Parallel Port I/O base address.
[0x100:0xFFC] on 4 byte boundary (EPP not supported) or
[0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base
address is on 8 byte boundary).
PNPCSV
CR70 (Default 0x07 if
= 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for Parallel Port.
CR74 (Default 0x04)
Bit 7 - 3: Reserved.
Bit 2 - 0: These bits select DRQ resource for Parallel Port.
0x00=DMA0
0x01=DMA1
0x02=DMA2
0x03=DMA3
0x04 - 0x07= No DMA active
CRF0 (Default 0x3F)
Bit 7: PP Interrupt Type:
Not valid when the parallel port is in the printer Mode (100) or the standard & Bi-directional
Mode (000).
= 1 Pulsed Low, released to high-Z .
= 0 IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP.
Bit [6:3]: ECP FIFO Threshold.
Bit 2 - 0 Parallel Port Mode
= 100 Printer Mode (Default)
= 000 Standard and Bi-direction (SPP) mode
= 001 EPP - 1.9 and SPP mode
= 101 EPP - 1.7 and SPP mode
= 010 ECP mode
= 011 ECP and EPP - 1.9 mode
= 111 ECP and EPP - 1.7 mode.
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11.4
Logical Device 2 (UART A)¢ )
PNPCSV
CR30 (Default 0x01 if
Bit 7 - 1: Reserved.
Bit 0:
= 0 during POR, default 0x00 otherwise)
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Serial Port 1.
CRF0 (Default 0x00)
Bit 7 - 2: Reserved.
Bit 1 - 0: SUACLKB1, SUACLKB0
= 00 UART A clock source is 1.8462 Mhz (24MHz/13)
= 01 UART A clock source is 2 Mhz (24MHz/12)
= 10 UART A clock source is 24 Mhz (24MHz/1)
= 11 UART A clock source is 14.769 Mhz (24MHz/1.625)
11.5 Logical Device 3 (UART B)
PNPCSV
CR30 (Default 0x01 if
Bit 7 - 1: Reserved.
Bit 0:
= 0 during POR, default 0x00 otherwise)
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for Serial Port 2.
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CRF0 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3: RXW4C
= 0
= 1
No reception delay when SIR is changed from TX mode to RX mode.
Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode
to RX mode.
Bit 2: TXW4C
= 0
= 1
No transmission delay when SIR is changed from RX mode to TX mode.
Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX
mode to TX mode.
Bit 1 - 0: SUBCLKB1, SUBCLKB0
= 00 UART B clock source is 1.8462 Mhz (24MHz/13)
= 01 UART B clock source is 2 Mhz (24MHz/12)
= 10 UART B clock source is 24 Mhz (24MHz/1)
= 11 UART B clock source is 14.769 Mhz (24MHz/1.625)
CRF1 (Default 0x00)
Bit 7: Reserved.
Bit 6: IRLOCSEL. IR I/O pins' location select.
= 0
= 1
Through SINB/SOUTB.
Through IRRX/IRTX.
Bit 5: IRMODE2. IR function mode selection bit 2.
Bit 4: IRMODE1. IR function mode selection bit 1.
Bit 3: IRMODE0. IR function mode selection bit 0.
IR MODE IR FUNCTION
IRTX
IRRX
00X
010*
011*
100
Disable
IrDA
tri-state
high
Demodulation into SINB/IRRX
Demodulation into SINB/IRRX
routed to SINB/IRRX
m
Active pulse 1.6 S
IrDA
Active pulse 3/16 bit time
Inverting IRTX/SOUTB pin
ASK-IR
ASK-IR
101
Inverting IRTX/SOUTB & 500
KHZ clock
routed to SINB/IRRX
110
ASK-IR
ASK-IR
Inverting IRTX/SOUTB
Demodulation into SINB/IRRX
Demodulation into SINB/IRRX
111*
Inverting IRTX/SOUTB & 500
KHZ clock
Note: The notation is normal mode in the IR function.
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Bit 2: HDUPLX. IR half/full duplex function select.
= 0
= 1
The IR function is Full Duplex.
The IR function is Half Duplex.
Bit 1: TX2INV.
= 0
= 1
the SOUTB pin of UART B function or IRTX pin of IR function in normal condition.
inverse the SOUTB pin of UART B function or IRTX pin of IR function.
Bit 0: RX2INV.
= 0
= 1
the SINB pin of UART B function or IRRX pin of IR function in normal condition.
inverse the SINB pin of UART B function or IRRX pin of IR function
11.6 Logical Device 5 (KBC)
CR30 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise)
Bit 7 - 1: Reserved.
Bit 0:
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x60 if PENKBC= 1 during POR, default 0x00 otherwise)
These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x64 if PENKBC= 1 during POR, default 0x00 otherwise)
These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
CR70 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for KINT (keyboard).
CR72 (Default 0x0C if PENKBC= 1 during POR, default 0x00 otherwise)
Bit 7 - 4: Reserved.
Bit [3:0]: These bits select IRQ resource for MINT (PS2 Mouse)
CRF0 (Default 0x83)
Bit 7 - 6: KBC clock rate selection
= 00 Select 6MHz as KBC clock input.
= 01 Select 8MHz as KBC clock input.
= 10 Select 12Mhz as KBC clock input.
= 11 Select 16Mhz as KBC clock input.
Bit 5 - 3: Reserved.
Bit 2: = 0 Port 92 disable.
= 1 Port 92 enable.
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Bit 1: = 0 Gate20 software control.
= 1 Gate20 hardware speed up.
Bit 0: = 0 KBRST software control.
= 1 KBRST hardware speed up.
11.7 Logical Device 7 (GP I/O Port I)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP1 I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x00)
These two registers select GP14 alternate function Primary I/O base address [0x100:0xFFE] on 2
byte boundary; They are available as you setting GP14 to be an alternate function (General
Purpose Address Decode).
CR64, CR 65 (Default 0x00, 0x00)
These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFF] on 1
byte boundary; They are available as you setting GP15 to be an alternate function (General
Purpose Write Decode).
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP10 as you setting GP10 to be an alternate function
(Interrupt Steering).
CR72 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP11 as you setting GP11 to be an alternate function
(Interrupt Steering).
CRE0 (GP10, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4: IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 3: Select Function.
= 1 Select Alternate Function: Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity.
= 1 Invert.
= 0 No Invert.
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Bit 0: In/Out selection.
= 1 Input.
= 0 Output.
CRE1 (GP11, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4: IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 3: Select Function.
= 1 Select Alternate Function: Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity.
= 1 Invert.
= 0 No Invert.
Bit 0: In/Out selection.
= 1 Input.
= 0 Output.
CRE2 (GP12, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Watch Dog Timer Output.
= 10 Reserved
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE3 (GP13, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Power LED output.
= 10 Reserved
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
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CRE4 (GP14, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: General Purpose Address Decoder(Active Low when
Bit 1 = 0, Decode two byte address).
= 10 Select 2nd alternate function: Keyboard Inhibit(P17).
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE5 (GP15, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 General Purpose Write Strobe(Active Low when Bit 1 = 0).
= 10 8042 P12.
= 11 Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE6 (GP16, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Watch Dog Timer Output.
= 1x Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE7 (GP17, Default 0x01)
Bit 7 - 4: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Select 1st alternate function: Power LED output. Please refer to TABLE C
= 1x Reserved
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
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TABLE C
WDT_CTRL1* BIT[1]*
WDT_CTRL0* BIT[3] WDT_CTRL1 BIT[0] POWER LED STATE
1
0
0
0
X
0
1
1
X
X
0
1
1 Hertz Toggle pulse
Continuous high or low*
Continuous high or low*
1 Hertz Toggle pulse
*Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8.
2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers.
CRF1 ( Default 0x00)
General Purpose Read/Write Enable*
Bit 7 - 2: Reserved
Bit 1:
= 1 Enable General Purpose Write Strobe
= 0 Disable General Purpose Write Strobe
Bit 0:
= 1 Enable General Purpose Address Decode
= 0 Disable General Purpose Address Decode
*Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect.
11.8 Logical Device 8 (GP I/O Port II)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE] on 2 byte
boundary. I/O base address + 1: Watch Dog I/O base address.
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Common IRQ of GP20~GP26 at Logic Device 8.
CR72 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for Watch Dog.
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CRE8 (GP20, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select basic I/O function
= 01 Reserved
= 10 Select alternate function: Keyboard Reset (connected to KBC P20)
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE9 (GP21, Default 0x01)
Bit 7 - 5: Reserved
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P13 I/O
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CREA (GP22, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function.
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P14 I/O.
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output¡ @¡ @
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CREB (GP23, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P15 I/O
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output¡ @
CREC (GP24, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4 - 3: Select Function.
= 00 Select Basic I/O function
= 01 Reserved
= 10 Select 2nd alternate function: Keyboard P16 I/O
= 11 Reserved
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRED (GP25, Default 0x01)
Bit 7 - 4: Reserved.
Bit 3: Select Function.
= 1 Select alternate function: GATE A20(Connect to KBC P21).
= 0 Select basic I/O function
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
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CREE (GP26, Default 0x01)
Bit 7 - 3: Reserved.
Bit 2: Int En
= 1 Enable Common IRQ
= 0 Disable Common IRQ
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRF0 (Default 0x00)
Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter
can reject a pulse with 1ms width or less.
Bit 7 - 4: Reserved
Bit 3: GP Common IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 2 - 0: Reserved
CRF1 (Reserved)
CRF2 (Default 0x00)
Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load
the value to Watch Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any Mouse
Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to Watch Dog
Counter and count down. Read this register can not access Watch Dog Timer Time-out value, but
can access the current value in Watch Dog Counter.
Bit 7 - 0:
= 0x00 Time-out Disable
= 0x01 Time-out occurs after 1 minute
= 0x02 Time-out occurs after 2 minutes
= 0x03 Time-out occurs after 3 minutes
................................................
= 0xFF Time-out occurs after 255 minutes
CRF3 (WDT_CTRL0, Default 0x00)
Watch Dog Timer Control Register #0
Bit 7 - 4: Reserved
Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output.
= 1 Enable
= 0 Disable
Bit 2: Mouse interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Mouse interrupt
= 0 Watch Dog Timer is not affected by Mouse interrupt
Bit 1: Keyboard interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Keyboard interrupt
= 0 Watch Dog Timer is not affected by Keyboard interrupt
Bit 0: Reserved.
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CRF4 (WDT_CTRL1, Default 0x00)
Watch Dog Timer Control Register #1
Bit 7 - 4: Reserved
Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
= 1 Enable
= 0 Disable
Bit 2: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.
Bit 1: Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W
= 1 Enable
= 0 Disable
Bit 0: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred.
= 0 Watch Dog Timer counting
*Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then
connect to set the Bit 0(Watch Dog Timer Status). The ORed signal is self-clearing.
11.9 Logical Device 9 (GP I/O Port III)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select GP3 I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x00)
These two registers select GP32 alternate function Primary I/O base address [0x100:0xFFE] on 2-
byte boundary; They are available as you setting GP32 to be an alternate function (General
Purpose Address Decode).
CR64, CR 65 (Default 0x00, 0x00)
These two registers select GP33 alternate function Primary I/O base address [0x100:0xFFF] on 2-
byte boundary; They are available as you setting GP33 to be an alternate function (General
Purpose Address Decode).
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP30 as you setting GP30 to be an alternate function
(Interrupt Steering).
CR72 (Default 0x00)
Bit 7 - 4: Reserved.
Bit 3 - 0: These bits select IRQ resource for GP31 as you setting GP31 to be an alternate function
(Interrupt Steering).
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CRE0 (GP30, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4: IRQ Filter Select
= 1 Debounce Filter Enabled.
= 0 Debounce Filter Bypassed.
Bit 3: Select Function.
= 1 Select Alternate Function: Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity.
= 1 Invert.
= 0 No Invert.
Bit 0: In/Out selection.
= 1 Input.
= 0 Output.
CRE1 (GP31, Default 0x01)
Bit 7 - 5: Reserved.
Bit 4: IRQ Filter Select
= 1 Debounce Filter Enabled
= 0 Debounce Filter Bypassed
Bit 3: Select Function.
= 1 Select Alternate Function: Interrupt Steering.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity.
= 1 Invert.
= 0 No Invert.
Bit 0: In/Out selection.
= 1 Input.
= 0 Output.
CRE2 (GP32, Default 0x01)
Bit 7 - 4: Reserved.
Bit 3: Select Function.
= 1 Select Alternate Function: General Purpose Address Decode.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE3 (GP33, Default 0x01)
Bit 7 - 4: Reserved.
Bit 3: Select Function.
= 1 Select Alternate Function: General Purpose Address Decode.
= 0 Select Basic I/O Function.
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Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE4 (GP34, Default 0x01)
Bit 7 - 4: Reserved.
Bit 3: Select Function.
= 1 Select Alternate Function: Watch Dog Timer output.
= 0 Select Basic I/O Function.
Bit 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE5 (GP35, Default 0x01)
Bit 7 - 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE6 (GP36, Default 0x01)
Bit 7 - 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRE7 (GP37, Default 0x01)
Bit 7 - 2: Reserved.
Bit 1: Polarity: 1: Invert, 0: No Invert
Bit 0: In/Out: 1: Input, 0: Output
CRF1 ( Default 0x00)
Bit 7 - 3: Reserved
Bit 2: SERIRQ
= 0 The IRQ system is in normal mode.
= 1 The IRQ system is in serial IRQ mode.
Bit 1:
= 1 Enable GP33 General Purpose Address Decode.
= 0 Disable GP33 General Purpose Address Decode.
Bit 0:
= 1 Enable GP32 General Purpose Address Decode.
= 0 Disable GP32 General Purpose Address Decode.
*Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect.
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11.10 Logical Device A (ACPI)
CR30 (Default 0x00)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select PM1 register block base address [0x100:0xFF0] on 16-byte boundary.
CR62, CR 63 (Default 0x00, 0x00)
These two registers select GPE0 register block base address [0x100:0xFFC] on 4-byte boundary.
CR64, CR 65 (Default 0x00, 0x00)
These two registers select GPE1 register block base address [0x100:0xFFC] on 4-byte boundary.
CR70 (Default 0x00)
Bit 7 - 4: Reserved.
SCI
Bit 3 - 0: These bits select IRQ resource for
.
CRE0 (Default 0x00)
Bit 7: DIS-PANSWIN. Disable panel switch input to turn system power supply on.
PANSWIN
PANSWIN
PANSWOUT
.
= 0
= 1
is wire-ANDed and connected to
is blocked and can not affect
PANSWOUT
.
PANSWOUT
Bit 6: ENKBWAKEUP. Enable Keyboard to wake-up system via
.
= 0
= 1
Disable Keyboard wake-up function.
Enable Keyboard wake-up function.
PANSWOUT
Bit 5: ENMSWAKEUP. Enable Mouse to wake-up system via
.
= 0
= 1
Disable Mouse wake-up function.
Enable Mouse wake-up function.
PANSWOUT
Bit 4: MSRKEY. Select Mouse Left/Right Botton to wake-up system via
.
= 0
= 1
Select click on Mouse Left-botton twice to wake the system up.
Select click on Mouse right-botton twice to wake the system up.
Bit 3: Reserved.
Bit 2: KB/MS Swap. Enable Keyboard/Mouse port-swap.
= 0
= 1
Keyboard/Mouse ports are not swapped.
Keyboard/Mouse ports are swapped.
Bit 1: MSXKEY. Enable any character received from Mouse to wake-up the system.
= 0
= 1
Just clicking Mouse left/right-botton twice can wake the system up.
Any character received from Mouse can wake the system up (the setting of Bit 4 is
ignored).
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Bit 0: KBXKEY. Enable any character received from Keyboard to wake-up the system.
= 0
= 1
Only predetermined specific key combination can wake up the system.
Any character received from Keyboard can wake up the system.
CRE1 (Default 0x00) Keyboard Wake-up Index Register
This register is used to indicate which Keyboard Wake-up Shift register or Predetermined key
Register is to be read/written via CRE2.
CRE2 Keyboard Wake-up Data Register
CRE3 (Read only) Keyboard/Mouse Wake-up Status Register
Bit 7-3: Reserved.
PANSWIN
Bit 2: PANSW_STS. The Panel switch event is caused by
reading this register.
. This bit is cleared by
Bit 1: Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is
cleared by reading this register.
Bit 0: Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is
cleared by reading this register.
CRE4 This Register is reserved for test.
CRF0 (Default 0x00)
Bit 7: CHIPPME. Chip level power management enable.
= 0
= 1
disable the ACPI/Legacy and the auto power management functions
enable the ACPI/Legacy and the auto power management functions.
Bit 6 - 4: Reserved. Return zero when read.
Bit 3: PRTPME. Printer port power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions provided
CRF0.bit7 (CHIPPME) is also set to 1.
Bit 2: FDCPME. FDC power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions provided
CRF0.bit7 (CHIPPME) is also set to 1.
Bit 1: URAPME. UART A power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions provided
CRF0.bit7 (CHIPPME) is also set to 1.
Bit 0: URBPME. UART B power management enable.
= 0
= 1
disable the auto power management functions.
enable the auto power management functions provided
CRF0.bit7 (CHIPPME) is also set to 1.
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CRF1 (Default 0x00)
Bit 7 - 4: Reserved. Return zero when read.
Bit 3 - 0: Devices' idle status.
These bits indicate that the individual device's idle timer expires due to no I/O access, no IRQ,
and no external input to the device. These 4 bits are controlled by the printer port, FDC, UART A,
and UART B power down machines individually. Writing a 1 clears this bit, and writing a 0 has no
effect. Note that: the user is not supposed to change the status while the power management
function is enabled.
Bit 3: PRTIDLSTS. Printer port idle status.
= 0
= 1
printer port is now in the working state.
printer port is now in the sleeping state due to no printer port access, no IRQ, no DMA
ACK
ERR
pins in a
acknowledge, and no transition on BUSY,
preset expiry time period.
, PE, SLCT, and
Bit 2: FDCIDLSTS. FDC idle status.
= 0
= 1
FDC is now in the working state.
FDC is now in the sleeping state due to no FDC access, no IRQ, no DMA
acknowledge, and no enabling of the motor enable bits in the DOR register in a
preset expiry time period.
Bit 1: URAIDLSTS. UART A idle status.
= 0
= 1
UART A is now in the working state.
UART A is now in the sleeping state due to no UART A access, no IRQ, the receiver
is now waiting for a start bit, the transmitter shift register is now empty, and no
transition on MODEM control input lines in a preset expiry time period.
Bit 0: URBIDLSTS. UART B idle status.
= 0
= 1
UART B is now in the working state.
UART B is now in the sleeping state due to no UART A access, no IRQ, the receiver
is now waiting for a start bit, the transmitter shift register is now empty, and no
transition on MODEM control input lines in a preset expiry time period.
CRF2 (Default 0x00)
Bit 7 - 4: Reserved. Return zero when read.
Bit 3 - 0: Devices' trap status.
These bits indicate that the individual device wakes up due to any I/O access, IRQ, and external
input to the device. The device's idle timer reloads the preset expiry depending on which device
wakes up. These 4 bits are controlled by the printer port, FDC, UART A, and UART B power down
machines respectively. Writing a 1 clears this bit, and writing a 0 has no effect. Note that: the
user is not supposed to change the status while power management function is enabled.
Bit 3: PRTTRAPSTS. Printer port trap status.
= 0
= 1
the printer port is now in the sleeping state.
the printer port is now in the working state due to any printer port access, any IRQ,
ACK
ERR
, PE, SLCT, and
any DMA acknowledge, and any transition on BUSY,
pins.
Publication Release Date: March 1998
Revision 0.62
-119-
W83977TF
PRELIMINARY
Bit 2: FDCTRAPSTS. FDC trap status.
= 0
= 1
FDC is now in the sleeping state.
FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, and any enabling of the motor enable bits in the DOR register.
Bit 1: URATRAPSTS. UART A trap status.
= 0
= 1
UART A is now in the sleeping state.
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting a
start bit, and any transition on MODEM control input lines.
Bit 0: URBTRAPSTS. UART B trap status.
= 0
= 1
UART B is now in the sleeping state.
UART B is now in the working state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting
a start bit, and any transition on MODEM control input lines.
CRF3 (Default 0x00)
Bit 7 - 6: Reserved. Return zero when read.
Bit 5 - 0: Device's IRQ status.
These bits indicate the IRQ status of the individual device. The device's IRQ status
by their source device and is cleared by writing a 1. Writing a 0 has no effect.
bit is set
Bit 5: MOUIRQSTS. MOUSE IRQ status.
Bit 4: KBCIRQSTS. KBC IRQ status.
Bit 3: PRTIRQSTS. printer port IRQ status.
Bit 2: FDCIRQSTS. FDC IRQ status.
Bit 1: URAIRQSTS. UART A IRQ status.
Bit 0: URBIRQSTS. UART B IRQ status.
CRF4 (Default 0x00)
Bit 7 - 4: Reserved. Return zero when read.
SMI
Bit 3 - 0: Enable bits of the
generation due to the device's idleness.
SMI
These bits enable the generation of an
interrupt due to the expiration of the device's idle
SMI
timer. These 4 bits control the printer port, FDC, UART A, and UART B
Bit 3: PRTIDLEN.
logics respectively.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to printer port's idleness.
interrupt due to printer port's idleness.
Bit 2: FDCIDLEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to FDC's idleness.
interrupt due to FDC's idleness.
Publication Release Date: March 1998
Revision 0.62
-120-
W83977TF
PRELIMINARY
Bit 1: URAIDLEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to UART A's idleness.
interrupt due to UART A's idleness.
Bit 0: URBIDLEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to UART B's idleness.
interrupt due to UART B's idleness.
CRF5 (Default 0x00)
Bit 7 - 4: Reserved. Return zero when read.
SMI
Bit 3 - 0: Enable bits of the
generation due to device's trap.
SMI
These bits enable the generation of an
interrupt due to any I/O access, IRQ, and external
input to the device. These 4 bits control the printer port, FDC, UART A, and UART B SMI logics
respectively.
Bit 3: PRTTRAPEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to printer port's trap.
interrupt due to printer port's trap.
Bit 2: FDCTRAPEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to FDC's trap.
interrupt due to FDC's trap.
Bit 1: URATRAPEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to UART A's trap.
interrupt due to UART A's trap.
Bit 0: URBTRAPEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to UART B's trap.
interrupt due to UART B's trap.
CRF6 (Default 0x00)
Bit 7 - 6: Reserved. Return zero when read.
SMI
Bit 5 - 0: Enable bits of the
generation due to the device's IRQ.
SMI
These bits enable the generation of an
interrupt due to any IRQ of the devices. These 4 bits
SMI
SMI
logic
control the printer port, FDC, UART A, and UART B
output for the IRQs is as follows:
logics respectively. The
SMI
logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or
(FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS)
(KBCIRQEN and KBCIRQSTS) or (MOUIRQEN and MOUIRQSTS)
Publication Release Date: March 1998
Revision 0.62
-121-
W83977TF
PRELIMINARY
Bit 5: MOUIRQEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to MOUSE's IRQ.
interrupt due to MOUSE's IRQ.
Bit 4: KBCIRQEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to KBC's IRQ.
interrupt due to KBC's IRQ.
Bit 3: PRTIRQEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to printer port's IRQ.
interrupt due to printer port's IRQ.
Bit 2: FDCIRQEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to FDC's IRQ.
interrupt due to FDC's IRQ.
Bit 1: URAIRQEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to UART A's IRQ.
interrupt due to UART A's IRQ.
Bit 0: URBIRQEN.
SMI
SMI
= 0
= 1
disable the generation of an
enable the generation of an
interrupt due to UART B's IRQ.
interrupt due to UART B's IRQ.
CRF7 (Default 0x00)
Bit 7 - 1: Reserved. Return zero when read.
Bit 0: SMI_EN.
SMI
SMI SMI
event is raised on the output of the
This bit is the
output pin enable bit. When an
SMI
SMI
. If this bit is
logic, setting this bit enables the
interrupt to be generated on the pin
SMI
cleared, only the IRQ status bit in CRF3 is set, and no SMI interrupt is generated on the pin
.
SMI
SMI
= 0
= 1
Disable
Enable
CRFE, FF (Default 0x00)
Reserved for Winbond test.
Publication Release Date: March 1998
Revision 0.62
-122-
W83977TF
PRELIMINARY
12.0 SPECIFICATIONS
12.1 Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage
Input Voltage
-0.5 to 7.0
V
V
V
DD
-0.5 to V +0.5
BAT
Battery Voltage V
4.0 to 1.8
0 to +70
Operating Temperature
Storage Temperature
°
°
C
C
-55 to +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
12.2 DC CHARACTERISTICS
DD
SS
°
°
±
(Ta = 0 C to 70 C, V = 5V 10%, V = 0V)
PARAMETER
SYM. MIN.
TYP.
MAX.
UNIT
CONDITIONS
= 2.5 V
BAT
BAT
SB
Battery Quiescent Current
I
2.4
2.0
uA
V
BAT
Stand-by Power Supply
Quiescent Current
I
mA
V
= 5.0 V, All ACPI pins are
not connected.
I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA
IL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.8
V
V
V
V
IH
V
2.0
2.4
OL
OL
OH
IN
= 8 mA
V
0.4
I
I
OH
= - 8 mA
V
LIH
DD
= V
I
+10
-10
V
V
m
A
LIL
IN
I
= 0V
mA
I/O6t - TTL level bi-directional pin with source-sink capability of 6 mA
IL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.8
0.4
V
V
V
V
IH
V
2.0
2.4
OL
OL
OH
IN
= 6 mA
V
I
I
OH
= - 6 mA
V
LIH
DD
= V
I
+10
-10
V
V
m
A
LIL
IN
= 0V
I
m
A
Publication Release Date: March 1998
Revision 0.62
- 123 -
W83977TF
PRELIMINARY
12.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O8 - CMOS level bi-directional pin with source-sink capability of 8 mA
IL
DD
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.3xV
0.4
V
V
V
V
IH
DD
V
0.7xV
3.5
OL
OL
OH
IN
= 8 mA
V
I
I
OH
= - 8 mA
V
LIH
LIL
DD
= V
I
+ 10
- 10
V
V
m
A
IN
I
= 0V
m
A
I/O12 - CMOS level bi-directional pin with source-sink capability of 12 mA
IL
DD
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.3xV
0.4
V
V
V
V
IH
DD
V
0.7xV
3.5
OL
OL
OH
IN
= 12 mA
V
I
I
OH
= - 12 mA
V
LIH
LIL
DD
= V
I
+ 10
- 10
V
V
m
A
IN
I
= 0V
m
A
I/O16u - CMOS level bi-directional pin with source-sink capability of 16 mA, with internal pull-up
resistor
IL
DD
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.3xV
V
V
V
V
IH
DD
V
0.7xV
3.5
OL
OL
OH
IN
= 16 mA
V
0.4
I
I
OH
= - 16 mA
V
LIH
LIL
DD
= V
I
+ 10
- 10
V
V
m
A
IN
I
= 0V
m
A
I/OD16u - CMOS level Open-Drain pin with source-sink capability of 16 mA, with internal pull-up
resistor
IL
DD
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.3xV
V
V
V
V
IH
DD
V
0.7xV
3.5
OL
OL
OH
IN
= 16 mA
V
0.4
I
I
OH
= - 16 mA
V
LIH
LIL
DD
= V
I
+ 10
- 10
V
V
m
A
IN
I
= 0V
m
A
Publication Release Date: March 1998
Revision 0.62
- 124 -
W83977TF
PRELIMINARY
12.2 DC CHARACTERISTICS, continued
PARAMETER SYM. MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
IL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.8
V
V
V
V
IH
V
2.0
2.4
OL
OL
OH
IN
= 12 mA
V
0.4
I
OH
= - 12 mA
V
I
LIH
DD
= V
I
+ 10
- 10
V
V
m
A
LIL
IN
= 0V
I
m
A
I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA
IL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Leakage
Input Low Leakage
V
0.8
0.4
V
V
V
V
IH
V
2.0
2.4
OL
OL
OH
IN
= 24 mA
V
I
OH
= - 24 mA
V
I
LIH
DD
= V
I
+ 10
- 10
V
V
m
A
LIL
IN
= 0V
I
m
A
OUT8t - TTL level output pin with source-sink capability of 8 mA
OL
OL
= 8 mA
Output Low Voltage
Output High Voltage
V
0.4
V
I
OH
OH
I
= - 8 mA
V
2.4
V
OUT12t - TTL level output pin with source-sink capability of 12 mA
OL
OL
= 12 mA
= -12 mA
Output Low Voltage
Output High Voltage
V
0.4
V
V
I
OH
OH
I
V
2.4
OD12 - Open-drain output pin with sink capability of 12 mA
OL
OL
= 12 mA
= 24 mA
Output Low Voltage
V
0.4
V
V
I
I
OD24 - Open-drain output pin with sink capability of 24 mA
OL
V
OL
Output Low Voltage
0.4
INt - TTL level input pin
Input Low Voltage
IL
V
0.8
V
V
IH
Input High Voltage
V
2.0
LIH
LIL
IN
DD
Input High Leakage
Input Low Leakage
I
+10
-10
V
= V
m
A
IN
V
I
= 0 V
mA
Publication Release Date: March 1998
Revision 0.62
- 125 -
W83977TF
PRELIMINARY
12.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
INc - CMOS level input pin
Input Low Voltage
IL
V
V
V
DD
´
0.3 V
IH
Input High Voltage
V
DD
´
0.7 V
LIH
IN
DD
= V
Input High Leakage
Input Low Leakage
I
+10
-10
V
m
A
LIL
IN
V = 0 V
I
m
A
INcs - CMOS level Schmitt-triggered input pin
t-
DD
DD
DD
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
V
1.3
3.2
1.5
1.5
3.5
2
1.7
3.8
V
V
V
V
V
V
= 5 V
= 5 V
= 5 V
DD
t+
V
V
V
TH
V
LIH
LIL
IN
Input High Leakage
Input Low Leakage
I
+10
-10
= V
m
A
IN
I
= 0 V
m
A
INcu - CMOS level input pin with internal pull-up resistor
IL
DD
Input Low Voltage
Input High Voltage
Input High Leakage
Input Low Leakage
V
0.7xV
V
IH
DD
V
0.7xV
V
LIH
IN
IN
DD
= V
I
+10
-10
V
m
A
LIL
I
V
= 0 V
m
A
INts - TTL level Schmitt-triggered input pin
t-
DD
DD
DD
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
V
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
V
V
V
V
= 5 V
= 5 V
= 5 V
DD
t+
V
V
V
TH
V
LIH
LIL
IN
Input High Leakage
Input Low Leakage
I
+10
-10
= V
m
A
IN
I
= 0 V
m
A
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
t-
DD
DD
DD
Input Low Threshold Voltage
Input High Threshold Voltage
Hystersis
V
0.5
1.6
0.5
0.8
2.0
1.2
1.1
2.4
V
V
V
V
V
V
= 5 V
= 5 V
= 5 V
DD
t+
V
V
V
TH
V
LIH
LIL
IN
Input High Leakage
Input Low Leakage
I
+10
-10
= V
m
A
IN
I
= 0 V
m
A
Publication Release Date: March 1998
Revision 0.62
- 126 -
W83977TF
PRELIMINARY
12.3 AC Characteristics
12.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec.
PARAMETER
SYM. TEST
CONDITIONS
MIN.
TYP.
(NOTE 1)
MAX.
UNIT
AR
T
T
T
25
nS
DACK
SA9-SA0, AEN,
CS
,
IOR¡ õ
, setup time to
AR
0
nS
DACK
SA9-SA0, AEN,
IOR¡ ô
,
hold time for
IOR
RR
FD
80
nS
nS
width
CL = 100 pf
Data access time from
T
80
IOR¡ õ
DH
CL = 100 pf
CL = 100 pf
T
10
10
nS
nS
nS
IOR¡ õ
Data hold from
DF
RI
T
50
IOR ¡ ô
SD to from
T
360/570
/675
IOR¡ ô
IRQ delay from
AW
T
25
0
nS
nS
DACK
IOW¡ õ
SA9-SA0, AEN,
setup time to
,
,
WA
T
DACK
SA9-SA0, AEN,
IOW ¡ ô
hold time for
WW
DW
T
60
60
0
nS
nS
nS
IOW
width
Data setup time to
T
T
IOW ¡ ô
WD
Data hold time from
IOW ¡ ô
WI
T
360/570
/675
nS
IOW ¡ ô
IRQ delay from
MCY
AM
DRQ cycle time
DRQ delay time
T
27
0
m
S
T
50
nS
nS
nS
DACK ¡ õ
MA
T
DACK
width
DRQ to
delay
AA
T
260/430
/510
DACK
MR
T
0
0
nS
nS
DRQ
IOR
delay from
delay from
MW
T
IOW
DRQ
Publication Release Date: March 1998
Revision 0.62
- 127 -
W83977TF
PRELIMINARY
12.3.1 AC Characteristics, FDC continued
PARAMETER SYM. TEST
MIN.
TYP.
MAX.
UNIT
CONDITIONS
(NOTE 1)
MRW
TC
T
6/12
/20/24
m
S
IOW
from DRQ
IOR
response time
or
TC width
T
135/220
/260
nS
RST
RESET width
T
1.8/3/3.
5
m
S
IDX
T
0.5/0.9
/1.0
m
S
INDEX
width
DST
T
1.0/1.6
/2.0
m
S
DIR
DIR
STEP
setup time to
STD
STP
T
24/40/48
m
S
STEP
hold time from
T
6.8/11.5
/13.8
7/11.7
/14
7.2/11.9
/14.2
m
S
STEP
pulse width
SC
T
Note 2
Note 2
Note 2
mS
STEP
cycle width
pulse width
WDD
T
100/185
/225
125/210
/250
150/235
/275
m
S
WD
WPC
Write precompensation
T
100/138
/225
125/210
/250
150/235
/275
m
S
Notes:
1. Typical values for T = 25 C and normal supply voltage.
°
2. Programmable from 2 mS through 32 mS in 2 mS increments.
Publication Release Date: March 1998
Revision 0.62
- 128 -
W83977TF
PRELIMINARY
12.3.2 UART/Parallel Port
PARAMETER
SYMBOL TEST
CONDITIONS
MIN.
MAX.
UNIT
SINT
T
Delay from Stop to Set Interrupt
9/16
Baud
Rate
RINT
IRS
T
100 pf Loading
100 pf Loading
1
m
S
IOR
Delay from
Reset Interrupt
Delay from Initial IRQ Reset to
Transmit Start
T
1/16
9/16
8/16
Baud
Rate
HR
SI
T
175
nS
IOW
Delay from
to Reset interrupt
IOW
T
16/16
Baud
Rate
Delay from Initial
to interrupt
STI
Delay from Stop to Set Interrupt
T
1/2
Baud
Rate
IR
T
100 pF Loading
100 pF Loading
250
200
250
nS
nS
nS
IOR
IOR
Delay from
Delay from
to Reset Interrupt
to Output
MWO
T
SIM
Set Interrupt Delay from Modem
Input
T
RIM
IAD
T
250
nS
IOR
Reset Interrupt Delay from
Interrupt Active Delay
Interrupt Inactive Delay
Baud Divisor
T
T
100 pF Loading
100 pF Loading
100 pF Loading
25
30
216-1
nS
nS
IID
N
12.3.3 Parallel Port Mode Parameters
PARAMETER
SYM.
MIN.
TYP. MAX.
UNIT
t1
100
nS
INDEX STROBE AUTOFD
PD0-7,
IOW
,
,
Delay from
t2
t3
t4
t5
60
nS
nS
nS
nS
ACK
IOW
IRQ Delay from
IRQ Delay from
, nFAULT
105
300
105
IRQ Active Low in ECP and EPP Modes
ERROR
200
Active to IRQ Active
Publication Release Date: March 1998
Revision 0.62
- 129 -
W83977TF
PRELIMINARY
12.3.4 EPP Data or Address Read Cycle Timing Parameters
PARAMETER
SYM.
MIN.
40
MAX.
UNIT
t1
t2
t3
t4
t5
nS
nS
nS
IOR
Ax Valid to
Asserted
0
IOR
IOCHRDY Deasserted to
Deasserted
10
40
0
10
24
IOR
IOR
IOR
Deasserted to Ax Valid
IOR
Deasserted to IOW or
Asserted
nS
nS
Asserted to IOCHRDY Asserted
PD Valid to SD Valid
IOR
t6
t7
0
0
75
40
m
S
Deasserted to SD Hi-Z (Hold Time)
SD Valid to IOCHRDY Deasserted
WAIT
t8
t9
0
85
nS
nS
60
160
Deasserted to IOCHRDY Deasserted
PD Hi-Z to PDBIR Set
WRITE
t10
t13
t14
t15
t16
0
0
nS
nS
nS
nS
nS
IOR
Deasserted to
Asserted
0
185
190
50
WAIT
WRITE
Asserted to
WRITE
Deasserted
60
0
Deasserted to
Modified
Asserted to PD Hi-Z
WAIT
IOR
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
60
0
180
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Asserted to PD Hi-Z
Command Asserted to PD Valid
Command Deasserted to PD Hi-Z
0
60
1
190
WAIT Deasserted to PD Drive
WRITE Deasserted to Command
PBDIR Set to Command
0
20
30
PD Hi-Z to Command Asserted
Asserted to Command Asserted
0
0
195
180
12
60
10
0
WAIT Deasserted to Command Deasserted
Time out
PD Valid to WAIT Deasserted
PD Hi-Z to WAIT Deasserted
0
mS
Publication Release Date: March 1998
Revision 0.62
- 130 -
W83977TF
PRELIMINARY
12.3.5 EPP Data or Address Write Cycle Timing Parameters
PARAMETER
SYM.
MIN.
40
MAX.
UNIT
nS
t1
t2
IOW
Ax Valid to
Asserted
SD Valid to Asserted
10
10
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t3
IOW
Deasserted to Ax Invalid
t4
WAIT
Deasserted to IOCHRDY Deasserted
t5
10
40
0
WAIT
Command Asserted to
Deasserted
Asserted
t6
IOW
IOW
IOR
Deasserted to
or
t7
24
160
70
IOW
IOCHRDY Deasserted to
Deasserted
Asserted to Command Asserted
t8
60
0
WAIT
t9
IOW
WAIT
Asserted to
Asserted
Asserted
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
0
WRITE
PBDIR Low to
60
60
0
185
185
50
WAIT
WAIT
IOW
WRITE
Asserted to
Asserted to
Asserted
Change
WRITE
Asserted to PD Valid
0
WAIT
Asserted to PD Invalid
10
5
PD Invalid to Command Asserted
35
210
190
10
IOW
to Command Asserted
60
60
0
WAIT
Asserted to Command Asserted
WAIT Deasserted to Command Deasserted
m
S
Command Asserted to WAIT Deasserted
Time out
10
0
12
m
S
nS
nS
Command Deasserted to WAIT Asserted
0
IOW Deasserted to WRITE Deasserted and PD invalid
Publication Release Date: March 1998
Revision 0.62
- 131 -
W83977TF
PRELIMINARY
12.3.6 Parallel Port FIFO Timing Parameters
PARAMETER
SYMBOL
MIN.
600
MAX.
UNIT
nS
DATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
DATA Hold from nSTROBE Inactive
BUSY Inactive to PD Inactive
t1
t2
t3
t4
t5
t6
600
450
80
nS
nS
nS
nS
nS
BUSY Inactive to nSTROBE Active
nSTROBE Active to BUSY Active
680
500
12.3.7 ECP Parallel Port Forward Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
nAUTOFD Valid to nSTROBE Asserted
PD Valid to nSTROBE Asserted
t1
t2
t3
t4
t5
t6
t7
t8
0
0
60
60
nS
nS
nS
nS
nS
nS
nS
nS
BUSY Deasserted to nAUTOFD Changed
BUSY Deasserted to PD Changed
80
80
0
180
180
nSTROBE Deasserted to BUSY Deasserted
BUSY Deasserted to nSTROBE Asserted
nSTROBE Asserted to BUSY Asserted
BUSY Asserted to nSTROBE Deasserted
80
0
200
180
80
12.3.8 ECP Parallel Port Reverse Timing Parameters
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
PD Valid to nACK Asserted
t1
t2
t3
t4
0
0
0
0
nS
nS
nS
nS
nAUTOFD Deasserted to PD Changed
nAUTOFD Asserted to nACK Asserted
nAUTOFD Deasserted to nACK Deasserted
nACK Deasserted to nAUTOFD Asserted
PD Changed to nAUTOFD Deasserted
t5
t6
80
80
200
200
nS
nS
Publication Release Date: March 1998
Revision 0.62
- 132 -
W83977TF
PRELIMINARY
12.3.9 KBC Timing Parameters
NO.
T1
DESCRIPTION
MIN.
MAX.
UNIT
Address Setup Time from WRB
Address Setup Time from RDB
WRB Strobe Width
0
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
T2
T3
20
T4
RDB Strobe Width
20
0
T5
Address Hold Time from WRB
Address Hold Time from RDB
Data Setup Time
T6
0
T7
50
0
T8
Data Hold Time
T9
Gate Delay Time from WRB
RDB to Drive Data Delay
RDB to Floating Data Delay
Data Valid After Clock Falling (SEND)
K/B Clock Period
10
30
40
20
4
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
0
m
S
20
10
4
m
S
K/B Clock Pulse Width
m
S
Data Valid Before Clock Falling (RECEIVE)
K/B ACK After Finish Receiving
RC Fast Reset Pulse Delay (8 Mhz)
RC Pulse Width (8 Mhz)
Transmit Timeout
m
S
20
2
m
S
3
2
m
S
6
m
S
mS
Data Valid Hold Time
0
m
S
83
30
30
5
167
50
nS
-
Input Clock Period (6 12 Mhz)
Duration of CLK inactive
Duration of CLK active
m
S
50
m
S
Time from inactive CLK transition, used to time when
the auxiliary device sample DATA
25
m
S
T25
T26
T27
T28
T29
Time of inhibit mode
100
5
300
T28-5
50
mS
mS
Time from rising edge of CLK to DATA transition
Duration of CLK inactive
30
30
5
m
S
Duration of CLK active
50
m
S
Time from DATA transition to falling edge of CLK
25
m
S
Publication Release Date: March 1998
Revision 0.62
- 133 -
W83977TF
PRELIMINARY
12.3.10 GPIO Timing Parameters
SYMBOL
PARAMETER
Write data to GPIO update
MIN.
MIN.
MAX.
UNIT
tWGO
300(Note 1)
ns
Note : Refer to Microprocessor Interface Timing for Read Timing.
12.3.11 Keyboard/Mouse Timing Parameters
SYMBOL
tSWL
PARAMETER
MAX.
20
UNIT
ns
PANSWIN falling edge to PANSWOUT falling edge
tSWH
50
ns
PANSWIN
PANSWOUT
falling edge to
Hi-Z
tWKUPD
200
ns
KCLK/MCLK falling edge to PANSWOUT falling
edge delay
tWKUPW
0.5
1
sec
PANSWOUT
active pulse width
Publication Release Date: March 1998
Revision 0.62
- 134 -
W83977TF
PRELIMINARY
13.0 TIMING WAVEFORMS
13.1 FDC
Write Date
Processor Read Operation
WD
SA0-SA9
AEN
TWDD
CS
TAR
TRA
DACK
TRR
IOR
TDH
Index
TFD
TDF
D0-D7
IRQ
INDEX
TR
TIDX
TIDX
Processor Write Operation
Terminal Count
SA0-SA9
AEN
TC
TAW
TWA
DACK
IOW
TTC
TWW
TWD
Reset
TDW
D0-D7
IRQ
RESET
TWI
TRST
DMA Operation
Drive Seek operation
TAM
DRQ
DIR
TMCY
TAA
DACK
TMA
TSTP
TSTD
TDST
TMRW
IOW or
IOR
STEP
TMW (IOW)
TMR (IOR)
TSC
Publication Release Date: March 1998
Revision 0.62
- 135 -
W83977TF
PRELIMINARY
13.2 UART/Parallel
Receiver Timing
SIN
(RECEIVER
STAR
INPUT DATA)
DATA BITS
(5-8)
PARITY
STOP
TSINT
IRQ3 or IRQ4
IOR
TRINT
(READ RECEIVER
BUFFER REGISTER)
Transmitter Timing
SERIAL OUT
(SOUT)
STAR
STAR
TSTI
DATA
(5-8)
PARITY
STOP
(1-2)
THRS
THR
IRQ3 or IRQ4
THR
IOW
TSI
(WRITE THR)
TIR
IOR
(READ TIR)
Publication Release Date: March 1998
Revision 0.62
- 136 -
W83977TF
PRELIMINARY
13.2.1 Modem Control Timing
MODEM Control Timing
IOW
¢x
¢x
¢x
(WRITE MCR)
¢x
¢x
¢x
¢x
TMWO
¢x
TMWO
¡ ÷
¡ ÷ ¡ ö
¢¡x ö
¢x
RTS,DTR
¢x
¢x
¢x
¢x
¢x
¢x
¢
¢x
¢x
¢x
¢x
¢x
CTS,DSR
DCD
¢x
¢x
¡ ÷
TSIM
TSIM
¡ ö
¡ ö
¡ ÷
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
IRQ3 or
IRQ4
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¡ öTRIM
¢x
¢x
¢x
¢x
¡ öTRIM
¡ ÷
¡ ÷
¢x
¢x
¢x
¢x
IOR
(READ MSR)
TSIM
¡ ÷
¡ ö
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢
RI
Printer Interrupt Timing
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
¢x
ACK
¢x
TLAD
TLID
¢x
¡ ÷
¡ ö
¡ ÷
¢x¡ ö
¢x
¢x
¢x
¢x
¢x
¢x
¢x
IRQ7
Publication Release Date: March 1998
Revision 0.62
- 137 -
W83977TF
PRELIMINARY
13.3 Parallel Port
13.3.1 Parallel Port Timing
IOW
t1
INIT, STROBE
AUTOFD, SLCTIN
PD<0:7>
ACK
t2
IRQ (SPP)
IRQ
t3
t4
(EPP or ECP)
nFAULT
(ECP)
ERROR
(ECP)
t5
t2
t4
IRQ
Publication Release Date: March 1998
Revision 0.62
- 138 -
W83977TF
PRELIMINARY
13.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)
t3
A<0:10>
t1
t2
t4
IOR
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE
t16
t18
t19
t20
t17
t21
PD<0:7>
t22
t23
t25
t24
ADDRSTB
DATASTB
t27
t28
t26
WAIT
Publication Release Date: March 1998
Revision 0.62
- 139 -
W83977TF
PRELIMINARY
13.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)
t3
t4
A10-A0
SD<0:7>
t5
t1
t2
t6
IOW
IOCHRDY
t7
t8
t9
t10
t11
t12
t14
WRITE
t13
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t21
t20
WAIT
t22
PBDIR
Publication Release Date: March 1998
Revision 0.62
- 140 -
W83977TF
PRELIMINARY
13.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)
t3
A<0:10>
t1
t2
t4
IOR
t6
t7
SD<0:7>
t8
t9
t5
IOCHRDY
t10
t13
t14
t15
WRITE
t16
t18
t19
t20
t17
t21
PD<0:7>
t22
t23
t25
ADDRSTB
DATASTB
t24
t26
t28
t27
WAIT
Publication Release Date: March 1998
Revision 0.62
- 141 -
W83977TF
PRELIMINARY
13.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)
t3
t4
A10-A0
SD<0:7>
t5
t1
t2
t6
IOW
t7
t8
IOCHRDY
t9
t10
t11
t22
t22
WRITE
t13
PD<0:7>
t15
t16
t17
t18
DATAST
ADDRSTB
t19
t20
WAIT
13.3.6 Parallel Port FIFO Timing
t4
>|
t3
>|
PD<0:7>
t1
t2
t5
>|
>
>|
nSTROBE
t6
>|
BUSY
Publication Release Date: March 1998
Revision 0.62
- 142 -
W83977TF
PRELIMINARY
13.3.7 ECP Parallel Port Forward Timing
t3
t4
nAUTOFD
PD<0:7>
t1
t2
t6
t8
nSTROBE
t5
t5
t7
BUSY
13.3.8 ECP Parallel Port Reverse Timing
t2
PD<0:7>
t1
t3
t4
nACK
t5
t5
t6
nAUTOFD
Publication Release Date: March 1998
Revision 0.62
- 143 -
W83977TF
PRELIMINARY
13.4 KBC
13.4.1 Write Cycle Timing
A2, CSB
T1
T5
T3
WRB
ACTIVE
T7
T8
D0~D7
DATA IN
T9
GA20
OUTPUT PORT
T17
T18
FAST RESET PULSE RC
FE COMMAND
13.4.2 Read Cycle Timing
A2,CSB
AEN
T2
T6
T4
RDB
ACTIVE
T10
T11
D0-D7
DATA OUT
13.4.3 Send Data to K/B
CLOCK
(KCLK)
T12
T13
T16
T14
D3
SERIAL DATA
(KDAT)
D5
D4
D1
START
D2
D0
D6
D7
P
STOP
T19
Publication Release Date: March 1998
Revision 0.62
- 144 -
W83977TF
PRELIMINARY
13.4.4 Receive Data from K/B
CLOCK
(KCLK)
T14
T13
T15
SERIAL DATA
(T1)
D5
START
T20
D1
D2
D3
D4
D0
D6
D7
P
STOP
13.4.5 Input Clock
CLOCK
CLOCK
T21
13.4.6 Send Data to Mouse
MCLK
T25
T23
T24
T22
MDAT
START
Bit
D5
D1
D2
D3
D4
D0
D6
D7
P
STOP
Bit
13.4.7 Receive Data from Mouse
MCLK
T29
T26
D1
T27
T28
D3
MDAT
D5
START
D2
D4
D0
D6
D7
P
STOP
Bit
Publication Release Date: March 1998
Revision 0.62
- 145 -
W83977TF
PRELIMINARY
13.5 GPIO Write Timing Diagram
VALID
VALID
A0-A15
IOW
D0-7
GPIO10-17
GPIO20-25
PREVIOUS STATE
VALID
tWGO
13.6 Master Reset (MR) Timing
Vcc
MR
tVMR
13.7 Keyboard/Mouse Wake-up Timing
KCLK
MCLK
PANSWIN
tWKUPW
PANSWOUT
HI-Z
tWKUPD
tSWZ
tSWL
Publication Release Date: March 1998
Revision 0.62
- 146 -
W83977TF
PRELIMINARY
14.0 APPLICATION CIRCUITS
14.1 Parallel Port Extension FDD
JP13
13
WE2/SLCT
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
JP 13A
WD2/PE
DCH2
34
32
30
28
26
24
22
20
18
16
14
12
10
8
33
31
29
27
25
23
21
19
17
15
13
11
9
MOB2/BUSY
HEAD2
RDD2
WP2
DSB2/ACK
TRK02
WE2
PD7
WD2
PD6
STEP2
DIR2
PD5
MOB2
DSB2
IDX2
DCH2/PD4
RDD2/PD3
7
5
3
1
STEP2/SLIN
WP2/PD2
6
4
2
RWC2
DIR2/INIT
TRK02/PD1
EXT FDC
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
14.2 Parallel Port Extension 2FDD
JP13
13
25
12
WE2/SLCT
JP 13A
34
WD2/PE
DCH2
HEAD2
RDD2
WP2
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
33
MOB2/BUSY
32
30
28
26
24
22
20
18
16
14
12
10
8
31
29
27
25
23
21
19
17
15
13
11
9
DSB2/ACK
TRK02
DSA2/PD7
MOA2/PD6
WE2
WD2
STEP2
DIR2
PD5
MOB2
DSA2
DCH2/PD4
RDD2/PD3
DSB2
MOA2
IDX2
7
5
3
1
STEP2/SLIN
WP2/PD2
6
4
2
RWC2
DIR2/INIT
TRK02/PD1
15
2
14
1
EXT FDC
HEAD2/ERR
IDX2/PD0
RWC2/AFD
STB
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
Publication Release Date: March 1998
Revision 0.62
- 147 -
W83977TF
PRELIMINARY
14.3 Four FDD Mode
74LS139
G1
7407(2)
W83977F
1Y0
1Y1
DSA
DSB
DSC
DSD
MOA
DSA
DSB
A1
B1
1Y2
1Y3
2Y0
2Y1
MOA
MOB
MOB
MOC
MOD
G2
2Y2
2Y3
A2
B2
15.0 ORDERING INFORMATION
PART NO.
W83977TF-P
W83977TF-A
W83977TF-PW
W83977TF-AW
KBC FIRMWARE
Phoenix MultiKey/42TM
AMIKEYTM-2
Phoenix MultiKey/42TM
AMIKEYTM-2
REMARKS
with OnNow / security keyboard wake-up
with OnNow / security keyboard wake-up
16.0 HOW TO READ THE TOP MARKING
Example: The top marking of W83977TF-A
inbond
W83977TF-A
ã AM. MEGA. 87-96
730AC2722968SA
1st line: Winbond logo
2nd line: the type number: W83977TF-A
3rd line: the source of KBC F/W -- American Megatrends IncorporatedTM
4th line: the tracking code
730 A C 2 722968 SA
730: packages made in '97, week 30
A: assembly house ID; A means ASE, S means SPIL.... etc.
C: IC revision; B means version B, C means version C
2: wafers manufactured in Winbond FAB 2
722968: wafer production series lot number
SA: if made by 0.5-um process: SA; otherwise by 0.6-um process: blank
Publication Release Date: March 1998
Revision 0.62
- 148 -
W83977TF
PRELIMINARY
17.0 PACKAGE DIMENSIONS
(128-pin PQFP)
Dimension in mm
Dimension in inch
H E
E
Symbol
Min Nom Max
Min
0.25
2.57
Nom
0.35
Max
0.45
2.87
65
102
0.010
0.101
0.014
0.107
0.018
0.113
1
A
2.72
2
A
64
103
0.10
0.10
0.20
0.15
0.30
0.20
0.004 0.008
0.012
b
c
0.004 0.006 0.008
13.90
19.90
14.00
20.00
0.50
14.10
20.10
0.547
0.551
0.555
0.791
D
E
e
0.783 0.787
0.020
HD
D
H
D
17.20
23.20
0.669
0.677 0.685
0.921
17.40
23.40
0.95
17.00
23.00
0.905 0.913
HE
L
L
0.80
1.60
0.025
0
0.031 0.037
0.063
0.65
39
128
1
0.08
7
y
0.003
7
1
38
e
b
0
0
c
Note:
A
1.Dimension D & E do not include interlead
flash.
2
1
A
2.Dimension b does not include dambar
protrusion/intrusion
.
3.Controlling dimension : Millimeter
4.General appearance spec. should be based
on final visual inspection spec.
A
See Detail F
Seating Plane
L
y
L 1
Detail F
5. PCB layout please use the "mm".
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
original owners.
Publication Release Date: March 1998
- 149 -
Revision 0.62
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