W49L401TT70B_技术文档

W49L401(T)

´ 16 CMOS FLASH MEMORY

256K

1. GENERAL DESCRIPTION

The W49L401(T) is a 4-megabit, 3.3-volt only CMOS flash memory organized as 256K ´ 16 bits. The

device can be programmed and erased in-system with a standard 3.3-volt power supply. A 12-volt VPP

is not required. The unique cell architecture of the W49L401(T) results in fast program/erase

operations with extremely low current consumption (compared to other comparable 3.3-volt flash

memory products). The device can also be programmed and erased using standard EPROM

programmers.

2. FEATURES

· Single Voltage operations:

· Optional Uniform Page configuration

· Low power consumption

- 3.0 - 3.6V Read/Erase/Program

· Fast Program operation:

- Active current: 10 mA (typ.)

- Standby current: 5 mA (typ.)

- Word-by-Word programming: 30 mS (typ.)

· Fast Erase operation:

· Automatic program and erase timing with

- Page/Block Erase time: 50 mS (typ.)

- Chip Erase time: 200 mS (typ.)

· Fast Read access time: 70 nS

· Endurance: 10K cycles (typ.)

· Twenty-year data retention

· Hardware data protection

· Block configuration

internal VPP generation

· End of program or erase detection

- Toggle bit

- Data polling

· RY/#BY open-drain output provides hardware

end-of-write detection

· Hardware #RESET pin

· Latched address and data

-

One 8K-word boot block with lockout

protection

· TTL compatible I/O

-

Two 4K-word parameter blocks

· JEDEC standard word-wide pinouts

· Available packages: 44-pin SOP, 48-pin TSOP

One 16K-word main memory array block

Seven 32K-word main memory array blocks

128 uniform 2K-word pages

Publication Release Date: August 16, 2002

- 1 -

Revision A4

W49L401(T)

3. PIN CONFIGURATIONS

4. BLOCK DIAGRAM

RY/#BY

#CE

DQ0

#RESET

.

NC

RY/#BY

A17

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

OUTPUT

.

CONTROL

2

#WE

A8

A9

A10

A11

A12

BUFFER

#OE

#WE

DQ15

3

4

A7

5

#RESET

A6

A5

A4

A3

A2

A1

A0

#CE

SS

V

6

W49L401

3FFFF

W49L401T

3FFFF

7

8

MAIN MEMORY

A13

A14

A15

A16

NC

240K WORDS

(1x16K WORDS

7x32K WORDS)

9

44-pin

SOP

BOOT BLOCK

8K WORDS

10

11

12

13

14

15

16

17

18

19

20

A0

3E000

3DFFF

04000

03FFF

D

E

C

O

D

E

R

PARAMETER

BLOCK2

PARAMETER

BLOCK1

.

SS

V

4K WORDS

#OE

DQ0

DQ8

DQ1

4K WORDS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

03000

02FFF

3D000

3CFFF

PARAMETER

BLOCK2

PARAMETER

BLOCK1

A17

4K WORDS

DQ9

DQ2

DQ10

DQ3

3C000

3BFFF

02000

01FFF

26

25

BOOT BLOCK

8K WORDS

MAIN MEMORY

240K WORDS

DQ12

00000

24

23

DQ4

V^DD

21

22

(1x16K WORDS

7x32K WORDS)

DQ11

00000

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A15

A14

A13

A12

A11

A10

1

A16

NC

SS

V

2

3

4

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V^DD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

5

5. PIN DESCRIPTION

SYMBOL

6

7

A9

A8

8

PIN NAME

9

48-pin

TSOP

NC

#WE

#RESET

NC

RY/#BY

NC

10

11

12

13

14

15

16

17

18

19

20

#RESET

RY/#BY

A0 - A17

DQ0 - DQ15

#CE

Reset

Ready/#Busy Output

Address Inputs

Data Inputs/Outputs

Chip Enable

A17

A7

A6

A5

A4

A3

A2

A1

#OE

VSS

21

#OE

Output Enable

Write Enable

22

23

24

#CE

A0

#WE

VDD

Power Supply

Ground

VSS

NC

No Connection

- 2 -

W49L401(T)

6. FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49L401(T) is controlled by #CE and #OE, both of which have to be low for

the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip

is de-selected and only standby power will be consumed. #OE is the output control and is used to gate

data to the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer

to the timing waveforms for further details.

Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the device

is in normal operation mode. When #RESET pin is driven low for at least a period of TRP, it will halt the

device and all outputs are at high impedance state. The device also resets the internal state machine

to read array data. The operation that was interrupted should be reinitiated once the device is ready to

accept another command sequence to assure data integrity. As the high state re-asserted to the

#RESET pin, the device will return to read or standby mode, it depends on the control signals. The

system can read data T

after the #RESET pin returns to VIH. The other function for #RESET pin is

RH

temporary reset the boot block. By applying the 12V to #RESET pin, the boot block can be

reprogrammed even though the boot block lockout function is enabled.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in

the first 8K words (for W49L401T, located in the last 8K words) of the memory with the address range

from 0000(hex) to 1FFF(hex). (for W49L401T, address range from 3E000h to 3FFFFh)

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set, the

data for the designated block cannot be erased or programmed (programming lockout); the regular

programming method can change the data in other memory locations.

There is one condition that the lockout feature can be over-ridden. Just apply 12V to #RESET pin, the

lockout feature will temporarily be inactivated and the boot block can be erased/programmed. Once the

#RESET pin returns to CMOS/TTL level, the lockout feature will be activated again.

In order to detect whether the boot block feature is set on the 8K-words block, users can perform

software command sequence: enter the product identification mode (see Command Codes for

Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex".

If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the output

data in DQ0 is "0", the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed in a fast 200 mS (typical). The host system is not required to provide any control or timing

during this operation. The entire memory array will be erased to FFFF(hex) by the chip erase operation

if the boot block programming lockout feature is not activated. Once the boot block lockout feature is

activated, the chip erase function will erase all the blocks/pages except the boot block.

Publication Release Date: August 16, 2002

- 3 -

Revision A4

W49L401(T)

Block/Page Erase Operation

The W49L401(T) provides both uniform small page (2K-word) and non-symmetrical block

(4K/8K/16K/32K-word) erase capabilities for versatile Flash applications.

Each block or page can be erased individually by initiating a six-word command sequence. The block

address (BA) or page address (PA) is latched on the falling #WE edge of the sixth cycle while the

XX30/XX50(hex) data input command is latched at the rising edge of #WE. After the command loading

cycle, the device enters the internal block/page erase mode, which is automatically timed and will be

completed in a fast 50 mS (typical). The host system is not required to provide any control or timing

during this operation. The device will automatically return to normal read mode after the erase

operation completed. Data-polling, Toggle-Bit and/or RY/#BY pin can be used to detect end of erase

cycle.

The bootblock (8K-words) consists of 4 corresponding uniform pages of 2K-words each. When the

boot block lockout feature is activated, any page/block erase command with the associated PA/BA

within the bootblock address range (0000-01FFF for W49L401, and 3E000-3FFFF for W49L401T) will

be ignored and the device will return to read mode without any data changes.

Program Operation

The W49L401(T) is programmed on a word-by-word basis. Program operation can only change logical

data "1" to logical data "0" The erase operation (changed entire data in individual page/block or whole

chip from "0" to "1") is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word

Programming). The device will internally enter the program operation immediately after the word-

program command is entered. The internal program timer will automatically time-out (50 mS max. -

TBP) once completed and return to normal read mode. Data_polling, Toggle_Bit and/or RY/#BY pin

can be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49L401(T) is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 10 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming operation and read are inhibited when VDD is

less than 1.8V typical.

(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out

10 mS before any write (erase/program) operation.

Data Polling (DQ7)- Write Status Detection

The W49L401(T) includes a data polling feature to indicate the end of a program or erase cycle.

When the W49L401(T) is in the internal program or erase cycle, any attempt to read DQ7 of the last

word loaded will receive the complement of the true data. Once the program or erase cycle is

completed, DQ7 will show the true data. Note that, DQ7 will show logical "0" during the erase cycle.

And it will become logical "1" or true data when the erase cycle is completed.

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49L401(T) provides another method for determining the end of a

program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will

- 4 -

W49L401(T)

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between

0's and 1's will stop. The device is then ready for the next operation.

Ready/#Busy

The W49L401(T) also provides the hardware method to detect the completion of program/erase cycle .

The RY/#BY output pin will be asserted low (busy) during programming/erasing operations, and will be

released to high state by an external pull-up (ready) when internal program/erase cycle is completed.

This is an open-drain output pin for easy external connection.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment

automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the

software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the

product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from

address 0001(hex) outputs the device code, 003D(hex) for bottom boot (and TBD for top boot). The

product ID operation can be terminated by a three-word command sequence or an alternative one-

word command sequence (see Command Definition table).

In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE

high, and raising A9 to VHH (12V ⁺/_-0.5V).

Table of Operating Modes

Operating Mode Selection

(VHH = 12V

± 0.5V)

PINS

ADDRESS

MODE

#CE

VIL

VIH

X

#OE

VIL

VIH

X

#WE

VIH

VIL

X

#RESET

VIH

DQ.

Read

AIN

X

Dout

Erase/Program

Standby

VIH

Din

VIH

High Z

X

VIH

X

Erase/Program

Inhibit

VIL

X

VIH

X

High Z/DOUT

High Z

X

VIH

X

VIH

X

Output Disable

Product ID

Reset

X

VIH

X

A0 = VIL;

A1- A15 = VIL;

A9 = VHH

Manufacturer Code

00DA (Hex)

VIL

X

VIL

X

VIH

X

VIH

VIL

Device Code

003D (Hex) for bottom

A0 = VIH;

A1 - A15 = VIL;

A9 = VHH

TBD for Top

High Z

X

Publication Release Date: August 16, 2002

Revision A4

- 5 -

W49L401(T)

Table of Software Command Definition

NO. OF

1ST CYCLE

Addr. Data

2ND CYCLE

Addr. Data

3RD CYCLE

Addr. Data

4TH CYCLE

Addr. Data

5TH CYCLE

Addr. Data

6TH CYCLE

Addr. Data

COMMAND

Cycles

DESCRIPTION

Chip Erase

6

4

6

3

1

5555

XXXX

AA 2AAA

55 5555

80 5555

AA 2AAA

55 5555

10

30

50

Block Erase

AA 2AAA

F0

55 5555

80 5555

A0 A_IN

80 5555

90

AA 2AAA

D_IN

55 BA(5)

55 PA(4)

Page Erase

Word Program

Boot Block Lockout

Product ID Entry

Product ID Exit ⁽¹⁾

Notes:

AA 2AAA

55 5555

40

F0

1. Address Format: A14 - A0 (Hex); Data Format: DQ15 - DQ8 (Don't Care); DQ7 - DQ0 (Hex)

2. If any invalid command or read cycle (both #CE & #OE are active low) is inserted during any of the above software command

sequence, it will abort the operation and the device return to read mode.

3. Either one of the two Product ID Exit commands can be used, and Read mode is resumed after this command executed.

4. PA: Page Address

W49L401

W49L401T

PA = 00000h to 007FFh for Page0

PA = 00800h to 00FFFh for Page1

PA = 01000h to 017FFh for Page2

PA = 01800h to 01FFFh for Page3

PA = 02000h to 027FFh for Page4

PA = 02800h to 02FFFh for Page5

…

PA = 3F800h to 3FFFFh for Page0

PA = 3F000h to 3F7FFh for Page1

PA = 3E800h to 3EFFFh for Page2

PA = 3E000h to 3E7FFh for Page3

PA = 3D800h to 3DFFFh for Page4

PA = 3D000h to 3D7FFh for Page5

…

PA = 3D000h to 3D7FFh for Page122

PA = 3D800h to 3DFFFh for Page123

PA = 3E000h to 3E7FFh for Page124

PA = 3E800h to 3EFFFh for Page125

PA = 3F000h to 3F7FFh for Page126

PA = 3F800h to 3FFFFh for Page127

PA = 02800h to 02FFFh for Page122

PA = 02000h to 027FFh for Page123

PA = 01800h to 01FFFh for Page123

PA = 01000h to 017FFh for Page125

PA = 00800h to 00FFFh for Page126

PA = 00000h to 007FFh for Page127

5. BA: Block Address

W49L401

W49L401T

BA = 00000h to 01FFFh for Boot Block (8KW)

BA = 02XXXh for Parameter Block1 (4KW)

BA = 3E000h to 3FFFFh for Boot Block (8KW)

BA = 3DXXXh for Parameter Block1 (4KW)

BA = 03XXXh for Parameter Block2 (4KW)

BA = 3CXXXh for Parameter Block2 (4KW)

BA = 04000h to 07FFFh for Main Memory Block1 (16KW)

BA = 08000h to 0FFFFh for Main Memory Block2 (32KW)

BA = 10000h to 17FFFh for Main Memory Block3 (32KW)

BA = 18000h to 1FFFFh for Main Memory Block4 (32KW)

BA = 20000h to 27FFFh for Main Memory Block5 (32KW)

BA = 28000h to 2FFFFh for Main Memory Block6 (32KW)

BA = 30000h to 37FFFh for Main Memory Block7 (32KW)

BA = 38000h to 3FFFFh for Main Memory Block8 (32KW)

BA = 38000h to 3BFFFh for Main Memory Block1 (16KW)

BA = 30000h to 37FFFh for Main Memory Block2 (32KW)

BA = 28000h to 2FFFFh for Main Memory Block2 (32KW)

BA = 20000h to 27FFFh for Main Memory Block3 (32KW)

BA = 18000h to 1FFFFh for Main Memory Block4 (32KW)

BA = 10000h to 17FFFh for Main Memory Block5 (32KW)

BA = 08000h to 07FFFh for Main Memory Block7 (32KW)

BA = 00000h to 07FFFh for Main Memory Block8 (32KW)

- 6 -

W49L401(T)

Embedded Programming Algorithm

Start

Write Program Command Sequence

(see below)

#Data Polling/ Toggle bit

EC SEC

Pause T /T

No

Last Address

?

Increment Address

Yes

Programming Completed

Program Command Sequence (Address/Command):

5555H/AAH

2AAAH/55H

5555H/A0H

Program Address/Program Data

Publication Release Date: August 16, 2002

Revision A4

- 7 -

W49L401(T)

Embedded Erase Algorithm

Start

Write Erase Command Sequence

(see below)

#Data Polling or Toggle

Successfully Completed

Pause

T EC /TSEC

Bit

Erasure Completed

Chip Erase Command Sequence

Individual PageErase

Command Sequence

(Address/Command):

Individual BlockErase

Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/80H

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/10H

5555H/AAH

2AAAH/55H

5555H/AAH

2AAAH/55H

PageAddress/50H

Block Address/30H

- 8 -

W49L401(T)

Embedded #Data Polling Algorithm

Start

VA = Byte address for programming

Read Byte

= Any of the sector addresses within

the sector being erased during sector

erase operation

= Valid address equals any sector group

address during chip erase

(DQ0 - DQ7)

Address = VA

No

DQ7 = Data

?

Yes

Pass

Embedded Toggle Bit Algorithm

Start

Read Byte

(DQ0 - DQ7)

Address = Don't Care

Yes

DQ6 = Toggle

?

No

Pass

Publication Release Date: August 16, 2002

Revision A4

- 9 -

W49L401(T)

Software Product Identification and Boot Block Lockout Detection Acquisition

Flow

Product

Identification

Entry (1)

Product

Identification Exit(6)

Identification

and Boot Block

Lockout Detection

Mode (3)

Load data AA

to

address 5555

Load data AA

to

address 5555

(2)

Load data 55

to

address 2AAA

Load data 55

to

Read address = 0000

data = 00DA

address 2AAA

Load data 90

Load data F0

to

address 5555

Read address = 0001

data = 003D for bottom

to

address 5555

TBD for top

(4)

Pause 10 S

m

Pause 10

S

m

Read address = 0002

data in DQ0 =1/0

(5)

Normal Mode

- 10 -

W49L401(T)

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Pause 200 mS

Exit

Publication Release Date: August 16, 2002

Revision A4

- 11 -

W49L401(T)

7. DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

V

Power Supply Voltage to Vss Potential

-0.5 to +4.6

0 to +70

Operating Temperature

°C

V

Storage Temperature

-65 to +150

D.C. Voltage on Any Pin to Ground Potential except A9 or #RESET

Transient Voltage (<20 nS) on Any Pin to Ground Potential

Voltage on A9 or #RESET Pin to Ground Potential

-0.5 to VDD +1.0

-1.0 to VDD +1.0

-0.5 to 12.5

V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DC Operating Characteristics

(VDD = 3.0 ~ 3.6V, VSS = 0V, TA = 0 to 70° C)

LIMITS

PARAMETER

SYM.

TEST CONDITIONS

UNIT

MIN. TYP. MAX.

#CE = #OE = VIL, #WE = VIH,

all DQs open

mA

VDD Current - Read

ICC

-

10

20

Address inputs = VIL/VIH, at f = 5 MHz

VDD Current - Write

Standby VDD

ICCW #CE = #WE = VIL, #OE = VIH

ISB1 #CE = VIH, all DQs open

Other inputs = VIL/VIH

-

15

-

25

1

mA

Current (TTL input)

Standby VDD Current

(CMOS input)

#CE = VDD -0.3V, all DQs open

ISB2

-

5

-

50

10

Other inputs = VDD -0.3V / VSS

Input Leakage

Current

ILI

VIN = VSS to VDD

mA

Output Leakage

Current

ILO VOUT = VSS to VDD

-

10

mA

V

Input Low Voltage

Input High Voltage

VIL

VIH

-

-0.2

2.0

0.8

VDD

+0.3

-

V

Output Low Voltage

Output High Voltage

VOL IOL = 2.1 mA

VOH IOH = -0.4 mA

-

0.45

-

V

2.4

- 12 -

W49L401(T)

Power-up Timing

PARAMETER

SYMBOL

TPU. READ

TPU. WRITE

TYPICAL

200

UNIT

mS

Power-up to Read Operation

Power-up to Write Operation

10

mS

Capacitance

(VDD = 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER

I/O Pin Capacitance

Input Capacitance

SYMBOL

CI/O

CONDITIONS

VI/O = 0V

MAX.

12

UNIT

pf

CIN

VIN = 0V

6

pf

8. AC CHARACTERISTICS

AC Test Conditions

PARAMETER

Input Pulse Levels

CONDITIONS

0V to 0.9 VDD

< 5 nS

Input Rise/Fall Time

Input/Output Timing Level

Output Load

1.5V/1.5V

1 TTL Gate and CL = 30 pF

AC Test Load and Waveform

+3.3V

1.8K

W

D_OUT

30 pF

(Including Jig and Scope)

1.3K

W

Input

Output

0.9V

DD

1.5V

0V

Test Point

Publication Release Date: August 16, 2002

Revision A4

- 13 -

W49L401(T)

AC Characteristics, continued

Read Cycle Timing Parameters

(VDD = 3.0 ~ 3.6V, VSS = 0V, TA = 0 to 70° C)

70 nS

PARAMETER

SYMBOL

UNIT

MAX.

MIN.

Read Cycle Time

TRC

70

-

nS

Chip Enable Access Time

Address Access Time

TCE

70

35

-

TAA

-

Output Enable Access Time

#CE Low to Active Output

#OE Low to Active Output

#CE High to High-Z Output

#OE High to High-Z Output

Output Hold from Address Change

TOE

-

TCLZ

TOLZ

TCHZ

TOHZ

TOH

0

-

25

-

0

Note: The parameter of TCLZ, TOLZ, TCHZ, TOHZ are characterized only and is not 100% tested.

Write Cycle Timing Parameters

PARAMETER

Address Setup Time

SYMBOL

TAS

MIN.

10

100

10

0

TYP.

MAX.

UNIT

nS

-

Address Hold Time

#WE and #CE Setup Time

#WE and #CE Hold Time

#OE High Setup Time

#OE High Hold Time

#CE Pulse Width

TAH

-

nS

TCS

-

nS

TCH

-

nS

TOES

TOEH

TCP

-

nS

100

50

100

10

-

nS

#WE Pulse Width

TWP

TWPH

TDS

-

nS

#WE High Width

-

nS

Data Setup Time

-

nS

Data Hold Time

TDH

-

nS

Word programming Time

Page Erase Cycle Time

Block Erase Cycle Time

Chip Erase Cycle Time

TBP

30

25

100

50

200

mS

TPEC

TBEC

TEC

-

mS

-

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.

- 14 -

W49L401(T)

AC Characteristics, continued

Data Polling and Toggle Bit Timing Parameters

70 nS

PARAMETER

SYM.

UNIT

MAX.

MIN.

#OE to Data Polling Output Delay

#CE to Data Polling Output Delay

TOEP

TCEP

-

35

70

nS

#WE High to #OE Low for Data Polling

TOEHP

100

-

nS

#OE to Toggle Bit Output Delay

#CE to Toggle Bit Output Delay

#WE High to #OE Low for Toggle Bit

TOET

TCET

-

35

70

-

nS

TOEHT

100

Hardware Reset Timing Parameters

PARAMETER

#RESET Pulse Width

SYM.

TRP

MIN.

500

50

MAX.

UNIT

nS

-

#RESET High Time Before Read (1)

TRH

mS

Note: 1. The parameters are characterized only and is not 100% tested.

Publication Release Date: August 16, 2002

Revision A4

- 15 -

W49L401(T)

9. TIMING WAVEFORMS

Read Cycle Timing Diagram

T

RC

Address A17-0

#CE

T_CE

T_OE

#OE

T_OHZ

TOLZ

V

IH

#WE

T_CLZ

T

OH

T_CHZ

High-Z

DQ15-0

Data Valid

AA

T

#WE Controlled Command Write Cycle Timing Diagram

T_AS

T_AH

Address A17-0

#CE

T_CS

T_CH

T_OEH

T_OES

#OE

#WE

T_WP

T_WPH

T_DS

DQ15-0

Data Valid

T_DH

- 16 -

W49L401(T)

Timing Waveforms, continued

#CE Controlled Command Write Cycle Timing Diagram

AS

T

TAH

Address A17-0

#CE

TCPH

T

CP

T

OES

TOEH

#OE

#WE

T

DS

High Z

DQ15-0

Data Valid

TDH

Program Cycle Timing Diagram

Word Program Cycle

5555 Address

2AAA

Address A17-0

DQ15-0

5555

XX55

XXA0

Data-In

XXAA

#CE

*

#OE

#WE

T

WPH

BP

T

WP

T

Internal Write Start

Word 0

Word 1

Word 2

Word 3

*Note: It is not allowed to assert read operation(#CE & #OE are both active) during the

command sequence. If read command is asserted during the command

sequence, then the device will return to read mode (abort write).

Publication Release Date: August 16, 2002

Revision A4

- 17 -

W49L401(T)

Timing Waveforms, continued

#DATA Polling Timing Diagram

Address A17-0

#WE

An

T

CEP

#CE

#OE

T

OEHP

T

OEP

DQ7

X

T

BP, EC, BEC or PEC

Toggle Bit Timing Diagram

Address A17-0

#WE

T

CET

#CE

T

OET

#OE

DQ6

T

OEHT

T

BP, EC, BEC or PEC

- 18 -

W49L401(T)

Timing Waveforms, continued

Boot Block Lockout Enable Timing Diagram

Six-word code for Boot Block

Lockout Feature Enable

Address A17-0

5555

2AAA

XX55

5555

2AAA

XX55

DQ15-0

#CE

XX80

XXAA

XX40

XXAA

#OE

WP

T

200uS

#WE

WPH

T

SW0

SW23

SW3

SW5

SW4

SW1

*Note: It is not allowed to assert read operation(#CE & #OE are both active) during the

command sequence. If read command is asserted during the command

sequence, then the device will return to read mode(abort write).

Chip Erase Timing Diagram

Six-word code for 3.3V-only software

chip erase

Address A17-0

5555

2AAA

XX55

5555

2AAA

XX55

DQ15-0

XX80

XXAA

XX10

XXAA

#CE

#OE

T

WP

T

EC

#WE

T

WPH

Internal Erase starts

SW0

SW2

SW3

SW5

SW4

SW1

Publication Release Date: August 16, 2002

Revision A4

- 19 -

W49L401(T)

Timing Waveforms, continued

Block/Page Erase Timing Diagram

Six-word code for 3.3V-only software

Block/Page Erase

XX555

XXAA

XX2AA

XX55

XX555

XXAA

XX2AA

XX55

BA

PA

Address A17-0

DQ15-0

#CE

XX80

XX30

XX50

#OE

T

WP

T

PEC

BEC or

#WE

T

WPH

Internal Erase starts

SW0

SW2

SW3

SW5

SW4

SW1

*Note: It is not allowed to assert read operation(#CE & #OE are both active) during

command sequence. If read command is asserted during the comma

sequence, then the device will return to read mode(abort writ

BA = Block Address; PA = Page Address

Ready/#Busy Timing Diagram

Address A17-0

An

#WE

#CE

T_CEP

T_OEHP

T_OES

#OE

T_OEP

DQ15-DQ0

invalid

X

PD

X

Program/Erase in Progress

tRB

tBUSY

RY/#BY

- 20 -

W49L401(T)

Timing Waveforms, continued

Reset Timing Diagram

#CE

#OE

T

RH

#RESET

T

RP

Publication Release Date: August 16, 2002

Revision A4

- 21 -

W49L401(T)

10. ORDERING INFORMATION

ACCESS TIME

PART NO.

OPERATING

VOLTAGE (V)

BOOT BLOCK

LOCATION

PACKAGE

(nS)

70

W49L401S-70B

W49L401T-70B

W49L401TS70B

W49L401TT70B

3.0 ~ 3.6

BOTTOM

TOP

44-pin SOP

70

3.0 ~ 3.6

48-pin TSOP (12 mm ´ 20 mm)

44-pin SOP

70

3.0 ~ 3.6

70

3.0 ~ 3.6

TOP

48-pin TSOP (12 mm ´ 20 mm)

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

11. HOW TO READ THE TOP MARKING

Example: The top marking of 48-pin TSOP W49L401T-70B

W49L401T-

70B

2138977A-A12

149OBAA

1^stline: winbond logo

2^ndline: the part number: W49L401T-70B

3^rdline: the lot number

4^thline: the tracking code: 149 O B AA

149: Packages made in 0’ 1, week 49

O: Assembly house ID: A means ASE, O means OSE, ... etc.

B: IC revision; A means version A, B means version B, ... etc.

AA: Process code

- 22 -

W49L401(T)

12. PACKAGE DIMENSIONS

48-pin TSOP (12 mm

´ 20 mm)

1

48

Dimension in mm

Dimension in Inches

Symbol

MIN.

NOM.

NOM. MAX.

0.047

MAX.

1.20

MIN.

e

b

A

0.05

0.95

18.3

19.8

11.9

0.002

A1

A2

D

1.00 1.05 0.037 0.039 0.041

E

18.4 18.5

20.0 20.2

0.724 0.728

0.720

0.780 0.787 0.795

HD

E

12.1

0.476

12.0

0.468

0.472

0.009

0.011

0.008

b

c

0.17

0.10

0.22 0.27 0.007

0.21 0.004

0.50

c

0.020

e

D

0.024

0.031

H_D

0.50

0

L

0.60

0.80

0.70 0.020

0.028

A2

A1

L1

Y

A

0.10

0.004

5

q

L

0

5

q

L1

Y

44-pin SOP

44

23

L

Dimension in mm

Dimension in Inches

L1

Symbol

A

MIN. NOM. MAX. MIN. NOM. MAX.

3.00

2.82

0.118

0.004

0.089

0.014

0.10

2.26

A1

A2

b

E

H

E

0.111

0.020

0.016

0.36

0.41

0.15

0.50

0.21

0.10

0.004 0.006 0.008

1.105 1.110 1.115

0.516 0.524 0.531

0.622 0.630 0.638

c

28.07

13.10

15.80

1.12

28.32

D

28.19

c

1

22

E

13.30 13.50

16.00 16.20

q

HE

e

1.27

1.42

1.00

0.044 0.050 0.056

0.024 0.032 0.040

0.053

D

L

0.60

0.80

1.35

L1

Y

A2

A

0.10

7

Y

0.004

SEATING PLANE

e

A1

0

q

7

b

Publication Release Date: August 16, 2002

Revision A4

- 23 -

W49L401(T)

13. VERSION HISTORY

VERSION

DATE

Apr. 2001

PAGE

DESCRIPTION

A1

A2

A3

-

18

Initial Issued

July 2001

Change TRH from 50 nS to 10 mS

January 2, 2002

1, 3, 6, 15

18

Delete the description of Auto-Power Saving

Change TRH from 10 mS to 30 mS (min.)

Change TEC from 200/1000 to 100/200 mS (typ./max.)

Change TPEC, TPBC from 50/200 to 25/50 mS (typ./max.)

17

1, 18, 19, 26 Delete read access time of 55 nS

26 Add HOW TO READ THE TOP MARKING

9, 10, 11, 12, 13 Delete old flow chart and add embedded algorithm

Modify VDD Power Up/Down Detection in Hardware

Data Protection

4

21

9 - 13

23

Modify Program Cycle Timing Diagram

Modify Flow charts

A4

August 16, 2002

Modify Reset Timing Diagram

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

2727 North First Street, San Jose,

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

200336 China

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

TEL: 86-21-62365999

FAX: 86-21-62365998

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

FAX: 81-45-4781800

TEL: 852-27513100

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

- 24 -


型号：	W49L401TT70B
厂家：	WINBOND
描述：	Flash, 256KX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48 光电二极管内存集成电路
文件：	总24页 (文件大小：307K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W49L401TT70B [WINBOND]

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