W49V002 [WINBOND]
256K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE; 256K ×8 CMOS闪光灯FWH接口存储器
| 型号： | W49V002 |
| 厂家： | 
WINBOND |
| 描述： | 256K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE |
| 文件： | 总32页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W49V002FA
256K
´ 8 CMOS FLASH MEMORY
WITH FWH INTERFACE
GENERAL DESCRIPTION
The W49V002FA is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K ´ 8 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49V002FA results in fast program/erase operations
with extremely low current consumption. This device can operate at two modes, Programmer bus
interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the
traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device
complies with the Intel FWH specification. The device can also be programmed and erased using
standard EPROM programmers.
FEATURES
· Single 3.3-volt operations:
- 3.3-volt Read
· Two 8K bytes Parameter Blocks
· Four main memory blocks (with 32K bytes, 64K
bytes, 64K bytes, 64K bytes each)
- 3.3-volt Erase
· Low power consumption
- 3.3-volt Program
- Active current: 40 mA (typ. for FWH)
· Fast program operation:
- Byte-by-byte programming: 50 mS (typ.)
· Fast erase operation: 150 mS (typ.)
· Fast read access time: Tkq 11 nS
· Endurance: 10K cycles (typ.)
· Twenty-year data retention
· Automatic program and erase timing with
internal VPP generation
· End of program or erase detection
- Toggle bit
- Data polling
· Latched address and data
· TTL compatible I/O
· Hardware data protection
- #TBL & #WP serve as hardware protection
· Available packages: 32L PLCC, 32L STSOP
· One 16K bytes Boot Block with lockout
protection
Publication Release Date: February 19, 2002
- 1 -
Revision A2
W49V002FA
PIN CONFIGURATIONS
BLOCK DIAGRAM
#WP
#TBL
3FFFF
BOOT BLOCK
16K BYTES
3C000
3BFFF
CLK
Interface
FWH[3:0]
PARAMETER
BLOCK1
8K BYTES
3A000
39FFF
FWH4
IC
PARAMETER
BLOCK2
8K BYTES
38000
37FFF
#RESET
#INIT
MAIN MEMORY
BLOCK1
32K BYTES
A
1
0
^
F
G
P
I
4
v
A
9
^
F
G
P
I
3
v
A
8
^
F
G
P
I
2
v
R
#
30000
2FFFF
#
R
E
S
E
T
C
^
R/#C
MAIN MEMORY
BLOCK2
64K BYTES
C
L
K
v
A[10:0]
V
D
D
N
C
Program-
20000
1FFFF
mer
DQ[7:0]
MAIN MEMORY
BLOCK3
64K BYTES
Interface
4
3
2
1
32 31 30
#OE
#WE
10000
0FFFF
MAIN MEMORY
BLOCK4
64K BYTES
A7(FGPI1)
A6(FGPI0)
A5(#WP)
A4(#TBL)
A3(ID3)
5
6
29
28
27
26
25
24
23
22
21
IC
GND
NC
00000
7
8
32L
GND
9
PLCC
VDD
10
11
12
13
#OE(#INIT)
#WE(FWH4)
NC
A2(ID2)
A1(ID1)
PIN DESCRIPTION
A0(ID0)
SYM.
INTERFACE
PGM FWH
PIN NAME
DQ0(FWH0)
DQ7(RSV)
14 15 16 17 18 19 20
D
Q
1
D
Q
2
D
Q
5
D
Q
3
D
Q
4
D
Q
6
G
N
D
IC
*
*
*
*
Interface Mode Selection
Reset
^
^
^
^
^
^
#RESET
F
W
H
1
F
W
H
2
R
S
V
v
F
W
H
3
R
S
V
v
R
S
V
v
#INIT
#TBL
*
*
*
*
*
*
Initialize
v
v
v
Top Boot Block Lock
Write Protect
#WP
CLK
CLK Input
FGPI[4:0]
ID[3:0]
General Purpose Inputs
Identification Inputs They
Are Internal Pull Down to
VSS
#OE(#INIT)
#WE(FWH4
NC
DQ7(RSV)
DQ6(RSV)
DQ5(RSV)
DQ4(RSV)
DQ3(FWH3)
GND
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
NC
2
3
4
GND
IC
5
6
A10(FGPI4)
FWH[3:0]
FWH4
R/#C
*
*
Address/Data Inputs
FWH Cycle Initial
Row/Column Select
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
32L
TSOP
7
R/#C(CLK)
VDD
8
9
NC
#RESET
10
11
12
13
14
15
16
DQ2(FWH2)
DQ1(FWH1)
DQ0(FWH0)
A0(ID0)
A9(FGPI3)
A8(FGPI2)
*
*
*
*
*
*
*
*
*
A7(FGPI1)
A6(FGPI0)
A5(#WP)
A4(#TBL)
A1(ID1)
A[10:0]
DQ[7:0]
#OE
A2(ID2)
A3(ID3)
#WE
VDD
*
*
*
*
Power Supply
GND
Ground
RSV
Reserved Pins
No Connection
NC
- 2 -
W49V002FA
FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, the other is
FWH interface mode. The IC pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When
IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low
state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just
behaves like traditional flash parts with 8 data lines. But the row and column address inputs are
multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH
Interface Specification. Through the FWH[3:0] to communicate with the system chipset .
Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE
(#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0
& bit 1 of START CYCLE ". Refer to the FWH cycle definition for further details.
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device
is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will
be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to
read or standby mode, it depends on the control signals.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed within fast 150 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the other
memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains
as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)
by the chip erase operation if the boot block programming lockout feature is not activated. The device
will automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.
Sector Erase Operation
The seven sectors, one boot block and two parameter memory and four main blocks, can be erased
individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE
edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.
After the command loading cycle, the device enters the internal sector erase mode, which is
automatically timed and will be completed within fast 150 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal
read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect
end of erase cycle.
Publication Release Date: February 19, 2002
- 3 -
Revision A2
W49V002FA
Program Operation
The W49V002FA is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or
boot block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the byte-
program command is entered. The internal program timer will automatically time-out (100 mS max. -
TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. One is software command sequences method; the
other is hardware method. 16K-byte in the top location of this device can be locked as boot block,
which can be used to store boot codes. It is located in the last 16K bytes of the memory with the
address range from 3C000(hex) to 3FFFF(hex).
Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is
set, the data for the designated block cannot be erased or programmed (programming lockout), other
memory locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block
will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will
override the software method setting. That is, if #TBL is at low state, then top boot block cannot be
programmed/erased no matter how the software boot block lock setting.
Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The
enable of this pin will override the #TBL setting. That is, the top boot block cannot be
programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.
Hardware Data Protection
The integrity of the data stored in the W49V002FA is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is
less than 1.5V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5
mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49V002FA includes a data polling feature to indicate the end of a program or erase cycle.
When the W49V002FA is in the internal program or erase cycle, any attempts to read DQ7 of the last
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and
when erase cycle has been completed it becomes logical "1" or true data.
- 4 -
W49V002FA
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49V002FA provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
General Purpose Inputs Register
This register reads the FGPI[4:0] pins on the W49V002FA.This is a pass-through register which can
read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.
BIT
FUNCTION
Reserved
7 - 5
4
3
2
1
0
Read FGPI4 pin status
Read FGPI3 pin status
Read FGPI2 pin status
Read FGPI1 pin status
Read FGPI0 pin status
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software operation. In the software access
mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for
programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex).
A read from address 0001(hex) outputs the device code, 32(hex).” The product ID operation can be
terminated by a three-byte command sequence or an alternate one-byte command sequence (see
Command Definition table).
As for FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code,
DA(hex). A read from FFBC, 0001(hex) can output the device code 32(hex).
TABLE OF OPERATING MODES
Operating Mode Selection - Programmer Mode
(VHH = 12V ± 5%)
MODE
PINS
ADDRESS
DQ.
#OE
VIL
VIH
X
#WE
VIH
VIL
X
#RESET
VIH
Read
AIN
AIN
X
Dout
Din
Write
VIH
Standby
VIL
High Z
Write Inhibit
VIL
X
X
VIH
X
High Z/DOUT
High Z/DOUT
High Z
VIH
X
VIH
X
Output Disable
VIH
VIH
X
Publication Release Date: February 19, 2002
Revision A2
- 5 -
W49V002FA
Operating Mode Selection - FWH Mode
Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When
it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle
Definition".
TABLE OF COMMAND DEFINITION
COMMAND
NO. OF 1ST CYCLE
2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
Addr. Data
AIN DOUT
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
XXXX F0
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
DESCRIPTION
Cycles
Read
1
6
6
4
6
3
3
1
Chip Erase
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
5555 80
5555 80
5555 A0
5555 80
5555 90
5555 F0
5555 AA
5555 AA
2AAA 55
2AAA 55
5555 10
Sector Erase
SA
30
Byte Program
AIN
DIN
Boot Block Lockout
Product ID Entry
Product ID Exit (1)
Product ID Exit (1)
5555 AA
2AAA 55
5555 40
Notes:
1. The cycle means the write command cycle not the FWH clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]
3. Address Format: A14- A0 (Hex); Data Format: DQ7-DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
SA = 3C000h to 3FFFFh for Boot Block
SA = 3A000h to 3BFFFh for Parameter Block1
SA = 38000h to 39FFFh for Parameter Block2
SA = 30000h to 37FFFh for Main Memory Block1
SA = 2XXXXh for Main Memory Block2
SA = 1XXXXh for Main Memory Block3
SA = 0XXXXh for Main Memory Block4
- 6 -
W49V002FA
FWH CYCLE DEFINITION
FIELD
NO. OF
DESCRIPTION
CLOCKS
START
1
"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH
Memory Write cycle.
IDSEL
MSIZE
TAR
1
1
2
7
This one clock field indicates which FWH component is being selected.
Memory Size. There is always show “0000b” for single byte access.
Turned Around Time
ADDR
Address Phase for Memory Cycle. FWH supports the 28 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[27:24] on FWH[3:0] first , and
Address[3:0] on FWH[3:0] last.)
SYNC
DATA
N
2
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then
DQ[7:4] on FWH[3:0] last.)
Publication Release Date: February 19, 2002
- 7 -
Revision A2
W49V002FA
Embedded Programming Algorithm
Start
Write Program Command Sequence
(see below)
#Data Polling/ Toggle bit
Pause T
BP
No
Last Address
?
Increment Address
Yes
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
- 8 -
W49V002FA
Embedded Erase Algorithm
Start
Write Erase Command Sequence
(see below)
#Data Polling or Toggle
Successfully Completed
Pause
EC
SEC
/T
T
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector Erase
Command Sequence
(Address/Command):
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
5555H/AAH
2AAAH/55H
Sector Address/30H
Publication Release Date: February 19, 2002
Revision A2
- 9 -
W49V002FA
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during sector
erase operation
Read Byte
(DQ0 - DQ7)
Address = VA
= Valid address equals any sector group
address during chip erase
No
DQ7 = Data
?
Yes
Pass
Embedded Toggle Bit Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = Don't Care
Yes
DQ6 = Toggle
?
No
Pass
- 10 -
W49V002FA
Software Product Identification and Boot Block Lockout Detection Acquisition
Flow
Product
Product
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Identification
Entry (1)
Identification Exit(6)
Load data AA
to
address 5555
Load data AA
to
address 5555
(2)
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Read address = 00000
data = DA
(2)
(4)
Load data 90
Load data F0
to
Read address = 00001
data = 32 (Hex)
to
address 5555
address 5555
Read address = 00002
Pause 10 S
Pause 10 S
m
m
DQ0 of data outputs = 1/0
(5)
Normal Mode
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7 - DQ0 (Hex); Address Format: A14 - A0 (Hex)
(2) A1 - A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the
lockout feature is inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout
detection.
Publication Release Date: February 19, 2002
- 11 -
Revision A2
W49V002FA
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Pause T
Exit
BP
- 12 -
W49V002FA
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
V
Power Supply Voltage to VSS Potential
Operating Temperature
-0.5 to +4.1
0 to +70
°C
°C
V
Storage Temperature
-65 to +150
D.C. Voltage on Any Pin to Ground Potential
Transient Voltage (<20 nS) on Any Pin to Ground Potential
-0.5 to VDD +0.5
-1.0 to VDD +0.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Programmer interface Mode DC Operating Characteristics
(VDD = 3.3V ± 5%, VGND= 0V, TA = 0 to 70° C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
MIN. TYP.
UNIT
MAX.
Power Supply
Current
ICC In Read or Write mode, all DQs open
Address inputs = 3.0V/0V, at f = 3 MHz
-
20
30
mA
Input Leakage
Current
ILI
VIN = GND to VDD
-
-
-
-
10
10
mA
mA
Output Leakage
Current
ILO
VOUT = GND to VDD
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIL
VIH
-
-
-0.3
2.0
-
-
-
-
-
0.8
VDD +0.5
0.45
V
V
V
V
VOL IOL = 2.1 mA
VOH IOH = -0.1mA
2.4
-
Publication Release Date: February 19, 2002
Revision A2
- 13 -
W49V002FA
FWH interface Mode DC Operating Characteristics
(VDD = 3.3V ±5 %, VGND = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
UNIT
mA
MIN.
TYP.
MAX.
Power Supply
Current
ICC All Iout = 0A, CLK = 33 MHz,
in FWH mode operation.
-
40
60
Standby Current
ISB1 FWH4 = 0.9 VDD, CLK = 33 MHz,
-
-
20
3
100
10
mA
all inputs = 0.9 VDD/ 0.1 VDD, no
internal operation
Standby Current
ISB2 FWH4 = 0.1 VDD, CLK = 33 MHz,
mA
all inputs = 0.9 VDD/ 0.1 VDD,
no internal operation
Input Low Voltage
Input High Voltage
VIL
VIH
-
-
-
-0.5
0.5 VDD
-0.5V
-
-
-
0.3 VDD
VDD +0.5
0.2 VDD
V
V
V
Input Low Voltage for VILI
#INIT
Input High Voltage
for #INIT
VIHI
-
1.35V
-
VDD +0.5
V
Output Low Voltage
Output High Voltage
VOL IOL = 1.5 mA
VOH IOH = -0.5 mA
-
-
-
0.1 VDD
-
V
V
0.9 VDD
Power-up Timing
PARAMETER
SYMBOL
TYPICAL
UNIT
Power-up to Read Operation
Power-up to Write Operation
TPU. READ
TPU. WRITE
100
5
mS
mS
CAPACITANCE
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER
I/O Pin Capacitance
Input Capacitance
SYMBOL
CI/O
CONDITIONS
VI/O = 0V
MAX.
12
UNIT
pF
CIN
VIN = 0V
6
pF
- 14 -
W49V002FA
PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 0.9 VDD
< 5 nS
Input Rise/Fall Time
Input/Output Timing Level
Output Load
1.5V/1.5V
1 TTL Gate and CL = 30 pF
AC Test Load and Waveform
+3.3V
1.8K
W
D
OUT
Input
Output
30 pF
0.9V
DD
(Including Jig and
Scope)
1.3K
1.5V
W
1.5V
0V
Test Point
Test Point
Publication Release Date: February 19, 2002
Revision A2
- 15 -
W49V002FA
Programmer Interface Mode AC Characteristics, continued
AC Characteristics
Read Cycle Timing Parameters
(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
W49V002FA
UNIT
MIN.
MAX.
Read Cycle Time
TRC
TAS
300
50
50
-
-
nS
nS
nS
nS
nS
nS
nS
nS
Row/Column Address Set Up Time
Row/Column Address Hold Time
Address Access Time
-
-
TAH
TAA
200
100
-
Output Enable Access Time
#OE Low to Active Output
#OE High to High-Z Output
Output Hold from Address Change
TOE
TOLZ
TOHZ
TOH
-
0
-
50
-
0
Write Cycle Timing Parameters
PARAMETER
Reset Time
SYMBOL
TRST
TAS
MIN.
TYP.
MAX.
UNIT
1
50
50
50
100
100
50
50
0
-
-
mS
nS
nS
nS
nS
nS
nS
nS
nS
mS
S
Address Setup Time
Address Hold Time
R/#C to Write Enable High Time
#WE Pulse Width
-
-
TAH
-
-
TCWH
TWP
-
-
-
-
#WE High Width
TWPH
TDS
-
-
-
Data Setup Time
-
-
Data Hold Time
TDH
-
#OE Hold Time
TOEH
TBP
-
-
Byte programming Time
Erase Cycle Time
-
50
0.15
100
0.2
TEC
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
PARAMETER
SYMBOL
W49V002FA
UNIT
MIN.
MAX.
40
#OE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
TOEP
TOET
-
-
nS
nS
40
- 16 -
W49V002FA
TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
Read Cycle Timing Diagram
#RESET
TRST
T
RC
Row Address
Column Address
Column Address
Row Address
TAH
TAS
A[10:0]
R/#C
TAH
TAS
VIH
#WE
#OE
TAA
TOH
TOE
TOHZ
TOLZ
High-Z
High-Z
DQ[7:0]
Data Valid
Write Cycle Timing Diagram
T
RST
#RESET
A[10:0]
Column Address
Row Address
T
AS
T
AS
T
AH
T
AH
R/#C
T
CWH
T
T
OEH
#OE
T
WP
WPH
#WE
T
DH
T
DS
DQ[7:0]
Data Valid
Publication Release Date: February 19, 2002
Revision A2
- 17 -
W49V002FA
Timing Waveforms for Programmer Interface Mode, continued
Program Cycle Timing Diagram
Byte Program Cycle
A[10:0]
Programmed Address
2AAA
55
5555
5555
(Internal A[17:0])
DQ[7:0]
A0
Data-In
AA
R/#C
#OE
T
WPH
BP
T
WP
T
#WE
Internal Write Start
Byte 0
Byte 1
Byte 2
Byte 3
Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
#DATA Polling Timing Diagram
A[10:0]
(Internal A[17:0])
An
An
An
An
R/#C
#WE
#OE
DQ7
T
OEP
X
X
X
T
BP or
T
EC
- 18 -
W49V002FA
Timing Waveforms for Programmer Interface Mode, continued
Toggle Bit Timing Diagram
A[10:0]
R/#C
#WE
#OE
T
OET
DQ6
T
BP or T
EC
Boot Block Lockout Enable Timing Diagram
Six-byte code for 3.3V-only software chip erase
A[10:0]
2AAA
55
5555
AA
5555
80
5555
AA
2AAA
55
5555
40
(Internal A[17:0])
DQ[7:0]
R/#C
#OE
WP
T
WC
T
#WE
WPH
T
SB0
SB2
SB3
SB5
SB4
SB1
Note: The internal address A[17:0] are converted from external Column/Row addr
Column/Row Address are mapped to the Low/High order internal addre
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
Publication Release Date: February 19, 2002
Revision A2
- 19 -
W49V002FA
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Timing Diagram
Six-byte code for 3.3V-only software chip erase
A[10:0]
2AAA
5555
5555
5555
2AAA
5555
(Internal A[17:0])
AA
55
80
55
DQ[7:0]
AA
10
R/#C
#OE
T
WP
T
EC
T
WPH
#WE
Internal Erasure Starts
SB0
SB2
SB3
SB5
SB4
SB1
Note: The internal address A[17:0] are converted from external Column/Row addre
Column/Row Address are mapped to the Low/High order internal addres
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
Sector Erase Timing Diagram
Six-byte code for 3.3V-only software
sector erase
A[10:0]
5555
AA
2AAA
55
(Internal A[17:0])
DQ[7:0]
5555
80
5555
AA
2AAA
55
SA
30
R/#C
#OE
#WE
T
WP
T
EC
T
WPH
Internal Erase starts
SB0
SB2
SB3
SB5
SB4
SB1
Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
SA = Sector Address, Please ref. to the "Table of Command Definition"
- 20 -
W49V002FA
FWH INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0.6 VDD to 0.2 VDD
1 V/nS
Input Rise/Fall Slew Rate
Input/Output Timing Level
Output Load
0.4 VDD / 0.4 VDD
1 TTL Gate and CL = 10 pF
AC Test Load and Waveform
D
OUT
D
OUT
Input
Output
10 pF
10 pF
V
DD
25
25
W
W
0.6V
0.2V
DD
DD
0.4V
0.4V
DD
DD
Test Point
Test Point
Test when output from high to low
Test when output from low to high
Read/Write Cycle Timing Parameters
(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
W49V002FA
UNIT
MIN.
MAX.
Clock Cycle Time
TCYC
TSU
THD
TKQ
30
7
-
-
nS
nS
nS
nS
Input Set Up Time
Input Hold Time
0
-
Clock to Data Valid
-
11
Reset Timing Parameters
PARAMETER
VDD stable to Reset Active
Clock Stable to Reset Active
Reset Pulse Width
SYM.
MIN.
TYP.
MAX.
UNIT
TPRST
TKRST
TRSTP
TRSTF
TRST
1
100
100
-
-
-
-
-
-
-
-
mS
mS
nS
nS
mS
-
Reset Active to Output Float
Reset Inactive to Input Active
50
-
1
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
Publication Release Date: February 19, 2002
Revision A2
- 21 -
W49V002FA
TIMING WAVEFORMS FOR FWH INTERFACE MODE
Read Cycle Timing Diagram
TCYC
CLK
#RESET
FWH4
TSU
THD
THD
TKQ
TSU
Start
FWH
Read
M Size
0000b] 1111b Tri-State 0000b
2 Clocks
1 Clock Data out 2 Clocks
Address
A[15:12] A[11:8] A[7:4]
Load Address in 7 Clocks
TAR
Next Star
Data
IDSEL
0000b
Sync
FWH[3:0]
0000b
XA[22]XXb XXA[17:16]
D[3:0]
TAR
XXXXb
A[3:0]
D[7:4]
1101b
1 Clock
1 Clock
1 Clock
Note: When A22 = high, the host will read the BIOS code from the FWH de
While A22 = low, the host will read the GPI (Add = FFBC0100
Product ID (Add = FFBC0000/FFBC0001) from the FWH dev
Write Cycle Timing Diagram
T
CYC
CLK
#RESET
FWH4
T
T
SU HD
Start
FWH
TAR
1111b
2 Clocks
M Size
Sync
0000b
Address
Next Star
0000b
IDSEL
0000b
Data
D[7:4]
Load Data in 2 Clocks
Write
FWH[3:0]
XXXXb XXXXb XXA[17:16]b
A[7:4]
TAR
A[15:12] A[11:8]
A[3:0]
0000b
Tri-State
1110b
D[3:0]
1 Clock
1 Clock
1 Clock
Load Address in 7 Clocks
1 Clock
- 22 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Program Cycle Timing Diagram
CLK
#RESET
FWH4
Start next
Data
TAR
Sync
0000b
TAR
1111b
2 Clocks
Address
X101b
M Size
0000b
IDSEL
0000b
1st Start
1110b
command
FWH[3:0 ]
XXXXb
XXXXb
XXXXb
0101b
0101b
0101b
1111b
Load Data "AA" in 2 Clocks
Tri-State
Tri-State
1010b
1010b
2 Clocks
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
1 Clock
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
TAR
TAR
1111b
2 Clocks
Address
X010b
M Size
0000b
Sync
0000b
IDSEL
2nd Start
1110b
FWH[3:0 ]
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
1010b
1010b
1010b
XXXXb
0101b
0101b
1111b
2 Clocks
Tri-State
Tri-State
0000b
Load Data "55"
in 2 Clocks
1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
1 Clock
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
TAR
1111b
2 Clocks
TAR
1111b
2 Clocks
Sync
0000b
IDSEL
M Size
Address
3rd Start
1110b
0000b
]
FWH[3:0
XXXXb
0101b
0101b
0101b
X101b
0000b
1010b
Tri-State
Tri-State
0000b
Load Data "A0"
in 2 Clocks
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
1 Clock
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
Internal
program start
Address
A[15:12]
Data
TAR
1111b
2 Clocks
IDSEL
TAR
M Size
0000b
Sync
4th Start
1110b
FWH[3:0 ]
D[3:0]
D[7:4]
0000b 1111b Tri-State Internal
program start
XXA[17:16]b
A[11:8]
A[7:4]
A[3:0]
Tri-State
0000b
Load Din in 2 Clocks
1 Clock
Load Ain in 7 Clocks
2 Clocks
1 Clock
1 Clock
Write the 4th command(target location to be programmed) to the device in FWH mode.
Publication Release Date: February 19, 2002
Revision A2
- 23 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
#DATA Polling Timing Diagram
CLK
#RESET
FWH4
Data
Dn[3:0] Dn[7:4]
TAR
Sync
0000b
TAR
Next Start
1 Clock
Address
An[15:12]
M Size
Start
IDSEL
0000b
FWH[3:0]
XXXXb
XXXXb
XXA[17:16]b
0000b
1111b
2 Clocks
1110b
An[7:4]
An[3:0]
Tri-State
1111b
2 Clocks
Tri-State
An[11:8]
Load Data "Dn"
in 2 Clocks
1 Clock
Load Address "An" in 7 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET
XXXXb
FWH4
TAR
Next Start
1 Clock
Address
An[15:12]
M Size
TAR
Tri-State
Start
Sync
Data
XXXXb Dn7,xxx
Data out 2 Clocks
IDSEL
0000b
FWH[3:0]
XXXXb
XXXXb
XXA[17:16]b
An[3:0]
0000b
An[11:8]
An[7:4]
1111b
2 Clocks
1101b
1111b
0000b
Tri-State
1 Clock
2 Clocks
Read the DQ7 to see if the internal write complete or not.
1 Clock
Load Address in 7 Clocks
1 Clock
CLK
#RESET
FWH4
TAR
Next Start
1 Clock
Address
TAR
Tri-State
IDSEL
0000b
Start
1101b
Data
XXXXb Dn7,xxx
Data out 2 Clocks
M Size
Sync
FWH[3:0]
XXXXb
XXXXb
1111b
2 Clocks
0000b
1111b
Tri-State
XXA[17:16]b An[15:12]
An[11:8]
An[7:4]
An[3:0]
0000b
1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock
1 Clock
When internal write complete, the DQ7 will equal to Dn7.
- 24 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Toggle Bit Timing Diagram
CLK
#RESET
FWH4
Data
D[7:4]
TAR
TAR
1111b
2 Clocks
Next Start
1 Clock
Sync
0000b
Address
M Size
Start
1110b
IDSEL
0000b
FWH[3:0]
XXXXb
XXXXb
XXA[17:16]b A[15:12]
A[7:4]
A[3:0]
0000b
A[11:8]
D[3:0]
1111b
2 Clocks
Tri-State
Tri-State
Load Data "Dn"
in 2 Clocks
1 Clock
Load Address "An" in 7 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET
FWH4
TAR
1111b
Next Start
1 Clock
Address
XXXXb
XXXXb
TAR
Tri-State 0000b
1 Clock Data out 2 Clocks
Start
IDSEL
0000b
M Size
Data
Sync
FWH[3:0]
XXXXb
XXXXb
1101b
XXXXb
XXXXb
XXXXb
0000b
1111b
XXXXb
X,D6,XXb
Tri-State
2 Clocks
1 Clock
2 Clocks
Read the DQ6 to see if the internal write complete or not.
Load Address in 7 Clocks
1 Clock
CLK
#RESET
FWH4
TAR
1111b
Next Start
1 Clock
Address
TAR
Tri-State 0000b
2 Clocks
1 Clock Data out 2 Clocks
When internal write complete, the DQ6 will stop toggle.
Start
1101b
M Size
Sync
Data
IDSEL
0000b
FWH[3:0]
XXXXb
XXXXb
XXXXb
XXXXb
0000b
1111b
XXXXb
Tri-State
2 Clocks
XXXXb
XXXXb
XXXXb
X,D6,XXb
Load Address in 7 Clocks
1 Clock
1 Clock
Publication Release Date: February 19, 2002
Revision A2
- 25 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Boot Block Lockout Enable Timing Diagram
CLK
#RESET
FWH4
Start next
command
Data
1010b
TAR
Sync
TAR
Address
X101b
IDSEL
0000b
M Size
1st Start
1110b
FWH[3:0]
XXXXb
XXXXb
XXXXb
0101b
1111b
0000b
0101b
0000b
Tri-State
1111b
Tri-State
0101b
1010b
Load Data "AA"
in 2 Clocks
1 Clock
Load Address "5555" in 7 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
TAR
1111b
2 Clocks
Address
X010b
Data
0101b
TAR
Sync
0000b
M Size
IDSEL
0000b
2nd Start
1110b
FWH[3:0]
XXXXb
XXXXb
XXXXb
1010b
1010b
1111b
2 Clocks
Tri-State
1010b
0000b
Tri-State
0101b
Load Data "55"
in 2 Clocks
1 Clocks
1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
0000b 1000b
TAR
1111b
Tri-State
2 Clocks
TAR
1111b
2 Clocks
Sync
0000b
IDSEL
0000b
Address
X101b
M Size
3rd Start
1110b
FWH[3:0]
XXXXb
XXXXb
XXXXb
0101b
Tri-State
0101b
0101b
0000b
Load Data "80"
in 2 Clocks
1 Clock
1 Clock
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Address
X101b
M Size
Data
1010b
TAR
TAR
1111b
2 Clocks
IDSEL
Sync
0000b
4th Start
1110b
FWH[3:0]
XXXXb
XXXXb
XXXXb
1111b
2 Clocks
Tri-State
0101b
0101b
0101b
0000b
1010b
Tri-State
0000b
Load Data "AA"
in 2 Clocks
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
1 Clock
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
0101b
TAR
1111b
Tri-State
2 Clocks
TAR
1111b Tri-State
Sync
0000b
Address
X010b
M Size
5th Start IDSEL
FWH[3:0]
XXXXb
XXXXb
XXXXb
1110b
0000b
1010b
1010b
0000b
1010b
0101b
Load Data "55"
in 2 Clocks
1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
2 Clocks
1 Clock
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal
program start
Address
X101b
Data
0100b
0000b
TAR
1111b
2 Clocks
TAR
Sync
0000b
IDSEL
0000b
M Size
6th Start
1110b
FWH[3:0]
XXXXb
Internal
program start
XXXXb
XXXXb
0000b
0101b
0101b
0101b
Tri-State
1111b Tri-State
2 Clocks
Load Data "40"
in 2 Clocks
1 Clock
1 Clock
1 Clock
Load Address "5555" 7 Clocks
mode.
Write the 6th command to the device in FWH
- 26 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
FWH4
Start next
Data
1010b
TAR
Sync
IDSEL
TAR
Address
X101b
M
Size
1st Start
1110b
command
XXXXb
XXXXb
XXXXb
1111b
2 Clocks
0000b
FWH[3:0]
0101b
0101b
0101b
0000b
Tri-State
1111b
Tri-State
1010b
0000b
Load Data "AA"
in 2 Clocks
1 Clock
2 Clocks
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Address
X010b
M
Size
Data
0101b
TAR
Tri-State
2 Clocks
TAR
Sync
0000b
IDSEL
0000b
2th Start
1110b
XXXXb
XXXXb
FWH[3:0]
XXXXb
0000b
1111b
1010b
1010b
1010b
1111b
Tri-State
0101b
Load Data "55"
in 2 Clocks
1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
2 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
TAR
1111b
2 Clocks
M
Size
Sync
TAR
Tri-State
2 Clocks
Address
X101b
IDSEL
0000b
3th Start
1110b
XXXXb
XXXXb
FWH[3:0]
XXXXb
0101b
0101b
0101b
0000b
1000b
0000b
0000b
Tri-State
1111b
Load Data "80"
in 2 Clocks
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
1 Clock
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Address
X101b
Data
1010b
TAR
M
Size
Sync
0000b
TAR
IDSEL
0000b
4th Start
1110b
FWH[3:0]
XXXXb
XXXXb
XXXXb
0101b
0101b
0101b
0000b
1111b
Tri-State
1111b
Tri-State
1010b
Load Data "AA"
in 2 Clocks
1 Clock
2 Clocks
1 Clock
1 Clock
Load Address "5555" in 7 Clocks
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
0101b
TAR
1111b
Tri-State
2 Clocks
M
Size
Sync
TAR
IDSEL
0000b
Address
X010b
5th Start
1110b
FWH[3:0]
XXXXb
XXXXb
XXXXb
0000b
0000b
1111b
1010b
1010b
1010b
Tri-State
0101b
Load Data "55"
in 2 Clocks
1 Clock
1 Clock
1 Clock
Load Address "2AAA" in 7 Clocks
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal
erase start
Address
X101b
Data
TAR
1111b
2 Clocks
TAR
Sync
IDSEL
0000b
M
Size
6th Start
1110b
FWH[3:0]
XXXXb
XXXXb
Internal
erase start
XXXXb
0001b
0000b
1111b Tri-State
2 Clocks
0000b
0000b
Tri-State
0101b
0101b
0101b
Load Data "10"
in 2 Clocks
1 Clock
1 Clock
1 Clock
Load Address "5555" in 7 Clocks
Write the 6th command to the device in FWH mode.
Publication Release Date: February 19, 2002
Revision A2
- 27 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Sector Erase Timing Diagram
CLK
#RESET
FWH4
Start next
Data
1010b
TAR
Sync
TAR
M Size
0000b
Address
X101b
Load Address "5555" in 7 Clocks
command
1st Start IDSEL
XXXXb
XXXXb
0000b
1110b
XXXXb
1111b
2 Clocks
0000b
Tri-State
FWH[3:0]
0101b
0101b
0101b
1010b
1111b
Tri-State
Load Data "AA"
in 2 Clocks
1 Clock
2 Clocks
1 Clock 1 Clock
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Address
X010b
Data
0101b
TAR
TAR
Sync
0000b
IDSEL
0000b
M
2nd Start
1110b
Size
XXXXb
XXXXb
FWH[3:0]
XXXXb
1111b
0000b
1111b
2 Clocks
Tri-State
1010b
1010b
1010b
0101b
Tri-State
Load Data "55"
in 2 Clocks
1 Clock
2 Clocks
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
TAR
TAR
M Size
0000b
Sync
Address
X101b
Load Address "5555" in 7 Clocks
3rd Start IDSEL
1110b
1 Clocks1 Clocks
XXXXb
XXXXb
FWH[3:0]
XXXXb
0000b
Tri-State 0000b
0000b
1000b
1111b
Tri-State
2 Clocks
0101b
0101b
0101b
1111b
Load Data "80"
in 2 Clocks
2 Clocks
1 Clocks
1 Clocks
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Address
X101b
Data
1010b
TAR
1111b Tri-State 0000b
2 Clocks
TAR
1111b Tri-State
2 Clocks
M Size
0000b
Sync
IDSEL
0000b
4th Start
1110b
FWH[3:0]
XXXXb
XXXXb
XXXXb
0101b
0101b
0101b
1010b
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
0101b
TAR
TAR
1111b
M Size
0000b
Sync
Address
X010b
5th Start
1110b
IDSEL
0000b
FWH[3:0]
XXXXb
XXXXb
XXXXb
Tri-State 0000b
Tri-State
1010b
1010b
1111b
1010b
0101b
Load Data "55"
in 2 Clocks
2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal
erase start
Address
Data
0000b
0011b
TAR
Tri-State
2 Clocks
TAR
Sync
M Size
0000b
IDSEL
0000b
6th Start
1110b
FWH[3:0]
Internal
erase start
XXXXb
XXXXb
1111b
0000b
1111b Tri-State
2 Clocks
XXA[17:16]b SA[15:12]
XXXXb
XXXXb XXXXb
Load Din
in 2 Clocks
1 Clock
1 Clock
Load Sector Address in 7 Clocks
1 Clock
Write the 6th command(target sector to be erased) to the device in FWH mode.
- 28 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
FGPI Register/Product ID Readout Timing Diagram
CLK
#RESET
FWH4
M Size
0000b
IDSEL
0000b
Address
0000b
TAR
Next Start
1 Clock
TAR
Start
Data
Sync
FWH[3:0]
0001b
/0000b
0000b
/0001b
1101b
Tri-State 1111b
D[3:0]
D[7:4]
A[27:24]
Tri-State 1111b
A[23:20] A[19:16]
0000b
0000b
Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register
& "FFBC0000(hex)/FFBC0001(hex) for Product ID
2 Clocks
1 Clock Data out 2 Clocks
1 Clock 1 Clock
2 Clocks
Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pi
Reset Timing Diagram
VDD
CLK
T
PRST
T
KRST
T
RSTP
#RESET
FWH[3:0]
FWH4
T
RST
T
RST
Publication Release Date: February 19, 2002
Revision A2
- 29 -
W49V002FA
ORDERING INFORMATION
PART NO.
ACCESS
TIME
POWER SUPPLY
CURRENT MAX.
(mA)
STANDBY VDD
CURRENT MAX.
PACKAGE
(nS)
(mA)
W49V002FAP
W49V002FAQ
11
11
25
25
20
20
32L PLCC
32L STSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
HOW TO READ THE TOP MARKING
Example: The top marking of 32L-PLCC W49V002FA
W49V002FAP
2123055C-082
132GHSA
1st line: winbond logo
2nd line: the part number: W49V002FAP
3rd line: the lot number
4th line: the tracking code: 132 G H SA
132: Packages made in ’01, week 32
G: Assembly house ID: A means ASE, G means Greatek, ...etc.
H: IC revision; A means version A, H means version H, ...etc.
SA: Process code
- 30 -
W49V002FA
PACKAGE DIMENSIONS
32L PLCC
Dimension in Inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
H E
E
0.140
3.56
A
A
A
b
b
c
D
E
e
G
G
H
H
L
y
0.020
0.105
0.026
0.016
0.008
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
0.50
2.67
1
4
1
32
30
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
0.115
0.032
0.022
0.014
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.004
2.80
0.71
2.93
0.81
2
0.66
1
0.41
0.56
0.46
5
29
0.20
0.35
0.25
13.89
11.35
1.12
14.05
11.51
1.42
13.97
11.43
1.27
12.45
9.91
12.95
10.41
14.99
12.45
2.29
13.46
10.92
15.11
12.57
2.41
D
G
D
E
D
HD
14.86
12.32
1.91
D
E
0.10
°
°
°
°
10
0
10
0
q
21
13
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusi
3. Controlling dimension: Inches
14
20
c
4. General appearance spec. should be based on final
visual inspection sepc.
L
A2
A1
A
q
e
b
b
1
Seating Plane
y
GE
32L STSOP (8 x 14 mm)
D
H
D
Dimension in Inches Dimension in mm
Symbol
c
Max.
Min. Nom. Max. Min. Nom.
0.047
1.20
A
e
0.006
0.041
0.05
0.95
0.17
0.10
0.002
0.035
0.15
1
A
A
b
c
0.040
1.00
0.22
2
1.05
0.27
0.007 0.009 0.010
E
0.004
0.008
-----
12.40
8.00
0.21
-----
b
0.488
D
E
0.315
0.551
0.020
14.00
D
H
e
0.50
0.60
0.80
0.50
0.70
0.020 0.024 0.028
0.031
L
1
L
Y
q
0.000
0
0.00
0
0.10
5
0.004
5
£
c
3
3
A
A
1 A
2
L
Y
L
1
Publication Release Date: February 19, 2002
Revision A2
- 31 -
W49V002FA
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
April 2001
-
Initial Issued
Feb. 19, 2002
4
Modify VDD Power Up/Down Detection in Hardware
Data Protection
6
Modify the description on start in TABLE OF
COMMAND DEFINITION
Delete old flow chart and add embedded algorithm
Add in Input High Voltage for #INIT (VIHI) parameter
7 - 10
13
Change VIL (max.) from 0.2 VDD to 0.3 VDD; VIH (min.)
from 0.6 VDD to 0.5 VDD.
Add the VIHI/ VILI for the #INIT pin input spec.
29
Add HOW TO READ THE TOP MARKING
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
2727 North First Street, San Jose,
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
200336 China
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
TEL: 86-21-62365999
FAX: 86-21-62365998
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
FAX: 81-45-4781800
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 32 -
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