W49V002A [WINBOND]
256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE; 256K ×8 CMOS闪光灯LPC接口存储器
| 型号： | W49V002A |
| 厂家： | 
WINBOND |
| 描述： | 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| 文件： | 总32页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary W49V002A
256K x 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
GENERAL DESCRIPTION
The W49V002A is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K ´ 8 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49V002A results in fast program/erase operations with
extremely low current consumption. This device can operate at two modes, Programmer bus interface
mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional
flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the
Intel LPC specification 1.0. The device can also be programmed and erased using standard EPROM
programmers.
FEATURES
bytes, 64K bytes, 64K bytes each)
· Low power consumption
·Single 3.3-volt operations:
- 3.3-volt Read
- Active current: 25 mA (typ.)
- Standby current: 20 mA (typ.)
- 3.3-volt Erase
- 3.3-volt Program
· Automatic program and erase timing with
internal VPP generation
· Fast Program operation:
- Byte-by-Byte programming: 50 mS (typ.)
· Fast Erase operation: 150 mS (typ.)
· Endurance: 10K cycles (typ.)
· Twenty-year data retention
· End of program or erase detection
- Toggle bit
- Data polling
· Latched address and data
· TTL compatible I/O
· Available packages: 32L PLCC and 32L
STSOP
· Hardware data protection
- #TBL & #WP serve as hardware protection
· One 16K bytes Boot Block with lockout
protection
· Two 8K bytes Parameter Blocks
· Four Main Memory Blocks (with 32K bytes, 64K
Publication Release Date: April 2001
- 1 -
Revision A1
Preliminary W49V002A
PIN CONFIGURATIONS
PIN DESCRIPTION
INTERFACE
SYMB
PIN NAME
A
1
0
^
G
P
I
4
v
A
A
R
#
8
^
G
P
I
2
9
^
G
P
I
3
C
#
R
E
S
E
T
^
C
L
K
v
PGM
LPC
V
D
D
N
C
v
v
MODE
#RESET
#INIT
*
*
Interface Mode Selection
Reset
4
3
2
1
32 31 30
*
*
5
29
28
A7(GPI1)
A6(GPI0)
MODE
GND
6
*
Initialize
7
NC
A5(#WP)
A4(#TBL)
27
26
8
9
32-pin
PLCC
NC
A3(RSV)
25
24
VDD
#TBL
*
*
*
*
Top Boot Block Lock
Write Protect
CLK Input
10
11
A2(RSV)
A1(RSV)
#OE(#INIT)
#WE(#LFRAM)
NC
23
22
#WP
12
13
A0(RSV)
DQ0(LAD0)
21
DQ7(RSV)
14 15 16 17 18 19 20
CLK
D
Q
1
^
L
A
D
1
D
Q
2
^
L
A
D
2
D
Q
3
^
L
A
D
D
Q
4
^
R
S
V
D
Q
5
^
R
S
V
v
D
Q
6
^
R
S
V
G
N
D
GPI[4:0]
General Purpose
Inputs
3
v
v
v
v
v
LAD[3:0]
#LFRAM
R/#C
*
*
Address/Data Inputs
LPC Cycle Initial
Row/Column Select
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
1
2
32
#OE(#INIT)
#WE(#LFRAM
NC
NC
NC
31
30
NC
3
4
5
GND
DQ7(RSV)
DQ6(RSV)
DQ5(RSV)
29
28
27
26
25
*
*
*
*
*
*
*
*
*
MODE
A10(GPI4)
R/#C(CLK)
6
7
DQ4(RSV)
DQ3(LAD3)
GND
A[10:0]
DQ[7:0]
#OE
32-pin
TSOP
V
DD
8
NC
9
24
23
22
10
DQ2(LAD2)
#RESET
A9(GPI3)
A8(GPI2)
11
12
13
14
15
DQ1(LAD1)
DQ0(LAD0)
A0(RSV)
21
20
19
18
17
A7(GPI1)
A6(GPI0)
A5(#WP)
A4(#TBL)
A1(RSV)
A2(RSV)
A3(RSV)
16
#WE
VDD
*
*
*
*
Power Supply
GND
Ground
RSV
Reserve Pins
BLOCK DIAGRAM
NC
No Connection
#WP
#TBL
CLK
LAD[3:0]
#LFRAM
MODE
3FFFF
BOOT BLOCK
16K BYTES
LPC
Interface
3C000
3BFFF
PARAMETER
BLOCK1
8K BYTES
3A000
39FFF
PARAMETER
BLOCK2
8K BYTES
#INIT
38000
37FFF
#RESET
MAIN MEMORY
BLOCK1
32K BYTES
30000
R/#C
2FFFF
MAIN MEMORY
BLOCK2
64K BYTES
A[10:0]
Program-
mer
Interface
20000
1FFFF
DQ[7:0]
MAIN MEMORY
BLOCK3
64K BYTES
#OE
#WE
10000
0FFFF
MAIN MEMORY
BLOCK4
64K BYTES
00000
- 2 -
Preliminary W49V002A
FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, the other is LPC
interface mode. The MODE pin of the device provides the control between these two interface modes.
These interface modes need to be configured before power up or return from #RESET. When MODE pin
is set to high state, the device is in the Programmer mode; while the MODE pin is set to low state(or
leaved no connection), it is in the LPC mode. In Programmer mode, this device just behaves like
traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go
through the address inputs A[10:0]. For LPC mode, It complies with the LPC Interface Specification
Revision 1.0. Through LAD[3:0] to communicate with the system chipset .
Read(Write) Mode
In Programmer interface mode, the read(write) operation of the W49V002A is controlled by #OE (#WE).
The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when #OE is high. As in the LPC interface mode, the read or write is determined by the "bit 1 of CYCLE
TYPER+DIR".
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device
is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will
be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to
read or standby mode, it depends on the control signals.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed within fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the other
memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as
the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by
the chip erase operation if the boot block programming lockout feature is not activated. The device will
automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle
Bits can be used to detect end of erase cycle.
Sector Erase Operation
The seven sectors, one boot block and two parameter blocks and four main blocks, can be erased
individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE
edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.
After the command loading cycle, the device enters the internal sector erase mode, which is
automatically timed and will be completed within fast 150 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal read
mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of
erase cycle.
Program Operation
The W49V002A is programmed on a byte-by-byte basis. Program operation can only change logical data
Publication Release Date: April 2001
- 3 -
Revision A1
Preliminary W49V002A
"1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot
block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the byte-program
command is entered. The internal program timer will automatically time-out (100 mS max. - TBP) once it
is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect
end of program cycle.
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. One is software command sequences method; the other
is hardware method. 16K-byte in the top location of this device can be locked as boot block, which can
be used to store boot codes. It is located in the last 16K bytes of the memory with the address range
from 3C000(hex) to 3FFFF(hex).
Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is
set, the data for the designated block cannot be erased or programmed (programming lockout), other
memory locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block
will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will
override the software method setting. That is, if #TBL is at low state, then top boot block cannot be
programmed/erased no matter how the software boot block lock setting.
Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The
enable of this pin will override the #TBL setting. That is, the top boot block cannot be
programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.
Hardware Data Protection
The integrity of the data stored in the W49V002A is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 1.5V
typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5
mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49V002A includes a data polling feature to indicate the end of a program or erase cycle. When
the W49V002A is in the internal program or erase cycle, any attempts to read DQ7 of the last byte
loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7
will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and when erase cycle
has been completed it becomes logical "1" or true data.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49V002A provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce
alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.
- 4 -
Preliminary W49V002A
Memory Address Map
There are 8M bytes space reserved for BIOS Addressing. The ROM will respond to 256K byte pages
whenever the memory address rang is within the top 4M bytes and bottom 128K bytes.
The 32bit address space is as below:
Block
Address Range
FFFF,FFFFh:FFC0,0000h
000F,FFFFh:000E,0000h
FFBC,0100h
4M Byte BIOS ROM
128K Byte BIOS ROM
Registers
General Purpose Inputs Register
This register reads the GPI[4:0] pins on the W49V002A.This is a pass-through register which can read
via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.
Bit
7-5
4
Function
Reserved
Read GPI4 pin status
Read GPI3 pin status
Read GPI2 pin status
Read GPI1 pin status
Read GPI0 pin status
3
2
1
0
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software operation. In the software access
mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID. A read
from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs
the device code, B0(hex).” The product ID operation can be terminated by a three-byte command
sequence or an alternate one-byte command sequence (see Command Definition table).
Publication Release Date: April 2001
- 5 -
Revision A1
Preliminary W49V002A
TABLE OF OPERATING MODES
Operating Mode Selection - Programmer Mode
(VHH = 12V ± 5%)
MODE
PINS
#OE
VIL
VIH
X
#WE
VIH
VIL
X
#RESET
VIH
ADDRESS
DQ.
Read
AIN
AIN
X
Dout
Din
Write
VIH
Standby
Write Inhibit
VIL
High Z
VIL
X
X
VIH
X
High Z/DOUT
High Z/DOUT
High Z
VIH
X
VIH
X
Output Disable
VIH
VIH
X
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".
TABLE OF COMMAND DEFINITION
COMMAND
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
DESCRIPTION
Cycles Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Read
1
6
6
4
6
3
3
1
AIN DOUT
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
5555 AA
XXXX F0
Chip Erase
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
2AAA 55
5555 80
5555 80
5555 A0
5555 80
5555 90
5555 F0
5555 AA
5555 AA
2AAA 55
2AAA 55
5555 10
Sector Erase
SA
30
Byte Program
AIN
D
IN
Boot Block Lockout
Product ID Entry
Product ID Exit (1)
Product ID Exit (1)
5555 AA
2AAA 55
5555 40
Note: 1. The cycle means the write command cycle not the LPC clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]
3. Address Format: A14- A0 (Hex); Data Format: DQ7-DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA : Sector Address
SA = 3C000h to 3FFFFh for Boot Block
SA = 3A000h to 3BFFFh for Parameter Block1
SA = 38000h to 39FFFh for Parameter Block2
SA = 30000h to 37FFFh for Main Memory Block1
SA = 2XXXXh for Main Memory Block2
SA = 1XXXXh for Main Memory Block3
SA = 0XXXXh for Main Memory Block4
- 6 -
Preliminary W49V002A
STANDARD LPC MEMORY CYCLE DEFINITION
FIELD
NO. OF CLOCKS
DESCRIPTION
Start
1
1
"0000b" appears on LPC bus to indicate the initial
Cycle Type & Dir
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
TAR
2
8
Turned Around Time
Addr.
Address Phase for Memory Cycle. LPC supports the 32 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and
Address[3:0] on LAD[3:0] last.)
Sync.
Data
N
2
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4]
on LAD[3:0] last.)
Note: 1. For detail related LPC specification, please refer to Intel LPC spec. 1.0 or later.
Publication Release Date: April 2001
Revision A1
- 7 -
Preliminary W49V002A
Command Codes for Byte Program
BYTE SEQUENCE
0 Write
ADDRESS
DATA
AAH
5555H
2AAAH
1 Write
55H
2 Write
5555H
A0H
3 Write
Programmed-Address
Programmed-Data
Byte Program Flow Chart
Byte Program
Command Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data Din
to
programmed-
address
Pause TBP
Exit
Notes for software program code:
Data Format: DQ7- DQ0 (Hex); XX = Don't Care
Address Format: A14- A0 (Hex)
- 8 -
Preliminary W49V002A
Command Codes for Chip Erase
BYTE SEQUENCE
1 Write
ADDRESS
5555H
DATA
AAH
55H
2 Write
2AAAH
5555H
3 Write
80H
4 Write
5555H
AAH
55H
5 Write
2AAAH
5555H
6 Write
10H
Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause TEC
Exit
Notes for chip erase:
Data Format: DQ7- DQ0 (Hex)
Address Format: A14- A0 (Hex)
Publication Release Date: April 2001
Revision A1
- 9 -
Preliminary W49V002A
Command Codes for Sector Erase
BYTE SEQUENCE
1 Write
ADDRESS
5555H
2AAAH
5555H
5555H
2AAAH
SA*
DATA
AAH
55H
2 Write
3 Write
80H
4 Write
AAH
55H
5 Write
6 Write
30H
Sector Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 30
to
address SA*
Pause T
EC
Exit
Notes for chip erase:
Data Format: DQ7- DQ0 (Hex)
Address Format: A14- A0 (Hex)
SA : Sector Address
SA = 3C000h to 3FFFFh for Boot Block
SA = 3A000h to 3BFFFh for Parameter Block1 SA = 2XXXXh for Main Memory Block2
SA = 38000h to 39FFFh for Parameter Block2 SA = 1XXXXh for Main Memory Block3
SA = 30000h to 37FFFh for Main Memory Block1 SA = 0XXXXh for Main Memory Block4
- 10 -
Preliminary W49V002A
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE
SEQUENCE
SOFTWARE PRODUCT IDENTIFICATION /
BOOT BLOCK LOCKOUT DETECTION
ENTRY
SOFTWARE PRODUCT IDENTIFICATION /
BOOT BLOCK LOCKOUT DETECTION
EXIT (6)
ADDRESS
5555
DATA
AA
ADDRESS
5555H
DATA
AAH
55H
1 Write
2 Write
3 Write
2AAA
55
2AAAH
5555
90
5555H
F0H
Pause 10mS
Pause 10mS
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Identification
and Boot Block
Lockout Detection
Product
Identification
Entry (1)
Product
Identification Exit(6)
Mode (3)
Load data AA
to
address 5555
Load data AA
to
address 5555
(2)
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Read address = 00000
data = DA
(2)
(4)
Load data 90
Load data F0
to
Read address = 00001
data = B0
to
address 5555
address 5555
Read address = 00002
m
Pause 10m S
Pause 10 S
DQ0 of data outputs = 1/0
(5)
Normal Mode
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7- DQ0 (Hex); Address Format: A14- A0 (Hex)
(2) A1- A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the lockout feature
is inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
Publication Release Date: April 2001
- 11 -
Revision A1
Preliminary W49V002A
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE
BOOT BLOCK LOCKOUT FEATURE SET
ADDRESS
5555H
DATA
1 Write
2 Write
3 Write
4 Write
5 Write
6 Write
AAH
55H
80H
AAH
55H
40H
2AAAH
5555H
5555H
2AAAH
5555H
Pause 1 Sec.
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Pause T
BP
Exit
Notes for boot block lockout enable:
Data Format: DQ7- DQ0 (Hex)
Address Format: A14- A0 (Hex)
- 12 -
Preliminary W49V002A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
-0.5 to +4.1
0 to +70
UNIT
V
Power Supply Voltage to Vss Potential
Operating Temperature
°C
°C
V
Storage Temperature
-65 to +150
D.C. Voltage on Any Pin to Ground Potential
Transient Voltage (<20 nS ) on Any Pin to Ground Potential
-0.5 to VDD +0.5
-1.0 to VDD +0.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Programmer interface Mode DC Operating Characteristics
(VDD 3.3V ± 5%, VGND= 0V, TA = 0 to 70° C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
MIN. TYP.
UNIT
MAX.
Power Supply
Current
ICC In Read or Write mode, all DQs open
Address inputs = 3.0V/0V, at f = 3 MHz
-
20
30
mA
Input Leakage
Current
ILI
VIN = GND to VDD
-
-
-
-
10
10
mA
mA
Output Leakage
Current
ILO VOUT = GND to VDD
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIL
-
-0.3
2.0
-
-
-
-
-
0.8
VDD +0.5
0.45
V
V
V
V
VIH
-
VOL IOL = 2.1 mA
VOH IOH = -0.1mA
2.4
-
Publication Release Date: April 2001
Revision A1
- 13 -
Preliminary W49V002A
LPC interface Mode DC Operating Characteristics
(VDD = 3.3V ± 5%, VGND= 0V, TA = 0 to 70° C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
MIN. TYP.
UNIT
mA
uA
MAX.
Power Supply
Current
ICC All Iout = 0A, CLK = 33MHz,
in LPC mode operation.
-
40
20
3
60
CMOS Standby
Current
Isb1 #LFRAM = 0.9 VDD, CLK = 33MHz,
all inputs = 0.9 VDD / 0.1 VDD
-
-
100
10
TTL Standby Current
Isb2 #LFRAM = 0.1 VDD, CLK = 33MHz,
all inputs = 0.9 VDD / 0.1 VDD
mA
Input Low Voltage
Input High Voltage
VIL
-
-
-0.3
-
-
0.2 VDD
V
V
VIH
0.6
VDD +0.5
VDD
Output Low Voltage
Output High Voltage
VOL IOL = 1.5 mA
VOH IOH = -0.5 mA
-
-
-
0.1 VDD
-
V
V
0.9
VDD
Power-up Timing
PARAMETER
SYMBOL
TPU. READ
TPU. WRITE
TYPICAL
UNIT
Power-up to Read Operation
Power-up to Write Operation
100
5
mS
mS
CAPACITANCE
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER
I/O Pin Capacitance
Input Capacitance
SYMBOL
CI/O
CONDITIONS
VI/O = 0V
MAX.
12
UNIT
pf
CIN
VIN = 0V
6
pf
- 14 -
Preliminary W49V002A
PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
Input Rise/Fall Time
Input/Output Timing Level
Output Load
0V to 0.9VDD
< 5 nS
1.5V/1.5V
1 TTL Gate and CL = 30 pF
AC Test Load and Waveform
+3.3V
1.8K
W
DOUT
Input
Output
0.9VDD
30 pF
(Including Jig and
Scope)
1.3K
W
1.5V
1.5V
0V
Test Point
Test Point
Publication Release Date: April 2001
Revision A1
- 15 -
Preliminary W49V002A
Programmer Interface Mode AC Characteristics, continued
AC Characteristics
Read Cycle Timing Parameters
(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
W49V002A
UNIT
MIN.
MAX.
Read Cycle Time
TRC
TAS
300
50
50
-
-
nS
nS
nS
nS
nS
nS
nS
nS
Row / Column Address Set Up Time
Row / Column Address Hold Time
Address Access Time
-
-
TAH
TAA
200
100
-
Output Enable Access Time
#OE Low to Active Output
TOE
TOLZ
TOHZ
TOH
-
0
#OE High to High-Z Output
Output Hold from Address Change
-
50
-
0
Write Cycle Timing Parameters
PARAMETER
Reset Time
SYMBOL
TRST
TAS
MIN.
1
TYP.
MAX.
UNIT
-
-
mS
nS
nS
nS
nS
nS
nS
nS
nS
mS
S
Address Setup Time
Address Hold Time
R/#C to Write Enable High Time
#WE Pulse Width
50
50
50
100
100
50
50
0
-
-
TAH
-
-
TCWH
TWP
-
-
-
-
#WE High Width
TWPH
TDS
-
-
-
Data Setup Time
-
-
Data Hold Time
TDH
-
#OE Hold Time
TOEH
TBP
-
-
Byte programming Time
Erase Cycle Time
-
50
0.15
100
0.2
TEC
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
MIN.
MAX.
40
#OE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
TOEP
TOET
-
-
nS
nS
40
- 16 -
Preliminary W49V002A
TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
Read Cycle Timing Diagram
#RESET
T
RST
T
RC
Column Address
Row Address
A[10:0]
R/#C
Column Address
Row Address
T
T
T
T
AH
AS
AH
AS
V
IH
#WE
#OE
T
AA
TOH
T
T
OHZ
OE
T
OLZ
High-Z
High-Z
DQ[7:0]
Data Valid
Write Cycle Timing Diagram
T
RST
#RESET
A[10:0]
Column Address
Row Address
T
AS
T
T
AS
T
AH
AH
R/#C
#OE
T
T
OEH
CWH
T
WP
T
WPH
#WE
T
DH
T
DS
DQ[7:0]
Data Valid
Publication Release Date: April 2001
Revision A1
- 17 -
Preliminary W49V002A
Timing Waveforms for Programmer Interface Mode, continued
Program Cycle Timing Diagram
Byte Program Cycle
A[10:0]
Programmed Address
(Internal A[17:0])
DQ[7:0]
5555
2AAA
5555
55
A0
Data-In
AA
R/#C
#OE
TWPH
BP
T
WP
T
#WE
Internal Write Start
Byte 0
Byte 1
Byte 2
Byte 3
Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
#DATA Polling Timing Diagram
A[10:0]
(Internal A[17:0])
R/#C
An
An
An
An
#WE
#OE
DQ7
T
OEP
X
X
X
TBP orTEC
- 18 -
Preliminary W49V002A
Timing Waveforms for Programmer Interface Mode, continued
Toggle Bit Timing Diagram
A[10:0]
R/#C
#WE
#OE
TOET
DQ6
BP or EC
T
T
Boot Block Lockout Enable Timing Diagram
Six-byte code for 3.3V-only software chip erase
A[10:0]
2AAA
55
5555
AA
5555
80
5555
2AAA
55
(Internal A[17:0])
DQ[7:0]
5555
40
AA
R/#C
#OE
TWP
SB0
T
WC
#WE
TWPH
SB1
SB2
SB3
SB4
SB5
Note: The internal address A[17:0] are converted from external Column/Row add
Column/Row Address are mapped to the Low/High order internal addre
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
Publication Release Date: April 2001
Revision A1
- 19 -
Preliminary W49V002A
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Timing Diagram
Six-byte code for 3.3V-only software chip erase
A[10:0]
2AAA
55
5555
5555
5555
2AAA
5555
10
(Internal A[17:0])
DQ[7:0]
R/#C
AA
80
AA
55
#OE
T
WP
T
EC
#WE
T
WPH
Internal Erasure Starts
SB0
SB2
SB3
SB4
SB5
SB1
Note: The internal address A[17:0] are converted from external Column/Row add
Column/Row Address are mapped to the Low/High order internal addre
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
Sector Erase Timing Diagram
Six-byte code for 5V-only software
Main Memory Erase
A[10:0]
5555
AA
2AAA
55
5555
80
SA
30
(Internal A[17:0])
DQ[7:0]
5555
AA
2AAA
55
R/#C
#OE
TWP
SB0
TEC
#WE
TWPH
Internal Erase starts
SB2
SB3
SB5
SB1
SB4
Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
SA = Sector Address, Please ref. to the "Table of Command Definition"
- 20 -
Preliminary W49V002A
LPC INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0.6 VDD to 0.2 VDD
Input Rise/Fall Slew Rate
Input/Output Timing Level
Output Load
1 V/nS
0.4VDD / 0.4VDD
1 TTL Gate and CL = 10 pF
AC Test Load and Waveform
D
OUT
D
OUT
Input
Output
10 pF
10 pF
V
DD
25W
25W
0.6V
0.2V
DD
DD
0.4V
0.4V
DD
DD
Test Point
Test Point
Test when output from high to low
Test when output from low to high
Read/Write Cycle Timing Parameters
(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
W49V002A
UNIT
MIN.
MAX.
Clock Cycle Time
TCYC
TSU
30
7
-
-
nS
nS
nS
nS
Input Set Up Time
Input Hold Time
Clock to Data Valid
THD
TKQ
0
-
-
11
Reset Timing Parameters
PARAMETER
Vdd stable to Reset Active
Clock Stable to Reset Active
Reset Pulse Width
SYMBOL
TPRST
TKRST
TRSTP
TRSTF
TRST
MIN.
1
TYP.
MAX.
UNIT
-
-
-
-
-
-
-
mS
mS
nS
nS
mS
100
100
-
-
Reset Active to Output Float
Reset Inactive to Input Active
50
-
1
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
Publication Release Date: April 2001
Revision A1
- 21 -
Preliminary W49V002A
TIMING WAVEFORMS FOR LPC INTERFACE MODE
Read Cycle Timing Diagram
T
CYC
CLK
#RESET
#LFRAM
T
T
SU HD
T
T
T
SU
HD
KQ
Memory
Read
Address
A[23:20] A[19:16] A[15:12] A[11:8]
TAR
Tri-State
Next Start
Start
Sync
Data
D[3:0]
Cycle
0000b
A[27:24]
D[7:4]
TAR
LAD[3:0]
010Xb A[31:28]
A[7:4]
A[3:0]
1111b
2 Clocks
0000b
0000b
1 Clock 1 Clock
1 Clock Data out 2 Clocks
1 Clock
Load Address in 8 Clocks, the address should be within the top 4MByte,
FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000
Write Cycle Timing Diagram
T
CYC
CLK
#RESET
T
T
#LFRAM
SU HD
Memory
Write
TAR
Sync
Next Start
0000b
Start
Address
A[23:20] A[19:16] A[15:12] A[11:8]
Load Address in 8 Clocks, the address should be within the top 4MByte,
Data
D[7:4]
Load Data in 2 Clocks
Cycle
0000b
011Xb
A[27:24]
A[7:4]
1111b
2 Clocks
0000b
TAR
LAD[3:0]
A[31:28]
A[3:0]
D[3:0]
Tri-State
1 Clock 1 Clock
1 Clock
1 Clock
FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E000
- 22 -
Preliminary W49V002A
Program Cycle Timing Diagram
CLK
#RESET
#LFRAM
Memory
Start next
Write
Data
TAR
Tri-State 0000b
Load Data "AA" in 2 Clocks 2 Clocks
Sync
Address
A[19:16]
Load Address "5555" in 8 Clocks
1st Start Cycle
command
LAD[3:0]
1111b
TAR
0000b
A[31:28]
A[27:24]
A[23:20]
011Xb
X101b
0101b
0101b
0101b
1010b
1010b
1 Clock 1 Clock
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
0101b 0101b
TAR
Tri-State 0000b
Address
Sync
2nd Start Cycle
TAR
0000b
A[31:28]
A[31:28]
A[31:28]
A[27:24]
A[23:20]
A[19:16]
1111b
2 Clocks
011Xb
X010b
1010b
1010b
1010b
Load Data "55"
in 2 Clocks
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Start next
command
Write
Data
0000b 1010b
TAR
Sync
Address
A[19:16]
Load Address "5555" in 8 Clocks
3rd Start Cycle
A[27:24]
TAR
0000b
A[23:20]
1111b
Tri-State 0000b
011Xb
0101b
0101b
0101b
X101b
Load Data "A0"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
Internal
program start
#LFRAM
LAD[3:0]
Memory
Write
Cycle
Address
Data
D[3:0]
Load Din in 2 Clocks
TAR
Tri-State 0000b
2 Clocks
Sync
4th Start
0000b
TAR
A[27:24]
A[23:20]
A[19:16]
1111b
Internal
011Xb
A[15:12]
A[11:8]
A[7:4]
A[3:0]
D[7:4]
program start
1 Clock
1 Clock 1 Clock
Load Ain in 8 Clocks
Write the 4th command(target location to be programmed) to the device in LPC mode.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
Publication Release Date: April 2001
Revision A1
- 23 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
#DATAPolling Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
TAR
Sync
0000b
Address
Cycle
command
1st Start
0000b
0000b
Dn[3:0] Dn[7:4]
LAD[3:0]
1111b
2 Clocks
TAR
TAR
TAR
011Xb
An[27:24]
An[7:4]
An[3:0]
Tri-State
An[31:28]
An[23:20] An[19:16] An[15:12] An[11:8]
Load Data "Dn"
in 2 Clocks
Load Address "An" in 8 Clocks
1 Clock
1 Clock
1 Clock 1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
XXXXb
#LFRAM
LAD[3:0]
Memory
Read
Address
TAR
Tri-State 0000b
2 Clocks 1 Clock
Read the DQ7 to see if the internal write complete or not.
Next Start
0000b
Start
Cycle
Sync
Data
0000b
010Xb
1111b
An[27:24]
An[11:8]
An[7:4]
An[3:0]
XXXXb Dn7,xxx
An[31:28]
An[23:20] An[19:16] An[15:12]
Load Address in 8 Clocks
1 Clock 1 Clock
Data out 2 Clocks
1 Clock
CLK
#RESET
#LFRAM
Memory
Read
Address
TAR
Tri-State 0000b
2 Clocks
When internal write complete, the DQ7 will equal to Dn7.
Next Start
0000b
Start
Cycle
Sync
Data
0000b
LAD[3:0]
010Xb
1111b
XXXXb Dn7,xxx
An[31:28] An[27:24] An[23:20] An[19:16]
An[15:12] An[11:8]
An[7:4]
An[3:0]
1 Clock 1 Clock
Load Address in 8 Clocks
1 Clock Data out 2 Clocks
1 Clock
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 24 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Toggle Bit Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
D[7:4]
TAR
Tri-State 0000b
2 Clocks 1 Clock
Address
A[23:20] A[19:16]
Sync
Cycle
1st Start
0000b
command
TAR
LAD[3:0]
011Xb
A[27:24]
A[27:24]
A[27:24]
D[3:0]
1111b
A[31:28]
A[15:12]
A[7:4]
A[3:0]
A[11:8]
Load Data "Dn"
in 2 Clocks
1 Clock 1 Clock
Load Address "An" in 8 Clocks
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Read
Start
Cycle
Address
TAR
Tri-State 0000b
2 Clocks 1 Clock Data out 2 Clocks
Read the DQ6 to see if the internal write complete or not.
Next Start
0000b
Sync
Data
0000b
010Xb
A[31:28]
A[23:20]
A[19:16]
XXXXb XXXXb XXXXb XXXXb
1111b
XXXXb
TAR
X,D6,XXb
Load Address in 8 Clocks
1 Clock1 Clock
1 Clock
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Read
Start
Address
TAR
Tri-State 0000b
2 Clocks 1 Clock Data out 2 Clocks
Data
Next Start
0000b
Sync
Cycle
0000b
010Xb
XXXXb
TAR
XXXXb
XXXXb XXXXb
1111b
XXXXb
A[31:28]
A[23:20]
A[19:16]
X,D6,XXb
1 Clock
Load Address in 8 Clocks
1 Clock
1 Clock
When internal write complete, the DQ6 will stop toggle.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
Publication Release Date: April 2001
Revision A1
- 25 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Boot Block Lockout Enable Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Cycle
Start next
command
Data
TAR
Address
Sync
1st Start
0000b
A[31:28] A[27:24] A[23:20] A[19:16]
1111b
0000b
TAR
LAD[3:0]
011Xb
0101b
0101b 0101b 1010b 1010b
Tri-State
X101b
Load Data "AA"
in 2 Clocks
1 Clock1 Clock
Load Address "5555" in 8 Clocks
2 Clocks
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
Data
TAR
Cycle
Sync
0000b
2nd Start
0000b
A[27:24]
A[31:28]
A[23:20] A[19:16]
1111b Tri-State
2 Clocks
TAR
011Xb
X010b 1010b 1010b
1010b 0101b 0101b
Load Data "55"
in 2 Clocks
1 Clocks
1 Clock1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
Cycle
Sync
3rd Start
Address
A[31:28] A[27:24] A[23:20] A[19:16]
TAR
0000b 011Xb
0101b 0101b 0101b 0000b 1000b
1111b Tri-State 0000b
X101b
Load Data "80"
in 2 Clocks
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
2 Clocks
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
Data
TAR
Sync
0000b
4th Start Cycle
0000b
A[31:28] A[27:24] A[23:20] A[19:16]
1111b
2 Clocks
TAR
011Xb
X101b 0101b 0101b
0101b 1010b 1010b
Tri-State
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
Sync
5th Start Cycle
Address
TAR
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
1010b 1010b 1010b 0101b
0101b 1111b Tri-State 0000b
2 Clocks 1 Clock
X010b
Load Data "55"
1 Clock1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
in 2 Clocks
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Internal
program start
Memory
Write
Address
Data
Cycle
TAR
Sync
6th Start
0000b 0100b
TAR
Internal
program start
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] X101b
0101
b
0101b
0101b
1111b Tri-State 0000b
2 Clocks 1 Clock
Load Data "40"
in 2 Clocks
1 Clock1 Clock
Load Address "5555" 8 Clocks
mode.
Write the 6th command to the device in LPC
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 26 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
TAR
Tri-State
Cycle
Address
A[19:16]
Load Address "5555" in 8 Clocks
Sync
1st Start
0000b
command
LAD[3:0]
A[31:28]
A[27:24]
A[23:20]
X101b
1111b
0000b
TAR
011Xb
0101b
0101b
0101b
1010b
1010b
Load Data "AA"
in 2 Clocks
1 Clock 1 Clock
2 Clocks
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Cycle
Address
Data
0101b
TAR
Sync
2nd Start
0000b
A[31:28]
A[27:24]
A[23:20]
A[19:16]
1111b
0000b
TAR
011Xb
X010b
1010b
1010b
1010b
0101b
Tri-State
Load Data "55"
in 2 Clocks
1 Clock
Load Address "2AAA" in 8 Clocks
2 Clocks
1 Clock
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Cycle
Start next
command
Data
TAR
Address
Sync
0000b
3rd Start
0000b
TAR
011Xb
A[31:28]
A[27:24]
A[23:20]
A[19:16]
0101b
0101b
0101b
0000b
1000b
1111b
Tri-State
X101b
Load Data "80"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Cycle
Start next
command
Address
Data
1010b
TAR
1111b Tri-State
Sync
0000b
4th Start
0000b
A[27:24]
TAR
011Xb
A[31:28]
A[23:20]
A[19:16]
X101b
0101b
0101b
0101b
1010b
Load Data "AA"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Cycle
Start next
command
Data
TAR
Address
Sync
5th Start
0000b
A[31:28]
A[27:24]
A[23:20]
A[19:16]
1111b
Tri-State
0000b
TAR
011Xb
X010b
1010b
1010b
1010b
0101b
0101b
Load Data "55"
in 2 Clocks
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
2 Clocks
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Internal
erase start
Memory
Write
Address
Data
TAR
Sync
Cycle
6th Start
0000b
Internal
erase start
A[31:28]
A[27:24]
A[23:20]
A[19:16]
0001b
1111b
0000b
TAR
011Xb
X101b
0101b
0101b
0101b
0000b
Tri-State
Load Data "10"
in 2 Clocks
1 Clock 1 Clock
2 Clocks
1 Clock
Load Address "5555" in 8 Clocks
Write the 6th command to the device in LPC mode.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
Publication Release Date: April 2001
Revision A1
- 27 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Sector Erase Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
TAR
1111b
2 Clocks
Address
Sync
Cycle
command
1st Start
0000b
TAR
LAD[3:0]
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
0101b 0101b 0101b 1010b 1010b
Tri-State
X101b
Load Data "AA"
in 2 Clocks
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
Data
TAR
1111b Tri-State 0000b
2 Clocks 1 Clock
Cycle
Sync
2nd Start
0000b
A[31:28] A[27:24] A[23:20] A[19:16]
TAR
011Xb
X010b 1010b 1010b
1010b 0101b 0101b
Load Data "55"
in 2 Clocks
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
X101b 0101b 0101b 0101b 0000b 1000b
TAR
1111b Tri-State 0000b
2 Clocks
Address
A[31:28] A[27:24] A[23:20] A[19:16]
Load Address "5555" in 8 Clocks
Sync
3rd Start Cycle
0000b
TAR
011Xb
Load Data "80"
in 2 Clocks
1 Clocks1 Clocks
1 Clocks
1 Clocks
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
0101b 1010b 1010b 1111b Tri-State 0000b
Address
TAR
Sync
4th Start Cycle
0000b
TAR
011Xb A[31:28] A[27:24] A[23:20] A[19:16]
X101b 0101b 0101b
Load Data "AA"
in 2 Clocks
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
2 Clocks
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
Sync
Address
5th Start Cycle
TAR
0000b 011Xb
A[27:24]
X010b
1010b 1010b
0101b 0101b 1111b Tri-State 0000b
A[31:28]
A[23:20] A[19:16]
1010b
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55"
in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Internal
erase start
Memory
Write
Address
A[31:28] A[27:24] A[23:20] A[19:16]
Data
TAR
Sync
6th Start Cycle
Internal
erase start
0000b
0000b 0011b
1111b
0000b
TAR
011Xb
SA[15:12]
XXXXb
XXXXb XXXXb
Tri-State
Load Din
in 2 Clocks
2 Clocks
1 Clock 1 Clock
Load Sector Address in 8 Clocks
1 Clock
Write the 6th command(target sector to be erased) to the device in LPC mode.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
- 28 -
Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
GPI Register Readout Timing Diagram
CLK
#RESET
#LFRAM
Memory
Read
Start
Address
A[23:20] A[19:16]
Load Address "FFBC0100(hex)" in 8 Clocks
TAR
Tri-State
2 Clocks
Data
D[3:0]
Next Start
0000b
Sync
Cycle
0000b
A[27:24]
A[31:28]
0000b
0001b
0000b
0000b
D[7:4]
TAR
LAD[3:0]
010Xb
1111b
0000b
1 Clock Data out 2 Clocks
1 Clock 1 Clock
1 Clock
Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved pins.
Reset Timing Diagram
VDD
CLK
T
PRST
T
KRST
T
RSTP
#RESET
LAD[3:0]
T
RST
TRST
#LFRAM
Publication Release Date: April 2001
Revision A1
- 29 -
Preliminary W49V002A
ORDERING INFORMATION
PART NO.
ACCESS
TIME
POWER SUPPLY
CURRENT MAX.
STANDBY VDD
CURRENT MAX.
PACKAGE
(nS)
11
(mA)
25
(m A)
W49V002AP
W49V002AQ
20
20
32L PLCC
32L STSOP
11
25
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
- 30 -
Preliminary W49V002A
PACKAGE DIMENSIONS
32L PLCC
Dimension in Inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
H E
E
0.140
3.56
A
A
A
b
b
c
D
E
e
G
G
H
0.020
0.105
0.026
0.50
2.67
0.66
1
4
1
32
30
0.110
0.115
0.032
2.80
2.93
0.81
2
1
0.028
0.018
0.71
0.46
0.016
0.008
0.022
0.014
0.41
0.20
0.56
0.35
5
29
0.010
0.550
0.25
0.547
0.447
0.553
0.453
13.89
11.35
13.97
14.05
11.51
0.450
0.050
11.43
1.27
0.044
0.056
1.12
1.42
12.95
0.490
0.390
0.585
0.510
0.410
0.530
0.430
0.595
12.45
9.91
13.46
10.92
15.11
D
G D
10.41
E
D
HD
14.86
0.590
0.490
14.99
12.45
2.29
D
0.485
0.075
0.495
0.095
0.004
12.32
1.91
12.57
2.41
0.10
E
H
L
y
0.090
0
0
10
10
q
21
13
Notes:
1. Dimensions D & E do not include interlead flash
14
20
c
2. Dimension b1 does not include dambar protrusion/in
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
visual inspection sepc.
L
A2
A1
A
q
e
b
b
1
Seating Plane
y
G
E
32L STSOP(8 x 14mm)
H
D
D
c
Dimension in Inches Dimension in mm
Symbol
Max.
Min. Nom. Max. Min. Nom.
e
0.047
1.20
A
0.002
0.035
0.006
0.041
0.05
0.95
0.17
0.10
1
0.15
1.05
A
E
0.040
1.00
2
A
b
0.007 0.009 0.010
0.22 0.27
b
c
0.004 -----
0.488
0.008
-----
0.21
12.40
D
E
0.315
8.00
0.551
0.020
0.024
0.031
14.00
D
H
e
L
L1
Y
0.50
0.60
0.020
0.028
0.50
0.70
θ
0.80
1
A
A
0.000
0
0.00
0
0.10
5
0.004
5
L
2
Y
A
3
3
q
1
L
Publication Release Date: April 2001
Revision A1
- 31 -
Preliminary W49V002A
VERSION HISTORY
VERSION
DATE
Apr. 2001
PAGE
DESCRIPTION
A1
-
Initial Issued
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
FAX: 852-27552064
http://www.winbond.com.tw/
TEL: 408-9436666
FAX: 408-5441798
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, M-iSnheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
- 32 -
相关型号：
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