EDI2CG264128V85D1 [WEDC]
SRAM Module, 256KX64, 8.5ns, CMOS, SODIMM-144;
| 型号： | EDI2CG264128V85D1 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | SRAM Module, 256KX64, 8.5ns, CMOS, SODIMM-144 静态存储器 |
| 文件： | 总11页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI2CG264128V
2x128Kx64, 3.3V Sync/Sync Burst Flow-Through
FEATURES
DESCRIPTION
■ 2x128Kx64 Synchronous, Synchronous Burst
The EDI2CG264128VxxD1 is a Synchronous/Synchronous Burst
SRAM, 64 position DIMM (144 contacts) Module, small outline.
The Module contains four (4) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm TQFP
placed on a Multilayer FR4 Substrate. The module architecture is
defined as a Sync/Sync Burst, Flow-Through, with support for
either linear or sequential burst. This module provides High
Performance, 2-1-1-1 accesses when used in Burst Mode, and
used as a Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS aysnchronous device architectures.
■ Flow-Through Architecture
■ Linear and Sequential Burst Support via MODE pin
■ Access Speed(s): TKHQV = 8.5, 9, 12, 15ns
■ Clock Controlled Registered Bank Enables (E1, E2)
■ Clock Controlled Registered Address
■ Clock Controlled Registered Global Write (GW)
■ Aysnchronous Output Enable (G)
■ Internally Self-timed Write
Synchronous Only operations are performed via strapping ADSC
Low, and ADSP / ADV High, which provides for Ultra Fast Accesses
in Read Mode while providing for internally self-timed Early
Writes.
■ Individual Bank Sleep Mode Enables (ZZ1, ZZ2)
■ Gold Lead Finish
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined for Quad Word access in
both read and write operations.
■ 3.3V ±10% Operation
■ Common Data I/O
■ High Capacitance (30pF) Drive, at Rated Access Speed
■ Single Total Array Clock
■ Multiple Vcc and Gnd
August 2000 Rev.0
ECO#13089
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG264128V
PIN CONFIGURATION
PIN NAMES
DQ0-63
A0-16
Input/Output Bus
Address Bus
PIN
FUNCTION PIN FUNCTION
PIN
1
FUNCTION PIN
FUNCTION
V
V
SS
SS
VSS
SS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
109
110
DQ41
DQ46
DQ42
DQ45
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
7
1
6
2
5
3
4
2
V
E1, E2 Synchronous Bank Enables
3
A
0
ZZ
2
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
CLK
GW
Array Clock
RFU
16
NC
4
5
A
V
CC
CC
DQ43
DQ44
Synchronous Global Write
Enable
6
A
1
2
78
79
V
A
DQ24
DQ31
DQ25
DQ30
DQ26
DQ29
DQ27
DQ28
7
VSS
G
Asynchronous Output Enable
A
A
15
14
80
8
VSS
ZZ1, ZZ2 Blank Sleep Mode Enables
9
V
SS
SS
81
RFU
NC
Vcc
Vss
NC
3.3V Power Supply
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A
3
4
V
82
ZZ
1
A
83
V
CC
CC
A
A
13
12
NC
84
V
No Connect
V
CC
85
DQ48
DQ55
DQ49
DQ54
DQ50
DQ53
DQ51
DQ52
A
5
NC
86
A
6
DQ
DQ15
DQ
8
87
V
V
SS
SS
88
A
A
11
10
9
89
RFU
NC
DQ14
DQ10
DQ13
DQ11
DQ12
90
A
7
8
9
91
V
CC
CC
A
FIG. 1
FUNCTIONAL BLOCK DIAGRAM
A
92
V
93
DQ32
DQ39
DQ33
DQ38
V
SS
SS
V
V
CC
CC
V
94
A0-16
ADSC
ADSP
ADV
CLK
G
G
V
SS
SS
RFU
NC
95
RFU
GW
ADV
V
96
E
2
97
DQ34
DQ37
DQ35
DQ36
V
CC
CC
NC
98
V
DQ56
DQ63
DQ57
DQ62
DQ58
DQ61
DQ59
DQ60
GW
ADSP
ADSC
V
V
CC
CC
99
ADSC
100
101
102
103
104
105
106
107
ADSP
ADV
CLK
DQ16
DQ23
DQ17
V
V
SS
SS
MODE
CLK
DQ0-31
DQ
G
GW
E
E1
RFU
NC
V
V
SS
SS
ZZ1
ZZ
U1
DQ22
DQ18
140
141
142
143
144
E
1
V
V
CC
CC
ADSC
ADSP
ADV
CLK
G
DQ21
DQ19
DQ20
NC
DQ40
DQ47
V
SS
SS
V
V
CC
CC
DQ0-31
DQ
V
GW
E
108
E2
ZZ
U2
ADSC
ADSP
ADV
CLK
G
DQ32-63
DQ
GW
E
ZZ
ZZ2
U3
ADSC
ADSP
ADV
CLK
G
DQ32-63
DQ
GW
E
ZZ
U4
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
August 2000 Rev.0
ECO#13089
EDI2CG264128V
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 6, 10, 11, 14, 15,
18, 19, 20, 17, 16,
13, 12, 9, 8, 3, 5
A0-16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK.
The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.
25
GW
CLK
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE and BWx lines
and must meet the setup and hold times around the rising edge of CLK.
30
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times around the clock’s rising edge.
33, 61
E1, E2
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP
23
26
G
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
ADV
Input
Synchronous
Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
27
28
ADSP
ADSC
Input
Synchronous
Address Status Processor: This active LOW input, along with EL and EH being LOW, causes a new externaladdress
to be registered and a READ cycle is initiated using the new address.
Input
Synchronous
Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
29
MODE
ZZ1, ZZ2
DQ0-63
Input Static
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST.
47, 75
Various
Input
Asynchronous
Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode. For normal
operation, this input has to be either LOW or NC (no connect).
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is
DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
Various
Various
Vcc
Vss
Supply
Ground
Core power supply: +3.3V -5%/+10%
Ground
August 2000 Rev.0
ECO#13089
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG264128V
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1
H
X
L
E2
X
H
H
H
L
ADSP
X
X
L
ADSC
L
ADV
X
X
X
X
X
X
X
X
X
X
X
X
L
GW
X
X
X
X
X
X
L
G
X
X
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
Addr. Used
None
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
High-Z
L
High-Z
None
X
X
X
X
L
Q
External
External
External
External
External
External
External
External
External
External
Next
L
L
H
L
High-Z
H
H
L
L
Q
L
L
H
X
X
L
High-Z
H
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
X
H
X
H
H
H
H
X
X
X
X
H
X
H
X
D
H
L
L
L
D
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
X
X
X
X
L
High-Z
Next
L
D
Next
L
L
D
Next
L
L
D
Next
L
L
D
Next
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
High-Z
Q
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
L
H
L
High-Z
Q
H
L
High-Z
Q
H
X
X
X
X
High-Z
D
L
D
L
D
L
D
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
August 2000 Rev.0
ECO#13089
EDI2CG264128V
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1
L
E2
H
H
L
GW
L
G
H
L
ZZ
L
CLK
↑
DQ
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
Synchronous Write-Bank 3
Synchronous Read-Bank 3
Synchronous Write-Bank 4
Synchronous Read-Bank 4
Snooze Mode
High-Z
↑
L
H
L
L
↑
H
H
H
H
H
H
X
H
L
L
High-Z
High-Z
High-Z
High-Z
↑
L
H
L
L
↑
H
H
H
H
X
H
L
L
↑
H
L
L
↑
H
L
L
↑
H
X
L
X
H
X
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Sym
VCC
VSS
VIH
VIL
Min
3.14
0.0
2.0
-0.3
-2
Typ
3.3
0.0
3.0
0.0
1
Max
Units
V
Voltage on Vcc Relative to Vss
Vin
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
0°C to +70°C
Supply Voltage
Supply Voltage
Input High
3.6
Storage Temperature
0.0
V
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
VCC +0.3
V
-40°C to +85°C
10 mA
Input Low
0.8
2
V
Input Leakage
Output Leakage
ILI
µA
µA
ILo
-2
1
2
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in operational sections of this
specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
Symbol
Icc1
Typ
1.55
750
8.5
2.2
1.5
9
12
2.1
1.0
15
Units
Power Supply Current
2.1
1.5
2.0
1.0
A
A
Power Supply Current
Device Selected, No Operation
Icc
Snooze Mode
IccZZ
Icc3
IccK
150
400
600
200
600
1.0
200
600
1.0
200
600
0.75
200
600
0.75
mA
mA
A
CMOS Standby
Clock Running-Deselect
FIG. 2 AC OUTPUT LOAD EQUIVALENT
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
I/O
Unit
Input Pulse Levels
VSS to 3.0
1.25
V
V
I/O
Z0=50Ω
Input and Output Timing Levels
Output Test Equivalencies
See figure, at left
50Ω
Vt = 1.25V
August 2000 Rev.0
ECO#13089
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White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG264128V
BURST ADDRESS TABLE (MODE = NC/VCC)
BURST ADDRESS TABLE (MODE = VSS)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A..A00
A..A01
A..A10
A..A11
A..A01
A..A10
A..A11
A..A00
A..A10
A..A11
A..A00
A..A01
A..A11
A..A00
A..A01
A..A10
A..A00
A..A01
A..A10
A..A11
A..A01
A..A00
A..A11
A..A10
A..A10
A..A11
A..A00
A..A01
A..A11
A..A10
A..A01
A..A00
READ CYCLE TIMING PARAMETERS
8.5ns
9ns
12ns
15ns
Description
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time
Clock High Time
Clock Low Time
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
10
4
12
5
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
5
Clock to Output Valid
9
10
12
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
3
2
3
2
3
2
4
4
4
4
5
5
0
0
0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
Bank Enable Setup
Address Hold
Bank Enable Hold
*TBD
FIG. 3 SYNCHRONOUS ONLY READ CYCLE
t
KHKH
t
KLKH
t
KHKL
CLK
t
AVKH
EX
Addr 1
Addr 1
Addr 2
ADDR
t
KHAX
t
KHQV
G
GW
DQ
t
GLQV
t
GLQX
t
KHQX
Q(Addr 1)
Q(Addr 1)
Q(Addr 2)
t
KHQZ
t
KHQX1
Read Cycle
Back to Back Read
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6
August 2000 Rev.0
ECO#13089
EDI2CG264128V
FIG. 4 SYNCHRONOUS-BURST READ CYCLE
t
KHKH
t
KHKL KLKH
t
CLK
t
SPVKH
KHSPX
t
ADSP
t
SCVKH
KHSCX
t
ADSC
ADDR
t
AVKH
t
KHAX
BWx,
GW
t
EVKH
t
KHEX
Ex
t
AVVKH
KHAVX
t
ADV
G
t
GHQX
t
KHQV
t
GLQV
t
GHQZ
t
GLQX
DQ
t
KHQX
t
KHQX
Burst Read Cycle
Read Cycle
August 2000 Rev.0
ECO#13089
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White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG264128V
WRITE CYCLE TIMING PARAMETERS
8.5ns
9ns
12ns
15ns
Description
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time
Clock High Time
Clock Low Time
Address Setup
tKHKH
tKHKL
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
9
12
5
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
Data Hold
FIG. 5 SYNCHRONOUS (NON-BURST) WRITE CYCLE
t
KHKH
t
AVKH
t
KHKL
tKLKH
t
KHAX
CLK
Ex
ADDR
Addr 1
Addr 1
Addr 2
tKHGWH
t
GWLKH
GW
G
t
KHGH
DQ
t
KHDX
t
DVKH
t
GHKH
Write Cycle
Back to Back Writes
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
8
August 2000 Rev.0
ECO#13089
EDI2CG264128V
FIG. 6 SYNCHRONOUS-BURST WRITE CYCLE
t
KHKH
t
KHKL
t
KLKH
CLK
ADSP
ADSC
ADDR
t
AVKH
t
KHAX
BWx,
GW
t
EVKH
t
KHEX
Ex
t
AVVKH
KHAVX
t
ADV
G
t
DVKH
t
KHQX
DQ
t
KHQX
Early Write Cycle
Burst - Late Write- Cycle
August 2000 Rev.0
ECO#13089
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White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG264128V
FIG. 7 SYNCHRONOUS (NON-BURST) READ/WRITE CYCLE
t
KHKH
t
KHKL
t
KLKH
CLK
tAVKH
Ex
Addr 1
Addr 2
ADDR
tKHQV
tKHDX
G
GW
t
KHQX
DQ
Q (Addr 1)
D (Addr 2)
t
KHDX
t
DVKH
Read Cycle
Write Cycle
Back to Back Cycles
G Controlled
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August 2000 Rev.0
ECO#13089
EDI2CG264128V
PACKAGE DESCRIPTION: 144 LEAD SMALL OUTLINE DIMM
Package No. 409
0.175
MAX.
2.667 MAX.
0.157
R18
1.000
MAX.
U1
U3
0.788
R17
P1
0.181 TYP
0.913
1.112
1.291
1.490
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
Part Number
Organization
Voltage
Speed (ns)
Package
EDI2CG264128V85D1*
EDI2CG264128V9D1*
EDI2CG264128V12D1
EDI2CG264128V15D1
2x128Kx64
2x128Kx64
2x128Kx64
2x128Kx64
3.3
3.3
3.3
3.3
8.5
9
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
12
15
*Consult Factory for Availability
August 2000 Rev.0
ECO#13089
11
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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