EDI2CG472128V-D2 [ETC]
SSRAM Modules ; SSRAM模块\n
| 型号： | EDI2CG472128V-D2 |
| 厂家： | 
ETC |
| 描述： | SSRAM Modules
|
| 文件： | 总12页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI2CG472128V
4x128Kx72, 3.3V Sync/Sync Burst SRAM Dual Key DIMM
FEATURES
■ 4x128Kx72 Synchronous, Synchronous Burst
■ Access Speed(s): tKHQV = 8.5, 10, 12, 15ns
■ Flow-Through Architecture
The EDI2CG472128VxxD2 is a Synchronous/Synchronous Burst
SRAM, 84 position Dual Key; Double High DIMM (168 contacts)
Module, organized as 4x128Kx72. The Module contains eight (8)
Synchronous Burst Ram Devices, packaged in the industry stan-
dard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/Sync
Burst, Flow-Through, with support for either linear or sequential
burst. This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only Mode,
provides a high performance cost advantage over BiCMOS asyn-
chronous device architectures.
■ Linear and Sequential Burst Support via MODE pin
■ Clock Controlled Registered Module Enable (EM\)
■ Clock Controlled Registered Bank Enables (E1\, E2\, E3\, E4\)
■ Clock Controlled Byte Write Mode Enable (BWE\)
■ Clock Controlled Byte Write Enables (BW1-8\)
■ Clock Controlled Registered Address
■ Clock Controlled Registered Global Write (GW\)
■ Aysnchronous Output Enable (G\)
Synchronous Only operations are performed via strapping ADSC\
Low, and ADSP\ / ADV\ High, which provides for Ultra Fast
Accesses in Read Mode while providing for internally self-timed
Early Writes.
■ Internally self-timed Write
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined with full flexibility, which
allows individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
■ Individual Bank Sleep Mode enables (ZZ1, ZZ2, ZZ3, ZZ4)
■ Gold Lead Finish
■ 3.3V ± 10% Operation
■ Common Data I/O
■ High Capacitance (30pF) drive, at rated Access Speed
■ Single total array Clock
■ Multiple Vcc and Vss
March 1998 Rev. 0
ECO# 10038
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472128V
PIN CONFIGURATION
PIN SYMBOLS
PIN NAMES
DQ0-63
DQP0-7
A0-6
Input/Output Bus
Parity Bits
PIN
PIN
FRONT PIN
BACK
SS
FRONT PIN
BACK
DQP
CC
NC
1
2
3
4
5
6
7
V
SS
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
2
85
86
87
88
127
V
V
CC
V
128
129
130
131
132
133
134
135
136
137
138
139
140
141
A
0
RFU
Address Bus
DQ16
DQ17
DQ18
DQ19
DQ23
DQ22
DQ21
DQ20
A1
A
A
16
E1\, E2\,
E3\, E4\
Synchronous Bank Enables
A15
2
A
14
A3
89
90
BWE\
BW1-8\
CLK
Byte Write Mode Enable
Byte Write Enables
Array Clock
VCC
V
A
A
CC
A13
V
SS
ZZ
CC
A
4
V
SS
DQP
CC
91
A5
2
8
9
12
3
92
V
A
6
A11
93
V
GW\
Synchronous Global Write
Enable
DQ24
DQ25
DQ26
DQ27
A7
DQ31
DQ30
DQ29
DQ28
10
10
11
12
94
VSS
VSS
95
G\
Asynchronous Output Enable
Synchronous Bank Enables
A8
96
A9
ZZ1, ZZ2,
ZZ3, ZZ4
13
97
RFU
RFU
E
4
\
\
E1\
98
V
SS
DQP
CC
14
15
16
V
NC
SS
E
2
99
E
3\
4
Vcc
Vss
NC
3.3V Power Supply
Ground
V
SS
142
143
144
145
100
101
102
103
104
105
106
107
V
SS
CLK
SS
V
V
CC
DQ39
DQ38
DQ37
DQ36
17
18
19
20
MODE
EM\
DQ32
DQ33
No Connect
V
GW\
G\
DQ34
DQ35
BWE\
RFU
146
147
148
149
150
151
152
153
154
155
156
157
158
159
V
CC
BW
BW
V
SS
DQP
CC
21
22
VCC
V
SS
ZZ
CC
63
64
BW
BW
BW
BW
4
3
8
7
\
\
\
\
2
\
3
5
1
\
65
66
67
68
69
70
71
72
73
74
75
76
77
V
V
23
24
25
26
27
28
29
BW6\
DQ40
DQ41
DQ42
DQ43
108
109
110
111
112
113
114
115
DQ47
DQ46
DQ45
DQ44
BW
5\
ADSC\
ADSP\
V
SS
ADV\
SS
DQP
CC
V
SS
V
V
SS
DQP
CC
VSS
NC
6
0
NC
30
31
32
33
34
35
36
V
DQ
CC
V
VCC
V
0
DQ
DQ
DQ
7
DQ48
DQ49
DQ50
DQ51
DQ55
DQ54
DQ53
DQ52
DQ
1
6
5
116
117
DQ
DQ
2
3
118
119
120
DQ
SS
DQP
CC
4
160
161
V
SS
ZZ
CC
V
V
SS
ZZ
CC
V
SS
DQP
CC
1
1
4
7
162
163
164
165
166
167
168
78
79
80
81
82
83
84
V
V
V
37
38
39
V
121
122
123
DQ
DQ
8
9
DQ63
DQ62
DQ61
DQ60
DQ15
DQ14
DQ13
DQ12
DQ56
DQ57
DQ58
DQ59
DQ10
DQ11
124
125
40
41
42
VSS
VSS
VSS
VSS
126
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
EDI2CG472128V
FUNCTIONAL BLOCK DIAGRAM
A0-16
GW\
G\
ZZ
ZZ
ZZ1
DQ
DQ
GW\
GW\
U1
U2
G\
E\
G\
E\
DQP
DQP
CLK
CLK
CLK
CLK
CLK
CLK
E1\
ZZ
2
ZZ
DQ
ZZ
DQ
GW\
GW\
U4
U3
G\
E\
G\
E\
DQP
DQP
E2\
ZZ
DQ
ZZ
3
ZZ
DQ
GW\
GW\
U5
U6
G\
E\
G\
E\
DQP
DQP
E3\
ZZ
ZZ
ZZ
4
DQ
DQ
GW\
GW\
U7
U8
G\
E\
G\
E\
DQP
DQP
CLK
CLK
E4\
DQP0-3
DQ0-31
DQ32-63
CLK
DQP4-7
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472128V
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
2, 87, 4, 89, 7, 92
9, 94, 12, 96, 10
93, 8, 91, 5, 88, 3
A0-16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The
burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.
107, 106, 23,
22, 109, 108,
25, 24
BW1\, BW1\,
BW3\, BW4\,
BW5\, BW6\,
BW7\, BW8\
Input
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW0/ controls DQ0-7 and DQP0, BW1\
controls DQ8-15 and DQP1. BW2\ controls DQ16-23 and DQP2. BW3\ controls DQ24-31 and DQP3. BW4\ controls DQ32-39
and DQP4. BW5\ controls DQ40-47 and DQP5. BW6\ controls DQ48-55 and DQP6. BW7\ controls DQ56-64 and DQP7.
104
19
BWE\
GW\
CLK
Input
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the
rising edge of CLK.
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines and
must meet the setup and hold times around the rising edge of CLK.
101
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times around the clock’s rising edge.
98, 15,
99,14
E1\, E2\
E3\, E4\
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\.
103
111
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
ADV\
Input
Synchronous
Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
27
26
17
ADSP\
ADSC\
MODE
Input
Synchronous
Address Status Processor: This active LOW input, along with EL\ and EH\ being LOW, causes a new external
address to be registered and a READ cycle is initiated using the new address.
Input
Synchronous
Address Status Controller: This active LOW input causes device to be de-selected or selected along with new
external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
Input Static
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin
selects INTERLEAVED BURST.
36, 50,
64, 78
ZZ1, ZZ2,
ZZ3, ZZ4
Input
Asynchronous
Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode.
For normal operation, this input has to be either LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is
DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
113, 120, 127,
134, 141, 148,
155, 162
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is parity bit for DQ16-23. DQP3
is parity bit for DQ24-31. DQP4\ is parity bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6\ is parity bit for DQ48-55.
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a 128K x 64, the parity bits need to
be tied to Vss through a 10K ohm resistor.
Various
Various
Vcc
Vss
Supply
Ground
Core power supply: +3.3V -5%/+10%
Ground
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
EDI2CG472128V
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1\
H
X
L
E2\
X
H
H
H
L
E3\
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
E4\ ADSP\ ADSC\ ADV\ GW\
G\
X
X
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
Addr. Used
None
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
High-Z
High-Z
None
X
X
X
X
L
Q
External
External
External
External
External
External
External
External
External
External
Next
L
L
H
L
High-Z
H
H
L
L
Q
L
L
H
X
X
L
High-Z
H
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
X
H
X
H
H
H
H
X
X
X
X
H
X
H
X
D
H
L
L
L
D
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
X
X
X
X
L
High-Z
Next
L
D
Next
L
L
D
Next
L
L
D
Next
L
L
D
Next
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
L
High-Z
Q
H
L
High-Z
Q
H
L
High-Z
Q
H
X
X
X
X
High-Z
D
D
D
D
L
L
L
*All Truth Table Functions Repeat for Bank 3 (E3\) and Bank 4 (E4\)
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472128V
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1\
L
E2\
H
H
L
E3\
H
H
H
H
L
E4\
H
H
H
H
H
H
L
GW\
L
G\
H
L
ZZ
L
CLK
↑
DQ
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
Synchronous Write-Bank 3
Synchronous Read-Bank 3
Synchronous Write-Bank 4
Synchronous Read-Bank 4
Snooze Mode
High-Z
L
H
L
L
↑
H
H
H
H
H
H
X
H
L
L
↑
High-Z
High-Z
High-Z
High-Z
L
H
L
L
↑
H
H
H
H
X
H
L
L
↑
L
H
L
L
↑
H
H
X
H
L
L
↑
L
H
X
L
↑
X
X
H
X
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS*
Parameter
Sym
VCC
VSS
VIH
VIL
ILI
Min
3.14
0.0
2.2
-0.3
-2
Typ
3.3
0.0
Max
3.6
Units
V
Voltage on Vcc Relative to Vss
Vin
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
0°C to +70°C
Supply Voltage
Supply Voltage
Input High
Storage Temperature
0.0
V
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
3.0 VCC +0.3
V
-40°C to +85°C
10 mA
Input Low
0.0
1
0.3
2
V
Input Leakage
Output Leakage
µA
µA
ILo
-2
1
2
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in
operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
Symbol
Icc1
Typ
2.0
8.5
2.9
1.8
10
2.7
1.8
12
2.7
1.3
15
2.5
1.3
Units
Power Supply Current
A
A
Power Supply Current
Icc
875
Device Selected,No Operation
Snooze Mode
IccZZ
Icc3
500
270
900
700
300
1.1
700
350
1.1
700
350
1.0
700
350
1.0
mA
mA
A
CMOS Standby
Clock Running-Deselect
IccK
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
I/O
Unit
Output
Z0=50Ω
Input Pulse Levels
VSS to 3.0
1.25
V
V
Input and Output Timing Levels
Output Test Equivalencies
See figure, at left
50Ω
Vt = 11.25
V
AC Output Load Equivalent
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
6
EDI2CG472128V
BURST ADDRESS TABLE (MODE = NC/VCC)
BURST ADDRESS TABLE (MODE = VSS)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A..A00
A..A01
A..A10
A..A11
A..A01
A..A10
A..A11
A..A00
A..A10
A..A11
A..A00
A..A01
A..A11
A..A00
A..A01
A..A10
A..A00
A..A01
A..A10
A..A11
A..A01
A..A00
A..A11
A..A10
A..A10
A..A11
A..A00
A..A01
A..A11
A..A10
A..A01
A..A00
READ CYCLE TIMING PARAMETERS
8.5ns
10ns
12ns
15ns
Description
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time
Clock High Time
Clock Low Time
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
15
5
15
5
20
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
6
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
10
12
15
3
4
3
4
3
4
5
5
5
5
6
5
0
0
0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
Bank Enable Setup
Address Hold
Bank Enable Hold
*TBD
SYNCHRONOUS ONLY READ CYCLE
t
KHKH
t
KLKH
t
KHKL
CLK
t
AVKH
Ex\
Addr 1
Addr 1
Addr 2
ADDR
t
KHAX
t
KHQV
G\
t
GLQV
GW\
DQ
t
GLQX
t
KHQX
Q(Addr 1)
Q(Addr 1)
Q(Addr 2)
t
KHQZ
t
KHQX1
Read Cycle
Back to Back Read
7
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472128V
SYNCHRONOUS-BURST READ CYCLE
t
KHKH
t
KHKL KLKH
t
CLK
t
SPVKH
KHSPX
t
ADSP\
t
SCVKH
KHSCX
t
ADSC\
ADDR
t
AVKH
t
KHAX
BWx\,
GW\
t
EVKH
t
KHEX
Ex\
t
AVVKH
KHAVX
t
ADV\
G\
t
GHQX
t
KHQV
t
GLQV
t
GHQZ
t
GLQX
DQ
t
KHQX
t
KHQX
Burst Read Cycle
Read Cycle
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
8
EDI2CG472128V
WRITE CYCLE TIMING PARAMETERS
8.5ns
10ns
12ns
15ns
Description
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time
Clock High Time
Clock Low Time
Address Setup
tKHKH
tKHKL
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
15
5
15
5
20
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
6
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
Data Hold
*TBD
SYNCHRONOUS (NON-BURST) WRITE CYCLE
t
KHKH
t
AVKH
t
KHKL
tKLKH
t
KHAX
CLK
Ex\
ADDR
GW\
Addr 1
Addr 1
Addr 2
tKHGWH
t
GWLKH
G\
t
KHGH
DQ
t
KHDX
t
DVKH
t
GHKH
Write Cycle
Back to Back Writes
9
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472128V
SYNCHRONOUS-BURST WRITE CYCLE
tKHKH
tKHKL
tKLKH
CLK
ADSP\
ADSC\
ADDR
t
AVKH
tKHAX
BWx\,
GW\
tEVKH
tKHEX
Ex\
tAVVKH
tKHAVX
ADV\
G\
t
DVKH
tKHQX
DQ
tKHQX
Early Write Cycle
Burst - Late Write - Cycle
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
10
EDI2CG472128V
SYNCHRONOUS (NON-BURST) READ/WRITE CYCLE
t
KHKH
t
KHKL
t
KLKH
CLK
tAVKH
Ex\
Addr 1
Addr 2
ADDR
t
KHQV
tKHDX
G\
GW\
t
KHQX
DQ
Q (Addr 1)
D (Addr 2)
t
KHDX
t
DVKH
Read Cycle
Write Cycle
Back to Back Cycles
G\ Controlled
11
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI2CG472128V
PACKAGE DESCRIPTION: 168 GOLD LEAD DIMM
Package No. 410
.195
MAX.
.157
(2x)
5.255 MAX.
199
1.00
MAX.
.160
MIN.
U5
U6
U1
U2
.700
P1
.050 TYP.
.078 (2X)
.050±.004
.250 (2x)
2.150
.450
.125
1.450
1.700
P85
U8
U7
U3
U4
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
Part Number
Organization
4x128Kx72
Voltage
Speed (ns)
Package
EDI2CG472128V85D2*
EDI2CG472128V10D2*
EDI2CG472128V12D2
EDI2CG472128V15D2
3.3
3.3
3.3
3.3
8.5
10
12
15
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
4x128Kx72
4x128Kx72
4x128Kx72
*Consult Factory for Availability
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
12
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