EDI2CG472256V12D2 [WEDC]
8 Megabyte Sync/Sync Burst, Dual Key DIMM; 8兆字节同步/同步连拍，双DIMM关键
| 型号： | EDI2CG472256V12D2 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| 文件： | 总11页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI2CG472256V
White Electronic Designs
ADVANCED*
8 Megabyte Sync/Sync Burst, Dual Key DIMM
FEATURES
DESCRIPTION
The EDI2CG472256VxxD2 is a Synchronous/Synchronous
Burst SRAM, 84 position Dual Key; Double High DIMM (168
contacts) Module, organized as 4x256Kx72. The Module
contains sixteen (16) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm
TQFP placed on a Multilayer FR4 Substrate. The module
architecture is defined as a Sync/Sync Burst, Flow-
Through, with support for either linear or sequential burst.
This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only
Mode, provides a high performance cost advantage over
BiCMOS aysnchronous device architectures.
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4x256Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear and Sequential Burst Support via MODE pin
Clock Controlled Registered Module Enable (EM#)
Clock Controlled Registered Bank Enables (E1#, E2#,
E3#, E4#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables (BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally Self-timed Write
Individual Bank Sleep Mode enables (ZZ1, ZZ2, ZZ3, ZZ4)
Gold Lead Finish
3.3V +10%, - 5% Operation
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ꢀ
ꢀ
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Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP# / ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well as
an Asynchronous Output enable. This Module has been
defined with full flexibility, which allows individual control
of each of the eight bytes, as well as Quad Words in both
Read and Write Operations.
Access Speed(s): TKHQV=9, 10, 12, 15ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access Speed
Single Total Array Clock
Multiple Vcc and Gnd
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN
FRONT
PIN
BACK
PIN NAMES
Input/Output Bus
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
FRONT
NC4
VCC
DQ16
DQ17
DQ18
DQ19
VSS
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
BACK
DQP2
VCC
DQ23
DQ22
DQ21
DQ20
VSS
1
VSS
85
VSS
DQ0-DQ63
DQP0-DQP7
A0-A17
2
A0
86
A17
Parity Bits
3
A16
87
A1
4
A2
88
A15
Address Bus
Module Enable
5
A14
89
A3
EM#
6
VCC
90
VCC
E1#, E2#, E3#, E4# Synchronous Bank Enables
7
A4
91
A13
8
A12
92
A5
ZZ2
VCC
DQP3
VCC
BWE#
Byte Write Mode Enable
Byte Write Enables
9
A6
93
A11
BWE1#-BW8#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
A10
VSS
A8
NC
E4#
E2#
VSS
MODE
EM#
GW#
NC1
VCC
BW4#
BW3#
BW8#
BW7#
ADSC#
ADSP#
NC2
E1#
94
95
96
97
98
99
A7
VSS
A9
NC3
E1#
E3#
VSS
CK
VSS
G#
BWE#
VCC
BW2#
BW1#
BW6#
BW5#
VSS
ADV#
VSS
DQP0
VCC
DQ7
DQ6
DQ5
DQ4
VSS
DQ24
DQ25
DQ26
DQ27
VSS
DQ31
DQ30
DQ29
DQ28
VSS
CK
Array Clock
GW#
Synchronous Global Write Enable
Asynchronous Output Enable
Blank Sleep Mode Enables
3.3V Power Supply
G#
ZZ1, ZZ2, ZZ3, ZZ4
NC5
VCC
DQP4
VCC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Vcc
Vss
DQ32
DQ33
DQ34
DQ35
VSS
DQ39
DQ38
DQ37
DQ36
VSS
Ground
ZZ3
VCC
DQP5
VCC
DQ40
DQ41
DQ42
DQ43
VSS
DQ47
DQ46
DQ45
DQ44
VSS
NC6
VCC
DQP6
VCC
VCC
DQ0
DQ1
DQ2
DQ3
VSS
DQ48
DQ49
DQ50
DQ51
VSS
DQ55
DQ54
DQ53
DQ52
VSS
ZZ1
VCC
DQP1
VCC
ZZ4
VCC
DQP7
VCC
DQ8
DQ9
DQ10
DQ11
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ56
DQ57
DQ58
DQ59
VSS
DQ63
DQ62
DQ61
DQ60
VSS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
ZZ1
E1#
MODE
ZZ2
E2#
ZZ3
E3#
ZZ4
E4#
GW#
G #
EM#
CK
ADSC#
ADSP#
ADV#
A0-17
BW1#
BW2#
DQP0
DQP1
DQ0-15
U1
U2
U3
U4
U5
U6
U7
U8
U9
U13
U14
U15
U16
BW3#
BW4#
DQP2
DQP3
U10
U11
U12
DQ16-31
BW5#
BW6#
DQP4
DQP5
DQ32-47
BW7#
BW8#
DQP6
DQP7
DQ48-63
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
2, 87, 4, 89, 7, 92,
9, 94, 12, 96, 10, 93,
8, 91, 5, 88, 3, 86
Addresses: These inputs are registered and must meet the setup and hold times
around the rising edge of CK. The burst counter generates internal addresses
associated with A0 and A1, during burst and wait cycle.
Input
Synchronous
A0-A17
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.
BW0/ controls DQ0-7 and DQP0, BW1# controls DQ8-15 and DQP1.
BW2# controls DQ16-23 and DQP2. BW3# controls DQ24-31 and DQP3.
BW4# controls DQ32-39 and DQP4. BW5# controls DQ40-47 and DQP5.
BW6# controls DQ48-55 and DQP6. BW7# controls DQ56-64 and DQP7.
BW1#, BW2#,
BW3#, BW4#,
BW5#, BW6#,
BW7#, BW8#
107, 106, 23, 22,
109, 108, 25, 24
Input
Synchronous
Input
Write Enable: This active LOW input gates byte write operations and must meet the
setup and hold times around the rising edge of CK.
104
19
BWE#
GW#
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent
of the BWE# and BWx# lines and must meet the setup and hold times around the
rising edge of CK.
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
Input
Synchronous
101
CK
E1#, E2#,
E3#, E4#
Input
Bank Enables: These active LOW inputs are used to enable each individual bank
and to gate ADSP#.
98, 15, 99, 14
103
Synchronous
G#
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
Input
Address Status Processor: This active LOW input is used to control the internal burst
counter. A HIGH on this pin generates wait cycle (no address advance).
111
27
ADV#
Synchronous
Address Status Processor: This active LOW input, along with EL# and EH# being
LOW, causes a new external address to be registered and a READ cycle is initiated
using the new address.
Input
Synchronous
ADSP#
Address Status Controller: This active LOW input causes device to be de-selected or
selected along with new external address to be registered.
Input
26
17
ADSC#
MODE
Synchronous
A READ or WRITE cycle is initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR
BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.
Input Static
Snooze: These active HIGH inputs put the individual banks in low power
consumption standby mode. For normal operation, this input has to be either
LOW or NC (no connect).
36, 50,
64, 78
ZZ1, ZZ2,
ZZ3, ZZ4
Input
Asynchronous
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
Various
DQ0-63
DQP0-7
Input/Output
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15.
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity
bit for DQ-32-39. DQP5 is parity bit for DQ40-47. DQP6# is parity bit for DQ48-55.
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a
128K x 64, the parity bits need to be tied to VSS through a 10K ohm resistor.
113, 120, 127, 134,
141, 148, 155, 162
Various
Various
Vcc
Vss
Supply
Ground
Power Supply: +3.3V -5%/+10%
Ground
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1# E2# E3# E4# ADSP# ADSC# ADV# GW# G#
CK
L-H
DQ
High-Z
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Addr. Used
None
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
H
X
L
X
H
H
H
L
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
X
X
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
None
External
External
External
External
External
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Next
Next
Next
X
X
X
X
L
L
L
L
L
H
L
H
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
L
H
L
H
L
H
H
L
H
L
L
H
L
H
H
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
X
H
X
H
H
H
H
X
X
X
X
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
L
L
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Next
Next
Next
D
D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
High-Z
Q
High-Z
Q
High-Z
Q
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
L
H
X
High-Z
D
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
H
H
H
H
X
H
*
*
*
*
*
*
X
H
X
H
H
H
H
H
H
L
L
L
X
X
X
L-H
L-H
L-H
D
D
D
Current
Current
Current
*All Truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1#
L
E2#
H
H
L
E3#
H
H
H
H
L
E4#
H
H
H
H
H
H
L
GW#
L
G#
H
L
H
L
ZZ
L
L
L
L
L
L
L
L
CK
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X
DQ
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
Synchronous Write-Bank 3
Synchronous Read-Bank 3
Synchronous Write-Bank 4
Synchronous Read-Bank 4
Snooze Mode
High-Z
L
H
L
H
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
L
H
H
H
H
H
X
L
H
L
H
H
L
H
L
L
H
H
X
L
X
X
X
H
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS
VIN
-0.5V to +4.6V
-0.5V to VCC +0.5V
-55°C to +125°C
0°C to +70°C
-40°C to +85°C
20 mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
Supply Voltage
Input High
Input Low
Input Leakage
Output Leakage
VCC
3.14
3.3
3.6
0.0
VCC+0.3
0.8
2
V
V
V
V
µA
µA
VSS
VIH
VIL
ILI
0.0
2.0
-0.3
-2
0.0
3.0
0.0
1
Storage Temperature
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
ILO
-2
1
2
*Stress greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in operational sections of this specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Parameter
Sym
Max
2.4V
Min
Condition
IOH= -4mA
IOL= 8mA
Output High
VOH
Output Low
VOL
0.4V
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Description
SYM
Typ
9
10
12
15
Units
Power Supply Current
Icc1
2.0
2.9
2.7
2.7
2.5
A
Power Supply Current Device
Selected, No Operation
Icc
875
1.8
1.8
1.3
1.3
A
Snooze Mode
CMOS Standby
Clock Running-Deselect
IccZZ
Icc3
IccK
500
270
900
700
350
1.1
700
350
1.1
700
350
1.0
700
350
1.0
mA
mA
A
AC TEST CONDITIONS
AC TEST LOAD
Input Pulse Levels
Vss to 3.0V
1.25V
DQ
Input and Output Timing Ref.
Output Test equivalencies
Z0 = 50 Ω
50 Ω
Fig. 1 Output Load Equivalent
Vt = 1.25V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
BURST ADDRESS TABLE (MODE=NC/VCC)
BURST ADDRESS TABLE (MODE=GND)
First
Second
Address
(internal)
A-A01
A-A00
A-A11
A-A10
Third
Fourth
First
Second
Address
(internal)
A-A01
A-A10
A-A11
A-A00
Third
Fourth
Address
Address
Address
Address
Address
(external)
A-A00
Address
(external)
A-A00
(internal)
A-A10
A-A11
A-A00
A-A01
(internal)
A-A11
A-A10
A-A01
A-A00
(internal)
A-A10
A-A11
A-A00
A-A01
(internal)
A-A11
A-A00
A-A01
A-A10
A-A01
A-A10
A-A11
A-A01
A-A10
A-A11
READ CYCLE TIMING PARAMETERS
9ns
10ns
Max
12ns
Max
15ns
Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
Sym
tKHKH
Min
15
5
Max
Min
15
5
Min
15
5
20
6
6
tKHKL
tKLKH
tKHQV
tKHQX
tKHQX
tGLQV
tGLQX
5
5
5
9
10
12
15
1
3
4
3
4
3
4
3
4
5
5
5
5
5
5
6
0
0
0
0
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
5
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
SYNCHRONOUS ONLY READ CYCLE
t
KHKH
t
KLKH
t
KHKL
CK
t
AVKH
Ex#
Addr 1
Addr 1
Addr 2
ADDR
t
KHAX
t
KHQV
G#
GW#
DQ
t
GLQV
t
GLQX
t
KHQX
Q(Addr 1)
Q(Addr 1)
Q(Addr 2)
t
KHQZ
t
KHQX1
Read Cycle
Back to Back Read
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
SYNC-BURST READ CYCLE
tKHKH
t
KHKL KLKH
t
CK
t
SPVKH
tKHSPX
ADSP#
t
SCVKH
tKHSCX
ADSC#
ADDR
t
AVKtHKHAX
BWx,
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
tGHQX
tKHQV
t
GLQV
tGHQZ
t
GLQX
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
WRITE CYCLE TIMING PARAMETERS
9ns
Max
10ns
12ns
Max
15ns
Min Max
Units
ns
ns
Description
Sym
tKHKH
tKHKL
tKLKH
Min
Min
Max
Min
Clock Cycle Time
Clock High Time
15
15
15
20
6
6
5
5
5
5
5
5
Clock Low Time
ns
Address Setup
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
SYNC (NON-BURST) WRITE CYCLE
t
KHKH
t
AVKH
t
KHKL
tKLKH
t
KHAX
CK
Ex#
ADDR
Addr 1
Addr 1
Addr 2
tKHGWH
t
GWLKH
GW#
OE#
DQ
t
KHGH
t
KHDX
t
DVKH
t
GHKH
Write Cycle
Back to Back Writes
SYNCBURST WRITE CYCLE
t
KHKH
t
KHKL
tKLKH
CK
ADSP#
ADSC#
ADDR
t
AVKH
t
KHAX
BWx#
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
t
DVKH
t
KHQX
DQ
tKHQX
Early Write Cycle
Burst - Late Write - Cycle
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
SYNC (NON-BURST) READ/WRITE CYCLE
t
KHKH
t
KLKH
CK
t
AVKH
Ex#
Addr 1
Addr 2
ADDR
t
KHQV
tKHDX
G#
GW#
t
KHQX
DQ
Q (Addr 1)
D (Addr 2)
t
KHDX
t
DVKH
Read Cycle
Write Cycle
Back to Back Cycles
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG472256V
White Electronic Designs
ADVANCED
PACKAGE DESCRIPTION
Package No. 406
168 Lead
Dual Key DIMM
0.195
MAX.
5.255 MAX.
0.157
195
(2x)
1.500
MAX.
0.700
P1
0.078 (2X)
.050 TYP.
0.225
MIN.
0.450
0.575
2.150
0.250
1.450
0.125
(2X)
0.125
0.350
0.925
1.700
ORDERING INFORMATION
Part Number
Organization
Voltage
3.3
Speed (ns)
Package
EDI2CG472256V9D2*
EDI2CG472256V10D2*
EDI2CG472256V12D2
EDI2CG472256V15D2
*Consult Factory for Availability
4x256Kx72
4x256Kx72
4x256Kx72
4x256Kx72
9
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
3.3
10
12
15
3.3
3.3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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