EDI2DL32256V35BC [WEDC]
256Kx32 Synchronous Pipline Burst SRAM 3.3V; 256Kx32同步Pipline突发3.3V SRAM
| 型号： | EDI2DL32256V35BC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 256Kx32 Synchronous Pipline Burst SRAM 3.3V |
| 文件： | 总8页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI2DL32256V
256Kx32 Synchronous Pipline Burst SRAM 3.3V
FEATURES
DESCRIPTION
■ tKHQV times of 3.5, 3.8 and 4.0ns
■ 166, 150 and 133 MHz clock speed
■ DSP Memory Solution
The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline
Burst SRAM constructed with two 256Kx16 die mounted on a
multi-layer laminate substrate. The device is packaged in a 119
lead,14mmby22mm,BGA.It is available withclockspeeds of166,
150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing
the user to develop a fast external memory for Texas Instruments’
“C6x”. In Burst Mode data from the first memory location is
available in three clock cycles, while the subsequent data is
available in one clock cycle (3/1/1/1). Subsequent burst ad-
dresses are generated by the TMS320C6x DSP. Individual address
locations can also be read, allowing one memory access in 3 clock
cycles. Allsynchronous inputs are gatedbyregisters controlledby
a positive-edge-triggered clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, chip enable (CE\), burst
control input (ADSC\), byte write enables (BW0\ to BW3\) and
Write Enable (BWE\).
• Texas Instruments’ TMS320C6201
• Texas Instruments’ TMS320C67x
■ Package:
• 119 pin BGA, JEDEC MO-163
■ 3.3V Operating Supply Voltage
■ 3.5ns Output Enable access time
■ Single Write Control and Output Enable Lines
■ Single Chip Enable Line
■ 56% space savings vs. monolithic TQFPs
■ Multiple VCC and VSS pins
Asynchronous inputs include the output enable (OE\), burst mode
control (MODE), and sleep mode control (ZZ). The data outputs
(DQ), enabled by OE\, are also asynchronous.
■ Reduced inductance and capacitance
Address lines and the chip enable are registered with the address
status controller (ADSC\) input pin.
FIG. 1
PIN CONFIGURATION
BLOCK DIAGRAM
1
2
3
4
NC
ADSC\
VDD
NC
CE\
OE\
NC
NC
VDD
CLK
NC
BWE\
A1
5
6
7
A
B
C
D
E
F
VDD
NC
A
A
A
A
VDD
NC
A
B
C
D
E
F
A0-17
CLK
NC
A
A
A
NC
A
A
A
A
NC
ADSC\
OE\
BWE\
CE\
MODE
ZZ
DQ16
DQ18
VDD
DQ21
DQ23
VDD
DQ31
DQ29
VDD
DQ26
DQ24
NC
NC
VSS
VSS
VSS
BE2\
VSS
NC
VSS
BE3\
VSS
VSS
VSS
MODE
A
VSS
VSS
VSS
BE1\
VSS
NC
VSS
BE0\
VSS
VSS
VSS
NC
A
NC
DQ9
DQ11
DQ12
DQ14
VDD
DQ6
DQ4
DQ3
DQ1
NC
A
DQ8
DQ10
VDD
DQ13
DQ15
VDD
DQ7
DQ5
VDD
DQ2
DQ0
NC
256K X 16
SSRAM
DQ17
DQ19
DQ20
DQ22
VDD
DQ30
DQ28
DQ27
DQ25
NC
BE
BE
0
1
\
\
G
H
J
G
H
J
BE
BE
2
3
\
\
DQ
DQ
DQ16
0
8
-
-
7
15
K
L
M
N
P
K
L
M
N
P
-
-
23
31
256K X 16
SSRAM
DQ24
A0
R
T
U
A
VDD
A
R
T
U
NC
NC
NC
NC
6
ZZ
VDD
1
NC
NC
3
NC
4
NC
5
VDD
7
2
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
Various
A0-17
Input
Synchronous
Addresses: These inputs are registered and must meet setup and hold times around the rising edge
of CLK.
L5,G5
G3,L3
BE0\,BE1\,
BE2\,BE3\
Input
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ BE2\, BE3\ cycle. BE0\ controls
DQ0-7. BE1\ controls DQ8-15. BE2\ controls DQ16-23. BE3\ controls DQ24-31
M4
K4
E4
BWE\
CLK
CE\
Input
Synchronous
Byte Write Enable: This active LOW input gates byte write operations and must meet the setup and hold
times around the rising edge of CLK.
Input
Synchronous
Clock:This signal registers the addresses, data, chip enables, write control and burst control inputs on
its rising edge. All synchronous inputs must meet setup and hold times around the clockís rising edge.
Input
Chip Enable: This active LOW inputs is used to enable the device.
Synchronous
F4
OE\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers
B4
ADSC\
Input
Synchronous
Address Status Controller: This active LOW input causes device to be deselected or selected along with new
external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
R3
T7
MODE
ZZ
Input
Static Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or
HIGH on this pin selects INTERLEAVED BURST.
Input
Synchronous
Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal
operation, this input has to be either LOW or NC (no connect)
Various
Various
Various
DQ0-31
Vcc
Input/Output
Supply
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31
Core power supply: +3.3V -5%/+5%
Ground
Vss
Ground
TRUTH TABLE
Operation
Address Used
CE\
H
L
ADSC\
L
WRITE\
OE\
X
X
L
DQ
High-Z
D
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
None
X
L
External
External
External
Current
Current
Current
Current
Current
Current
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst
L
L
H
L
High-Z
Q
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
H
H
H
L
High-Z
Q
H
H
H
X
X
High-Z
D
H
H
L
D
NOTE:
1. X means ìdonít careî, H means logic HIGH. L means logic LOW.
2a.WRITE\ = L, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals LOW
2b.WRITE\ = H, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals HIGH
3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle
5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time plus High-Z time for OE\ and staying HIGH though
out the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED OPERATING CONDITIONS
Voltage on Vcc Supply Relative to Vss
VIN
-0.5V to 4.6V
-0.5V to Vcc+0.5V
-55°C to +110°C
+110°C
Description
Symbol
VIH
Min
2
Max
Vcc+0.3
0.7
Unit
V
Input High Voltage
Input Low Voltage
Supply Voltage
Storage Temperature
VIL
-0.3
3.135
V
Junction Temperature
Power Dissipation
Vcc
3.465
V
3 Watts
Short Circuit Output Current (per I/O)
20 mA
CAPACITANCE
(f = 1MHz, VIN = VCC or VSS)
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
CA
Max
Unit
Address Lines
Data Lines
TBD
TBD
TBD
pF
pF
pF
CD/Q
CC
Control Lines
PARTIAL TRUTH TABLE
Function
BWE\
BE0\
BE1\
BE2\
BE\3
READ
H
L
L
X
L
L
X
H
L
X
H
L
X
H
L
WRITE one Byte (DQ0-7)
WRITE all Bytes
DC ELECTRICAL CHARACTERISTICS
(f = 1MHz, VIN = VCC or Vss)
Parameter
Symbol
Conditions
Min
Max
Units
Device Selected; all inputs ≤ VIL or ≥ VIH;
cycle time ≥ tKC MIN; VCC = MAX; outputs open
Power Supply Current: Operating
ICC1
850
mA
Device deselected; VCC = MAX; all inputs ≤
VSS +0.2 or ≥ VCC -0.2; all inputs static;
CLK frequency = 0
CMOS Standby
ISB2
20
mA
Device deselected; all inputs ≤ VIL or ≥ VIH;
all inputs static; VCC = MAX; CLK frequency = 0
TTL Standby
TTL Standby
ISB3
ISB4
40
40
mA
mA
Device deselected; all inputs ≤ VIL or ≥ VIH;
VCC = MAX; CLK cycle time ≥ tCK MIN
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
ILO
VOH
VOL
0V < VIN < VCC
-2
-2
2
2
µA
µA
V
Output(s) disabled, 0V ≤ VOUT ≤ VCC
IOH = -2.0mA
2.4
IOL = 2.0mA
0.7
V
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
I/O
Unit
V
Output
Z0=50Ω
Input Pulse Levels
VSS to 2.5
1.8
Input Rise and Fall Times (max)
Input and Output Timing Levels
Output Load
ns
1.25
V
50Ω
See figure, at left
1 V
Vt = 125
AC Output Load Equivalent
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
AC ELECTRICAL CHARACTERISTICS
Symbol
3.5ns
3.8ns
4.0ns
Description
Min
Max
Min
Max
Min
Max
Units
Clock
Clock cycle time
tKHKH
tKHKL
tKLKH
6
6.7
2.6
2.6
7.5
2.8
2.8
Clock HIGH time
2.4
2.4
Clock LOW time
Output Times
Clock to output valid
Clock to output in Low-Z
Clock to output in High-Z
OE to output valid
tKHQV
tKHQX
tKHQZ
3.5
3.8
4.0
0
0
0
1.5
6
1.5
6.7
3.5
1.5
7.5
3.8
tOELQV
tOELQX
tOEHQZ
3.5
OE to output in Low-Z
OE to output in High-Z
Setup Times
0
0
0
3.5
3.5
3.8
Address Status Controller valid to Clock
Address valid to Clock
Chip Enable valid to Clock
Write Enable (BWE\) valid to Clock
Data Valid to Clock
tSCVKH
tAVKH
tEVKH
tWLKH
tDVKH
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Hold Times
Address Status Controller Hold time
Address Hold time
tKHSCX
tKHAX
tKHEX
tKHWX
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Chip Enable Hold time
Write Enable (BWE\) Hold time
Data Hold time
tKHDX
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4
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
FIG. 2 READ TIMING
t
KHKL
t
KLKH
t
KHKH
CLK
tSC VKH
tKHSCX
ADSC\
CE\
tEVKH
tKHEX
tAVKH
A1
A5
A2
A3
A4
ADDR
OE\
tKHAX
tOELQX
tOEHQZ
tOELQV
WRITE\
DQ
tKHQZ
tKHQV
tKHQX
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A5)
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
FIG. 3 WRITE TIMING
tKHKL tKLKH
tKHKH
CLK
tSC VKH
tKHSCX
ADSC\
CE\
tEVKH
tKHEX
tAVKH
A4
A2
A3
A1
A5
ADDR
OE\
tKHAX
K
tWVKH
tKHWX
WRITE\
tKHDX
tDVKH
D(A2)
D(A3)
D(A5)
D(A1)
D(A4)
DQ
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November 2000, Rev. 1
ECO #13417
EDI2DL32256V
ORDERING INFORMATION
Industrial Temperature Range (-40°C to +85°C)
Commercial Temperature Range (0°C to +70°C)
Part Number
tKQ (ns)
Clock Frequency Package
Part Number
tKQ (ns)
Clock Frequency Package
(MHz)
No.
(MHz)
No.
EDI2DL32256V40BI
4.0
133
TBD
EDI2DL32256V35BC
EDI2DL32256V38BC
EDI2DL32256V40BC
3.5
3.8
4.0
166
TBD
150
133
TBD
TBD
PACKAGE DESCRIPTION: 119 LEAD BGA
JEDEC MO-163
0.110 MAX
0.551 BSC
0.300 BSC
R 0.062 MAX
(4x)
A
B
C
D
E
PIN 1 INDEX
F
0.050
G
H
J
TYP
0.800
BSC
0.866
BSC
K
L
M
N
P
R
T
U
0.028 MAX
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
7
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
November 2000, Rev. 1
ECO #13417
EDI2DL32256V
FIG. 5
INTERFACING THE TEXAS INSTRUMENTS TMS320C6201
WITH THE EDI2DL32256V (256Kx32 SSRAM)
EA0-22
A0-17
(NOTE 1)
(NOTE 4)
CE2
CE1
CE0
\
\
\
CE\
ZZ
MODE
NC, Vss, Vcc
(NOTE 2)
BE
BE
BE
BE
3\
2\
1\
0
\
BE3
BE2
BE1
BE0
\
\
\
\
Texas Instruments
TMS320C6201
EDI2DL32256V
SSOE\
OE\
SSADS\
SSADV\
ADSC\
ADV\
SSWE\
CLKOUT1
CLKOUT2
GW\ (NOTE 3)
CLK
ED0-31
DQ0-31
NOTES:
1. Either CE0 or CE2 can be used to enable the device.
2. When the ZZ pin is asserted HIGH, the device will be in CMOS standby mode regardless of the state of any other pins. While in standby mode the device will
take one complete Clock cycle to become active again after a LOW is asserted on the ZZ pin. One possible option for the designer concerned about power is
to tie the ZZ signal to the chip enable they are using for the device. Any time the chip is disabled (by driving the chip enable pin HIGH) the device will go into
standby mode. Standby mode can also be achieved by tying the ZZ pin LOW or allowing it to float and meeting all the signal conditions specified in the data
sheet.
3. Use CLKOUT1 for running the memory at the same clock speed as the C6x. Use CLKOUT2 for running the SBSRAM at one half the clock rate of the C6x.
4. The MODE pin can be tied to Vss (Linear Burst), tied to Vcc (Interleaved Burst) or allowed to float (Interleaved Burst).
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
8
November 2000, Rev. 1
ECO #13417
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