EDI2CG272128V15D1 [WEDC]
2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM; 2x128Kx72 ， 3.3V同步/同步突发SRAM SO -DIMM
| 型号： | EDI2CG272128V15D1 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| 文件： | 总12页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI2CG272128V
White Electronic Designs
ADVANCED*
2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM
DESCRIPTION
FEATURES
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2x128Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
The EDI2CG272128VxxD1 is a Synchronous/Synchronous
Burst SRAM, 72 position DIMM (144 contacts) Module,
small outline. The Module contains four (4) Synchronous
Burst Ram Devices, packaged in the industry standard
JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/
Sync Burst, Flow-Through, with support for linear burst.
This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous
Only Mode, provides a high performance cost advantage
over BiCMOS aysnchronous device architectures.
Linear and Sequential Burst Support via MODE pin
Access Speed(s): TKHQV = 8.5, 9, 12, 15ns
Clock Controlled Registered Bank Enables (E1#, E2#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally Self-timed Write
Individual Bank Sleep Mode enables (ZZ1, ZZ2)
Gold Lead Finish
3.3V 1ꢀ0 Operation
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP# / ADV# High, which provides
for Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well
as an Asynchronous Output enable. This Module has
been defined for Quad Words in both Read and Write
Operations.
Common Data I/O
High Capacitance (3ꢀpf) drive, at rated Access Speed
Single Total Array Clock
Multiple Vcc and Gnd
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN SYMBOLS
PIN NAMES
Input/Output Bus
PIN FUNCTION PIN FUNCTION
PIN FUNCTION PIN
FUNCTION
DQ41
DQ46
DQ42
DQ45
DQ43
DQ44
VSS
DQꢀ-DQ63
1
VSS
VSS
37
38
39
4ꢀ
41
42
43
44
45
46
47
48
49
5ꢀ
51
52
53
54
55
56
57
58
59
6ꢀ
61
62
63
64
65
66
67
68
69
7ꢀ
71
72
DQꢀ
DQ7
DQ1
DQ6
DQ2
DQ5
DQ3
DQ4
VSS
73
74
VSS
VSS
1ꢀ9
11ꢀ
111
112
113
114
115
116
117
118
119
12ꢀ
121
122
123
124
125
126
127
128
129
13ꢀ
131
132
133
134
135
136
137
138
139
14ꢀ
141
142
143
144
DQPꢀ-DQP7 Parity Bits
2
Aꢀ-A16
E1#, E2#
CK
Address Bus
3
Aꢀ
75
ZZ2
Synchronous Bank Enables
Array Clock
4
RFU
A16
A1
76
DQP3
VCC
5
77
GW#
Synchronous Global
Write Enable
6
78
VCC
7
A2
79
DQ24
DQ31
DQ25
DQ3ꢀ
DQ26
DQ29
DQ27
DQ28
VSS
G#
Asynchronous Output
Enable
8
A15
A14
A3
8ꢀ
VSS
9
81
RFU
ZZ1, ZZ2
Vcc
Blank Sleep Mode Enables
3.3V Power Supply
Ground
1ꢀ
11
12
13
14
15
16
17
18
19
2ꢀ
21
22
23
24
25
26
27
28
29
3ꢀ
31
32
33
34
35
36
VSS
82
DQP6
VCC
A4
ZZ1
83
Vss
A13
A12
A5
DQP1
VCC
84
VCC
NC
No Connect
85
DQ48
DQ55
DQ49
DQ54
DQ5ꢀ
DQ53
DQ51
DQ52
VSS
VCC
86
A6
DQ8
DQ15
DQ9
DQ14
DQ1ꢀ
DQ13
DQ11
DQ12
VSS
87
A11
A1ꢀ
A7
88
VSS
89
RFU
DQP4
VCC
9ꢀ
A8
91
A9
92
VCC
VCC
VCC
G#
93
DQ32
DQ39
DQ33
DQ38
DQ34
DQ37
DQ35
DQ36
VSS
94
VSS
95
RFU
RFU
GW#
ADV#
ADSP#
ADSC#
MODE
CK
VSS
96
DQP7
VCC
E2
97
DQP2
VCC
98
VCC
99
DQ56
DQ63
DQ57
DQ62
DQ58
DQ61
DQ59
DQ6ꢀ
VSS
VCC
1ꢀꢀ
1ꢀ1
1ꢀ2
1ꢀ3
1ꢀ4
1ꢀ5
1ꢀ6
1ꢀ7
1ꢀ8
DQ16
DQ23
DQ17
DQ22
DQ18
DQ21
DQ19
DQ2ꢀ
VSS
VSS
RFU
DQP5
VCC
VSS
E1#
DQPꢀ
VCC
VCC
VCC
DQ4ꢀ
DQ47
VSS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
FIG. 1
FUNCTIONAL BLOCK DIAGRAM
A0-16
ADSC#
ADSP#
ADV#
CK
G#
GW#
ADSC#
ADSP#
ADV#
CK
DQ0-31
DQP0-3
DQ
G#
GW#
E1#
E#
ZZ1
ZZ
U1
ADSC#
ADSP#
ADV#
CK
DQ0-31
DQP0-3
DQ
G#
GW#
E#
E2#
ZZ
U2
ADSC#
ADSP#
ADV#
CK
DQ32-63
DQP4-7
DQ
G#
GW#
E#
ZZ2
ZZ
U3
ADSC#
ADSP#
ADV#
CK
DQ32-63
DQP4-7
DQ
G#
GW#
E#
ZZ
U4
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
PIN DESCRIPTIONS
DIMM Pins
Symbol
Aꢀ-16
Type
Description
3, 6, 1ꢀ, 11, 14, 15,
18, 19, 2ꢀ, 17, 16,
13, 12, 9, 8, 3, 5
Addresses: These inputs are registered and must meet the setup and hold times around the
rising edge of CK. The burst counter generates internal addresses associated with Aꢀ and A1,
during burst and wait cycle.
Input
Synchronous
Input
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the
BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CK.
25
GW#
CK
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control
inputs on its rising edge. All synchronous inputs must meet setup and hold times around the
clock’s rising edge.
Input
Synchronous
3ꢀ
Input
Bank Enables: These active LOW inputs are used to enable each individual bank and to
33, 61
23
E1#, E2#
G#
Synchronous gate ADSP#.
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
Synchronous
Input
Address Status Processor: This active LOW input is used to control the internal burst counter.
26
ADV#
Synchronous A HIGH on this pin generates wait cycle (no address advance)
Address Status Processor: This active LOW input, along with EL# and EH# being LOW,
Input
27
28
ADSP#
ADSC#
causes a new external address to be registered and a READ cycle is initiated using the new
Synchronous
address.
Address Status Controller: This active LOW input causes device to be de-selected or selected
Input
along with new external address to be registered. A READ or WRITE cycle is initiated depend-
Synchronous
ing upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST.
A NC or HIGH on this pin selects INTERLEAVED BURST.
29
MODE
Input Static
Input
Snooze: These active HIGH inputs put the individual banks in low power consumption standby
47, 75
ZZ1, ZZ2
Asynchronous mode. For normal operation,this input has to be either LOW or NC (no connect).
Data Inputs/Outputs: First byte is DQꢀ-7, second byte is DQ8-15, third byte is DQ16-23, fourth
Input/Output byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ4ꢀ-47, seventh byte is DQ48-55 and
the eight byte is DQ56-64.
Various
DQꢀ-63
DQPꢀ-7
Parity Inputs/Outputs: DQPꢀ is parity bit for DQꢀ-7. DQP1 is parity bit for DQ8-15. DQP2 is
parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity bit for DQ32-39. DQP5
Input/Output is parity bit for DQ4ꢀ-47. DQP6# is parity bit for DQ48-55. DQP7 is parity bit for DQ56-64 and
DQP7. In order to use the device configured as a 128K x 64, the parity bits need to be tied to
Vss through a 1ꢀK ohm resistor.
34, 48, 62, 76,
9ꢀ, 1ꢀ4, 118, 132
Various
Various
Vcc
Vss
Supply
Ground
Core power supply: +3.3V -50/+1ꢀ0
Ground
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1#
H
X
L
E2#
X
H
H
H
L
ADSP# ADSC# ADV# GW#
G#
X
X
L
CK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
Addr. Used
None
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
High-Z
High-Z
None
X
X
X
X
L
Q
External
External
External
External
External
External
External
External
External
External
Next
L
L
H
L
High-Z
H
H
L
L
Q
L
L
H
X
X
L
High-Z
H
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
X
H
X
H
H
H
H
X
X
X
X
H
X
H
X
D
H
L
L
L
D
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
X
X
X
X
L
High-Z
Next
L
D
Next
L
L
D
Next
L
L
D
Next
L
L
D
Next
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
L
High-Z
Q
H
L
High-Z
Q
H
L
High-Z
Q
H
X
X
X
X
High-Z
D
D
D
D
L
L
L
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1#
L
L
H
H
H
H
H
H
X
E2#
H
H
L
GW#
L
H
G#
H
L
ZZ
L
L
CK
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X
DQ
High-Z
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
Synchronous Write-Bank 3
Synchronous Read-Bank 3
Synchronous Write-Bank 4
Synchronous Read-Bank 4
Snooze Mode
L
H
L
High-Z
L
H
L
L
H
H
H
H
X
L
H
L
H
H
L
H
L
L
L
L
L
High-Z
High-Z
High-Z
X
X
H
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
Voltage on VCC Relative to VSS
VIN
Storage Temperature
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
-ꢀ.5V to +4.6V
-ꢀ.5V to VCC +ꢀ.5V
-55°C to +125°C
ꢀ°C to +7ꢀ°C
-4ꢀ°C to +85°C
1ꢀ mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
Supply Voltage
Input High
Input Low
Input Leakage
Output Leakage
VCC
VSS
VIH
VIL
ILI
3.14
ꢀ.ꢀ
2.ꢀ
-ꢀ.3
-2
3.3
ꢀ.ꢀ
3.ꢀ
ꢀ.ꢀ
1
3.6
ꢀ.ꢀ
VCC+ꢀ.3
ꢀ.8
2
V
V
V
V
µA
µA
ILO
-2
1
2
*Stress greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in operational sections of this specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
Symbol
Typ
8.5
9
12
15
Units
Power Supply Current
Icc1
1.55
2.2
2.1
2.1
2.ꢀ
A
Power Supply Current Device
Selected, No Operation
Snooze Mode
CMOS Standby
Clock Running-Deselect
Icc
75ꢀ
1.5
1.5
1.ꢀ
1.ꢀ
A
Icczz
Icc3
IccK
15ꢀ
4ꢀꢀ
6ꢀꢀ
2ꢀꢀ
6ꢀꢀ
1.ꢀ
2ꢀꢀ
6ꢀꢀ
1.ꢀ
2ꢀꢀ
6ꢀꢀ
ꢀ.75
2ꢀꢀ
6ꢀꢀ
ꢀ.75
mA
mA
mA
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
I/0
Unit
I/O
Z0=50Ω
Input Pulse Levels
VSS to 3.ꢀ
V
Input and Output Timing Ref.
Output Test equivalencies
1.25
V
50Ω
See figure
at left
Vt = 1.25V
FIG. 2 AC Output Load Equivalent
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
BURST ADDRESS TABLE (MODE=NC/VCC
)
BURST ADDRESS TABLE (MODE=VSS
)
First
Second
Address
(internal)
A-Aꢀ1
A-Aꢀꢀ
A-A11
A-A1ꢀ
Third
Fourth
First
Second
Address
(internal)
A-Aꢀ1
A-A1ꢀ
A-A11
A-Aꢀꢀ
Third
Fourth
Address
Address
Address
Address
Address
(external)
A-Aꢀꢀ
Address
(external)
A-Aꢀꢀ
(internal)
A-A1ꢀ
A-A11
A-Aꢀꢀ
A-Aꢀ1
(internal)
A-A11
A-A1ꢀ
A-Aꢀ1
A-Aꢀꢀ
(internal)
A-A1ꢀ
A-A11
A-Aꢀꢀ
A-Aꢀ1
(internal)
A-A11
A-Aꢀꢀ
A-Aꢀ1
A-A1ꢀ
A-Aꢀ1
A-A1ꢀ
A-A11
A-Aꢀ1
A-A1ꢀ
A-A11
READ CYCLE TIMING PARAMETERS
8.5ns
9ns
12ns
15ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Sym
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
Min
Max
Min
1ꢀ
4
Max
Min
12
5
Max
Min
15
5
Max
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
4
5
5
9
1ꢀ
12
3
2
3
2
3
2
4
4
4
4
5
5
ꢀ
ꢀ
ꢀ
2.5
2.5
1.ꢀ
1.ꢀ
2.5
2.5
1.ꢀ
1.ꢀ
2.5
2.5
1.ꢀ
1.ꢀ
Bank Enable Setup
Address Hold
Bank Enable Hold
*TBD
SYNCHRONOUS ONLY READ CYCLE
FIG. 3
t
KHKH
t
KLKH
t
KHKL
CK
t
AVKH
EX#
Addr 1
Addr 1
Addr 2
ADDR
t
KHAX
t
KHQV
G#
GW#
DQ
t
GLQV
t
GLQX
t
KHQX
Q(Addr 1)
Q(Addr 1)
Q(Addr 2)
t
KHQZ
t
KHQX1
Read Cycle
Back to Back Read
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
FIG. 4
SYNCHRONOUS-BURST READ CYCLE
tKHKH
t
KHKL KLKH
t
CK
t
SPVKH
tKHSPX
ADSP#
t
SCVKH
tKHSCX
ADSC#
ADDR
t
AVKtHKHAX
BWx#,
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
tGHQX
tKHQV
t
GLQV
tGHQZ
t
GLQX
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
WRITE CYCLE TIMING PARAMETERS
8.5ns
Min Max
9ns
12ns
Max
15ns
Min Max
Units
ns
Description
Clock Cycle Time
Sym
tKHKH
Min
9
Max
Min
12
15
Clock High Time
Clock Low Time
Address Setup
tKHKL
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
4
4
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
ns
ns
Data Hold
SYNCHRONOUS (NON-BURST) WRITE CYCLE
FIG. 5
t
KHKH
t
AVKH
t
KHKL
tKLKH
t
KHAX
CK
Ex#
ADDR
GW#
Addr 1
Addr 1
Addr 2
tKHGWH
t
GWLKH
G#
t
KHGH
DQ
t
KHDX
t
DVKH
t
GHKH
Write Cycle
Back to Back Writes
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
FIG. 6 SYNCHRONOUS-BURST WRITE CYCLE
tKHKH
tKHKL
tKLKH
CK
ADSP#
ADSC#
ADDR
t
AVKH
tKHAX
BWx#,
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
t
DVKH
tKHQX
DQ
tKHQX
Early Write Cycle
Burst - Late Write- Cycle
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
FIG. 7
SYNCHRONOUS (NON-BURST) READ/WRITE CYCLE
t
KHKH
t
KHKL
tKLKH
CK
tAVKH
Ex#
Addr 1
Addr 2
ADDR
tKHQV
tKHDX
G#
GW#
t
KHQX
DQ
Q (Addr 1)
D (Addr 2)
t
KHDX
t
DVKH
Read Cycle
Back to Back Cycles
G# Controlled
Write Cycle
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2CG272128V
White Electronic Designs
ADVANCED
PACKAGE DESCRIPTION: 144 Lead SMALL OUTLINE DIMM
Package No. 409
2.667 MAX.
0.175
MAX.
0.157
R18
1.000
MAX.
U1
U3
0.788
R17
P1
0.181 TYP
0.913
1.112
1.291
1.490
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
Part Number
Organization
Voltage
3.3
Speed (ns)
Package
EDI2CG272128V85D1*
EDI2CG272128V9D1*
EDI2CG272128V12D1
EDI2CG272128V15D1
*Consult Factory for Availability
2x128Kx72
2x128Kx72
2x128Kx72
2x128Kx72
8.5
9
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
3.3
3.3
12
15
3.3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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