SI9122A [VISHAY]
500-kHz Half-Bridge DC/DC Controller With Integrated Secondary Synchronous Rectification Drivers; 集成二级同步整流驱动器的500 kHz的半桥DC / DC控制器
| 型号： | SI9122A |
| 厂家： | 
VISHAY |
| 描述： | 500-kHz Half-Bridge DC/DC Controller With Integrated Secondary Synchronous Rectification Drivers |
| 文件： | 总15页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9122A
Vishay Siliconix
500-kHz Half-Bridge DC/DC Controller
With Integrated Secondary Synchronous Rectification Drivers
FEATURES
28-V to 75-V Input Voltage Range
Compatible with ETSI 300 132-2
Integrated ꢀ1–A Half Bridge Primary Drivers
Secondary Synchronous Rectifier Control Signals With
Programmable Deadtime Delay
Frequency Foldback Eliminates Constant Current Tail
Advanced Maximum Current Control During Start-Up and
Shorted Load
Low Input Voltage Detection
Programmable Soft-Start Function
Over Temperature Protection
Voltage Mode Control
Voltage Feedforward Compensation
High Voltage Pre-Regulator Operates During Start-Up
Current Sensing On Low-Side Primary Device
APPLICATIONS
Network Cards
Power Supply Modules
DESCRIPTION
Si9122A is a half-bridge controller IC ideally suited to fixed
telecom applications where high efficiency is required at low
output voltages (e.g. <3.3 V). Designed to operate within the
fixed telecom voltage range of 33–75 V and withstand 100 V,
100 ms transients, the IC is capable of controlling and driving
both the low and high-side switching devices of a half bridge
circuit and also controlling the switching devices on the
secondary side of the bridge. Due to the very low on-resistance
of the secondary MOSFETs, a significant increase in
conversion efficiency can be achieved as compared with
conventional Schottky diodes. Control of the secondary
devices is by means of a pulse transformer and a pair of
inverters. Such a system has efficiencies well in excess of 90%
even for low output voltages. On-chip control of the dead time
delays between the primary and secondary synchronous
signals keep efficiencies high and prevent accidental
destruction of the power transformer. An external resistor sets
the switching frequency from 200 kHz to 625 kHz.
Si9122A has advanced current monitoring and control circuitry
which allow the user to set the maximum current in the primary
circuit. Such a feature acts as protection against output
shorting and also provides constant current into large
capacitive loads during start-up or when paralleling power
supplies. Current sensing is by means of a sense resistor on
the low-side primary device.
FUNCTIONAL BLOCK DIAGRAM
28 V to 75 V
BST
Synchronous
Rectifiers
DH
LX
1 V to 12 V Typ.
+
V
Si9122A
OUT
DL
–
CS2
V
IN_DET
CS1
SR
H
C
Error
L_CONT
Amplifier
V
CC
SR
L
+
–
V
REF
EP
Opto Isolator
Figure 1.
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
1
Si9122A
Vishay Siliconix
TECHNICAL DESCRIPTION
Si9122A is a voltage mode controller for the half-bridge
topology. With 100-V depletion mode MOSFET capability, the
Si9122A is capable of powering directly from the high voltage
bus to VCC through an external PNP pass transistor, or may be
powered through an external regulator directly through the
VCC pin. With PWM control, Si9122A provides peak efficiency
throughout the entire line and load range. In order to simplify
the design of efficient secondary synchronous rectification
circuitry, Si9122A provides intelligent gate drive signals to
control the secondary MOSFETs. With independent gate drive
signals from the controller, transformer design is no longer
limited by the gate to source rating of the secondary–side
MOSFETs. Si9122A provides constant VGS voltage,
independent of line voltage to minimize the gate charge loss
as well as conduction loss. A break-before-make function is
included to prevent shoot through current or transformer
shorting. Adjustable Break-Before-Make time is incorporated
into the IC and is programmable by an external resistor value.
Si9122A is packaged in lead (Pb)–free TSSOP-20 and
MLP65-20 packages. To satisfy stringent ambient tempe–
rature requirements, Si9122A is rated to handle the industrial
temperature range of –40 to 85 C. When a situation arises
which results in a rapid increase in primary (or secondary
current) such as output shorted or start-up with a large output
capacitor, control of the PWM generator is handed over to the
the current loop. Monitoring of the load current is by means of
an external current sense resistor in the source of the primary
low-side switch.
SI9122 BLOCK DIAGRAM
V
IN
V
CC
R
OSC
High-Side
Primary
Driver
BST
9.1 V
V
UVLO
REG_COMP
Pre-Regulator
+
–
Int
D
H
V
REF
8.8 V
L
X
Low-Side
Driver
V
CC
V
INDET
V
FF
V
D
UV
+
–
L
OSC
V
REF
EP
SS
Ramp
V
SD
+
–
PGND
132 k
550 mV
60 k
V
CC
–
+
Driver
Control
and
+
–
Error Amplifier
SR
H
V
PWM
Comparator
REF
Timing
2
20
A
SYNC
Driver High
I
SS
OTP
8 V
V
CC
SR
L
CS2
CS1
Duty Cycle
Control
+
–
Peak DET
SYNC
Driver Low
Si9122
Over Current Protection
GND
C
BBM
L_CONT
Figure 2.
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
2
Si9122A
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
V
V
V
V
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 V
(100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150 C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 C
IN
IN
a
Power Dissipation
CC
b
TSSOP-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 mW
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 V
(100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 V
BST
c
MLP65-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500 mW
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Thermal Impedance (
TSSOP-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 C/W
MLP65-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 C/W
)
LX
JA
– V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
BST
LX
, R
REF OSC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
CC
Notes
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
CC
a. Device mounted on JEDEC compliant 1S2P test board..
b. Derate –14 mW/ C above 25 C.
c. Derate –26 mW/ C above 25 C.
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
CC
HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 to 75 V
Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 to 13.2 V
R
C
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 to 50 k
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1
IN
BBM
F
F
REF
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1
BOOST
CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁ 4.7 F
CC
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V – 2 V
CC
f
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 625 kHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.6 to 72 k
OSC
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
CC
R
Reference Voltage Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 mA
OSC
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
–40 to 85 C
f
= 500 kHz, V = 75 V
IN
NOM
Parameter
Symbol
Minb
Typc
Maxb
Unit
V
= 7.5 V; 10.5 V ꢂ V ꢂ 13.2 V
CC
INDET
Reference (3.3 V)
Output Voltage
V
V
CC
= 12 V, 25 C Load = 0 mA
3.2
3.3
3.4
–50
–75
V
REF
Short Circuit Current
Load Regulation
I
V
REF
= 0 V
mA
mV
dB
SREF
dVr/dlr
PSRR
I
= 0 to –2.5 mA
@ 100Hz
–30
60
REF
Power Supply Rejection
Oscillator
Accuracy (1% R
)
R
= 30 k , f = 500 kHz
NOM
–20
500
20
%
OSC
OSC
h
Max Frequency
F
R
OSC
= 22.6 k
625
100
750
MAX
kHz
d
Foldback Frequency
F
f
= 500 kHz, V
– V
ꢃ
1
5
0
m
V
FOBK
NOM
CS2
CS1
Error Amplifier
Input Bias Current
Gain
I
V
= 0 V
–40
–15
A
V/V
MHz
dB
BIAS
EP
A
V
–2.2
5
Bandwidth
BW
Power Supply Rejection
Slew Rate
PSRR
SR
@ 100Hz
60
0.5
V/ s
Current Sense Amplifier
Input Voltage CM Range
Input Amplifier Gain
V
V
CS1
– GND, V – GND
CS2
ꢀ150
17.5
5
mV
dB
CM
A
VOL
Input Amplifier Bandwidth
BW
MHz
Input amplifier Offset Voltage
V
OS
ꢀ
5
mV
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
3
Si9122A
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
–40 to 85 C
f
= 500 kHz, V = 75 V
IN
NOM
Parameter
Symbol
Minb
Typc
Maxb
Unit
V
= 7.5 V; 10.5 V ꢂ V ꢂ 13.2 V
CC
INDET
Current Sense Amplifier
dV = 0
CS
120
0
A
dV = 100 mV
CS
CL_CONT Current
I
CL_CONT
dV = 170 mV
CS
ꢃ2
mA
I
= I – I
= 0
PD
PU
CL_CONT
Lower Current Limit Threshold
V
TLCL
100
See Figure 6
mV
V
Upper Current Limit Threshold
Hysteresis
V
I
ꢃ
2
m
A
150
–50
THCL
PD
I
ꢄ
5
0
0
A
PU
CL_CONT Clamp Level
C
I
= 500
A
0.6
90
1.5
95
L_CONT(min)
PU
PWM Operation
D
V
= 0 V
92
ꢄ15
3
MAX
EP
f
= 500 kHz
OSC
e
V
= 1.75 V
Duty Cycle
%
V
EP
D
MIN
V
– V
ꢃ
1
5
0
m
V
CS2
CS1
Pre-Regulator
Input Voltage
+V
I
= 10
A
28
75
10
IN
IN
Input Leakage Current
I
V
= 75 V, V ꢃ V
IN CC REG
LKG
A
I
I
V
= 75 V, V
ꢄ V
SD
86
8
200
14
REG1
REG2
IN
INDET
Regulator Bias Current
V
= 75 V, V
ꢃ
V
mA
IN
INDET
REF
I
–29
50
–19
82
–9
SOURCE
Regulator_Comp
V
CC
= 12 V
A
I
110
SINK
Pre-Regulator Drive Capacility
I
V
CC
ꢄ V
REG
20
mA
START
7.4
8.5
9.1
9.1
9.2
8.8
8.8
0.5
10.4
9.7
V
ꢃ V
REF
V
V
INDET
REG1
V
Pre-Regulator Turn Off
CC
T
= 25 C
= 25 C
A
Threshold Voltage
V
= 0 V
REG2
INDET
V
7.15
8.1
9.8
9.3
Undervoltage Lockout
g
V
UVLO
V
CC
Rising
T
A
V
UVLO
Hysteresis
V
UVLOHYS
Soft-Start
Soft-Start Current Output
I
Start-Up Condition
Normal Operation
12
20
28
A
V
SS
Soft-Start Completion Voltage
V
7.35
8.05
8.85
SS_COMP
Shutdown
V
Shutdown
V
V
Rising
INDET
350
550
200
720
INDET
SD
mV
V
V
SD
Hysteresis
V
INDET
VINDET Input Threshold Voltages
V
INDET
– V Under Voltage
V
UV
V
INDET
Rising
3.13
3.3
0.3
3.46
IN
V
UW
Hysteresis
V
INDET
Over Temperature Protection
Activating Temperature
T Increasing
160
130
J
C
De-Activating Temperature
T Decreasing
J
Converter Supply Current (VCC
)
Shutdown
I
I
I
Shutdown, V
= 0 V
50
4
350
12
A
CC1
CC2
CC3
INDET
Switching Disabled
Switching w/o Load
V
INDET
ꢄ
V
8
REF
V
ꢃ V , f = 500 kHz
REF NOM
5
10
15
INDET
mA
V
= 12 V, C = C = 3 nF
DH DL
CC
C
Switching with C
I
21
LOAD
CC4
= C
= 0.3 nF
SRH
SRL
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
4
Si9122A
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
–40 to 85 C
f
= 500 kHz, V = 75 V
IN
NOM
Parameter
Symbol
Minb
Typc
Maxb
Unit
V
= 7.5 V; 10.5 V ꢂ V ꢂ 13.2 V
INDET
CC
Output MOSFET DH Driver (High-Side)
Output High Voltage
Output Low Voltage
Boost Current
V
Sourcing 10 mA
Sinking 10 mA
V
BST
– 0.3
OH
V
mA
A
V
V
LX
+ 0.3
OL
I
V
V
= 75 V, V
= 75 V, V
= V + V
1.3
1.9
–0.7
–1.0
1.0
35
2.7
BST
LX
BST
BST
LX
CC
L
X
Current
I
= V + V
–1.1
–0.4
LX
SOURCE
LX
LX
CC
Peak Output Source
Peak Output Sink
Rise Time
I
–0.75
V
CC
= 10.5 V
I
0.75
SINK
t
r
C
DH
= 3 nF
ns
Fall Time
t
f
35
Output MOSFET DLDriver (Low-Side)
Output High Voltage
Output Low Voltage
Peak Output Source
Peak Output Sink
Rise Time
V
Sourcing 10 mA
Sinking 10 mA
V
CC
– 0.3
OH
V
A
V
0.3
OL
SOURCE
I
–1.0
1.0
35
–0.75
V
CC
= 10.5 V
I
0.75
SINK
t
r
C
DL
= 3 nF
ns
Fall Time
t
f
35
Synchronous Rectifier (SRH, SRL) Drivers
Output High Voltage
Output Low Voltage
V
Sourcing 10 mA
Sinking 10 mA
V
CC
– 0.4
OH
V
V
0.4
OL
t
t
t
t
55
40
BBM1
BBM2
BBM3
BBM4
T
A
= 25 C, R
= 33 k , See Figure 3
BBM
f
Break-Before-Make Time
ns
35
T
= 25 C,R
= 33 k , L = 75 V
BBM X
A
55
Peak Output Source
Peak Output Sink
Rise Time
I
–100
100
35
SOURCE
V
= 10.5 V
mA
ns
CC
I
SINK
t
r
C
= C
= 0.3 nF
SRH
SRL
Fall Time
t
f
35
Voltage Mode
Error Amplifier
Current Mode
Current Amplifier
Notes
Input to high-side switch off
Input to low-side switch off
ꢄ200
ꢄ200
t
d1DH
ns
ns
t
d2DL
Input to high-side switch off
Input to low-side switch off
ꢄ200
ꢄ200
t
d3DH
t
d4DL
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (–40 to 85 C).
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d.
F
when V
at clamp level. Typical foldback frequency change +20%, –30% over temperature.
MIN
CL_CONT
e. Measured on SRL or SRH outputs.
f.
g.
See Figure 3 for Break-Before-Make time definition.
tracks V by a diode drop
V
UVLO
REG1
h. Guaranteed by design and characterization, not tested in production.
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
5
Si9122A
Vishay Siliconix
TIMING DIAGRAM FOR MOS DRIVERS
V
CC
PWM
PWM
PWM
PWM
GND
V
CC
D
L
D
L
GND
V
CC
SR
L
SR
L
GND
V
BST
D
H
D
H
V
MID
D
H
D
H
GND
V
CC
SR
H
SR
H
GND
Time
D
H
t
t
t
t
BBM4
BST = L + V
BBM1
BBM2
BBM3
X
CC
50%
V L
X
L
X
D , L
H
X
D , L
V
V
H
X
MID
SR
H
CC
50%
D , L
H
X
GND
t
t
BBM4
BBM3
D
L
SR
L
SR
L
V
CC
GND
Specification Table
Return to:
Rectification Timing Sequence
t
t
BBM2
BBM1
Primary MOSFET Drivers
Secondary MOSFET Drivers
Figure 3.
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
6
Si9122A
Vishay Siliconix
PIN CONFIGURATION
Si9122ADQ (TSSOP-20)
Si9122ADLP (MLP65-20)
V
BST
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IN
1
2
3
4
5
20
19
18
17
16
REG_COMP
D
H
V
BST
IN
V
CC
L
X
REG_COMP
D
H
V
D
L
V
CC
L
X
REF
GND
PGND
V
D
L
REF
6
7
15
14
13
12
11
R
SR
H
GND
PGND
OSC
EP
SR
L
R
OSC
SR
H
8
V
SS
EP
SR
L
INDET
9
V
SS
CS1
CS2
BBM
INDET
10
CS1
CS2
BBM
C
L_CONT
C
L_CONT
Top View
Top View
ORDERING INFORMATION
Part Number
Temperature Range
Package
Si9122ADQ–T1–E3
TSSOP-20
MLP65-20
–40 to 85 C
Si9122ADLP–T1–E3
Eval Board
Temperature Range
Board Type
Surface Mount and
Thru-Hole
Contact Factory
–10 to 70 C
PIN DESCRIPTION
Pin Number
Name
Function
1
2
3
4
5
6
7
V
Input supply voltage for the start-up circuit.
Control signal for an external pass transistor.
Supply voltage for internal circuitry
3.3-V reference
IN
REG_COMP
V
CC
V
REF
GND
Ground
R
OSC
External resistor connection to oscillator
Voltage control input
EP
V
under voltage detect and shutdown function input. Shuts down or disables switching when V
falls below
IN
INDET
8
V
INDET
preset threshold voltages and provides the feed forward voltage.
9
CS1
CS2
Current limit amplifier negative input
10
11
12
13
14
15
16
17
18
19
20
Current limit amplifier positive input
C
Current limit compensation
L_CONT
BBM
Programmable Break-Before-Make time connection to an external resistor to set time delay
Soft-Start control – external capacitor connection
Signal transformer drive, sequenced with the primary side.
Signal transformer drive, sequenced with the primary side.
Power ground.
SS
SR
L
SR
H
PGND
D
L
Low-side gate drive signal – primary
L
X
High-side source and transformer connection node
High-side gate drive signal – primary
D
H
BST
Bootstrap voltage to drive the high-side n-channel MOSFET switch
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
7
Si9122A
Vishay Siliconix
V
CC
V
IN
Pre-Regulator
+
–
V
REG
9.1 V
Bandgap
Reference
3.3 V
9.1 V
V
REF
V
UVLO
+
–
+
–
V
V
UV
High-Side
Primary
Driver
V
INDET
V
REF
8.6 V
C
L_CONT
SD
BST
+
–
Voltage
Feedforward
Frequency
Foldback
160 C Temp
Protection
High Voltage
Interface
D
H
550 mV
L
X
V
SD
V
V
UV UVLO
R
OSC
OSC
OTP
Oscillator
Clock
V
CC
Clock
Logic
Low-Side
Driver
132 k
D
L
60 k
EP
–
+
–
+
Logic
Timer
V
/2
REF
PGND
PWM
Generator
Current
Control
Gain
V
V
CC
Synchronous
Driver
CS2
CS1
Loop
Control
+
–
(High)
SR
H
100 mV
Blanking
CC
Synchronous
Driver
C
L_CONT
GND
(Low)
V
CC
SR
L
BBM
Si9122A
20
A
8 V
Soft-Start
SS
SS Enable
Figure 4.
Detailed Si9122A Block Diagram
DETAILED OPERATION
Start-Up
of the VCC capacitor, bootstrap capacitor and the soft-start
capacitor. The value of the VCC capacitor should therefore be
chosen to be capable of maintaining switch mode operation
until the required VCC current can be supplied from the external
circuit (e.g via a power transformer winding and zener
regulator). Feedback from the output of the switch mode
supply charges VCC above VREG and fully disconnects the
pre-regulator, isolating VCC from VIN. VCC is then maintained
above VREG for the duration of switch mode operation. In the
event of an over voltage condition on VCC, an internal voltage
clamp turns on at 14.5 V to shunt excessive current to GND.
When VINEXT rises above 0 V, the internal pre-regulator begins
to charge up the Vcc capacitor. Current into the external VCC
capacitor is limited to typically 40 mA by the internal DMOS
device. When Vcc exceeds the UVLO voltage of 8.8 V a
soft-start cycle of the switch mode supply is initiated. The VCC
supply continues to be charged by the pre-regulator until VCC
equals VREG. During this period, between VUVLO and VREG
,
excessive load current will result in VCC falling below VUVLO
and stopping switch mode operation. This situation is avoided
by the hysteresis between VREG and VUVLO and correct sizing
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
8
Si9122A
Vishay Siliconix
Care needs to be taken if there is a delay prior to the external
circuit feeding back to the VCC supply. To prevent excessive
power dissipation within the IC it is advisable to use an external
PNP device. A pin has been incorporated on the IC,
(REG_COMP) to provide compensation when employing the
external device. In this case the VIN pin is connected to the
base of the PNP device and controls the current, while the
REG_COMP pin determines the frequency compensation of
the circuit. To understand the operation please refer to
Figure 5.
Half-Bridge and Synchronous Rectification Timing
Sequence
The PWM signal generated within the Si9122A controls the
low and high-side bridge drivers on alternative cycles. A period
of inactivity always results after initiation of the soft-start cycle
until the soft-start voltage reaches approximately 1.2 V and
PWM controlled switching begins. The first bridge driver to
switch is always the low-side (DL), as this allows charging of
the high-side boost capacitor.
The timing and coordination of the drives to the primary and
secondary stages is very important and shown in Figure 3. It
is essential to avoid the situation where both of the secondary
MOSFETs are on when either the high or the low-side switch
are active. In this situation the transformer would effectively be
presented with a short across the output. To avoid this, a
dedicated break-before-make circuit is included which will
generate non overlapping waveforms for the primary and the
secondary drive signals. This is achieved by a programmable
timer which delays the switching on of the primary driver
relative to the switching off of the related secondary and
subsequently delays the switching on of the secondary relative
to the switching off of the related primary.
The soft-start circuit is designed for the dc-dc converter to
start-up in an orderly manner and reduce component stress on
the IC. This feature is programmable by selecting an external
CSS. An internal 20- A current source charges CSS from 0 V
to the final clamped voltage of 8 V. In the event of UVLO or
shutdown, VSS will be held low (<1 V) disabling driver
switching. To prevent oscillations, a longer soft-start time may
be needed for highly capacitive loads and/or high peak output
current applications.
Reference
Typical variations of BBM times with respect to RBBM and other
operating parameters are shown on page 13 and 14.
The reference voltage of Si9122A is set at 3.3 V. The reference
voltage should be de-coupled externally with 0.1- F capacitor.
The VREF voltage is 0 V in shutdown mode and has 50-mA
source capability.
Primary High- and Low-Side MOSFET Drivers
The drive voltage for the low-side MOSFET switch is provided
directly from VCC. The high-side MOSFET however requires
the gate voltage to be enhanced above VIN. This is achieved
by bootstrapping the VCC voltage onto the LX voltage (the
high-side MOSFET source). In order to provide the
bootstrapping an external diode and capacitor are required as
shown on the application schematic. The capacitor will charge
up after the low-side driver has turned on. The switch gate
drive signals DH and DL are shown in Figure 3.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage mode
and generates a fixed frequency pulse width modulated signal
to the drivers. Duty cycle is controlled over a wide range to
maintain output voltage under line and load variation. Voltage
feed forward is also included to take account of variations in
supply voltage VIN.
Secondary MOSFET Drivers
In the half-bridge topology requiring isolation between output
and input, the reference voltage and error amplifier must be
supplied externally, usually on the secondary side. The error
information is thus passed to the power controller through an
opto-coupling device. This information is inverted, hence 0 V
represents the maximum duty cycle, whilst 2 V represents
minimum duty cycle. The error information enters the IC via pin
EP, and is passed to the PWM generator via an inverting
amplifier. The relationship between Duty cycle and VEP is
shown in the Typical Characteristic Graph,Duty Cycle vs. VEP
25 C , page 11. Voltage feedforward is implemented by taking
the attenuated VIN signal at VINDET and directly modulating the
duty cycle.
The secondary side MOSFETs are driven from the Si9122A
via a center tapped pulse transformer and inverter drivers. The
waveforms from SRH and SRL are shown in Figure 3. Of
importance is the relative voltage between SRH and SRL, i.e.
that which is presented across the primary of the pulse
transformer. When both potentials of SRL and SRH are equal
then by the action of the inverting drivers both secondary
MOSFETs are turned on.
Oscillator
The oscillator is designed to operate at a nominal frequency of
500 kHz. The 500-kHz operating frequency allows the converter
to minimize the inductor and capacitor size, improving the power
density of the converter. The oscillator and therefore the
switching frequency is programmable by attaching a resistor to
the ROSC pin. Under overload conditions the oscillator frequency
is reduced by the current overload protection to enable a constant
current to be maintained into a low impedance circuit.
At start-up, i.e., once VCC is greater than VUVLO, switching is
initiated under soft-start control which increases primary
switch on-times linearly from DMIN to DMAX over the soft-start
period. Start-up from a VINDET power down is also initiated
under soft-start control.
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
9
Si9122A
Vishay Siliconix
Current Limit
voltage of VREF (3.3 V, 300-mV hysteresis), is achieved. This
is achieved by choosing an appropriate resistive tap between
the ground and VIN, and comparing this voltage with the
reference voltage. When the applied voltage is greater than
VREF, the output drivers are activated as normal. VINDET also
provides the input to the voltage feed forward function.
Current mode control providing constant current operation is
achieved by monitoring the differential voltage between the
CS1and CS2 pins which are connected across a primary
low-side sense resistor. Once this differential voltage exceeds
the 100-mV trigger point, the voltage on the CL_CONT pin is
pulled lower at a rate proportional to the excess voltage and the
value of the external capacitor connected between the
CL_CONT pin and ground. If the voltage between CS1 and CS2
exceeds 150 mV the CL_CONT capacitor is discharged rapidly
resulting in minimum duty cycle and frequency immediately.
However, if the divided voltage applied to the VINDET pin is
greater than VCC –0.3 V, the high-side driver, DH, will stop
switching until the voltage drops below VCC –0.3 V. Thus, the
resistive tap on the VIN divider must be set to accommodate
the normal VCC operating voltage to avoid this condition.
Alternatively, a zener clamp diode from VINDET to GND may
also be used.
Lowering the CL_CONT voltage results in PWM control of the
output drive being taken over by the current limit control loop.
Current control works to initially reduce the switching duty
cycle down to DMIN (12.5%). Further reduction in the duty
cycle is accompanied by a reduction in switching frequency at
a rate proportional to the duty cycle. This prevents the on time
of the primary drivers from falling below 100 ns, thereby
avoiding “current tailing”. Frequency reduction will then occur
until the operating frequency reaches 20% of the nominal
frequency, yielding a duty cycle as low as 2.5% during output
overloads.
Shutdown Mode
If VINDET is forced below the lower VSD threshold, the device
will enter SHUTDOWN mode. This powers down all
unnecessary functions of the controller, ensures that the
primary switches are off, and results in a low level current
demand from the VIN or VCC supplies.
V
INEXT
With constant current mode control of on time and with
reduced operating frequency, protection of the MOSFET
switches is increased during fault conditions. Minimum duty
cycle and reduced frequency switching continues for the
duration of the fault condition. The converter reverts to voltage
mode operation immediately whenever the primary current
fails to reach the limit level. CL_CONT clamps to 6.5 V when not
in current limit.
R
EXT
V
IN
PNP Ext
(Si9122A)
Auxillary
CC
HV
DMOS
V
V
CC
REG_COMP
C
VCC
The soft-start function does not apply under current limit as this
would constitute hiccup mode operation.
C
EXT
2 nF
0.5
F
14.5 V
V
REF
GND
VIN Voltage Monitor –VINDET
Figure 5. High-Voltage Pre-Regulator Circuit
The chip provides a means of sensing the voltage of VIN, and
withholding operation of the output drivers until a minimum
V
CC
OSC
AV
I
PU
120 A (nom)
+
–
GM
Peak Detect
V
C
L_CLAMP
OFFSET
C
R
L_CONT
CS1
CS2
–
+
AV
A
V
ꢅ150 mV
EXT
Blank
+
–
C
EXT
GM
I
PD
0 – 240 A (nom)
A
V
ꢅ
1
0
0
m
V
Figure 6 . Current Limit Circuit
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
10
Si9122A
Vishay Siliconix
TYPICAL CHARACTERISTICS
F
OSC
vs. R
@ V = 12 V
V vs. Temperature, V = 12 V
REF CC
OSC
CC
600
500
400
300
200
3.300
3.295
3.290
3.285
3.280
3.275
3.270
20
30
40
50
(k
60
70
80
–50
–25
0
25
50
75
100
R
)
Temperature ( C)
OSC
V
vs. Temperature, V = 48 V
IN
SRL, SRH Duty Cycle vs. V
REG
EP
10.0
9.5
9.0
8.5
8.0
7.5
100
90
80
70
60
50
40
30
20
10
0
3.6 V = V
INDET
4.8 V
7.2 V
V
INDET
ꢃ V
REF
TC = –11 mV/C
V
CC
= 12 V
–50 –25
0
25
50
75
100 125 150
0.0
0.5
1.0
1.5
2.0
Temperature ( C)
V
EP
(V)
I
SS
vs. Temperature
V
SS
vs. Temperature, V = 12 V
CC
25
23
21
19
17
15
8.20
8.15
8.10
8.05
8.00
7.95
7.90
V
CC
= 13 V
TC = +1.25 mV/C
V
CC
= 12 V
V
INDET
ꢃ V
REF
V
CC
= 10 V
–50
–25
0
25
50
75
100
125
–50 –25
0
25
50
75
100 125 150
Temperature ( C)
Temperature ( C)
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
11
Si9122A
Vishay Siliconix
TYPICAL CHARACTERISTICS
I
vs. Temperature
REG2
I
vs. Temperature
CC3
11
10
9
13
12
11
10
9
8
7
6
8
5
7
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
800
800
Temperature ( C)
Temperature ( C)
D , D I
H
vs. V
OL
D , D I
vs. V
OH
L
SINK
H
L
SOURCE
250
200
150
100
50
250
200
150
100
50
V
= 12 V
V
CC
= 12 V
CC
0
0
0
200
400
600
0
200
400
600
800
V
(mV)
V
(mV)
OL
OH
SRL, SRH I
vs. V
OH
SRL, SRH I
vs. V
OL
SOURCE
SINK
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V
CC
= 12 V
V
CC
= 12 V
0
0
0
200
400
600
800
0
200
400
(mV)
600
V
(mV)
V
OH
OL
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
12
Si9122A
Vishay Siliconix
TYPICAL CHARACTERISTICS
t
vs. R , V = 0 V
BBM EP
t
vs. R , V = 1.65 V
BBM EP
BBM
BBM
100
90
80
70
60
50
40
30
20
65
55
45
35
25
15
t
t
BBM4
V
CC
= 12 V
V
CC
= 12 V
t
t
BBM1
BBM1
BBM4
t
t
BBM2
BBM3
t
t
BBM3
BBM2
25
30
35
(k
40
45
25
30
35
40
45
R
)
R
(k )
BBM
BBM
t
vs. Temperature, V = 0 V
t
vs. Temperature, V = 1.65 V
BBM1, 2
EP
BBM1, 2
EP
80
70
60
50
40
30
60
55
50
45
40
35
30
t
V
= 13 V
t
V
= 1.65 V
= 33 k
BBM1, CC
t
V
= 10 V
EP
BBM1, CC
V
= 12 V
R
BBM
BBM1, CC
t
V
= 10 V
BBM1, CC
VEP = 0 V
= 33 k
t
V
= 13 V
= 12 V
BBM1, CC
R
BBM
t
V
= 12 V
BBM1, CC
t
V
= 10 V
BBM2, CC
t
V
= 10 V
= 13 V
BBM2, CC
t
V
= 12 V
BBM2, CC
t
V
BBM2, CC
t
V
= 13 V
BBM2, CC
t
V
BBM2, CC
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
Temperature ( C)
Temperature ( C)
t
vs. Temperature, V = 0 V
t vs. Temperature, V = 1.65 V
BBM3, 4 EP
BBM3, 4
EP
80
70
t
V
= 10 V
V
= 0 V
BBM
V
= 1.65 V
BBM
BBM4, CC
EP
R
EP
R
t
V
= 13 V
BBM4, CC
= 33 k
= 33 k
65
60
55
50
45
40
35
30
70
60
50
40
30
20
t
V
= 12 V
t
V
= 12 V
BBM4, CC
BBM4, CC
t
t
V
= 10 V
= 12 V
BBM4, CC
t
V
= 13 V
BBM4, CC
t
V
= 13 V
BBM3, CC
V
BBM3, CC
t
V
= 12 V
BBM3, CC
t
V
= 10 V
BBM3, CC
t
V
= 13 V
BBM3, CC
t
V
= 10 V
25
BBM3, CC
–50
–25
0
50
75
100
125
–50
–25
0
25
50
75
100
125
Temperature ( C)
Temperature ( C)
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
13
Si9122A
Vishay Siliconix
TYPICAL CHARACTERISTICS
t
vs. V vs. V
t vs. V vs. V
BBM1, 2 CC INDET
BBM1, 2
CC
INDET
80
70
60
50
40
30
55
50
45
40
35
t
V
= 13 V
= 10 V
BBM1, CC
t
t
V
= 13 V
BBM1, CC
t
V
= 12 V
t
V
BBM1, CC
BBM1, CC
V
= 12 V
= 10 V
BBM1, CC
t
V
BBM1, CC
V
EP
= 0 V
V
= 1.65 V
EP
t
V
= 12 V
BBM2, CC
t
V
= 10 V
BBM2, CC
t
V
= 13 V
BBM2, CC
t
V
= 13 V
BBM2, CC
t
V
= 12 V
5.5
BBM2, CC
t
V
= 10 V
BBM2, CC
3.5
4.5
6.5
7.5
3.5
4.5
5.5
6.5
7.5
V
INDET
(V)
V
INDET
(V)
t
vs. V vs. V
t
vs. V vs. V
BBM3, 4
CC
INDET
BBM3, 4
CC
INDET
80
70
60
50
40
30
65
60
55
50
45
40
35
30
t
V
= 10 V
BBM4, CC
V
= 0 V
EP
t
V
= 12 V
BBM4, CC
t
t
V
= 12 V
= 13 V
BBM4, CC
t
V
= 10 V
BBM4, CC
V
BBM4, CC
t
V
= 13 V
BBM4, CC
V
= 1.65 V
EP
t
V
= 12 V
BBM3, CC
t
V
= 10 V
BBM3, CC
t
V
= 12 V
BBM3, CC
t
V
= 13 V
t
V
= 10 V
BBM3, CC
BBM3, CC
t
V
= 13 V
BBM3, CC
3.5
4.5
5.5
6.5
7.5
3.5
4.5
5.5
6.5
7.5
V
INDET
(V)
V
INDET
(V)
V
, F
, and Duty Cycle vs. V
ROSC OSC CLCONT
I
vs. R
(V = 72 V)
IN
OUT
LOAD
500
400
500
400
300
200
100
0
50
45
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
Frequency
Frequency
D%
D%
300
200
D
DL
D
SRL
I
OUT
100
0
V
ROSC
V
OUT
0
1
2
3
4
5
0.0
0.2
0.4
0.6
)
0.8
1.0
V
(V)
R
(
CLCONT
LOAD
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
14
Si9122A
Vishay Siliconix
TYPICAL WAVEFORMS
Figure 7.
Foldback Mode, R = 0.02
Figure 8.
Normal Mode, R = 0.1
L
L
SRL 10 V/div
SRL 10 V/div
I
5 A /div
I
5 A /div
5 V/div
OUT
OUT
D
L
10 V/div
D
L
CS2 5 V/div
CS2 50 mV/div
2
s/div
2 s/div
Figure 9.
V
CC
Ramp-Up
Figure 10. Overload Recovery
V
2 V/div
2 V/div
CL
V
IN
2 V/div
V
EP
I
10 A/div
OUT
V
OUT
2 V/div
V
CC
2 V/div
2 ms/div
200 s/div
Figure 11. Effective BBM—Measured On Secondary
Figure 12. Drive Waveforms
DH 5 V/div
LX 20 V/div
SRL 5 V/div
D
L
5 V/div
SRH 2 V/div
SRL 2 V/div
SRH 5 V/div
500 ns/div
500 ns/div
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and
Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see
http://www.vishay.com/ppg?73492.
Document Number: 73492
S–51921—Rev. A, 12-Sep-05
www.vishay.com
15
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