SI9122DQ-E3 [VISHAY]
Switching Regulator/Controller, Voltage-mode, 600kHz Switching Freq-Max, PDSO20;型号: | SI9122DQ-E3 |
厂家: | VISHAY |
描述: | Switching Regulator/Controller, Voltage-mode, 600kHz Switching Freq-Max, PDSO20 光电二极管 |
文件: | 总18页 (文件大小:211K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si9122
Vishay Siliconix
500-kHz Half-Bridge DC-DC Converter
With Integrated Secondary Synchronous Rectification Drivers
FEATURES
D 12-V to 72-V Input Voltage Range
D Compatible with ETSI 300 132-2
D Frequency Foldback Eliminates Constant Current Tail
D Advanced Maximum Current Control During Start-Up and
Shorted Load
D Integrated Half Bridge Primary Drivers
(1-A Drive Capability)
D Low Input Voltage Detection
D Secondary Synchronous Signals With Programmable
D Programmable Soft-Start Function
Deadtime Delay
D Over Temperature Protection
APPLICATIONS
D Voltage Mode Control
D Voltage Feedforward Compensation
D Network Cards
D High Voltage Pre-Regulator Operates During Start-Up
D Power Supply Modules
D Current Sensing On Low-Side Primary Device
DESCRIPTION
Si9122 is a dedicated half-bridge IC ideally suited to fixed
telecom applications where efficiency is required at low output
voltages (e.g <3.3 V). Designed to operate within the fixed
telecom voltage range of 33−72 V and withstand 100 V,
100 ms transients, the IC is capable of controlling and driving
both the low and high-side switching devices of a half bridge
circuit and also controlling the switching devices on the
secondary side of the bridge. Due to the very low on-resistance
of the secondary MOSFETs, a significant increase in the
efficiency can be achieved as compared with conventional
Schottky diodes. Control of the secondary devices is by means
of a pulse transformer and a pair of inverters. Such a system
has efficiencies well in excess of 90% even for low output
voltages. On-chip control of the dead time delays between the
primary and secondary synchronous signals keep efficiencies
high and prevent accidental destruction of the power
transformer. An external resistor sets the switching frequency
from 200 kHz to 600 kHz.
Si9122 has advanced current monitoring and control circuitry
which allow the user to set the maximum current in the primary
circuit. Such a feature acts as protection against output
shorting and also provides constant current into large
capacitive loads during start-up or when paralleling power
supplies. Current sensing is by means of a sense resistor on
the low-side primary device.
FUNCTIONAL BLOCK DIAGRAM
V
IN
+
C
D
VIN1
−
C
D
1
BOOST
To
CC
Power
Transformer
V
BST
L
X
V
CC
Pre-Reg
H
CV
CC
(High)
V
OUT
EP
Voltage
Control
Primary
Drivers
Voltage
Information
C
LOAD
R
LOAD
D
L
(Low)
PWM
t
R
S
CS2
Current
Control
Secondary
Drivers
Timer
BBM
Pulse
Transformer
CS1
SRH
Si9122
Half-Bridge
R
BBM
SRL
Synchronous
Controller
Current
Sense
Error
Amp
Opto
1.215 V
Figure 1.
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
1
Si9122
Vishay Siliconix
TECHNICAL DESCRIPTION
Si9122 is a voltage mode controller for the half-bridge
topology. With 100-V depletion mode MOSFET capability, the
Si9122 is capable of powering directly from the high voltage
bus to VCC through an external PNP pass transistor, or may be
powered through an external regulator directly through the
VCC pin. With PWM control, Si9122 provides peak efficiency
throughout the entire line and load range. In order to simplify
the traditional secondary synchronous rectification, Si9122
provides intelligent gate drive signals to control the secondary
MOSFETs. With independent gate drive signals from the
controller, transformer design is no longer limited by the gate
to a source rating of the MOSFETs. Si9122 provides constant
VGS voltage, independent of line voltage to minimize the gate
charge loss as well as conduction loss. A break-before-make
function is included to prevent shoot through current or
transformer shorting. Adjustable Break-Before-Make time is
incorporated into the IC and is programmable by an external
resistor value.
Si9122 is available in both standard and lead (Pb)-free
TSSOP-20 and standard SOIC-20 pin packages. In order to
satisfy the stringent ambient temperature requirements,
Si9122 is rated to handle the industrial temperature range of
–40 to 85_C. When a situation arises which results in a rapid
increase in primary (or secondary current) such as output
shorted or start-up with a large output capacitor, control of the
PWM generator is handed over to the the current loop.
Monitoring of the load current is by means of a sense resistor
on the primary low-side switch.
DETAILED BLOCK DIAGRAM
V
IN
V
CC
R
OSC
High-Side
Primary
Driver
BST
9.1 V
V
UVLO
REG_COMP
Pre-Regulator
+
−
Int
D
H
V
REF
8.8 V
L
X
Low-Side
Driver
V
V
CC
V
INDET
V
FF
V
D
UV
+
L
OSC
−
V
REF
EP
SS
Ramp
V
SD
+
−
PGND
132 kW
550 mV
60 kW
Error Amplifier
CC
−
+
Driver
Control
and
+
−
SR
H
V
PWM
Comparator
REF
Timing
2
20 mA
SYNC
Driver High
I
SS
OTP
8 V
V
CC
SR
L
CS2
CS1
Duty Cycle
Control
+
−
Peak DET
SYNC
Driver Low
Si9122
Over Current Protection
GND
C
BBM
L_CONT
Figure 2.
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
2
Si9122
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
V
V
V
V
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V
(100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150_C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C
IN
IN
a
Power Dissipation
CC
TSSOP-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 mW
SOIC-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 mW
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 V
(100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 V
BST
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V
Thermal Impedance (Q
)
LX
JA
b
TSSOP-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75_C/W
− V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
BST
LX
c
SOIC-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56_C/W
, R
REF OSC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
Notes
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
a. Device mounted on JEDEC compliant 1S2P test board..
b. Derate −1.4 mW/_C above 25_C.
c. Derate −1.8 mW/_C above 25_C.
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
h
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 to 72 V
C
C
C
C
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >680 pF
IN
BBM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 nF
SS
C
ꢀ C
VIN2
. . . . . . . . . . . . . . . . . . . . . . . . . 100 mF/ESR ꢁ 100 mW, 0.1 mF
VIN1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF
REF
V
CC
Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 to 13.2 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mF
BOOST
LOAD
CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 mF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 600 kHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 to 72 kW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 to 50 kW
CC
f
OSC
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V − 2 V
CC
R
R
OSC
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
CC
Reference Voltage Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 mA
BBM
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
−40 to 85_C
f
= 500 kHz, V = 72 V
IN
NOM
Parameter
Symbol
Minb
Typc
Maxb
Unit
V
INDET
= 7.2 V; 10 V ꢁ V ꢁ 13.2 V
CC
Reference (3.3 V)
Output Voltage
V
V
CC
= 12 V, 25_C Load = 0 mA
3.2
3.3
3.4
−50
−75
V
REF
Short Circuit Current
Load Regulation
I
V
REF
= 0 V
mA
mV
dB
SREF
dVr/dlr
PSRR
I
= 0 to −2.5 mA
−30
REF
Power Supply Rejection
@ 100Hz
60
Oscillator
Accuracy (1% R
Max Frequency
)
R
= 30 kW, f = 500 kHz
NOM
−20
−40
20
%
OSC
OSC
F
R
OSC
= 24 kW
600
100
MAX
kHz
d
Foldback Frequency
F
f
= 500 kHz, V
− V
ꢂ
1
5
0
m
V
FOBK
NOM
CS2
CS1
Error Amplifier
Input Bias Current
Gain
I
V
EP
= 0 V
−15
mA
V/V
MHz
dB
BIAS
A
V
−2.2
5
Bandwidth
BW
Power Supply Rejection
Slew Rate
PSRR
SR
@ 100Hz
60
0.5
V/ms
Current Sense Amplifier
Input Voltage CM Range
Input Amplifier Gain
V
V
CS1
− GND, V − GND
CS2
ꢃ150
17.5
5
mV
dB
CM
A
VOL
Input Amplifier Bandwidth
BW
MHz
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
3
Si9122
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
−40 to 85_C
f
= 500 kHz, V = 72 V
IN
NOM
Parameter
Symbol
Minb
Typc
Maxb
Unit
V
= 7.2 V; 10 V ꢁ V ꢁ 13.2 V
CC
INDET
Current Sense Amplifier
Input amplifier Offset Voltage
V
ꢃ5
120
0
mV
OS
dV = 0
CS
mA
dV = 100 mV
CS
CL_CONT Current
I
CL_CONT
dV = 170 mV
CS
ꢂ
2
mA
I
= I − I
= 0
PD
PU
CL_CONT
Lower Current Limit Threshold
V
TLCL
100
See Figure 6
mV
V
Upper Current Limit Threshold
Hysteresis
V
I
ꢂ
2
m
A
150
THCL
PD
I
ꢄ 500 mA
= 500 mA
PU
−50
PU
CL_CONT Clamp Level
C
I
0.6
90
1.5
95
L_CONT(min)
PWM Operation
D
V
= 0 V
92
ꢄ15
3
MAX
EP
f
= 500 kHz
OSC
e
Duty Cycle
V
= 1.75 V
%
V
EP
D
MIN
V
− V
ꢂ
1
5
0
m
V
CS2
CS1
Pre-Regulator
Input Voltage
+V
I
= 10 mA
72
10
IN
IN
Input Leakage Current
I
V
= 72 V, V ꢂ V
IN CC REG
LKG
mA
I
I
V
= 72 V, V
ꢄ V
SD
86
8
200
14
REG1
REG2
IN
INDET
Regulator Bias Current
V
= 72 V, V
ꢂ
V
mA
IN
INDET
REF
I
−29
50
−19
82
−9
SOURCE
Regulator_Comp
V
CC
= 12 V
mA
I
110
SINK
Pre-Regulator Drive Capacility
I
V
CC
ꢄ V
REG
20
mA
START
7.4
8.5
9.1
9.1
9.2
8.8
8.8
0.5
10.4
9.7
V
V
V
ꢂ
V
REG1
INDET REF
V
Pre-Regulator Turn Off
CC
T
= 25_C
= 25_C
A
Threshold Voltage
V
= 0 V
REG2
INDET
V
7.15
8.1
9.8
9.3
Undervoltage Lockout
g
V
UVLO
V
CC
Rising
T
A
V
UVLO
Hysteresis
V
UVLOHYS
Soft-Start
Soft-Start Current Output
I
Start-Up Condition
Normal Operation
12
20
28
mA
SS
Soft-Start Completion Voltage
V
7.35
8.05
8.85
V
SS_COMP
Shutdown
V
Shutdown FN
Hysteresis
V
V
Rising
INDET
350
550
200
720
INDET
INDET
SD
mV
V
V
V
INDET
VINDET Input Threshold Voltages
V
− V Under Voltage
V
UV
V
INDET
Rising
3.13
3.3
0.3
3.46
INDET
INDET
IN
V
Hysteresis
V
INDET
Over Temperature Protection
Activating Temperature
T Increasing
160
130
J
_C
De-Activating Temperature
T Decreasing
J
Converter Supply Current (VCC
)
Shutdown
I
I
I
Shutdown, V
= 0 V
50
4
350
12
mA
CC1
CC2
CC3
INDET
Switching Disabled
Switching w/o Load
V
INDET
ꢄ
V
8
REF
V
ꢂ V , f = 500 kHz
REF NOM
5
10
14
INDET
mA
V
= 12 V, C = C = 3 nF
DH DL
CC
C
Switching with C
I
21
LOAD
CC4
= C
= 0.3 nF
SRH
SRL
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
4
Si9122
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
−40 to 85_C
f
= 500 kHz, V = 72 V
IN
NOM
Parameter
Symbol
Minb
Typc
Maxb
Unit
V
= 7.2 V; 10 V ꢁ V ꢁ 13.2 V
INDET
CC
Output MOSFET DH Driver (High-Side)
Output High Voltage
Output Low Voltage
Boost Current
V
Sourcing 10 mA
Sinking 10 mA
V
BST
− 0.3
OH
V
mA
A
V
V
LX
+ 0.3
OL
I
V
V
= 72 V, V
= 72 V, V
= V + V
1.3
1.9
−0.7
−1.0
1.0
2.7
BST
LX
BST
BST
LX
CC
L
X
Current
I
= V + V
−1.1
−0.4
LX
SOURCE
LX
LX
CC
Peak Output Source
Peak Output Sink
Rise Time
I
−0.75
V
= 10 V
= 3 nF
CC
I
0.75
SINK
t
35
r
C
ns
DH
Fall Time
t
f
35
Output MOSFET DLDriver (Low-Side)
Output High Voltage
Output Low Voltage
Peak Output Source
Peak Output Sink
Rise Time
V
Sourcing 10 mA
Sinking 10 mA
V
CC
− 0.3
OH
V
A
V
0.3
OL
SOURCE
I
−1.0
1.0
35
−0.75
V
CC
= 10 V
= 3 nF
I
0.75
SINK
t
r
C
DL
ns
Fall Time
t
f
35
Synchronous Rectifier (SRH, SRL) Drivers
Output High Voltage
Output Low Voltage
V
Sourcing 10 mA
Sinking 10 mA
V
CC
− 0.4
OH
V
V
0.4
OL
t
t
t
t
55
40
BBM1
BBM2
BBM3
BBM4
T
A
= 25_C, R
= 33 kW, See Figure 3
= 33 kW, L = 72 V
BBM
f
Break-Before-Make Time
ns
35
T
= 25_C,R
A
BBM
X
55
Peak Output Source
Peak Output Sink
Rise Time
I
−100
100
35
SOURCE
V
= 10 V
mA
ns
CC
I
SINK
t
r
C
= C
= 0.3 nF
SRH
SRL
Fall Time
t
f
35
Voltage Mode
Error Amplifier
Current Mode
Current Amplifier
Notes
Input to high-side switch off
Input to low-side switch off
ꢄ200
ꢄ200
t
d1DH
d2DL
ns
ns
t
Input to high-side switch off
Input to low-side switch off
ꢄ200
ꢄ200
t
d3DH
t
d4DL
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (−40_ to 85_C).
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d.
F
when V
at clamp level. Typical foldback frequency change +20%, −30% over temperature.
MIN
CL_CONT
e. Measured on SRL or SRH outputs.
f.
g.
h.
See Figure 3 for Break-Before-Make time definition.
tracks V by a diode drop
V
UVLO
REG1
C
may be required to reduce noise into BBM pin for non-optimum layout.
BBM
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
5
Si9122
Vishay Siliconix
TIMING DIAGRAM FOR MOS DRIVERS
V
CC
PWM
PWM
PWM
PWM
GND
V
CC
D
L
D
L
GND
V
CC
SR
L
SR
L
GND
V
BST
D
H
D
H
V
MID
D
H
D
H
GND
V
CC
SR
H
SR
H
GND
Time
D
H
t
t
t
t
BBM4
BST = L + V
BBM1
BBM2
BBM3
X
CC
50%
V L
X
L
X
D , L
H
X
D , L
V
V
H
X
MID
SR
H
CC
50%
D , L
H
X
GND
t
t
BBM4
BBM3
D
L
SR
L
SR
L
V
CC
GND
Specification Table
Return to:
Rectification Timing Sequence
t
t
BBM2
BBM1
Primary MOSFET Drivers
Secondary MOSFET Drivers
Figure 3.
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
6
Si9122
Vishay Siliconix
PIN CONFIGURATION
Si9122DQ (TSSOP-20)
Si9122DW (SOIC-20)
ORDERING INFORMATION
V
BST
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Part Number
Temperature Range
Package
IN
REG_COMP
D
H
Si9122DQ-T1
Si9122DQ-T1—E3
Si9122DQ
V
CC
L
X
Tape and Reel
V
D
L
REF
Bulk
Tape and Reel
Bulk
−40 to 85_C
GND
PGND
Si9122DW-T1
Si9122DW
R
SR
H
OSC
EP
SR
L
V
SS
INDET
CS1
CS2
BBM
Eval Kit
Temperature Range
Board Type
C
L_CONT
Si9122DB
Issue 3
Surface Mount and
Thru-Hole
−10 to 70_C
Top View
PIN DESCRIPTION
Pin Number
Name
Function
1
2
3
4
5
6
7
V
Input supply voltage for the start-up circuit.
IN
REG_COMP
Control signal for an external pass transistor.
Supply voltage for internal circuitry
3.3-V reference, decoupled with 1-mF capacitor
Ground
V
CC
V
REF
GND
R
OSC
External resistor connection to oscillator
Voltage control input
EP
V
under voltage detect and shutdown function input. Shuts down or disables switching when V
falls below
IN
INDET
8
V
INDET
preset threshold voltages and provides the feed forward voltage.
9
CS1
CS2
Current limit amplifier negative input
10
11
12
13
14
15
16
17
18
19
20
Current limit amplifier positive input
C
Current limit compensation
L_CONT
BBM
Programmable Break-Before-Make time connection to an external resistor to set time delay
Soft-Start control − external capacitor connection
Signal transformer drive, sequenced with the primary side.
Signal transformer drive, sequenced with the primary side.
Power ground.
SS
SR
L
SR
H
PGND
D
L
Low-side gate drive signal – primary
L
X
High-side source and transformer connection node
High-side gate drive signal – primary
D
H
BST
Bootstrap voltage to drive the high-side n-channel MOSFET switch
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
7
Si9122
Vishay Siliconix
V
CC
V
IN
Pre-Regulator
+
V
REG
9.1 V
Bandgap
Reference
3.3 V
−
9.1 V
V
REF
V
UVLO
+
−
+
−
V
V
UV
High-Side
Primary
Driver
V
INDET
V
REF
8.6 V
C
L_CONT
SD
BST
+
−
Voltage
Feedforward
Frequency
Foldback
160_C Temp
High Voltage
Interface
D
H
Protection
550 mV
L
X
V
SD
V
V
UV UVLO
R
OSC
OSC
OTP
Oscillator
Clock
V
CC
Clock
Logic
Low-Side
Driver
132 kW
D
L
60 kW
EP
−
+
−
+
Logic
Timer
V
/2
REF
PGND
PWM
Generator
Current
Control
Gain
V
V
CC
Synchronous
Driver
CS2
CS1
Loop
+
−
Control
(High)
SR
H
100 mV
Blanking
CC
Synchronous
Driver
C
L_CONT
GND
(Low)
V
CC
SR
L
BBM
Si9122
20 mA
8 V
Soft-Start
SS
SS Enable
Figure 4.
Detailed Functional Block
DETAILED OPERATION
Start-Up
of the VCC capacitor, bootstrap capacitor and the soft-start
capacitor. The value of the VCC capacitor should therefore be
chosen to be capable of maintaining switch mode operation
until the VCC can be supplied from the external circuit (e.g via
a power transformer winding and zener regulator). Feedback
from the output of the switch mode supply charges VCC above
VREG and fully disconnects the pre-regulator, isolating VCC
from VIN. VCC is then maintained above VREG for the duration
of switch mode operation. In the event of an over voltage
condition on VCC, an internal voltage clamp turns on at 14.5 V
to shunt excessive current to GND.
When VINEXT rises above 0 V, the internal pre-regulator begins
to charge up the Vcc capacitor. Current into the external VCC
capacitor is limited to typically 40 mA by the internal DMOS
device. When Vcc exceeds the UVLO voltage of 8.8 V a
soft-start cycle of the switch mode supply is initiated. The VCC
supply continues to be charged by the pre-regulator until VCC
equals Vreg. During this period, between VUVLO and VREG
,
excessive load current will result in VCC falling below VUVLO
and stopping switch mode operation. This situation is avoided
by the hysteresis between VREG and VUVLO and correct sizing
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
8
Si9122
Vishay Siliconix
Care needs to be taken if there is a delay prior to the external
circuit feeding back to the VCC supply. To prevent excessive
power dissipation within the IC it is advisable to use an external
PNP device. A pin has been incorporated on the IC,
(REG_COMP) to provide compensation when employing the
external device. In this case the VIN pin is connected to the
base of the PNP device and controls the current, while the
REG_COMP pin determines the frequency compensation of
the circuit. To understand the operation please refer to
Figure 5.
period. Start-up from a VINDET power down is also initiated
under soft-start control.
Half-Bridge and Synchronous Rectification Timing
Sequence
The PWM signal generated within the Si9122 controls the low
and high-side bridge drivers on alternative cycles. A period of
inactivity always results after initiation of the soft-start cycle
until the soft-start voltage reaches approximately 1.2 V and
PWM controlled switching begins. The first bridge driver to
switch is always the low-side, DL as this allows charging of the
high-side boost capacitor.
The soft-start circuit is designed for the dc-dc converter to
start-up in an orderly manner and reduce component stress on
the IC. This feature is programmable by selecting an external
C
SS. An internal 20-mA current source charges CSS from 0 V
The timing and coordination of the drives to the primary and
secondary stages is very important and shown in Figure 3. It
is essential to avoid the situation where both of the secondary
MOSFETs are on when either the high or the low-side switch
are active. In this situation the transformer would effectively be
presented with a short across the output. To avoid this, a
dedicated break-before-make circuit is included which will
generate non overlapping waveforms for the primary and the
secondary drive signals. This is achieved by a programmable
timer which delays the switching on of the primary driver
relative to the switching off of the related secondary and
subsequently delays the switching on of the secondary relative
to the switching off of the related primary.
to the final clamped voltage of 8 V. In the event of UVLO or
shutdown, VSS will be held low (<1 V) disabling driver
switching. To prevent oscillations, a longer soft-start time may
be needed for high capacitive loads and high peak output
current applications.
Reference
The reference voltage of Si9122 is set at 3.3 V. The reference
voltage is de-coupled externally with 0.1-mF capacitor. The
VREF voltage is 0 V in shutdown mode and has 50-mA source
capability.
Typical variation in the tBBM3 and tBBM4 delay with LX voltage
is shown in graphs tBBM3, tBBM4 and for RBBM = 33 kW. This
is due to a reduction in propagation delay through the high-side
driver path as the LX voltage increases and must be
considered in setting the delay for the system level design.
Variation of BBM time with RBBM is shown in graph tBBM1 to
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage mode
and generates a fixed frequency pulse width modulated signal
to the drivers. Duty cycle is controlled over a wide range to
maintain output voltage under line and load variation. Voltage
feed forward is also included to take account of variations in
supply voltage VIN.
tBBM4 vs. RBBM
.
Primary High- and Low-Side MOSFET Drivers
The drive voltage for the low-side MOSFET switch is provided
directly from VCC. The high-side MOSFET however requires
the gate voltage to be enhanced above VIN. This is achieved
by bootstraping the VCC voltage onto the LX voltage (the
high-side MOSFET source). In order to provide the
bootstrapping an external diode and capacitor are required as
shown on the application schematic. The capacitor will charge
up after the low-side driver has turned on. The switch gate
drive signals DH and DL are shown in Figure 3.
In the half-bridge topology requiring isolation between output
and input, the reference voltage and error amplifier must be
supplied externally, usually on the secondary side. The error
information is thus passed to the power controller through an
opto-coupling device. This information is inverted, hence 0 V
represents the maximum duty cycle, whilst 2 V represents
minimum duty cycle. The error information enters the IC via pin
EP, and is passed to the PWM generator via an inverting
amplifier. The relationship between Duty cycle and VEP is
shown in the Typical Characteristic Graph,Duty Cycle vs. VEP
25_C, page 19. Voltage feedforward is implemented by taking
the attenuated VIN signal at VINDET and directly modulating the
duty cycle. The relationship between Duty cycle and VINDET is
shown in the the Typical Characteristic Graph, Duty Cycle vs.
VINDET, page 16.
Secondary MOSFET Drivers
The secondary side MOSFETs are driven from the Si9122 via
a center tapped pulse transformer and inverter drivers. The
waveforms from the IC SRH and SRL are shown in Figure 3.
Of importance is the relative voltage between SRH and SRL,
i.e. that which is presented across the primary of the pulse
transformer. When both potentials of SRL and SRH are equal
then by the action of the inverting driver both secondary
MOSFETs are left on.
At start-up, i.e., once VCC is greater than VUVLO, switching is
initiated under soft-start control which increases primary
switch on-times linearly from DMIN to DMAX over the soft-start
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
9
Si9122
Vishay Siliconix
Oscillator
VIN Voltage Monitor –VINDET
The oscillator is designed to operate at a nominal frequency of
500 kHz. The 500-kHz operating frequency allows the
converter to minimize the inductor and capacitor size,
improving the power density of the converter. The oscillator
and therefore the switching frequency is programmable by
attaching a resistor to the ROSC pin. Under overload conditions
the oscillator frequency is reduced by the current overload
protection to enable a constant current to be maintained into
a low impedance circuit.
The chip provides a means of sensing the voltage of VIN, and
withholding operation of the output drivers until a minimum
voltage of VREF (3.3 V, 300-mV hysteresis), is achieved. This
is achieved by choosing an appropriate resistive tap between
the ground and VIN, and comparing this voltage with the
reference voltage. When the applied voltage is greater than
VREF, the output drivers are activated as normal. VINDET also
provides the input to the voltage feed forward function.
Current Limit
However, if the divided voltage applied to the VINDET pin is
greater than VCC −0.3 V, the high-side driver, DH, will stop
switching until the voltage drops below VCC −0.3 V. Thus, the
resistive tap on the VIN divider must be set to accommodate
the normal VCC operating voltage to avoid this condition.
Alternatively, a zener clamp diode from VINDET to GND may
also be used.
Current mode control providing constant current operation is
achieved by monitoring the differential voltage between the
CS1and CS2 pins which are connected across a primary
low-side sense resistor. Once this differential voltage exceeds
the 100-mV trigger point, the voltage on the CL_CONT pin is
pulled lower at a rate proportional to the excess voltage and the
value of the external capacitor connected between the
Shutdown Mode
CL_CONT pin and ground. If the voltage between CS1 and CS2
If VINDET is forced below the lower threshold, a minimum of
350 mV(VSD), the device will enter SHUTDOWN mode. This
powers down all unnecessary functions of the controller,
ensures that the primary switches are off and results in a low
level current demand from the VIN or VCC supplies.
exceeds 150 mV the CL_CONT capacitor is discharged rapidly
resulting in minimum duty cycle and frequency immediately.
Lowering the CL_CONT voltage results in PWM control of the
output drive being taken over by the current limit control loop.
Current control works to initially reduce the switching duty
cycle down to DMIN (12.5%). Further reduction in the duty
cycle is accompanied by a reduction in switching frequency at
a rate proportional to the duty cycle. This prevents the on time
of the primary drivers fnom from reducing below 100 ns and
avoiding a current tail. Frequency reduction occurs to a
maximum of one fifth of the nominal frequency.
V
INEXT
R
EXT
V
IN
PNP Ext
(Si9122)
Auxillary
CC
HV
DMOS
V
With constant current mode control of on time and with
reduced operating frequency, protection of the MOSFET
switches is increased during fault conditions. Minimum duty
cycle and reduced frequency switching continues for the
duration of the fault condition. The converter reverts to voltage
mode operation immediately whenever the primary current
fails to reach the limit level. CL_CONT clamps to 6.5 V when not
in current limit.
V
CC
REG_COMP
EXT
C
0.5 mF
VCC
C
2 nF
14.5 V
V
REF
GND
The soft-start function does not apply under current limit as this
would constitute hiccup mode operation.
Figure 5. High-Voltage Pre-Regulator Circuit
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
10
Si9122
Vishay Siliconix
V
CC
OSC
AV
I
PU
120 mA (nom)
+
GM
Peak Detect
V
C
L_CLAMP
OFFSET
−
C
R
L_CONT
CS1
CS2
−
AV
A
ꢅ150 mV
ꢅ100 mV
V
+
EXT
Blank
+
C
EXT
GM
I
PD
0 − 240 mA (nom)
−
A
V
Figure 6 . Current Limit Circuit
TYPICAL CHARACTERISTICS
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
11
Si9122
Vishay Siliconix
TYPICAL CHARACTERISTICS
F
OSC
vs. R
@ V = 12 V
V vs. Temperature, V = 12 V
REF CC
OSC
CC
600
500
400
300
200
3.300
3.295
3.290
3.285
3.280
3.275
3.270
20
30
40
50
(kW)
60
70
80
−50
−25
0
25
50
75
100
R
Temperature (_C)
OSC
V
REG
vs. Temperature, V = 48 V
IN
SRL, SRH Duty Cycle vs. V
EP
10.0
9.5
9.0
8.5
8.0
7.5
100
90
80
70
60
50
40
30
20
10
0
3.6 V = V
INDET
4.8 V
7.2 V
V
ꢂ V
REF
INDET
TC = −11 mV/C
V
CC
= 12 V
−50 −25
0
25
50
75
100 125 150
0.0
0.5
1.0
1.5
2.0
Temperature (_C)
V
EP
(V)
I
SS
vs. Temperature
V
SS
vs. Temperature, V = 12 V
CC
25
23
21
19
17
15
8.20
8.15
8.10
8.05
8.00
7.95
7.90
V
CC
= 13 V
TC = +1.25 mV/C
V
CC
= 12 V
V
INDET
ꢂ V
REF
V
CC
= 10 V
−50
−25
0
25
50
75
100
125
−50 −25
0
25
50
75
100 125 150
Temperature (_C)
Temperature (_C)
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
12
Si9122
Vishay Siliconix
TYPICAL CHARACTERISTICS
I
vs. Temperature
REG2
I
vs. Temperature
CC3
11
10
9
13
12
11
10
9
8
7
6
8
5
7
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
800
800
Temperature (_C)
Temperature (_C)
D , D I
H
vs. V
OL
D , D I
vs. V
OH
L
SINK
H
L
SOURCE
250
200
150
100
50
250
200
150
100
50
V
= 12 V
V
CC
= 12 V
CC
0
0
0
200
400
600
0
200
400
600
800
V
(mV)
V
(mV)
OL
OH
SRL, SRH I
vs. V
OH
SRL, SRH I
vs. V
OL
SOURCE
SINK
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V
CC
= 12 V
V
CC
= 12 V
0
0
0
200
400
600
800
0
200
400
(mV)
600
V
(mV)
V
OH
OL
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
13
Si9122
Vishay Siliconix
TYPICAL CHARACTERISTICS
t
vs. R , V = 0 V
BBM EP
t
vs. R , V = 1.65 V
BBM EP
BBM
BBM
100
90
80
70
60
50
40
30
20
65
55
45
35
25
15
t
t
BBM4
V
CC
= 12 V
V
CC
= 12 V
t
t
BBM1
BBM1
BBM4
t
t
BBM2
BBM3
t
t
BBM3
BBM2
25
30
35
(kW)
40
45
25
30
35
40
45
R
R
(kW)
BBM
BBM
t
vs. Temperature, V = 0 V
t vs. Temperature, V = 1.65 V
BBM1, 2 EP
BBM1, 2
EP
80
70
60
50
40
30
60
55
50
45
40
35
30
t
= 13 V
BBM1
V
= 12 V
BBM
CC
t
= 10 V
BBM1
t
= 12 V
BBM1
R
= 33 kW
t
t
= 12
= 13
BBM1
t
= 10 V
BBM1
BBM1
V
= 12 V
= 33 kW
CC
BBM
R
t
= 10 V
BBM2
t
= 10 V
BBM2
t
= 12 V
BBM2
t
= 12 V
BBM2
t
= 13 V
t
= 13 V
0
BBM2
BBM2
−50
−25
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (_C)
Temperature (_C)
t
vs. Temperature, V = 0 V
t vs. Temperature, V = 1.65 V
BBM3, 4 EP
BBM3, 4
EP
80
70
t
= 10 V
V
= 0 V
BBM
V
= 1.65 V
BBM
BBM4
EP
EP
t
= 13 V
R
= 33 kW
R
= 33 kW
BBM4
65
60
55
50
45
40
35
30
70
60
50
40
30
20
t
= 12 V
BBM4
t
= 12 V
BBM4
t
= 10 V
BBM4
t
= 13 V
BBM4
t
= 13 V
BBM3
t
= 12 V
BBM3
t
= 12 V
BBM3
t
= 10 V
BBM3
t
= 10 V
BBM3
t
= 13 V
BBM3
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (_C)
Temperature (_C)
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
14
Si9122
Vishay Siliconix
TYPICAL CHARACTERISTICS
t
vs. V vs. V
t
vs. V vs. V
INDET CC
BBM1, 2
CC
INDET
BBM1, 2
80
70
60
50
40
30
55
50
45
40
35
t
= 13 V
= 10 V
BBM1
BBM1
t
= 13 V
BBM1
t
= 12 V
BBM1
t
t
t
= 12 V
BBM1
BBM1
= 10 V
= 13 V
V
EP
= 0 V
V
= 1.65 V
EP
t
= 12 V
BBM2
t
= 10 V
BBM2
t
BBM2
t
= 13 V
BBM2
t
= 12 V
5.5
BBM2
t
= 10 V
4.5
BBM2
3.5
4.5
6.5
7.5
3.5
5.5
6.5
7.5
V
INDER
(V)
V
INDER
(V)
t
vs. V vs. V
t
vs. V vs. V
INDET CC
BBM3, 4
CC
INDET
BBM3, 4
80
70
60
50
40
30
65
60
55
50
45
40
35
30
t
= 10 V
BBM4
V
= 0 V
EP
t
t
= 12 V
= 13 V
BBM4
t
= 10 V
BBM4
t
= 12 V
BBM4
BBM4
t
= 13 V
BBM4
V
= 1.65 V
EP
t
= 12 V
BBM3
t
= 10 V
BBM3
t
= 12 V
BBM3
t
= 13 V
BBM3
t
= 10 V
BBM3
t
= 13 V
4.5
BBM3
3.5
5.5
6.5
7.5
3.5
4.5
5.5
6.5
7.5
V
INDER
(V)
V
INDER
(V)
Current Sense Duty Cycle vs. V
CLCONT
V
= 7.2 V 25_C
I
vs. R
(V = 7.2 V)
IN
INDET
OUT
LOAD
500
400
500
400
300
200
100
0
50
45
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
Frequency
Frequency
D%
D%
300
200
D
DL
D
SRL
I
OUT
100
0
V
ROSC
V
OUT
0
1
2
3
4
5
0.0
0.2
0.4
0.6
(W)
0.8
1.0
V
(V)
R
CLCONT
LOAD
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
15
Si9122
Vishay Siliconix
TYPICAL WAVEFORMS
Figure 7.
Foldback Mode, R = 0.02 W
Figure 8.
Normal Mode, R = 0.1 W
L
L
SRL 10 V/div
SRL 10 V/div
I
5 A /div
I
5 A /div
5 V/div
OUT
OUT
D
L
10 V/div
D
L
CS2 5 V/div
CS2 50 mV/div
2 ms/div
2 ms/div
Figure 9.
V
CC
Ramp-Up
Figure 10. Over Load Recovery—Minimum Overshoot
V
CL
2 V/div
V
IN
2 V/div
V
EP
2 V/div
I
10 A/div
OUT
V
OUT
2 V/div
V
CC
2 V/div
2 ms/div
200 ms/div
Figure 11. Effective BBM—Measured On Secondary
Figure 12. Drive Waveforms
DH 5 V/div
LX 20 V/div
SRL 5 V/div
D
L
5 V/div
SRH 2 V/div
SRL 2 V/div
SRH 5 V/div
500 ns/div
500 ns/div
Document Number: 71815
S-40697—Rev. E, 19-Apr-04
www.vishay.com
16
V
V
CC
P1
VIN
1
IN
36 − 72 V
C1
1 mF
100 V
R1
90 kW
R27
1 MW
5.6
P2
1
7, 8
D2
Q2
FZT953
Q1
FMMT493
10MQ100N
GND
4
3
2
3
2
R3
D1
1
1
1
3
Q3
Si4486EY
1, 2, 3
L
X
470 kW
PNP
BAS19
R2
R5
1 MW
10 kW
R2
10 W
1
20
V
BST
IN
C8
0.1 mF
2
3
4
5
6
7
8
19
18
17
16
15
14
13
V
CC
REG_COMP
D
H
5.6
7, 8
2 nF
V
L
X
D3
CC
JP1
10MQ100N
C9
C29
1
2
4
V
D
L
REF
SD
EN
C10
4.7 mF
16 V
Q4
Si4486EY
GND
ROSC
EP
PGND
SR
1, 2, 3
3
470 pF
10 V
1 mF
10 V
P3
1
H
C30
200 − 800 pF
R6
35 kW
SR
AGND
L
C11
1000 pF
R7
2 kW
V
SS
BBM
INDET
9
12
11
CS1
CS2
C12
15 pF
10
C14
CL_CONT
4.7 nF
R9
27 kW
R8
5 kW
C13
4700 pF
R10
R12
0.02 W
2
2 kW
R11
1
/
W
2 kW
SRH
SRL
V
CC
EP
V
CC
4
4
2
Si3552DV
5.6
7, 8
3
1, 2, 3
Q5
C17
0.1 mF
R16
10 W
V
IN
Si4886DY
Q7B
Q7A
4
6
C1
15 mF
50 V
C4
15 mF
50 V
+
+
C2
1 mF
50 V
5.6
7, 8
3
1, 2, 3
D8
BAS19
1
T1 1, 2
Q6
1
Si4886DY
T3
5
5, 6
LEP-9080
D4
30BQ040
C15
L
X
5
4
R14
P4
3.3 V
R13
3.3 V
11, 12
15 W
3.3 W
1000 pF
C16
7, 8, 9
1, 2, 3
800 mW
1
C20
680 pF
100 V
R15
15 A
9, 10
C22
47 mF
10 V
C23
47 mF
10 V
C24
47 mF
10 V
C32
10 mF
6.3 V
R17
NU
P5
D7
30BQ040
3.3 W
D5
1000 pF
30BQ040
7, 8
3, 4
1
5.6
EPC19
D6
1, 2, 3
7, 8
MBR0520
3.3 V
R21
Q7
Si4886DY
C25
C33
0.1 mF
51 W
0.033 mF
TP1
1
4
4
+
+
C7
C5
1 mF
50 V
C6
5.6
7, 8
15 mF
15 mF
50 V
C26
1, 2, 3
50 V
R26
5.6 kW
R18
0.1 mF
R22
Q8
Si4886DY
33 kW
R20
20 kW
(5)
7
300 kW
(3)
3
U3
AD820
6
2
5
Q10B
+
−
C18
0.1 mF
2
3
(1)
8
C19
4.7 mF
16 V
R23
1
(4)
18.6 kW
U03
LM7301
R25
2 kW
4
6
P6
1
4
(2)
1
R19
3.9 kW
C27
0.1 mF
C28
1000 pF
PGND
D9
3
2
1
P7
1
C21
0.047 mF
25 V
3
3
2
1
Q10A
T2
6
5
4
Si3552DV
5
PGND
BAV99
U2
MOC207
1
SRH
SRL
6
5
1
2
3
D10
2
1
EP7
R24
1 MW
7
BAV99
V
CC
EP
C34, 0.1 mF
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