SI4948BEY_05 [VISHAY]
Dual P-Channel 60-V (D-S) 175 Celsius MOSFET; 双P通道60 - V(D -S) 175摄氏度的MOSFET型号: | SI4948BEY_05 |
厂家: | VISHAY |
描述: | Dual P-Channel 60-V (D-S) 175 Celsius MOSFET |
文件: | 总4页 (文件大小:209K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Vishay Siliconix
Dual P-Channel 60-V (D-S) 175° MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 72872
S-52399Rev. B, 21-Nov-05
1
SPICE Device Model Si4948BEY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Condition
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
2.1
50
V
A
V
DS = VGS, ID = −250 µA
VDS = −5 V, VGS = −10 V
0.100
0.120
7
0.100
0.126
8.5
VGS = −10 V, ID = −3.1 A
VGS = −4.5 V, ID = −2 A
Drain-Source On-State Resistancea
rDS(on)
Ω
Forward Transconductancea
Diode Forward Voltagea
gfs
S
V
VDS = −15 V, ID = −3.1 A
VSD
I
S = −2 A, VGS = 0 V
−0.81
−0.80
Dynamicb
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Qg
Qgs
Qgd
td(on)
tr
13
2.2
3.7
10
14
40
22
14.5
2.2
3.7
10
nC
ns
V
DS = −30 V, VGS = −10 V, ID = − 3.1 A
15
VDD = −30 V, RL = 30 Ω
I
D ≅ −1 A, VGEN = −10 V, RG = 6 Ω
Turn-Off Delay Time
Fall Time
td(off)
tf
50
35
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
Document Number: 72872
S-52399Rev. B, 21-Nov-05
2
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 72872
S-52399Rev. B, 21-Nov-05
3
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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document or by any conduct of Vishay.
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Document Number: 91000
Revision: 18-Jul-08
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1
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