SI4948EY-T1-E3 [VISHAY]

Power Field-Effect Transistor, 60V, 0.12ohm, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, ROHS COMPLIANT, SOP-8;
SI4948EY-T1-E3
型号: SI4948EY-T1-E3
厂家: VISHAY    VISHAY
描述:

Power Field-Effect Transistor, 60V, 0.12ohm, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, ROHS COMPLIANT, SOP-8

脉冲 光电二极管 晶体管
文件: 总8页 (文件大小:219K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Si4948EY  
Vishay Siliconix  
Dual P-Channel 60-V (D-S), 175 °C MOSFET  
FEATURES  
PRODUCT SUMMARY  
Halogen-free According to IEC 61249-2-21  
Definition  
TrenchFET® Power MOSFETs  
VDS (V)  
RDS(on) (Ω)  
ID (A)  
3.1  
0.120 at VGS = - 10 V  
0.150 at VGS = - 4.5 V  
- 60  
2.8  
175 °C Maximum Junction Temperature  
Compliant to RoHS Directive 2002/95/EC  
S
1
S
2
SO-8  
S
G
S
D
1
D
1
D
2
D
2
1
2
3
4
8
7
6
5
1
1
2
2
G
1
G
2
G
Top View  
D
1
D
2
Ordering Information: Si4948EY-T1-E3 (Lead (Pb)-free)  
Si4948EY-T1-GE3 (Lead (Pb)-free and Halogen-free)  
P-Channel MOSFET  
P-Channel MOSFET  
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted  
A
Parameter  
Symbol  
Limit  
- 60  
Unit  
VDS  
Drain-Source Voltage  
Gate-Source Voltage  
V
VGS  
20  
TA = 25 °C  
A = 70 °C  
3.1  
Continuous Drain Current (TJ = 175 °C)a  
ID  
T
2.6  
A
IDM  
IS  
Pulsed Drain Current  
Continuous Source Current (Diode Conduction)a  
30  
- 2.0  
2.4  
TA = 25 °C  
TA = 70 °C  
Maximum Power Dissipationa  
PD  
W
1.7  
TJ, Tstg  
Operating Junction and Storage Temperature Range  
- 55 to 175  
°C  
THERMAL RESISTANCE RATINGS  
Parameter  
Symbol  
Limit  
Unit  
Maximum Junction-to-Ambienta  
RthJA  
62.5  
°C/W  
Notes:  
a. Surface Mounted on FR4 board, t 10 s.  
Document Number: 70166  
S09-1389-Rev. F, 20-Jul-09  
www.vishay.com  
1
Si4948EY  
Vishay Siliconix  
SPECIFICATIONS T = 25 °C, unless otherwise noted  
J
Parameter  
Symbol  
Test Conditions  
Min.  
Typ.a  
Max.  
Unit  
Static  
VGS(th)  
IGSS  
VDS = VGS, ID = - 250 µA  
Gate Threshold Voltage  
Gate-Body Leakage  
- 1  
V
VDS = 0 V, VGS  
=
20 V  
100  
- 2  
nA  
VDS = - 60 V, VGS = 0 V  
DS = - 60 V, VGS = 0 V, TJ = 55 °C  
VDS - 5 V, VGS = - 10 V  
IDSS  
ID(on)  
Zero Gate Voltage Drain Current  
On-State Drain Currentb  
µA  
A
V
- 25  
- 20  
VGS = - 10 V, ID = - 3.1 A  
0.100  
0.125  
7.5  
0.120  
0.150  
Drain-Source On-State Resistanceb  
RDS(on)  
Ω
V
GS = - 4.5 V, ID = - 2.8 A  
Forward Transconductanceb  
Diode Forward Voltageb  
Dynamica  
gfs  
VDS = - 15 V, ID = - 3.1 A  
IS = - 2.0 A, VGS = 0 V  
S
V
VSD  
- 0.8  
- 1.2  
25  
Qg  
Qgs  
Qgd  
td(on)  
tr  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
Turn-On Delay Time  
Rise Time  
16  
4
VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A  
nC  
ns  
1.6  
8
15  
20  
50  
25  
90  
10  
35  
12  
60  
V
DD = - 30 V, RL = 30 Ω  
ID - 1 A, VGEN = - 10 V, Rg = 6 Ω  
td(off)  
tf  
Turn-Off Delay Time  
Fall Time  
trr  
IF = - 2.0 A, dI/dt = 100 A/µs  
Source-Drain Reverse Recovery Time  
Notes:  
a. Guaranteed by design, not subject to production testing.  
b. Pulse test; pulse width 300 µs, duty cycle 2 %.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
www.vishay.com  
2
Document Number: 70166  
S09-1389-Rev. F, 20-Jul-09  
Si4948EY  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
30  
20  
16  
12  
8
V
= 10 V thru 6 V  
GS  
T = - 55 °C  
C
24  
18  
12  
6
25 °C  
5 V  
150 °C  
4 V  
3 V  
4
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
- Drain-to-Source Voltage (V)  
V
- Gate-to-Source Voltage (V)  
DS  
GS  
Output Characteristics  
Transfer Characteristics  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1400  
1200  
1000  
800  
600  
400  
200  
0
C
iss  
V
= 4.5 V  
GS  
C
oss  
V
= 10 V  
GS  
16  
C
oss  
0
4
8
12  
20  
0
10  
20  
30  
40  
50  
60  
I
- Drain Current (A)  
V
- Drain-to-Source Voltage (V)  
D
DS  
On-Resistance vs. Drain Current  
Capacitance  
10  
8
2.0  
1.6  
1.2  
0.8  
0.4  
0
I
= 3.1 A  
I
= 3.1 A  
D
D
V
= 10 V  
GS  
V
= 30 V  
DS  
6
4
2
0
0
4
8
12  
16  
20  
- 50 - 25  
0
25  
50  
75 100 125 150 175  
Q
-
Total Gate Charge (nC)  
T - Junction Temperature (°C)  
g
J
Gate Charge  
On-Resistance vs. Junction Temperature  
Document Number: 70166  
S09-1389-Rev. F, 20-Jul-09  
www.vishay.com  
3
Si4948EY  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
0.5  
0.4  
20  
I
D
= 3.1 A  
10  
T = 175 °C  
J
0.3  
0.2  
0.1  
0
T = 25 °C  
J
1
2
4
6
8
10  
0
0.25  
0.50  
0.75  
1.00  
1.25 1.50  
V
- Gate-to-Source Voltage (V)  
VSD - Source-to-Drain Voltage (V)  
Source-Drain Diode Forward Voltage  
GS  
On-Resistance vs. Gate-to-Source Voltage  
0.75  
0.50  
0.25  
0.00  
50  
40  
30  
20  
10  
0
T
= 25 °C  
C
Single Pulse  
I
= 250 µA  
D
- 0.25  
- 50 - 25  
0
25  
50  
75 100 125 150 175  
0.01  
0.1  
1
10  
30  
T - Temperature (°C)  
J
Time (s)  
Single Pulse Power  
Threshold Voltage  
2
1
Duty Cycle = 0.5  
0.2  
Notes:  
P
DM  
0.1  
0.1  
t
1
0.05  
t
2
t
t
1
1. Duty Cycle, D =  
2
2. Per Unit Base = R  
= 62.5 °C/W  
thJA  
0.02  
(t)  
3. T - T = P  
Z
JM  
A
DM thJA  
4. Surface Mounted  
Single Pulse  
0.01  
-4  
-3  
-2  
-1  
10  
10  
10  
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
1
10  
30  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see www.vishay.com/ppg?70166.  
www.vishay.com  
4
Document Number: 70166  
S09-1389-Rev. F, 20-Jul-09  
Package Information  
Vishay Siliconix  
SOIC (NARROW): 8-LEAD  
JEDEC Part Number: MS-012  
8
6
7
2
5
4
E
H
1
3
S
h x 45  
D
C
0.25 mm (Gage Plane)  
A
All Leads  
0.101 mm  
q
e
B
A
1
L
0.004"  
MILLIMETERS  
Max  
INCHES  
DIM  
A
Min  
Min  
Max  
1.35  
0.10  
0.35  
0.19  
4.80  
3.80  
1.75  
0.20  
0.51  
0.25  
5.00  
4.00  
0.053  
0.004  
0.014  
0.0075  
0.189  
0.150  
0.069  
0.008  
0.020  
0.010  
0.196  
0.157  
A1  
B
C
D
E
e
1.27 BSC  
0.050 BSC  
H
h
5.80  
0.25  
0.50  
0°  
6.20  
0.50  
0.93  
8°  
0.228  
0.010  
0.020  
0°  
0.244  
0.020  
0.037  
8°  
L
q
S
0.44  
0.64  
0.018  
0.026  
ECN: C-06527-Rev. I, 11-Sep-06  
DWG: 5498  
Document Number: 71192  
11-Sep-06  
www.vishay.com  
1
VISHAY SILICONIX  
TrenchFET® Power MOSFETs  
Application Note 808  
Mounting LITTLE FOOT®, SO-8 Power MOSFETs  
Wharton McDaniel  
0.288  
7.3  
Surface-mounted LITTLE FOOT power MOSFETs use  
integrated circuit and small-signal packages which have  
0.050  
1.27  
0.088  
2.25  
been been modified to provide the heat transfer capabilities  
required by power devices. Leadframe materials and  
design, molding compounds, and die attach materials have  
been changed, while the footprint of the packages remains  
the same.  
0.088  
2.25  
0.027  
0.69  
0.078  
1.98  
0.2  
5.07  
See Application Note 826, Recommended Minimum Pad  
Patterns With Outline Drawing Access for Vishay Siliconix  
MOSFETs, (http://www.vishay.com/ppg?72286), for the  
basis of the pad design for a LITTLE FOOT SO-8 power  
MOSFET. In converting this recommended minimum pad  
to the pad set for a power MOSFET, designers must make  
two connections: an electrical connection and a thermal  
connection, to draw heat away from the package.  
Figure 2. Dual MOSFET SO-8 Pad Pattern  
With Copper Spreading  
The minimum recommended pad patterns for the  
single-MOSFET SO-8 with copper spreading (Figure 1) and  
dual-MOSFET SO-8 with copper spreading (Figure 2) show  
the starting point for utilizing the board area available for the  
heat-spreading copper. To create this pattern, a plane of  
copper overlies the drain pins. The copper plane connects  
the drain pins electrically, but more importantly provides  
planar copper to draw heat from the drain leads and start the  
process of spreading the heat so it can be dissipated into the  
ambient air. These patterns use all the available area  
underneath the body for this purpose.  
In the case of the SO-8 package, the thermal connections  
are very simple. Pins 5, 6, 7, and 8 are the drain of the  
MOSFET for a single MOSFET package and are connected  
together. In a dual package, pins 5 and 6 are one drain, and  
pins 7 and 8 are the other drain. For a small-signal device or  
integrated circuit, typical connections would be made with  
traces that are 0.020 inches wide. Since the drain pins serve  
the additional function of providing the thermal connection  
to the package, this level of connection is inadequate. The  
total cross section of the copper may be adequate to carry  
the current required for the application, but it presents a  
large thermal impedance. Also, heat spreads in a circular  
fashion from the heat source. In this case the drain pins are  
the heat sources when looking at heat spread on the PC  
board.  
Since surface-mounted packages are small, and reflow  
soldering is the most common way in which these are  
affixed to the PC board, “thermal” connections from the  
planar copper to the pads have not been used. Even if  
additional planar copper area is used, there should be no  
problems in the soldering process. The actual solder  
connections are defined by the solder mask openings. By  
combining the basic footprint with the copper plane on the  
drain pins, the solder mask generation occurs automatically.  
0.288  
7.3  
0.050  
1.27  
0.196  
5.0  
A final item to keep in mind is the width of the power traces.  
The absolute minimum power trace width must be  
determined by the amount of current it has to carry. For  
thermal reasons, this minimum width should be at least  
0.020 inches. The use of wide traces connected to the drain  
plane provides a low impedance path for heat to move away  
from the device.  
0.027  
0.69  
0.078  
1.98  
0.2  
5.07  
Figure 1. Single MOSFET SO-8 Pad  
Pattern With Copper Spreading  
Document Number: 70740  
Revision: 18-Jun-07  
www.vishay.com  
1
Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM PADS FOR SO-8  
0.172  
(4.369)  
0.028  
(0.711)  
0.022  
0.050  
(0.559)  
(1.270)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
www.vishay.com  
22  
Document Number: 72606  
Revision: 21-Jan-08  
Legal Disclaimer Notice  
www.vishay.com  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular  
purpose, non-infringement and merchantability.  
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical  
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements  
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular  
product with the properties described in the product specification is suitable for use in a particular application. Parameters  
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All  
operating parameters, including typical parameters, must be validated for each customer application by the customer’s  
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,  
including but not limited to the warranty expressed therein.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.  
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree  
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and  
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay  
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by  
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.  
Material Category Policy  
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the  
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council  
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment  
(EEE) - recast, unless otherwise specified as non-compliant.  
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that  
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.  
Revision: 12-Mar-12  
Document Number: 91000  
1

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