SSM3K56ACT [TOSHIBA]
SMALL SIGNAL, FET;![SSM3K56ACT](http://pdffile.icpdf.com/pdf2/p00242/img/icpdf/SSM3K56ACT-L_1468426_icpdf.jpg)
型号: | SSM3K56ACT |
厂家: | ![]() |
描述: | SMALL SIGNAL, FET 开关 晶体管 |
文件: | 总8页 (文件大小:208K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SSM3K56ACT
MOSFETs Silicon N-Channel MOS
SSM3K56ACT
1. Applications
•
High-Speed Switching
2. Features
(1) 1.5-V gate drive voltage.
(2) Low drain-source on-resistance
: RDS(ON) = 235 mΩ (max) (@VGS = 4.5 V)
RDS(ON) = 300 mΩ (max) (@VGS = 2.5 V)
RDS(ON) = 480 mΩ (max) (@VGS = 1.8 V)
RDS(ON) = 840 mΩ (max) (@VGS = 1.5 V)
3. Packaging and Pin Configuration
1.Gate
2.Source
3.Drain
CST3
Start of commercial production
2015-11
©2015 Toshiba Corporation
2015-11-16
Rev.1.0
1
SSM3K56ACT
4. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25)
Characteristics
Symbol
Rating
Unit
V
Drain-source voltage
Gate-source voltage
Drain current (DC)
Drain current (pulsed)
Power dissipation
VDSS
VGSS
ID
20
±8
(Note 1)
(Note 1),(Note 2)
(Note 3)
1400
2800
500
mA
IDP
PD
mW
Channel temperature
Storage temperature
Tch
150
Tstg
-55 to 150
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Ensure that the channel temperature does not exceed 150.
Note 2: Pulse width (PW) ≤ 10 ms, duty ≤ 1%
Note 3: Mounted on an FR4 board.(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
Note: The MOSFETs in this device are sensitive to electrostatic discharge. When handling this device, the worktables,
operators, soldering irons and other objects should be protected against anti-static discharge.
Note: The channel-to-ambient thermal resistance, Rth(ch-a), and the power dissipation, PD, vary according to the
board material, board area, board thickness and pad area. When using this device, be sure to take heat
dissipation fully into account.
©2015 Toshiba Corporation
2015-11-16
Rev.1.0
2
SSM3K56ACT
5. Electrical Characteristics
5.1. Static Characteristics (Unless otherwise specified, Ta = 25)
Characteristics
Gate leakage current
Symbol
Test Condition
Min
Typ.
Max
Unit
IGSS
IDSS
VGS = ±6 V, VDS = 0 V
20
15
0.4
±1
1
µA
Drain cut-off current
VDS = 10 V, VGS = 0 V
Drain-source breakdown voltage
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS ID = 1 mA, VGS = 0 V
V
(Note 1) V(BR)DSX ID = 1 mA, VGS = -5 V
(Note 2)
Vth
VDS = 3 V, ID = 1 mA
1.0
235
300
480
840
Drain-source on-resistance
(Note 3) RDS(ON) ID = 800 mA, VGS = 4.5 V
ID = 600 mA, VGS = 2.5 V
186
230
290
360
1.4
mΩ
ID = 200 mA, VGS = 1.8 V
ID = 50 mA, VGS = 1.5 V
Forward transfer admittance
(Note 3)
|Yfs|
VDS = 3 V, ID = 200 mA
S
Note 1: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain-
source breakdown voltage is lowered in this mode.
Note 2: Let Vth be the voltage applied between gate and source that causes the drain current (ID) to below (1 mA for
this device). Then, for normal switching operation, VGS(ON) must be higher than Vth, and VGS(OFF) must be
lower than Vth. This relationship can be expressed as: VGS(OFF) < Vth < VGS(ON).
Take this into consideration when using the device.
Note 3: Pulse measurement.
5.2. Dynamic Characteristics (Unless otherwise specified, Ta = 25)
Characteristics
Input capacitance
Symbol
Test Condition
Min
Typ.
Max
Unit
pF
Ciss
Crss
Coss
ton
VDS = 10 V, VGS = 0 V,
f = 1 MHz
55
6
Reverse transfer capacitance
Output capacitance
16
5.5
Switching time (turn-on time)
VDD = 10 V, ID = 200 mA
ns
VGS = 0 to 2.5 V, RG = 50 Ω,
Duty ≤ 1%, Input: tr, tf < 5 ns
Common source, See Chapter 5.3
Switching time (turn-off time)
toff
8.5
5.3. Switching Time Test Circuit
Fig. 5.3.1 Test Circuit of Switching Time
Fig. 5.3.2 Input Waveform/Output Waveform
5.4. Gate Charge Characteristics (Unless otherwise specified, Ta = 25)
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
nC
Total gate charge (gate-source plus gate-drain)
Gate-source charge 1
Qg
Qgs1
Qgd
VDD = 10 V, VGS = 4.5 V,
ID = 800 mA
1.0
0.12
0.4
Gate-drain charge
©2015 Toshiba Corporation
2015-11-16
Rev.1.0
3
SSM3K56ACT
5.5. Source-Drain Characteristics (Unless otherwise specified, Ta = 25)
Characteristics
Diode forward voltage
Symbol
Test Condition
Min
Typ.
Max
-1.2
Unit
V
(Note 1)
VDSF
ID = -1.4 A, VGS = 0 V
-0.82
Note 1: Pulse measurement.
6. Marking
Fig. 6.1 Marking
Fig. 6.2 Pin Condition(top view)
©2015 Toshiba Corporation
2015-11-16
Rev.1.0
4
SSM3K56ACT
7. Characteristics Curves (Note)
Fig. 7.1 ID - VDS
Fig. 7.2 ID - VGS
Fig. 7.3 RDS(ON) - VGS
Fig. 7.4 RDS(ON) - ID
Fig. 7.5 RDS(ON) - Ta
Fig. 7.6 Vth - Ta
©2015 Toshiba Corporation
2015-11-16
Rev.1.0
5
SSM3K56ACT
Fig. 7.7 |Yfs| - ID
Fig. 7.8 IDR - VDS
Fig. 7.9 C - VDS
Fig. 7.10 t - ID
Fig. 7.11 Dynamic Input Characteristics
Fig. 7.12 PD - Ta
Note: The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2015 Toshiba Corporation
2015-11-16
Rev.1.0
6
SSM3K56ACT
Package Dimensions
Unit: mm
Weight: 0.75 mg (typ.)
Package Name(s)
Nickname: CST3
©2015 Toshiba Corporation
2015-11-16
Rev.1.0
7
SSM3K56ACT
RESTRICTIONS ON PRODUCT USE
•
•
•
Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's
written permission, reproduction is permissible only if reproduction is without alteration/omission.
ThoughTOSHIBAworkscontinuallytoimproveProduct'squalityandreliability,Productcanmalfunctionorfail.Customersareresponsible
for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage
to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate
the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA
information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the
precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application
with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications,
including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating
and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample
application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications.
TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
•
PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY
CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
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applicable laws or regulations.
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©2015 Toshiba Corporation
2015-11-16
Rev.1.0
8
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