74VHC163FT [TOSHIBA]

CMOS Logic ICs - 74VHC Series;
74VHC163FT
型号: 74VHC163FT
厂家: TOSHIBA    TOSHIBA
描述:

CMOS Logic ICs - 74VHC Series

光电二极管 逻辑集成电路 触发器
文件: 总17页 (文件大小:324K)
中文:  中文翻译
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74VHC161FT,74VHC163FT  
CMOS Digital Integrated Circuits Silicon Monolithic  
74VHC161FT,74VHC163FT  
1. Functional Description  
Synchronous Presettable 4-Bit Counter  
74VHC161FT: Binary , Asynchronous Clear  
74VHC163FT: Binary , Synchronous Clear  
2. General  
The 74VHC161FT and 74VHC163FT are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4 BIT  
BINARY COUNTERs fabricated with silicon gate C2MOS technology.  
They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS  
low power dissipation.  
The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level.  
Presetting of each IC's is synchronous to the rising edge of CK.  
The clear function of the 74VHC163FT is synchronous to CK, while the 74VHC161FT are cleared asynchronously.  
Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters,  
which facilitates easy implementation of n-bit counters without using external gates.  
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply  
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.  
This circuit prevents device destruction due to mismatched supply and input voltages  
3. Features  
(1) AEC-Q100 (Rev. H) (Note 1)  
(2) Wide operating temperature range: Topr = -40 to 125  
(3) High speed: fMAX = 185 MHz (typ.) at VCC = 5 V  
(4) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25   
(5) High noise immunity: VNIH = VNIL = 28 % VCC (min)  
(6) Power-down protection is provided on all inputs.  
(7) Balanced propagation delays: tPLH tPHL  
(8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V  
(9) Low noise: VOLP=0.8 V (max)  
(10) Pin and function compatible with 74 series (AC/HC/AHC/LV etc.) 161 or 163 type.  
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales  
representative.  
Start of commercial production  
2014-12  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
1
74VHC161FT,74VHC163FT  
4. Packaging  
TSSOP16B  
5. Pin Assignment  
6. Marking  
74VHC161FT  
74VHC163FT  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
2
74VHC161FT,74VHC163FT  
7. IEC Logic Symbol  
74VHC161FT  
74VHC163FT  
8. Truth Table  
X:  
Don't care  
A, B, C, D: Logic level of data inputs  
Carry: Carry = ENTQAQBQCQD  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
3
74VHC161FT,74VHC163FT  
9. Timing Diagrams  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
4
74VHC161FT,74VHC163FT  
10. System Diagram  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
5
74VHC161FT,74VHC163FT  
11. Absolute Maximum Ratings (Note)  
Characteristics  
Symbol  
Note  
Rating  
Unit  
Supply voltage  
VCC  
VIN  
-0.5 to 7.0  
-0.5 to 7.0  
-0.5 to VCC + 0.5  
-20  
V
V
Input voltage  
Output voltage  
VOUT  
IIK  
V
Input diode current  
Output diode current  
Output current  
mA  
mA  
mA  
mA  
mW  
IOK  
±20  
IOUT  
ICC  
±25  
VCC/ground current  
Power dissipation  
Storage temperature  
±50  
PD  
(Note 1)  
180  
Tstg  
-65 to 150  
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even  
destruction.  
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the  
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even  
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum  
ratings and the operating ranges.  
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook  
(“HandlingPrecautions”/“DeratingConceptandMethods”)andindividualreliabilitydata(i.e. reliabilitytestreport  
and estimated failure rate, etc).  
Note 1: 180 mW in the range of Ta = -40 to 85 . From Ta = 85 to 125 a derating factor of -3.25 mW/shall be  
applied until 50 mW.  
12. Operating Ranges (Note)  
Characteristics  
Supply voltage  
Symbol  
Test Condition  
Rating  
Unit  
VCC  
VIN  
2.0 to 5.5  
0 to 5.5  
V
V
Input voltage  
Output voltage  
VOUT  
Topr  
0 to VCC  
-40 to 125  
0 to 100  
0 to 20  
V
Operating temperature  
Input rise and fall times  
dt/dv  
VCC = 3.3 ± 0.3 V  
VCC = 5 ± 0.5 V  
ns/V  
Note: The operating ranges must be maintained to ensure the normal operation of the device.  
Unused inputs must be tied to either VCC or GND.  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
6
74VHC161FT,74VHC163FT  
13. Electrical Characteristics  
13.1. DC Characteristics (Unless otherwise specified, Ta = 25 )  
Characteristics  
Symbol  
VIH  
Test Condition  
VCC (V)  
2.0  
Min  
Typ.  
Max  
Unit  
V
High-level input voltage  
1.50  
3.0 to 5.5 VCC × 0.7  
Low-level input voltage  
High-level output voltage  
VIL  
2.0  
3.0 to 5.5  
2.0  
0.50  
VCC × 0.3  
V
V
VOH  
VIN = VIH or VIL  
IOH = -50 µA  
1.9  
2.9  
4.4  
2.58  
3.94  
2.0  
3.0  
4.5  
3.0  
4.5  
IOH = -4 mA  
IOH = -8 mA  
IOL = 50 µA  
3.0  
4.5  
Low-level output voltage  
VOL  
VIN = VIH or VIL  
2.0  
0.0  
0.0  
0.0  
0.1  
V
3.0  
0.1  
4.5  
0.1  
IOL = 4 mA  
IOL = 8 mA  
3.0  
0.36  
0.36  
±0.1  
4.0  
4.5  
Input leakage current  
IIN  
VIN = 5.5 V or GND  
VIN = VCC or GND  
0 to 5.5  
5.5  
µA  
µA  
Quiescent supply current  
ICC  
13.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 )  
Characteristics  
Symbol  
VIH  
Test Condition  
VCC (V)  
2.0  
Min  
Max  
Unit  
V
High-level input voltage  
1.50  
3.0 to 5.5 VCC × 0.7  
Low-level input voltage  
High-level output voltage  
VIL  
2.0  
3.0 to 5.5  
2.0  
0.50  
VCC × 0.3  
V
V
VOH  
VIN = VIH or VIL  
IOH = -50 µA  
1.9  
2.9  
4.4  
2.48  
3.80  
3.0  
4.5  
IOH = -4 mA  
IOH = -8 mA  
IOL = 50 µA  
3.0  
4.5  
Low-level output voltage  
VOL  
VIN = VIH or VIL  
2.0  
0.1  
V
3.0  
0.1  
4.5  
0.1  
IOL = 4 mA  
IOL = 8 mA  
3.0  
0.44  
0.44  
±1.0  
40.0  
4.5  
Input leakage current  
IIN  
VIN = 5.5 V or GND  
VIN = VCC or GND  
0 to 5.5  
5.5  
µA  
µA  
Quiescent supply current  
ICC  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
7
74VHC161FT,74VHC163FT  
13.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 )  
Characteristics  
Symbol  
VIH  
Test Condition  
VCC (V)  
2.0  
Min  
Max  
Unit  
V
High-level input voltage  
1.50  
3.0 to 5.5 VCC × 0.7  
Low-level input voltage  
High-level output voltage  
VIL  
2.0  
3.0 to 5.5  
2.0  
0.50  
VCC × 0.3  
V
V
VOH  
VIN = VIH or VIL  
IOH = -50 µA  
1.9  
2.9  
4.4  
2.40  
3.70  
3.0  
4.5  
IOH = -4 mA  
IOH = -8 mA  
IOL = 50 µA  
3.0  
4.5  
Low-level output voltage  
VOL  
VIN = VIH or VIL  
2.0  
0.1  
V
3.0  
0.1  
4.5  
0.1  
IOL = 4 mA  
IOL = 8 mA  
3.0  
0.55  
0.55  
±2.0  
80.0  
4.5  
Input leakage current  
IIN  
VIN = 5.5 V or GND  
VIN = VCC or GND  
0 to 5.5  
5.5  
µA  
µA  
Quiescent supply current  
ICC  
13.4. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns)  
Characteristics  
Minimum pulse width  
Symbol  
Note  
Test Condition  
Figure 1  
VCC (V)  
Limit  
Unit  
ns  
tw(L),tw(H)  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
5.0  
5.0  
5.0  
5.0  
5.5  
4.5  
8.0  
5.0  
7.5  
5.0  
4.0  
3.5  
1.0  
1.0  
1.0  
1.5  
2.5  
1.5  
(CK)  
Minimum pulse width  
(CLR)  
tw(L)  
tS  
(Note 1)  
Figure 4  
Figure 2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Minimum setup time  
(A,B,C,D)  
Minimum setup time  
(LOAD)  
tS  
Figure 2  
Minimum setup time  
(ENT,ENP)  
tS  
Figure 3  
Minimum setup time  
(CLR)  
tS  
(Note 2)  
Figure 5  
Minimum hold time  
th  
Figure 2, Figure 3  
Figure 5  
Minimum hold time  
(CLR)  
th  
(Note 2)  
(Note 1)  
Minimum removal time  
(CLR)  
trem  
Figure 4  
Note 1: For 74VHC161FT only  
Note 2: For 74VHC163FT only  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
8
74VHC161FT,74VHC163FT  
13.5. Timing Requirements  
(Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns)  
Characteristics  
Minimum pulse width  
Symbol  
Note  
Test Condition  
Figure 1  
VCC (V)  
Limit  
Unit  
ns  
tw(L),tw(H)  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
5.0  
5.0  
5.0  
5.0  
6.5  
4.5  
9.5  
6.0  
9.0  
6.0  
4.0  
3.5  
1.0  
1.0  
1.0  
1.5  
2.5  
1.5  
(CK)  
Minimum pulse width  
(CLR)  
tw(L)  
tS  
(Note 1)  
Figure 4  
Figure 2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Minimum setup time  
(A,B,C,D)  
Minimum setup time  
(LOAD)  
tS  
Figure 2  
Minimum setup time  
(ENT,ENP)  
tS  
Figure 3  
Minimum setup time  
(CLR)  
tS  
(Note 2)  
Figure 5  
Minimum hold time  
th  
Figure 2, Figure 3  
Figure 5  
Minimum hold time  
(CLR)  
th  
(Note 2)  
(Note 1)  
Minimum removal time  
(CLR)  
trem  
Figure 4  
Note 1: For 74VHC161FT only  
Note 2: For 74VHC163FT only  
13.6. Timing Requirements  
(Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns)  
Characteristics  
Minimum pulse width  
Symbol  
Note  
Test Condition  
Figure 1  
VCC (V)  
Limit  
Unit  
ns  
tw(L),tw(H)  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
5.0  
5.0  
5.0  
5.0  
6.5  
4.5  
9.5  
6.0  
9.0  
6.0  
4.0  
3.5  
1.0  
1.0  
1.0  
1.5  
3.5  
2.0  
(CK)  
Minimum pulse width  
(CLR)  
tw(L)  
tS  
(Note 1)  
Figure 4  
Figure 2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Minimum setup time  
(A,B,C,D)  
Minimum setup time  
(LOAD)  
tS  
Figure 2  
Minimum setup time  
(ENT,ENP)  
tS  
Figure 3  
Minimum setup time  
(CLR)  
tS  
(Note 2)  
Figure 5  
Minimum hold time  
th  
Figure 2, Figure 3  
Figure 5  
Minimum hold time  
(CLR)  
th  
(Note 2)  
(Note 1)  
Minimum removal time  
(CLR)  
trem  
Figure 4  
Note 1: For 74VHC161FT only  
Note 2: For 74VHC163FT only  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
9
74VHC161FT,74VHC163FT  
13.7. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns)  
Characteristics  
Symbol  
Note  
Test Condition VCC (V) CL (pF)  
Min  
Typ.  
Max  
Unit  
ns  
Propagation delay time  
(CK - Q)  
tPLH,tPHL  
Figure 1,  
Figure 2  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
80  
55  
135  
95  
8.3  
10.8  
4.9  
6.4  
8.7  
11.2  
4.9  
6.4  
11.0  
13.5  
6.2  
7.7  
7.5  
10.5  
4.9  
6.4  
8.9  
11.2  
5.5  
7.0  
8.4  
10.9  
5.0  
6.5  
130  
85  
12.8  
16.3  
8.1  
10.1  
13.6  
17.1  
8.1  
Propagation delay time  
(CK - CARRY , count-mode)  
tPLH,tPHL  
tPLH,tPHL  
tPLH,tPHL  
tPHL  
Figure 1  
Figure 2  
Figure 6  
Figure 4  
Figure 4  
ns  
ns  
10.1  
17.2  
20.7  
10.3  
12.3  
12.3  
15.8  
8.1  
Propagation delay time  
(CK - CARRY , preset-mode)  
Propagation delay time  
(ENT - CARRY)  
ns  
10.1  
13.6  
17.1  
9.0  
Propagation delay time  
(CLR - Q)  
(Note 1)  
(Note 1)  
ns  
11.0  
13.2  
16.7  
8.6  
Propagation delay time  
(CLR - CARRY)  
tPHL  
ns  
10.6  
Maximum clock frequency  
fMAX  
MHz  
185  
125  
4
Input capacitance  
CIN  
10  
pF  
pF  
Power dissipation capacitance  
CPD  
(Note 2)  
23  
Note 1: For 74VHC161FT only  
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current  
consumption without load.  
Average operating current can be obtained by the equation:  
ICC(opr) = CPD × VCC × fIN + ICC  
When the outputs drive a capacitive load, total current consumption is the sum of ICC(opr) and ICC which is  
obtained from the following formula:  
ICC = fCK × VCC × (CQA/2 + CQB/4 + CQC/8 + CQD/16 + CCO/16)  
CQA to CQD and CCO are the capacitances at QA to QD and Carry out, respectively.  
fCK is the input frequency of the CK.  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
10  
74VHC161FT,74VHC163FT  
13.8. AC Characteristics  
(Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns)  
Characteristics  
Symbol  
Note  
Test Condition  
VCC (V) CL (pF)  
Min  
Max  
Unit  
ns  
Propagation delay time  
(CK - Q)  
tPLH,tPHL  
Figure 1, Figure 2  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
70  
15.0  
18.5  
9.5  
11.5  
16.0  
19.5  
9.5  
Propagation delay time  
(CK - CARRY , count-mode)  
tPLH,tPHL  
tPLH,tPHL  
tPLH,tPHL  
tPHL  
Figure 1  
Figure 2  
Figure 6  
Figure 4  
Figure 4  
ns  
ns  
11.5  
20.0  
23.5  
12.0  
14.0  
14.5  
18.0  
9.5  
Propagation delay time  
(CK - CARRY , preset-mode)  
Propagation delay time  
(ENT - CARRY)  
ns  
11.5  
16.0  
19.5  
10.5  
12.5  
15.5  
19.0  
10.0  
12.0  
Propagation delay time  
(CLR - Q)  
(Note 1)  
(Note 1)  
ns  
Propagation delay time  
(CLR - CARRY)  
tPHL  
ns  
Maximum clock frequency  
fMAX  
MHz  
pF  
50  
115  
85  
Input capacitance  
CIN  
10  
Note 1: For 74VHC161FT only  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
11  
74VHC161FT,74VHC163FT  
13.9. AC Characteristics  
(Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns)  
Characteristics  
Symbol  
Note  
Test Condition  
VCC (V) CL (pF)  
Min  
Max  
Unit  
ns  
Propagation delay time  
(CK - Q)  
tPLH,tPHL  
Figure 1, Figure 2  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
15  
50  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
60  
17.0  
20.5  
11.0  
13.0  
18.0  
21.5  
11.0  
13.0  
22.5  
26.0  
13.5  
15.5  
16.5  
20.0  
11.0  
13.0  
18.0  
21.5  
12.0  
14.0  
17.5  
21.0  
11.5  
13.5  
Propagation delay time  
(CK - CARRY , count-mode)  
tPLH,tPHL  
tPLH,tPHL  
tPLH,tPHL  
tPHL  
Figure 1  
Figure 2  
Figure 6  
Figure 4  
Figure 4  
ns  
ns  
Propagation delay time  
(CK - CARRY , preset-mode)  
Propagation delay time  
(ENT - CARRY)  
ns  
Propagation delay time  
(CLR - Q)  
(Note 1)  
(Note 1)  
ns  
Propagation delay time  
(CLR - CARRY)  
tPHL  
ns  
Maximum clock frequency  
fMAX  
MHz  
pF  
40  
105  
75  
Input capacitance  
CIN  
10  
Note 1: For 74VHC161FT only  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
12  
74VHC161FT,74VHC163FT  
14. Noise Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns)  
Characteristics  
Symbol  
Test Condition  
VCC (V)  
Typ.  
Limit  
Unit  
Quiet output maximum dynamic VOL  
Quiet output minimum dynamic VOL  
Minimum high-level dynamic input voltage  
Maximum low-level dynamic input voltage  
VOLP CL = 50 pF  
VOLV CL = 50 pF  
VIHD CL = 50 pF  
5.0  
5.0  
5.0  
5.0  
0.4  
-0.4  
0.8  
-0.8  
3.5  
1.5  
V
V
V
V
VILD  
CL = 50 pF  
15. Internal Equivalent Circuit  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
13  
74VHC161FT,74VHC163FT  
16. AC Characteristics Test Waveform  
Figure 1 Count Mode  
Figure 4 Clear Mode (74VHC161FT)  
Figure 2 Preset Mode  
Figure 5 Clear Mode (74VHC163FT)  
Figure 3 Count Enable Mode  
Figure 6 Cascade Mode (fix maximum count)  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
14  
74VHC161FT,74VHC163FT  
17. Typical Application  
Parallel Carry N-Bit Counter  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
15  
74VHC161FT,74VHC163FT  
Package Dimensions  
Unit: mm  
Weight: 0.055 g (typ.)  
Package Name(s)  
Nickname: TSSOP16B  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
16  
74VHC161FT,74VHC163FT  
RESTRICTIONS ON PRODUCT USE  
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in this document, and related hardware, software and systems (collectively "Product") without notice.  
This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's  
written permission, reproduction is permissible only if reproduction is without alteration/omission.  
ThoughTOSHIBAworkscontinuallytoimproveProduct'squalityandreliability,Productcanmalfunctionorfail.Customersareresponsible  
for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which  
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage  
to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate  
the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA  
information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the  
precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application  
with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications,  
including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating  
and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample  
application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications.  
TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.  
PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE  
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AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.  
©2016 Toshiba Corporation  
2016-08-18  
Rev.3.0  
17  

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