74VHC164 [FAIRCHILD]
8-Bit Serial-In, Parallel-Out Shift Register; 8位串行输入，并行输出移位寄存器
| 型号： | 74VHC164 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Serial-In, Parallel-Out Shift Register |
| 文件： | 总7页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1993
Revised April 1999
74VHC164
8-Bit Serial-In, Parallel-Out Shift Register
to interface 5V to 3V systems and two supply systems such
as battery backup. This circuit prevents device destruction
due to mismatched supply and input voltages.
General Description
The VHC164 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC164 is a high-speed 8-Bit Serial-In/Paral-
lel-Out Shift Register. Serial data is entered through a 2-
input AND gate synchronous with the LOW-to-HIGH transi-
tion of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs
LOW independent of the clock. An input protection circuit
insures that 0V to 7V can be applied to the input pins with-
out regard to the supply voltage. This device can be used
Features
■ High Speed: fMAX = 175 MHz at VCC = 5V
■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (min)
■ Power down protection provided on all inputs
■ Low noise: VOLP = 0.8V (max)
■ Pin and function compatible with 74HC164
Ordering Code:
Order Number Package Number
Package Description
74VHC164M
74VHC164SJ
74VHC164MTC
74VHC164N
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
A, B
Description
Data Inputs
CP
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
MR
Q0–Q7
© 1999 Fairchild Semiconductor Corporation
DS011636.prf
www.fairchildsemi.com
Functional Description
Function Table
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Operating
Inputs
A
Outputs
MR
B
Q0
Q1–Q7
Mode
Reset (Clear)
Shift
L
H
H
H
H
X
L
X
L
L
L
L
L
H
L–L
Q0–Q6
Q0–Q6
Q0–Q6
Q0–Q6
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the log-
L
H
L
ical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
H
H
H
H = HIGH Voltage Levels
L = LOW Voltage Levels
X = Immaterial
Q = Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
DC Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
−0.5V to +7.0V
−0.5V to + 7.0V
−0.5V to VCC + 0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
2.0V to 5.5V
0V to +5.5V
)
)
)
)
0V to VCC
)
±20 mA
)
−40°C to +85°C
)
±25 mA
)
±75 mA
V
V
CC = 3.3V ± 0.3V
CC = 5.0V ± 0.5V
0 ns/V 100 ns/V
0 ns/V 20 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of circuits outside databook specifications.
260°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
1.50
0.7 V
Max
V
V
V
HIGH Level Input
Voltage
2.0
1.50
IH
V
V
3.0− 5.5 0.7 V
2.0
CC
CC
LOW Level Input
Voltage
0.50
0.50
IL
3.0 − 5.5
0.3 V
0.3 V
CC
CC
HIGH Level Output
Voltage
2.0
3.0
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V
I
= −50 µA
OH
IN
IH
OH
2.9
4.4
V
V
V
or V
IL
4.5
4.4
3.0
2.58
3.94
2.48
3.80
I
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
OL
4.5
V
LOW Level Output
Voltage
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V
IN
OL
IH
3.0
or V
IL
4.5
0.1
0.1
3.0
0.36
0.36
±0.1
0.44
0.44
±1.0
I
I
= 4 mA
= 8 mA
OL
OL
V
4.5
I
I
Input Leakage
Current
0 − 5.5
V
V
= 5.5V or GND
IN
IN
µA
µA
Quiescent Supply
Current
5.5
4.0
40.0
= V or GND
CC
CC
IN
Noise Characteristics
T
= 25°C
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum
5.0
0.5
0.8
0.8
3.5
1.5
V
V
V
V
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
OLP
L
L
L
L
(Note 3)
Dynamic V
OL
V
Quiet Output Minimum
Dynamic V
5.0
5.0
5.0
−0.5
OLV
(Note 3)
OL
V
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
IHD
(Note 3)
V
ILD
(Note 3)
Note 3: Parameter guaranteed by design.
3
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AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
MHz
MHz
ns
Conditions
= 15 pF
Min
80
Typ
125
75
Max
Min
Max
f
Maximum Clock Frequency 3.3 ± 0.3
5.0 ± 0.5
65
45
C
C
C
C
C
C
C
C
C
C
MAX
L
L
L
L
L
L
L
L
L
L
50
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
125
85
175
115
8.4
105
75
t
t
Propagation Delay
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
12.8
16.3
9.0
1.0
1.0
1.0
1.0
1.0
1.0
15.0
18.5
10.5
12.5
15.0
18.5
PLH
PHL
Time (CP–Q )
10.9
5.8
n
ns
7.3
11.0
12.8
16.3
t
t
Propagation Delay
8.3
PLH
PHL
ns
10.8
Time (MR–Q )
n
5.0 ± 0.5
5.2
6.7
4
8.6
10.6
10
1.0
1.0
10.0
12.0
10
C
C
= 15 pF
= 50 pF
L
ns
L
C
C
Input Capacitance
Power Dissipation
Capacitance
pF
V
= Open
IN
CC
76
pF (Note 4)
PD
Note 4: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained from the equation: I (opr.) = C * V * f + I .
CC
CC
PD
CC
IN
AC Operating Requirements
V
T
= 25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Minimum Pulse Width (CP)
Units
(V)
(Note 5)
Typ
Guaranteed Minimum
t
t
t
(L)
(H)
(L)
3.3
5.0
5.0
5.0
5.0
W
W
W
ns
ns
ns
ns
ns
5.0
5.0
5.0
3.3
Minimum Pulse Width (MR)
Minimum Setup Time
Minimum Hold Time
5.0
3.3
5.0
3.3
5.0
3.3
5.0
5.0
4.5
0.0
1.0
2.5
5.0
6.0
4.5
0.0
1.0
2.5
t
t
t
S
H
Minimum Removal Time (MR)
REC
5.0
2.5
2.5
Note 5:
V
is 3.3 ± 0.3V or 5.0 ± 0.5V
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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