TX517IZCQ [TI]
Dual Channel, High-Voltage â Multi-Level Output Fully Integrated Ultrasound Transmitter; 双通道，高电压的????多级输出完全集成的超声发射器
| 型号： | TX517IZCQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Channel, High-Voltage â Multi-Level Output Fully Integrated Ultrasound Transmitter |
| 文件： | 总19页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TX517
www.ti.com
SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
Dual Channel, High-Voltage – Multi-Level Output Fully Integrated Ultrasound Transmitter
Check for Samples: TX517
1
FEATURES
DESCRIPTION
The TX517 is a fully integrated, dual channel, high
voltage Transmitter. It is specifically designed for
demanding medical Ultrasound applications that
require a Multi-level high-voltage pulse pattern. The
output stages are designed to deliver typically ±2.5A
peak output currents, with 200Vpp swings.
•
Output Voltage:
Up to 200Vpp in Differential Mode
–
•
•
Peak Output Current: ±2.5A
Multi-Level Output
–
–
Differential : 17 Levels
Single Ended : 5 Levels
The TX517 is a complete transmitter solution with
low-voltage input logic, level translators, gate drivers
and P-channel and N-Channel MOSFETs for each
channel.
•
•
Integrated:
–
–
–
–
Level Translator
Driver
The TX517 also incorporates a CW output stage.
High Voltage Output Stages
CW output
The TX517 is available in a BGA package that is
Lead-Free (RoHS compliant) and Green. It is
specified for operation from 0°C to 85°C.
TX Output Update Rate
Up to 100MSPS
–
17 Level Pulser Chip:
•
•
Minimal External Components
Small Package: BGA 13x13mm
The chip consists of two 5-level channels to form a
single 17-level transmitter cell when used in
conjunction with a transformer. It is designed to drive
the transducer not only at various output levels, but
also to modulate the width of the output pulses to
obtain the added flexibility of pulse-width-modulation
spectral shaping.
APPLICATIONS
•
•
Medical Ultrasound
High Voltage Signal Generator
VAA
BIAS
HV2n LV2n
HV1n LV1n
HV0n LV0n
HV0A
VDD VEE
VCWn
VCWA
HV2A
HV1A
INP0A
INP1A
INP2A
CWINA
P0
P2
P1
CH_A
P1
P2
N2
N1
Input
Logic,
Level
Channel A
INN0A
INN1A
INN2A
OUTA
Translator
N0
N1
PCLKIN
N2
LV0A
LV2A
LV1A
GNDCWA
EN\
CWINA
PDM\
TX517
CWINB
VCWB
HV2B
HV0B
HV1B
P0
P1
P2
CH_B
INP0B
INP1B
INP2B
P1
P2
N2
N1
Input
Logic,
Level
Channel B
OUTB
INN0B
INN1B
INN2B
CWINB
Translator
N0
N1
N2
LV2B
LV1B
LV0B
GNDCWB
GNDCWA GNDCWB
GND
GNDCW
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TX517
SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION(1)
PACKAGED DEVICES
PACKAGE TYPE
PACKAGE MARKING TRANSPORT MEDIA, QUANTITY
ECO STATUS(2)
TX517IZCQ
BGA-144
TX517 Tray
Pb-Free, Green
(1) NOTE: These Packages conform to Lead-Free and Green Manufacturing Specifications
(2) Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfree
GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1%of total product weight.
N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree.
Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total
product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
DEVICE INFORMATION
BGA-144 PINS
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
HV2B
GND
HV1B
HV0B
VCWB
EN\
VAAB
NC
NC
INP1B
INN1B
INP2B
A
B
C
D
E
F
A
B
C
D
E
F
NC
OUTB
NC
LV1B
LV1B
LV1B
LV1B
LV1B
LV1A
LV1A
LV1A
LV1A
LV1A
LV1B
LV1B
LV1B
LV1B
LV1B
LV1A
LV1A
LV1A
LV1A
LV1A
LV1B
LV1B
LV1B
LV1B
LV1B
LV1A
LV1A
LV1A
LV1A
LV1A
LV1B
LV1B
LV1B
LV1B
LV1B
LV1A
LV1A
LV1A
LV1A
LV1A
LV1B
LV1B
GND
NC
NC
GND
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
GND
VAAC
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VAAD
INN2B
INN0B
INP0B
PCLKIN
GND
CWINB
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
NC
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
NC
LV1B GNDCWB
LV2B
LV1B
LV1A
LV2A
NC
LV1B
LV1B
LV1A
LV1A
VDDB
LV0B
LV0A
VDDA
VDD
G
H
J
G
H
J
CWINA
INP0A
INN0A
INN2A
LV1A GNDCWA
OUTA
NC
LV1A
LV1A
GND
GND
K
L
K
L
HV2A
GND
HV1A
HV0A
VCWA
PDM\
VAAA
BIAS
NC
INP1A
INN1A
INP2A
M
M
1
2
3
4
5
6
7
8
9
10
11
12
2
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Product Folder Link(s): TX517
TX517
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SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
PIN FUNCTIONS
PIN NAME
SUPPLIES
VAAx
DESCRIPTION
Input Logic Supply (+2.5V)
+5V Driver Supply
VDD
VEE
–5V Driver Supply
HV0A, HV0B
LV0A, LV0B
HV2A, HV2B
Positive Supply of Low-voltage FET Output stage; Channel A and B
Negative Supply of Low-voltage FET Output stage; Channel A and B
Positive Supply of Intermediate voltage FET Output stage; this stage includes an internal de-glitcher
circuit.Channel A and B
LV2A, LV2B
Negative Supply of Intermediate voltage FET Output stage; this stage includes an internal de-glitcher
circuit.Channel A and B
HV1A, HV1B
LV1A, LV1B
VCWA, VCWB
GND
Positive Supply of High-voltage FET Output stage; Channel A and B
Negative Supply of High-voltage FET Output stage; Channel A and B
Supply connections for CW FET output stage; Channel A and B
Ground connection; Driver
GNDCWA, GNDCWB
BIAS
Ground connection for CW FET output stage of Channel A and B
Connect to VAA (+2.5V); used for internal biasing; high-impedance input
INPUTS
INP0A, INP0B
Logic input signal for the Low-voltage P-FET stage of channel A and B; Low = ON, High = OFF. Controls
HV0A, HV0B. High impedance input.
INN0A, INN0B
INP2A, INP2B
INN2A, INN2B
INP1A, INP1B
INN1A, INN1B
CWINA
Logic input signal for the Low-voltage N-FET stage of channel A and B; Low = OFF, High = ON. Controls
LV0A, LV0B. High impedance input.
Logic input signal for the Intermediate voltage P-FET stage of channel A and B; Low = ON, High = OFF.
Controls HV2A, HV2B. High impedance input.
Logic input signal for the Intermediate Voltage N-FET stage of channel A and B; Low = OFF, High = ON.
Controls LV2A, LV2B. High impedance input.
Logic input signal for the High-voltage P-FET stage of channel A and B; Low = ON, High = OFF. Controls
HV1A, HV1B. High impedance input.
Logic input signal for the High-voltage N-FET stage of channel A and B; Low = OFF, High = ON. Controls
LV1A, LV1B. High impedance input.
CW gate input signal for A output. An input ‘1’ means that current sinks from OUTA. An input ‘0’ means that
current sources from OUTA. This pin directly accesses the output A CW FET gates.
CWINB
CW gate input signal for B output. An input ‘1’ means that current sinks from OUTB. An input ‘0’ means that
current sources from OUTB. This pin directly accesses the output B CW FET gates.
EN
Logic Input for non-CW path; use the Enable-pin to select between input data being latched or transparent
operation. Low = input data will be retimed by the internal (T&H) at the rate of the applied clock at PCLKIN.
High = use this mode when operating the TX517 without a clock. When High (1) the input data will bypass the
(T&H). This pin is a common control for Channel A and B. High impedance input.
PDM
Power-down control input non-CW path; Low = power-down, High = normal operation. The PDM-pin controls
the voltage translation circuits which draw some quiescent power. This pin is a common control for Channel A
and B. High impedance input.
PCLKIN
Clock input for usage in latch (T&H) mode. When clock signal is high, the (T&H) circuit is in track mode. When
clock signal is low, the (T&H) is in hold mode. This pin is a common clock input for both Channel A and B. High
impedance input.
OUTPUTS
OUTA
Output Channel A
Output Channel B
OUTB
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ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground potential (GND = 0V); over operating free-air temperature (unless otherwise noted)
(1)
VALUE
UNIT
V
High-Voltage, Positive Supply HV1,2 referred to OUTA/B, see also Max. delta voltage
High-Voltage, Positive Supply HV0 referred to OUTA/B, see also Max. delta voltage
High-Voltage VCWA/B supply referred to GNDCWA/B
High-Voltage, Negative Supply LV1,2 referred to OUTA/B, see also Max. delta voltage
High-Voltage, Negative Supply LV0 referred to OUTA/B, see also Max. delta voltage
Max. delta voltage: HV1-LV1 and HV2 – LV2
Max. delta voltage: HV0 – LV0
–0.3 to +80
–0.3 to +6
–0.3 to +16
–40 to +0.3
–6 to +0.3
110
VDS
V
V
V
VDS
V
V
12
V
VDD
VEE
VAA
Driver Supply, positive
-0.3 to +6
–6 to +0.3
–0.3 to +6
–0.3 to +6
–0.3 to +11
260
V
Driver Supply, negative
V
Logic Supply Voltage
V
Logic Inputs (INPx, INNx, EN, PDM, PCLKIN, U)
CW inputs (CWINA, CWINB)
Peak Solder Temperature(2)
Maximum junction temperature, any condition(3)
Maximum junction temperature, continuous operation, long term reliability(4)
Storage temperature range
V
V
°C
°C
°C
°C
V
TJ
150
TJ
125
Tstg
–65 to 150
500
HBM
ESD ratings CDM
MM
750
V
200
V
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
(2) Device complies with JSTD-020D.
(3) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
(4) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
THERMAL INFORMATION
TX517
THERMAL METRIC(1)
UNITS
BGA (144) (ZCQ) PINS
θJA
Junction-to-ambient thermal resistance
28
3.8
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
TA = 25°C
°C/W
11.3
0.2
ψJT
Power
3.57
Rating(2)(3)
(TJ = 125ºC)
W
TA = 85°C
1.47
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) This data was taken with the JEDEC High-K test PCB.
(3) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase and
long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and reliability.
4
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TX517
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SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
2.5
MAX UNIT
VAA
2.38
3.3
5.25
–4.75
5
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD
4.75
5.0
VEE
–5.25
–5.0
1.9
HV0A, HV0B
0
LV0A, LV0B
–5
–1.9
32
0
HV2A, HV2B
0
70
LV2A, LV2B
–30
–11.9
61
0
HV1A, HV1B
>HV0 and >HV2
70
LV1A, LV1B
–30
–20.9 <LV0 and <LV2
VCWA, VCWB
0
11
15
100
VAA
10
Maximum DELTA between HV1 to LV1 and HV2 to LV2
INNx, INPx, EN, PDM, PCLKIN, U
INCWA, INCWB
0
0
5
INNxx, INPxx input sample rate
INNxx, INPXX input unit interval
PCLKIN input frequency
Ambient Temperature, TA
1
100 Msps
10
1
1000
100
85
ns
MHz
°C
0
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ELECTRICAL CHARACTERISTICS
All Specifications at: TA = 0 to 85°C, VAA = 2.5V, VDD = 5V, VEE = –5V, HV0 = 1.9V, LV0= -1.9V, HV2 = 32V, LV2=-11.9V,
HV1 = +61.1V, LV1= -20.9V, VCW =11V, RL=100 Ω to GND for OUTA, RL=100 Ω to GND for OUTB, unless otherwise noted.
The parameter results are applicable to both OUTA and OUTB, and they are measured using Non-Latch Mode unless
otherwise noted.
PARAMETER
HV0/LV0 SIGNAL PATH – DC PERFORMANCE
P-CHANNEL
CONDITIONS
MIN
TYP
MAX
UNITS
TEST LEVEL(1)
Effective resistance, RDSon + Rdiode
HV0 = 2 V, OUTX = –750 mV to –1.25 V
6.5
9.5
13
12%
–1
Ω
A
C
Max output power to Min output power,
load = 100 Ω to 0 V
Effective resistance variation
Output saturation current
Output voltage
RL = 5 Ω to –30 V
–3.1
–1.3
A
V
A
C
1.0
N-CHANNEL
Effective resistance, RDSon + Rdiode
LV0 = –2V, OUTX = 750 mV to 1.25 V
2.5
1.4
5
8.5
5
Ω
A
C
Max output power to Min output power,
Load = 100 Ω to 0 V
Effective Resistance Variation
%
Output saturation current
Output voltage
RL = 5 Ω to +30 V
1.8
3.1
A
V
A
C
–1.2
HV0/LV0 SIGNAL PATH – AC PERFORMANCE
Single-tone output frequency
1
100
Msps
dBc
B
C
2nd Order harmonic distortion (when using
transformer bridge)
f = 5.0 MHz square wave, measured using transformer at
secondary coil with RL = 100 Ω
35
10% to 90% of 0 V to +Vout
Figure 8
tr
Output rise time
Output fall time
Propagation Delay
4.5
1
ns
ns
ns
C
C
B
10% to 90% of 0 V to –Vout
Figure 8
tf
Input 50% to Output 50%
Figure 8
tpr, tpf
30
HV2/LV2 SIGNAL PATH – DC PERFORMANCE
P-CHANNEL
Effective resistance, RDSon + Rdiode
HV2 = 30 V to HV2 = 20 V
4.5
9
12.5
12%
–1.8
Ω
A
C
Max output power to Min output power,
load = 100 Ω to 0 V
Effective resistance variation
Output saturation current
Output voltage
HV2 = 60 V; RL = 5 Ω to GND
–4.1
–2.3
A
V
A
C
28.5
N-CHANNEL
Effective resistance, RDSon + Rdiode
LV2 = –10 V to LV2 = –12 V
1.5
2.4
4.5
7.5
4%
5.0
Ω
A
C
Max output power to Min output power,
load = 100 Ω to 0 V
Effective resistance variation
Output saturation current
Output Voltage
LV2 = –60 V; RL = 5 Ω to GND
3.0
A
V
A
C
–10.5
HV2/LV2 SIGNAL PATH – AC PERFORMANCE
Single-tone Output Frequency
1
100
Msps
dBc
B
C
2nd Order harmonic distortion when using
transformer bridge
f = 5.0 MHz square wave, measured using transformer at
secondary coil with RL = 100 Ω
50
10% to 90% of 0 V to +Vout
Figure 8
tr
Output rise time
Output fall time
Propagation delay
7.5
3
ns
ns
ns
C
C
B
10% to 90% of 0 V to –Vout
Figure 8
tf
Input 50% to Output 50%
Figure 8
tpr, tpf
25
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS
All Specifications at: TA = 0 to 85°C, VAA = 2.5V, VDD = 5V, VEE = –5V, HV0 = 1.9V, LV0 = –1.9V, HV2 = 32V, LV2
= –11.9V, HV1 = +61.1V, LV1 = –20.9V, VCW = 11V, RL= 100Ω to GND for OUTA, RL= 100Ω to GND for OUTB, unless
otherwise noted. The parameter results are applicable to both OUTA and OUTB, and they are measured using Non-Latch
Mode unless otherwise noted.
PARAMETER
HV1/LV1 SIGNAL PATH – DC PERFORMANCE
P-CHANNEL
CONDITIONS
MIN
TYP
MAX UNITS
TEST LEVEL(1)
Effective resistance, RDSon + Rdiode
HV1 = 60 V to HV1 = 50 V
2.5
7
12.5
11%
–2
Ω
A
C
Max output power to Min output power
load = 100 Ω to GND
Effective resistance variation
Output saturation current
Output voltage
HV1 = 60 V; RL = 5 Ω to GND
–4.1
–2.5
A
V
A
C
58
N-CHANNEL
Effective resistance, RDSon + Rdiode
LV1 = –20 V to –10 V
1
2
4.5
3%
4.1
Ω
A
C
Max output power to Min output power
load = 100 Ω to 0 V
Effective resistance variation
Output saturation current
Output voltage
LV1 = –60 V; RL = 5 Ω to GND
2.9
3.4
A
V
A
C
–20
HV1/LV1 SIGNAL PATH – AC PERFORMANCE
Single-tone output frequency
1
100
Msps
dBc
B
C
2nd Order harmonic distortion (when using
transformer bridge)
f = 5.0 MHz square wave, measured using transformer at
secondary coil with RL = 100 Ω
60
10% to 90% of 0 V to +Vout
Figure 8
tr
Output rise time
Output fall time
Propagation Delay
6.5
3
ns
ns
ns
C
C
B
10% to 90% of 0 V to –Vout
Figure 8
tf
Input 50% to Output 50%
Figure 8
tpr, tpf
25
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
ELECTRICAL CHARACTERISTICS
All Specifications at: TA = 0 to 85°C, VAA = 2.5V, VDD = 5V, VEE = –5V, HV0 = 1.9V, LV0 = –1.9V, HV2 = 32V, LV2
= –11.9V, HV1 = +61.1V, LV1 = –20.9V, VCW = 11V, RL= 100 Ω to GND for OUTA, RL= 100Ω to GND for OUTB, unless
otherwise noted. The parameter results are applicable to both OUTA and OUTB, and they are measured using Non-Latch
Mode unless otherwise noted.
PARAMETER
CW SIGNAL PATH – DC PERFORMANCE
P-CHANNEL
CONDITIONS
MIN
TYP
MAX
UNITS
TEST LEVEL(1)
Effective resistance, RDSon + Rdiode
VCW = 4.5 Vto 5.5 V
9
21
31
30%
Ω
A
C
Max output power to Min output power,
load = 100 Ω to 0 V
Effective resistance variation
Output saturation current
Output voltage
RL = 5 Ω to –20 V
–0.16
–0.12
–0.06
A
V
A
C
8
N-CHANNEL
Effective resistance, RDSon + Rdiode
OUTX = 1 V to 2 V
9
14
18
10%
0.44
Ω
A
C
Max output power to Min output power,
load = 100 Ω to 0 V
Effective resistance variation
Output saturation current
Output voltage
RL = 5 Ω to 20 V
0.29
0.35
30
A
A
C
mV
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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ELECTRICAL CHARACTERISTICS (continued)
All Specifications at: TA = 0 to 85°C, VAA = 2.5V, VDD = 5V, VEE = –5V, HV0 = 1.9V, LV0 = –1.9V, HV2 = 32V, LV2
= –11.9V, HV1 = +61.1V, LV1 = –20.9V, VCW = 11V, RL= 100 Ω to GND for OUTA, RL= 100Ω to GND for OUTB, unless
otherwise noted. The parameter results are applicable to both OUTA and OUTB, and they are measured using Non-Latch
Mode unless otherwise noted.
PARAMETER
CW SIGNAL PATH – AC PERFORMANCE(2)
Single-tone output frequency
CONDITIONS
MIN
TYP
MAX
UNITS
TEST LEVEL(1)
0.5
10
MHz
dBc
B
C
f = 1MHz, measured using transformer at secondary coil with
47
33
RL = 100 Ω
2nd Order harmonic distortion
f = 5 MHz, measured using transformer at secondary coil with
dBc
C
RL = 100 Ω
Slew Rate + (Positive Edge)
0.6
V/ns
V/ns
C
C
20% to 80% of Voutpp, measured using transformer at
secondary coil with RL = 100 Ω
Slew Rate – (Negative Edge)
0.45
10% to 90% of 0 V to +Vout
Figure 8
tr
tf
Output rise time
Output fall time
30
10
25
20
ns
ns
ns
µs
C
C
B
C
10% to 90% of 0 V to –Vout
Figure 8
Input 50% to Output 50%
Figure 8
tpr, tpf Propagation Delay
AC-coupled gate drive time constant for
P-CHANNEL
CW INPUT CHARACTERISTIC
High input voltage
10
30
1.05
V
V
B
B
B
B
Low input voltage
0.35
1
Low input current
CWINX=0V
0
µA
µA
High input current
CWINX=5.0V
25
40
CWINX = 0 V to 5.0 V or
5.0 V to 0 V
Input Gate Charge
550
pC
C
LOGIC CHARACTERISTICS – INNXX, INPXX, EN\, PDM\, PCLKIN pins
INNxx, INPxx, PCLKIN @ 10 MHz
EN\ @ 10 MHz
6
9
4
Input capacitance
pF
C
PDM\ @ 10 MHz
Logic high input voltage
Logic low input voltage
Logic low input current
Logic high input current
Minimum clock period, tper
Minimum clock high time, tmin
Setup time
VAA=2.375V to 3.6V
VAA=2.375V to 3.6V
0.55*VAA
0
VAA
0.8
10
V
V
B
B
B
B
B
B
B
B
0.2
0.2
µA
µA
ns
ns
ns
ns
10
Figure 9, PCLKIN
10
2.0
0
Figure 9, PCLKIN
ts
th
Figure 9, PCLKIN, INNxx, INPxx
Figure 9, PCLKIN, INNxx, INPxx
Hold time
1.5
OUTPUT CHARACTERISTIC
Output resistance
Power Down Mode (Hi-Z Output) VTEST = 20 V
1
165
GΩ
pF
C
C
A
Power Down Mode (Hi-Z Output)
@1 to 100 MHZ
Output capacitance
Leakage current
Power Down Mode (Hi-Z Output) VTEST = 0V
0.001
10
µA
INTERNAL GATE CHARGE CHARACTERISTICS
HV0/LV0 internal FET gates driven from VEE to VDD or VDD
to VEE
3.5
4.6
7
nC
nC
nC
C
C
C
HV1/LV1 internal FET gates driven from VEE to VDD or VDD
to VEE
Input gate charge(3)
HV2/LV2 internal FET gates driven rom VEE to VDD or VDD to
VEE
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(2) TX517 CW outputs are complimentary. Thus a transformer is needed to enable CW output.
(3) Input gate charge is the amount of charge to change the internal FET gates of a given output from either a low to a high state or from a
high to a low state. Each gate charge value applies to both the P and N type FET for the given output. These values can be used to
estimate the amount of dynamic current that needs to be provided to the VDD and VEE power supplies in order to switch the internal
FET’s at a given sampling rate.
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ELECTRICAL CHARACTERISTICS
All Specifications at: TA = 0 to 85°C, VAA = 2.5V, VDD = 5V, VEE = –5V, HV0 = 1.9V, LV0 = –1.9V, HV2 = 32V, LV2
= –11.9V, HV1 = +61.1V, LV1 = –20.9V, VCW = 11V, RL= 100Ω to GND for OUTA, RL= 100 Ω to GND for OUTB, unless
otherwise noted. The parameter results are applicable to both OUTA and OUTB, and they are measured using Non-Latch
Mode unless otherwise noted.
TEST
PARAMETER
POWER SUPPLY
CONDITIONS
MIN
TYP MAX UNITS
LEVEL(1)
Total Quiescent Current (PW Mode) Power
supply VDD
INPxx = 1, INNxx = 0, PCLKIN= 0 or 1
INPxx = 1, INNxx = 0, PCLKIN= 0 or 1
13
–8
–2
15
mA
mA
mA
A
A
A
Total Quiescent Current (PW Mode) Power
supply VEE
–10
–3
Total Quiescent Current (PW Mode) Power
supply VAA
INPxx = 1, INNxx = 0, PCLKIN= 0 or 1
Input pattern = 10 cycle square wave, 5%
HV0/LV0
HV1/LV1
HV2/LV2
HV0/LV0
HV1/LV1
HV2/LV2
HV0/LV0
HV1/LV1
HV2/LV2
17
18
23
23
23
Dynamic Current Consumption (PW Mode) duty cycle at 10 Msps (5 MHz) on noted
Power supply VDD
mA
mA
mA
B
B
B
signal path. Load = transformer and 100
ohm differential load, see Figure 10.
20.5
–10
–15
Input pattern = 10 cycle square wave, 5%
Dynamic Current Consumption (PW Mode) duty cycle at 10 Msps (5 MHz) on noted
Power supply VEE
–15 –10.5
–15 –12.5
signal path. Load = transformer and 100
ohm differential load, see Figure 10.
–4
–4
–4
–2.3
–2.5
–2.5
Input pattern = 10 cycle square wave, 5%
Dynamic Current Consumption (PW Mode) duty cycle at 10 Msps (5 MHz) on noted
Power supply VAA
signal path. Load = transformer and 100
ohm differential load, see Figure 10.
Input pattern = 10 cycle square wave, 5% duty cycle at 10 Msps
(5 MHz) on noted signal path. Load = transformer and 100 ohm
differential load, see Figure 10.
Dynamic Current Consumption (PW Mode)
Power supply HV0
2
–2
4
60
60
mA
mA
mA
mA
mA
mA
B
B
B
B
B
B
Input pattern = 10 cycle square wave, 5% duty cycle at 10 Msps
(5 MHz) on noted signal path. Load = transformer and 100 ohm
differential load, see Figure 10.
Dynamic Current Consumption (PW Mode)
Power supply LV0
–3.5
–55
–35
Input pattern = 10 cycle square wave, 5% duty cycle at 10 Msps
(5 MHz) on noted signal path. Load = transformer and 100 ohm
differential load, see Figure 10.
Dynamic Current Consumption (PW Mode)
Power supply HV1
41
Input pattern = 10 cycle square wave, 5% duty cycle at 10 Msps
(5 MHz) on noted signal path. Load = transformer and 100 ohm
differential load, see Figure 10.
Dynamic Current Consumption (PW Mode)
Power supply LV1
–41
22
Input pattern = 10 cycle square wave, 5% duty cycle at 10
Msps(5 MHz) on noted signal path. Load = transformer and 100
ohm differential load, see Figure 10.
Dynamic Current Consumption (PW Mode)
Power supply HV2
Input pattern = 10 cycle square wave, 5% duty cycle at 10 Msps
(5 MHz) on noted signal path. Load = transformer and 100 ohm
differential load, see Figure 10.
Dynamic Current Consumption (PW Mode)
Power supply LV2
–22
HV0/LV0
HV1/LV1
HV2/LV2
0.15
1.1
0.25
1.7
Input pattern = 10 cycle square wave, 5%
duty cycle at 10 Msps on noted signal
path. Load = transformer and 100 ohm
differential load, see Figure 10.
Total Power Dissipation for device only
(PW Mode)
W
B
B
0.6
0.8
Input pattern = 10 cycle square wave, 100% duty cycle at 10
Dynamic Current Consumption (CW Mode) Msps on CW signal path. Load = transformer and 100 ohm
62
100
mA
Power supply VCWA + VCWB
differential load, see Figure 10.
EN\ = 0 or 1, PCLKIN = 0 or 1
Input pattern = 10 cycle square wave, 100% duty cycle at 10
Msps (5 MHz) on noted signal path. Load = transformer and
100 ohm differential load, see Figure 10.
Total Power Dissipation for device only
(CW Mode)
310
400
10
mW
B
B
EN\ = 0 or 1, PCLKIN = 0 or 1
Supply (HVx, LVx) Slew Rate Limit
V/ms
POWER-DOWN CHARACTERISTIC
Power Down Mode (Hi-Z Output)
PDM\ = 0, INPxx = 1, INNxx = 0
PCLKIN = 0 or 1
Power-Down Dissipation
3
15
mW
A
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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ELECTRICAL CHARACTERISTICS (any level to any level transitions – 17 level output, 289
unique transitions(1))
All Specifications at: TA = 0°C to 85°C, VAA = 2.5V, VDD = 5V, VEE = –5V, HV0 = 1.9V, LV0= -1.9V, HV2 = 32V, LV2
= –11.9V, HV1 = +61.1V, LV1 = –20.9V, VCW = 11V, RL= 100 Ω to GND for OUTA, RL=100Ω to GND for OUTB, unless
otherwise noted.
TEST
PARAMETER
POWER UP/DOWN TIMING
CONDITIONS
MIN
TYP
MAX UNITS
LEVEL(2)
Power down time
100
100
ns
ns
C
C
Power up time
HVX/LVX SIGNAL PATH – AC PERFORMANCE
Mean normalized output rise time
Mean delay (relative to clock edge of 1st sample)
Delay standard deviation
10% to 90% of 0 to 1, 20MHz
5
23
ns
ns
C
C
C
C
C
C
C
0-20 MHz
0-20 MHz
5 MHz
1.2
0.01
0.03
4
ns
cycles
cycles
%
Phase standard deviation
Gain standard deviation
20 MHz
5 MHz
20 MHz
8
%
(1) These parameters are measured on the differential output starting from 1 of 17 possible states to every other possible state. Therefore,
17X17 = 289 unique transitions.
(2) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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TYPICAL CHARACTERISTICS
All Specifications at: TA = 25°C, VAA = +2.5V, VDD = +5V. VEE = –5V, HV0 = 1.9V, LV0 = –1.9V, HV2 = 32V, LV2 = –11.9V,
HV1 = +61.1V, LV1 = –20.9V, VCW = 11V, RL = 100Ω to GND for OUTA, RL = 100Ω to GND for OUTB, unless otherwise
noted.
90
70
50
CHA-CHB
CHB
30
CHA
10
-10
-30
-50
-70
-90
0
0.05
0.1
0.15
0.2
0.25
0.3
t - Time - ms
Figure 1. 17-level Outputs with 10ns Pulse Width (100MSPS)
90
70
CHA-CHB
50
CHB
30
CHA
10
-10
-30
-50
-70
-90
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
t - Time - ms
Figure 2. 17-level Outputs with 20ns Pulse Width (50MSPS)
90
CHA
CHA-CHB
70
CHB
50
30
10
-10
-30
-50
-70
-90
-0.5
0
0.5
1
1.5
2
2.5
3
t - Time - ms
Figure 3. 5MHz 3-level 10 Cycles Outputs
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TYPICAL CHARACTERISTICS (continued)
All Specifications at: TA = 25°C, VAA = +2.5V, VDD = +5V. VEE = –5V, HV0 = 1.9V, LV0 = –1.9V, HV2 = 32V, LV2 = –11.9V,
HV1 = +61.1V, LV1 = –20.9V, VCW = 11V, RL = 100Ω to GND for OUTA, RL = 100Ω to GND for OUTB, unless otherwise
noted.
90
CHA-CHB
70
CHB
50
CHA
30
10
-10
-30
-50
-70
-90
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
t - Time - ms
Figure 4. 3-level Outputs with 100ns Pulse Width (10MSPS)
90
CHA-CHB
70
50
CHB
30
10
-10
-30
-50
-70
-90
CHA
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
t - Time - ms
Figure 5. 5MHz 5-level Outputs
10
8
CHB
CHA-CHB
CHA
6
4
2
0
-2
-4
-6
-8
-10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
t - Time - ms
Figure 6. 2MHz CW Outputs
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SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
APPLICATION INFORMATION
Table 1. Truth Table
Description
Power Down (Hi-Z Output)
CW Mode
EN
1
PDM
PCLKIN
x(2)
CWINA CWINB INPxx(1)
INNxx(1)
0
0
1
1
0
0/1
0
0
1/0
0
1
0
x
x
1
0
Non-Latch Mode
Latch Mode
1
x
0/1
0/1
0/1
0/1
0
0/1
0
0
(1) The logic device driving the inputs of the TX517 should include means to prevent a ’shoot-thru’ fault condition. Any input combination
that would result in an INP-input to be Low (0) and an INN-input to be High (1) at the same time on the same output (OUTA or OUTB)
could result in permanent damage to the TX517. See also disallowed logic state table. Table 3 is provided for an example of how to
properly drive the TX517 data inputs INPxx and INNxx.
(2) X = don’t care state. However, in order to prevent excessive power consumption it is recommended that all unused inputs be tied off to
a logic high or logic low. The logic inputs to the device have no internal tie-off’s.
Table 2. Disallowed Logic States
Description
EN
x
PDM
PCLKIN
CWINA
CWINB
INPxA
INNxA
INPxB
INNxB
Disallowed mode 1(1)
Disallowed mode 2(1)
Disallowed mode 3(2)
Disallowed mode 4(2)
Disallowed mode 5(2)
Disallowed mode 6(2)
Disallowed mode 7(3)
x
x
0
0
0
0
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
0
x
x
1
x
1
x
x
x
x
x
0
x
x
x
0
x
x
1
x
1
x
x
x
x
x
x
x
x
0
(1) This logic state causes a ’shoot-thru’ fault condition that could result in permanent damage to the TX517.
(2) This logic state causes a high power consumption condition in the internal logic circuitry of the TX517 and could result in a long term
reliability failure of the TX517.
(3) This disallowed logic state is only valid for DC conditions. i.e. it is not allowed to keep PCLKIN at a low logic state when EN\ is at a low
logic state. This causes a high power consumption condition in the internal logic circuitry of the TX517. However, it is acceptable to drive
EN\ low and drive PCLKIN with a clock waveform under the recommended operating conditions for PCLKIN.
Table 3. Example Input Data Set of a 17-Level Output(1)
Output
Level
INP0A
INP2A
INP1A
INP1B
INP2B
INP0B
INN0A
INN2A
INN1A
INN1B
INN2B
INN0B
8
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
off state
(1) The levels listed in this table are active high; the P signals need to be inverted before driving the chip. This note is only applicable to
THIS particular table (“the example input data set of a 17-level output).
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Table 4. Power Supplies Sequence
1
2
3
4
Power-up
Driver Supplies(VEE, VAA, VDD)
VCW, HV2, HV0, LV0, LV2
LV1
HV1
HV1
LV1
LV2, LV0, HV0, HV2, VCW
Power-down
Driver Supplies (VDD, VAA, VEE)
+
VS3 5
VS5 1.9
VS9 32
C2 1μ
+
+
VS10 61.1
+
C1 1μ
+
C5 1μ
VS1 2.5
C3 1μ
C4 1μ
BIAS VAA
VDD
HV0A/B
HV2A/B HV1A/B
INP0A
INP1A
INP2A
INN0A
INN1A
INN2A
Logic Inputs
Channel A
D1
D2
Clock Input
PCLKIN
EN\
OUTA
M1
N2
Enable Input
Power - down Mode Input
CWINB
C11 100pF
PDM\
TX517
N1
CWINB
R1 100Ω
OUTB
CWINA
CWINA
INP0B
INP1B
INP2B
INN0B
INN1B
INN2B
Logic Inputs
Channel B
GND
VEE
GNDCWA/B LV0A/B LV2A/B
LV1A/B
VCWA/B
C7 1μ
C8 1μ
C10 1μ
C9 1μ
C6 1μ
L2 1m
+
VS8 –20.9
VS2 –5
VS6 –1.9 VS7 –11.9
VS11 11
A. Diodes D1, D2 placeholders only; choose appropriate model (e.g. MMBD3004S)
B. Load resistor R1, and capacitor C11 usage and values may vary depending on final configuration
C. Bypass capacitors and values on all supplies are placeholders only. Capacitors between various supply rails may also
be necessary.
D. Inductors (ferrite beads) L1, L2 are optional components
E. Voltages levels on the voltage supplies correspond to the ones used at simulation
Figure 7. Typical Device Configuration
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SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
BLOCK DIAGRAM
VAA
BIAS
HV2n LV2n
HV0n LV0n
HV1n LV1n
VDD VEE
VCWn
VCWA
HV2A
HV0A
HV1A
CWINA
INP0A
INP1A
INP2A
P0
P2
P1
CH_A
P1
P2
N2
N1
Input
Logic,
Level
Channel A
INN0A
INN1A
INN2A
OUTA
Translator
N0
N1
PCLKIN
N2
LV0A
LV2A
LV1A
GNDCWA
EN\
CWINA
PDM\
TX517
CWINB
VCWB
HV2B
HV0B
HV1B
P0
P1
P2
CH_B
INP0B
INP1B
INP2B
P1
P2
N2
N1
Input
Logic,
Level
Channel B
OUTB
INN0B
INN1B
INN2B
CWINB
Translator
N0
N1
N2
LV2B
LV1B
LV0B
GNDCWB
GNDCWA GNDCWB
GND
GNDCW
TIMING RELATED INFORMATION
tpf
tpr
90%
INNxx or
INPxx
50%
tf
10%
OUTA –
OUTB
10%
tr
50%
50%
OUTA –
OUTB
90%
Figure 8. Output Timing Information
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INNxx
INPxx
th
ts
tmin
PCLKIN
50%
50%
tper
Figure 9. Timing Waveform for Latch Mode
TX517
OUTA
R=100
ohm
INXXX
NOTE A
OUTB
Note A: This signal is supplied by a function generator with the following characteristics: 0 to 2.5V square wave,
tr/tf < 3ns, frequency as noted in the electrical characteristics.
Figure 10. Loading for Power Consumption Tests
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SLOS725A –SEPTEMBER 2011–REVISED JANUARY 2012
REVISION HISTORY
Changes from Original (September 2011) to Revision A
Page
•
•
Fixed duty cycle typo, changed duty cycle from 5% to 100% for "Dynamic Current Consumption (CW Mode) Power
supply VCWA + VCWB" in the ELECTRICAL CHARACTERISTICS table. ......................................................................... 9
Fixed duty cycle typo, changed duty cycle from 5% to 100% for "Total Power Dissipation for device only (CW
Mode)" in the ELECTRICAL CHARACTERISTICS table. .................................................................................................... 9
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TX517IZCQ
ACTIVE
NFBGA
ZCQ
144
160
Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
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