TPS7A3501DRVR [TI]
具有使能功能的 1A、低噪声、可调节低压降稳压器 | DRV | 6 | -40 to 125;型号: | TPS7A3501DRVR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有使能功能的 1A、低噪声、可调节低压降稳压器 | DRV | 6 | -40 to 125 光电二极管 稳压器 |
文件: | 总30页 (文件大小:1893K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS7A3501
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
TPS7A3501 高 PSRR、低噪声、1A 电源滤波器
1 特性
2 应用
1
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稳定输入到输出电压:
•
•
•
•
•
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•
后置 DC/DC 转换器纹波滤除
基站和电信基础设施
专业音频
–
用户可编程输入至输出电压稳压范围:
200mV 至 500mV
•
电源抑制比:
通信
–
–
在 1MHz 时为 42dB
成像
≥ 32dB(360kHz 至 3.9MHz)
测试和测量
•
低噪声输出:
3.8μVRMS(10Hz 至 100kHz)
无源滤波器替代产品
–
3 说明
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输出电流:高达 1A
TPS7A3501 是一款正电压、低噪声
输出电压范围:1.21V 至 4.5V
出色的负载瞬态响应
(3.8µVRMS) 电源滤波器,可为 1A 负载供电,非常适合
无噪声电源解决方案。 诸如 TPS7A3501 的功率滤波
器在输入和输出引脚上提供高效电压稳压(低插入损
耗),以及电源抑制。 该器件非常适合用作最大电流
为 1A、电压为 3.3V、2.5V 和 1.8V 的电源噪声滤波
器。
陶瓷电容低至
10µF 也可保持稳定
•
•
•
电流限制和热关断故障保护
采用低热阻封装:2mm × 2mm WSON-6
工作温度范围:
–40°C 至 125°C
借助单独的外部电阻,用户可在 200mV 至 500mV 范
围内编程输入至输出稳压值。 如果未使用电阻
器,TPS7A3501 提供 330mV 的输入至输出电压稳
压。 此器件与 10µF 输入和输出陶瓷电容器和一个
10nF 减噪陶瓷电容器一同工作时保持稳定。
TPS7A3501 的额定工作温度范围为 –40°C 至
125°C。 该器件采用低热阻 2mm × 2mm WSON-6
封装。 与无源滤波器不同,TPS7A3501 为自身和周围
电路提供了过温保护和电流保护。
器件信息(1)
器件型号
TPS7A3501
封装
WSON (6)
封装尺寸(标称值)
2.00mm x 2.00mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
典型应用电路
(VIN – VOUT) = 300 mV
VIN = 3.6 V
VOUT = 3.3 V
–
+
IN
OUT
COUT = 10 µF
CIN = 10 µF
TPS7A3501
Load
EN
NR
SENSE
GND
RNR
CNR = 1 µF
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBVS228
TPS7A3501
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
8
9
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
8.3 Do's and Don'ts....................................................... 18
Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
10.3 Power Dissipation ................................................. 19
10.4 Estimating Junction Temperature ......................... 20
11 器件和文档支持 ..................................................... 21
11.1 器件支持................................................................ 21
11.2 文档支持 ............................................................... 21
11.3 商标....................................................................... 21
11.4 静电放电警告......................................................... 21
11.5 术语表 ................................................................... 21
12 机械封装和可订购信息 .......................................... 21
7
4 修订历史记录
Changes from Revision A (October 2013) to Revision B
Page
•
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ................... 5
Changed Figure 14 to Figure 18: collected new data ............................................................................................................ 8
Changes from Original (July 2013) to Revision A
Page
•
已添加 ESD 额定值表,特性描述部分,器件功能模式,应用和实施部分,电源相关建议部分,布局部分,器件和文档
支持部分以及机械、封装和可订购信息部分 ........................................................................................................................... 1
已更改 文档状态至量产数据.................................................................................................................................................... 1
已更改 文档标题...................................................................................................................................................................... 1
已删除 第一个特性着重号的第二个子着重号 .......................................................................................................................... 1
已更改 电源抑制比内的子着重号和低噪声输出特性着重号..................................................................................................... 1
已更改 输出电流,瞬态响应,陶瓷电容器,和封装特性着重号.............................................................................................. 1
已删除 输入电压范围特性着重号 ............................................................................................................................................ 1
已添加 输出电压范围特性着重号 ............................................................................................................................................ 1
已添加 第 4 个至第 7 个应用着重号........................................................................................................................................ 1
已更改 说明部分的第 1 段和第 3 段........................................................................................................................................ 1
已更改 说明第二段中的稳压值................................................................................................................................................ 1
已添加 更改为典型应用电路.................................................................................................................................................... 1
Changed descriptions of IN, NR, OUT, and PowerPAD pins in Pin Functions table ............................................................. 4
Added PowerPAD row to Pin Functions table........................................................................................................................ 4
Changed associated pins of Voltage parameter in Absolute Maximum Ratings table........................................................... 5
Changed TJ Temperature range parameter minimum specification in Absolute Maximum Ratings table............................. 5
Changed conditions of Electrical Characteristics table .......................................................................................................... 6
Changed VIN and VOUT parameter maximum specifications in Electrical Characteristics table.............................................. 6
Added VUVLO(in) parameter to Electrical Characteristics table................................................................................................. 6
Changed VIN – VOUT voltage range, Vn, and Tsd parameters in Electrical Characteristics table............................................. 6
Changed ICL and IEN parameter specifications in Electrical Characteristics table .................................................................. 6
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•
•
•
•
•
•
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•
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•
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•
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2
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7A3501
www.ti.com.cn
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
•
•
•
•
•
•
•
Changed IGND parameter typical specification in Electrical Characteristics table................................................................... 6
Changed ISHDN test conditions and parameter specifications in Electrical Characteristics table............................................ 6
Changed VEN(HI) parameter minimum specification in Electrical Characteristics table ........................................................... 6
Changed Typical Characteristics section ............................................................................................................................... 7
Added Functional Block Diagram ......................................................................................................................................... 11
Changed Application Information section............................................................................................................................. 15
Changed Board Layout Recommendations section ............................................................................................................. 19
Copyright © 2013–2015, Texas Instruments Incorporated
3
TPS7A3501
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
www.ti.com.cn
5 Pin Configuration and Functions
DRV Package
6-Pin WSON
Top View
IN
1
6
5
4
OUT
SENSE
NR
EN
2
3
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
2
Enable pin. Driving EN high turns on the device (if driven low, EN turns off the device).
EN must not be left floating and can be connected to IN if not used.
EN
I
GND
3
—
Ground
Input supply. A capacitor greater than or equal to 10 µF must be tied from this pin to ground
to assure stability. This configuration is especially important when long input traces or high
source impedances are encountered. TI recommends using X5R- or X7R-type dielectrics to
minimize the temperature variations inherent to capacitors.
IN
1
I
Noise-reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be
reduced to very low levels. A capacitor greater than or equal to 10 nF must be tied from this
pin to ground to assure stability. TI recommends connecting a 1-µF capacitor from NR to
GND (as close to the device as possible) to maximize AC performance and minimize noise.
TI recommends using X5R- or X7R-type dielectrics to minimize the temperature variations
inherent to capacitors. In addition, when a resistor is connected from this pin to GND or IN,
the device input-to-output voltage can be programmed; see Feature Description for details.
NR
4
6
O
O
Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to
ground to assure stability. TI recommends using a X5R- or X7R-type dielectrics to minimize
the temperature variations inherent to capacitors.
OUT
PowerPAD™
SENSE
—
5
—
I
Connect the PowerPAD to the ground plane for improved thermal performance.
Control-loop error amplifier input. This pin must be connected to OUT.
TI recommends connecting SENSE at the point of load to maximize accuracy.
4
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7A3501
www.ti.com.cn
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted).(1)
MIN
–0.3
–0.3
MAX
7
VIN + 0.3(2)
UNIT
IN, NR, EN
Voltage
V
OUT, SENSE
Current
OUT
Internally limited
Operating junction, TJ
Storage, Tstg
–40
–55
125
150
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute maximum rating is VIN + 0.3 V or + 7 V, whichever is smaller.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
1.71
0
NOM
MAX
5
UNIT
V
VIN
IOUT
TJ
Input voltage
Output current
1
A
Operating junction temperature
–40
125
°C
6.4 Thermal Information
DRV (WSON)
6 PINS
66.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
86.5
36.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.8
ψJB
36.6
RθJC(bot)
7.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013–2015, Texas Instruments Incorporated
5
TPS7A3501
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
www.ti.com.cn
6.5 Electrical Characteristics
At TJ = –40°C to 125°C, VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, and CIN = COUT = 10 µF, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
1.71
1.5
TYP
MAX
5
UNIT
V
VIN
Input voltage range
VIN increasing
VIN hysteresis
1.7
V
VUVLO(in)
VOUT
Input supply UVLO
200
mV
V
Output voltage range
1.21
200
4.5
500
mV
VOUT(nom) = VIN – 330 mV, IOUT ≤ 1 A,
1.71 V ≤ VIN ≤ 4.83 V
297
330
363
mV
VIN – VOUT voltage range
(1)
RNR_INTERNAL
110
1.4
170
1.8
10
210
2.4
kΩ
µA
(2)
INR_INTERNAL
∆VOUT(∆IOUT) Load regulation
10 mA ≤ IOUT ≤ 1 A
µV/mA
A
ICL
Output current limit
GND pin current
VOUT = 0.85 × VOUT(nom)
1.1
IGND
2.25
1
5
50
3
mA
nA
IEN
EN pin input current
Shutdown current (IGND
VEN = VIN
ISHUTDOWN
)
VEN ≤ 0.3 V
0.01
55
µA
f = 10 kHz, CNR = 1 µF, IOUT = 0.5 A
PSRR
Vn
Power-supply rejection ratio f = 100 kHz, CNR = 1 µF, IOUT = 0.5 A
f = 1 MHz, CNR = 1 µF, IOUT = 0.5 A
40
dB
42
BW = 10 Hz to 100 kHz, CNR = 1 µF, IOUT = 1 A
3.8
BW = 100 Hz to 100 kHz, CNR = 1 µF,
Output noise voltage
IOUT = 1 A
3.62
12.1
µVRMS
BW = 10 Hz to 1 MHz, CNR = 1 µF, IOUT = 1 A
EN pin input low (disable)
VEN(LO)
VEN(HI)
0.4
V
V
EN pin input high (enable)
1.1
Shutdown, temperature increasing
Shutdown, temperature hysteresis
165
20
Thermal shutdown junction
temperature
Tsd
°C
(1) RNR_INTERNAL refers to the internal resistor used to set (VIN – VOUT) for the device when no external RNR is used. See Adjustable Voltage
Drop and 典型应用电路 for details.
(2) INR_INTERNAL refers to the internal current source used to set (VIN – VOUT) for the device when no external RNR is used. See Adjustable
Voltage Drop and 典型应用电路 for details.
6
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7A3501
www.ti.com.cn
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
6.6 Typical Characteristics
At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless
otherwise noted.
0.345
0.34
0.322
0.321
0.32
-40C
+105C
0C
+125C
+25C
-40C
+105C
0C
+125C
+25C
0.335
0.33
0.319
0.318
0.317
0.316
0.325
0.32
IOUT = 1 A
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
C001
Input Voltage (V)
C002
Input Voltage (V)
Figure 1. Line Regulation
Figure 2. Line Regulation
0.345
0.34
0.6
0.5
0.4
0.3
0.2
0.1
-40C
+105C
0C
+125C
+25C
¨9ꢀ ꢀꢁꢂꢂꢀP9
¨9ꢀ ꢀꢃꢃꢂꢀP9
¨9ꢀ ꢀꢄꢂꢂꢀP9
0.335
0.33
0.325
0.32
IOUT = 100 mA
0.315
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
±40 ±25 ±10
5
20 35 50 65 80 95 110 125
C003
C004
Temperature (C)
Figure 3. Load Regulation
Figure 4. VDELTA vs Temperature
3.25
3
4.5
4
-40C
+105C
0C
+125C
+25C
-40C
+105C
0C
+125C
+25C
2.75
2.5
2.25
2
3.5
3
2.5
2
1.75
1.5
1.5
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
C005
C006
Input Voltage (V)
Figure 5. Ground Current vs Input Voltage
Figure 6. Ground Current vs Output Current
Copyright © 2013–2015, Texas Instruments Incorporated
7
TPS7A3501
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
www.ti.com.cn
Typical Characteristics (continued)
At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless
otherwise noted.
2
1.9
1.8
1.7
1.6
1.5
1000
900
800
700
600
500
400
300
200
100
0
-40C
+105C
0C
+125C
+25C
-40C
+105C
0C
+125C
+25C
VEN = 0 V
VOUT = 90% x VOUT(NOM)
1.8
2.1
2.4
2.7
3
3.3
3.6
1.8
2.1
2.4
2.7
3
3.3
3.6
C008
Input Voltage (V)
C007
Input Voltage (V)
Figure 8. Current Limit vs Input Voltage
Figure 7. Shutdown Current vs Input Voltage
3.5
3
100
90
80
70
60
50
40
30
20
10
0
IOUT= 100 mA
IOUT= 500 mA
IOUT= 1 A
2.5
2
1.5
1
0.5
0
CIN = 1 ꢀF, CNR = 1 µF
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
10
100
1k
10k
100k
1M
10M
C009
C010
Iout (A)
Frequency (Hz)
Figure 9. Foldback Current Limit
Figure 10. Power-Supply Rejection Ratio vs Frequency
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
¨9ꢀ ꢀꢁꢂꢂꢀP9
¨9ꢀ ꢀꢃꢃꢂꢀP9
¨9ꢀ ꢀꢄꢂꢂꢀP9
CNR= 10 nF
CNR= 100 nF
CNR= 1 uF
CIN = 1 ꢀF, Iout = 500 mA
CIN = 1 ꢀF, Iout = 500 mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
C010
C010
Frequency (Hz)
Frequency (Hz)
Figure 11. Power-Supply Rejection Ratio vs Frequency
Figure 12. Power-Supply Rejection Ratio vs Frequency
8
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7A3501
www.ti.com.cn
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
Typical Characteristics (continued)
At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless
otherwise noted.
10
RMS Noise
(BW 100Hz-100kHz)
VIN = 3.6 V, IOUT = 10 mA → 1 A → 10 mA
CIN = COUT = 10 mF, CNR = 10 nF
Cnr
1 uF
ꢀVrms
3.6
Slew Rate = 1 A/ms
1
0.1
100 nF
10 nF
4.2
20.7
IOUT (1 A/div)
V
OUT (50 mV/div)
0.01
0.001
C= 10 nF
NR
C= 100 nF
NR
IOUT = 1 A
C= 1 uF
NR
Time (50 ms/div)
10
100
1k
10k
100k
1M
10M
C010
Frequency (Hz)
Figure 14. Load Transient Response
Figure 13. Spectral Noise Density vs Frequency
VIN = 1.7 V → 4.8 V → 1.7 V, IOUT = 500 mA
VIN = 3.6 V, IOUT = 10 mA → 1 A → 10 mA
CIN = COUT = 10 mF, CNR = 1 mF
Slew Rate = 1 A/ms
CIN = COUT = 10 mF, CNR = 10 mF, Slew Rate = 1 A/ms
VIN (2 V/div)
IOUT (1 A/div)
V
OUT (50 mV/div)
V
OUT (2 V/div)
Time (50 ms/div)
Time (10 ms/div)
Figure 15. Load Transient Response
Figure 16. Line Transient Response
VIN = 1.7 V → 4.8 V → 1.7 V, IOUT = 500 mA
CIN = COUT = 10 mF, CNR = 1 mF, Slew Rate = 1 A/ms
VIN (2 V/div)
VIN (2 V/div)
VIN = VEN = 0 V → 3.6 V
IOUT = 1 A
V
V
OUT (2 V/div)
OUT (2 V/div)
CIN = COUT = 10 mF
CNR = 10 nF
Time (10 ms/div)
Time (1 ms/div)
Figure 17. Line Transient Response
Figure 18. Start-up
Copyright © 2013–2015, Texas Instruments Incorporated
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TPS7A3501
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
www.ti.com.cn
Typical Characteristics (continued)
At VIN = 3.6 V, RNR = ∞ (not connected), IOUT = 10 mA, VEN = VIN, COUT = 10 µF, CIN = 10 µF, and CNR = 0.1 µF, unless
otherwise noted.
VIN = VEN = 0 V → 3.6 V
IOUT = 1 A
VIN (2 V/div)
CIN = COUT = 10 mF
CNR = 1 mF
V
OUT (2 V/div)
Time (1 ms/div)
Figure 19. Start-up
10
Copyright © 2013–2015, Texas Instruments Incorporated
TPS7A3501
www.ti.com.cn
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
7 Detailed Description
7.1 Overview
The TPS7A3501 is a positive-voltage, low-noise (3.8-µVRMS) power filter capable of sourcing a 1-A load. Power
filters such as the TPS7A3501 provide voltage regulation across the input and output terminals with high
accuracy and power-supply rejection ratio. The device is ideally suited as a noise filter for 4.5-V, 3.3-V, and 1.8-V
supplies up to 1-A loads.
The input-to-output voltage drop is also user-programmable, from 200 mV up to 500 mV, with an external
resistor. If no resistor is used, the TPS7A3501 provides 330 mV of input-to-output voltage regulation.
The TPS7A3501 is stable with 10-µF ceramic input and output capacitors and a 10-nF ceramic noise-reduction
capacitor. The device is fully specified over a wide temperature range of –40°C to 125°C and is offered in a low
thermal resistance, 2-mm × 2-mm, 6-pin WSON package.
7.2 Functional Block Diagram
IN
VIN = 3.6 V
CIN = 10 µF
Charge Pump
VEN = 3.6 V
EN
NR
+
–
VOUT = VIN – 300 mV = 3.3 V
OUT
RNR
CNR
1 mF
SENSE
COUT = 10 µF
GND
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7.3 Feature Description
7.3.1 Power Filter Operation
A power filter is very similar to a low-dropout (LDO) regulator, except that instead of regulating output voltage
relative to ground, the power filter regulates output voltage relative to VIN. In other words, a power filter maintains
a fixed ΔV from input to output. The device is optimized for high PSRR with a low VIN-to-VOUT delta, leading to a
lower power dissipation than standard LDOs. Unlike a standard LDO, the bandgap and noise associated with the
device are never gained up, resulting in low output noise regardless of VOUT. The external noise capacitor on the
power filter lets the user set the frequency at which the power filter starts to reject noise from the input. Table 1
summarizes the differences between a power filter and a high-performance LDO.
Table 1. Power Filter vs LDO Characteristics
PARAMETER
POWER FILTER
LDO
Regulates input-to-output delta. Voltage delta can be
Regulates the output voltage referenced to ground.
Voltage regulation
set from 0.2 V to 0.5 V. Relies on the upstream power Outputs any output voltage within the output voltage
rail to set the output voltage. range (limited by power dissipation).
High PSRR at typical switching frequencies of DC-DC High PSRR over broad bandwidth. Effective rejection
converters with lower power dissipation. Lower PSRR of low-frequency noise and switching noise from DC-
PSRR
at low frequencies.
DC.
Lower noise, 3.8 µV. Noise is not gained up when
VOUT increases.
Low noise (typically in the range of 5 µVRMS to
20 µVRMS). Noise is gained up when VOUT increases.
Noise
High PSRR can be achieved with only 330 mV from
Typically requires 750 mV to 1 V of VIN-to-VOUT delta
to achieve high PSRR.
Power dissipation
VIN to VOUT
.
7.3.2 Minimum Load
The device is stable without an output load.
7.3.3 Shutdown
The enable pin (EN) is active high and compatible with standard and low-voltage TTL-CMOS levels. The enable
pin voltage level is independent of input voltage and can be biased to a higher value than VIN as long as EN is
within the maximum specification. When shutdown capability is not required, EN can be connected to IN.
7.3.4 Internal Current Limit
The device has an internal foldback current limit that helps protect the power filter during fault conditions. The
current supplied by the device is gradually reduced when the output voltage decreases. When the output is
shorted to GND, the LDO supplies a typical current of 550 mA. When in current limit, the output voltage is not
regulated and VOUT = IOUT × RLOAD. For reliable operation, do not operate the device in current limit for extended
periods of time.
Because of the nature of the foldback current limit circuitry, if OUT is forced below 0 V before EN goes high, the
device may not start up. To ensure proper start-up in applications that have both a positive and negative voltage
rail, extra care must be taken to ensure that OUT is greater than or equal to 0 V. There are several ways to help
ensure proper start-up for dual-rail applications:
•
•
Enable the device before the negative rail and disable the device after the negative rail.
Delaying the EN voltage with respect to IN voltage allows the internal pulldown resistor to discharge any
residual voltage at OUT.
•
If a faster discharge rate is required, or if EN is tied directly to IN, an external resistor from OUT to GND can
be used.
7.3.5 Reverse Current
The TPS7A3501 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at
IN. This current is not internally limited, so if reverse voltage conditions are anticipated, external limiting is
required.
If there are potential situations where reverse current is expected, place a diode from OUT to IN, as shown in
Figure 20.
12
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TPS7A3501
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ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
VIN
VOUT
IN
OUT
Device
Load
EN
NR
SENSE
GND
Figure 20. Reverse Current Protection Schematic
7.3.6 Undervoltage Lockout (UVLO)
The device uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating
properly, ensuring a well-controlled start-up.
7.3.7 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits device power dissipation, thus protecting the device from damage
resulting from overheating.
Any activation of the thermal protection circuit indicates excessive power dissipation or inadequate thermal
dissipation on the PCB. For reliable operation, limit junction temperature to 125°C (maximum). To estimate the
margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered
using worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C
above the maximum expected ambient condition of the application. This configuration produces a worst-case
junction temperature of 125°C at the highest-expected ambient temperature and worst-case load.
The device internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heat-sinking or thermal dissipation on the PCB. Continuously running the device into
thermal shutdown degrades device reliability.
7.4 Device Functional Modes
Table 2 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 2. Device Functional Mode Comparison
PARAMETER
OPERATING
MODE
VIN
1.71 ≤ VIN ≤ 5
—
EN
IOUT
IOUT < ICL
—
TJ
Normal
VEN > VEN(HI)
VEN < VEN(LO)
TJ < Tsd
TJ > Tsd
Disabled
7.4.1 Normal Operation
The device functions as a fixed voltage drop filter under the following conditions:
•
•
The input voltage is within the specified operating range of 1.71 V to 5 V.
The enable voltage has previously exceeded the enable rising threshold voltage and not yet decreased below
the enable falling threshold.
•
•
The output current is less than the current limit (IOUT < ICL).
The device junction temperature is less than the thermal shutdown temperature (TJ < Tsd).
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13
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7.4.2 Disabled
The device is disabled under the following conditions:
•
The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
•
The device junction temperature is greater than the thermal shutdown temperature (TJ > Tsd).
14
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TPS7A3501
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ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A3501 is well-suited for use as a filter for switching power supplies. The high PSRR of the device
significantly reduces the ripple caused by the switching frequency as well as the subsequent harmonic
frequencies. Figure 21 shows the basic circuit connections for the TPS7A3501. The IN pin should be connected
to a well-regulated power source, typically a switching power supply.
VIN
VOUT
±
+
IN
OUT
Device
Load
Decreases
EN
NR
SENSE
GND
'V
Increases
'V
(1) Refer to Table 4.
Figure 21. Basic Circuit Connections
8.2 Typical Application
Figure 22 shows a schematic for filtering the output of a switching regulator using the TPS7A3501 to power an
analog-to-digital converter (ADC).
PVIN
VIN
TPS54620
BOOT
EN
IN
PH
OUT
CIN
COUT
PWRGD
Device
ADC
VSENSE
GND
EN
NR
SENSE
GND
SS/TR
RT/CLK
COMP
CNR
Exposed
Thermal
Pad
Figure 22. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
Table 3 shows the design requirements.
Table 3. Design Requirements
PARAMETER
DESIGN REQUIREMENT
Input voltage
Output voltage
3.63 V
3.3 V
100-Hz to 100-kHz RMS noise
Maximum output current
< 4 µVRMS
700 mA
8.2.2 Detailed Design Procedure
Select the input and output capacitors to be at least 10 µF for stability. Select a value for RNR to give the desired
voltage drop. For this example of a 330-mV voltage drop, no external resistor on the NR pin is required. Pick a
value for CNR greater than 10 nF, but large enough to provide the required noise performance. Refer to Table 5
for guidelines on selecting CNR for a desired RMS noise target. For this example, to achieve an RMS noise (100
Hz to 100 kHz) less than 4 µVRMS, the noise reduction capacitor must be at least 1 µF.
8.2.2.1 Adjustable Voltage Drop
In the TPS7A3501, the nominal voltage drop (ΔV) from IN to OUT is 330 mV. ΔV can be adjusted from this
nominal setting with an external resistor. By connecting a resistor from the NR pin to IN, ΔV can be decreased to
as low as 200 mV. By connecting a resistor from the NR pin to GND, ΔV can be increased to as high as 500 mV.
The ability to change ΔV allows for the creation of standard voltage rails from higher voltage rails (for example,
2.5 V from 3 V, 1.5 V from 1.8 V, and so forth).
By connecting a resistor from the NR pin to IN, ΔV can be decreased to as low as 200 mV. Use Equation 1 to
determine the size of the resistor required to set ΔV.
R = ΔV / (0.33 – ΔV) × 150,000 Ω
(1)
By connecting a resistor from the NR pin to GND, ΔV can be increased to as high as 500 mV. Use Equation 2 to
determine the size of the resistor required to set ΔV.
R = VOUT / (ΔV – 0.33) × 150,000 Ω
(2)
Table 4 lists the standard external resistor values required for different input-to-output voltage drops.
Table 4. Common Input-to-Output Voltage Drops
ΔV (mV)
200
VOUT
Any
R TO VIN
240 kΩ
R TO GND
Do not install
Do not install
6.8 MΩ
330
Any
Do not install
Do not install
Do not install
Do not install
Do not install
Do not install
Do not install
3.3 V
2.5 V
1.8 V
3.3 V
2.5 V
1.8 V
400
500
5.1 MΩ
3.9 MΩ
3 MΩ
2.2 MΩ
1.6 MΩ
8.2.2.2 Input and Output Capacitor Requirements
Ceramic 10-µF or larger input and output capacitors are required to assure proper device operation. This
capacitor counteracts reactive source impedances, improving supply transient response and decreasing input
ripple. Higher-value capacitors may be used if large, fast slew rate load transients are anticipated, or if the device
is located several inches away from the power source. To assure correct device operation, there should be no
more than 100 µF of capacitance on the output of the device, including capacitance from downstream bypass
capacitors.
16
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TPS7A3501
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TI recommends X5R- and X7R-type ceramic capacitors because these types of capacitors have minimal
variation in value and equivalent series resistance (ESR) overtemperature. Other types of capacitors, such as
electrolytic or tantalum, can make the device unstable.
8.2.2.3 Output Noise
A 10-nF, or higher, noise-reduction capacitor is required to assure stability. Using a 1-μF ceramic capacitor
minimizes output noise (see Figure 13). To assure correct device operation, a maximum capacitor of 2.2 µF can
be connected to NR.
8.2.2.4 Power-Supply Rejection Ratio (PSRR)
Unlike standard LDOs, the TPS7A3501 PSRR is significantly affected by the noise-reduction capacitor. The
larger the noise-reduction capacitor, the higher the PSRR is for frequencies below 10 kHz. Using a 1-μF ceramic
capacitor maximizes PSRR.
One of the most compelling features of the TPS7A3501 is its high PSRR capabilities. The rejection ratio for this
device is lower than standard LDOs at frequencies below 1 kHz but becomes higher at higher frequencies. For
better low-frequency PSRR performance, a larger noise-reduction capacitor can be used. TI recommends
connecting a 1-µF ceramic capacitor to NR to maximize PSRR (see Figure 12). A higher input-to-output voltage
difference also increases the device rejection ratio. Although the device maximizes rejection ratio at 500 mV,
high rejection ratio can still be achieved with as little as a 330-mV input-to-output voltage differential, unlike most
standard LDOs.
8.2.2.5 Start-up
Because adding a noise-reduction capacitor leads to the formation of an RC filter, start-up time and the rate at
which the device tracks VIN are increased. Thus, consider the tradeoff between start-up time, noise, and PSRR
when selecting a noise-reduction capacitor to use with the TPS7A3501. Use Equation 3 to calculate the typical
start-up time.
T_startup = 250,000 × CNR (s)
(3)
Table 5 shows the effect of various noise-reduction capacitors on RMS noise (with a 100-Hz to 100-kHz
bandwidth), PSRR (at 1 kHz), and start-up time.
Table 5. Effect of Various Filter Capacitors
RMS NOISE
PSRR
START-UP TIME
FILTER CAPACITOR
(BW 100 Hz to 100 kHz)
(at 1 kHz)
(EN to 90% of VOUT)
1 µF
100 nF
10 nF
3.62 µV
4.21 µV
20.70 µV
60 dB
40 dB
20 dB
250 ms
25 ms
3 ms
8.2.2.6 Transient Response
Increasing the size of the output capacitor reduces overshoot and undershoot magnitude during transients;
however this size increase also slows the recovery from these transients.
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8.2.3 Application Curves
10
1
100
RMS Noise
(BW 100Hz-100kHz)
¨9ꢀ ꢀꢁꢂꢂꢀP9
¨9ꢀ ꢀꢃꢃꢂꢀP9
¨9ꢀ ꢀꢄꢂꢂꢀP9
90
80
70
60
50
40
30
20
10
0
Cnr
1 uF
ꢀVrms
3.6
100 nF
10 nF
4.2
20.7
0.1
0.01
0.001
C= 10 nF
NR
C= 100 nF
NR
IOUT = 1 A
CIN = 1 ꢀF, Iout = 500 mA
C= 1 uF
NR
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
C010
Frequency (Hz)
C010
Frequency (Hz)
Figure 24. Spectral Noise Density vs Frequency
Figure 23. Power-Supply Rejection Ratio vs Frequency
8.3 Do's and Don'ts
Place at least 10-μF ceramic capacitors on both the IN and OUT pins of the device, as close as possible to the
pins of the regulator.
Do not place the input or output capacitor more than 10 mm away from the regulator.
Connect a 10-nF or greater, low-equivalent series resistance (ESR) capacitor across the NR pin and GND of the
regulator. Larger capacitors provide lower noise performance.
Do not use a capacitor larger than 2.2 µF on the NR pin.
Do not exceed the absolute maximum ratings.
9 Power Supply Recommendations
For best performance, connect a low-output impedance power supply directly to the IN pin of the device.
Inductive impedances between the input supply and the IN pin create significant voltage excursions at the IN pin.
18
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10 Layout
10.1 Layout Guidelines
Input and output capacitors should be placed as close to the device pins as possible. TI recommends that all
components be on the same side of the printed-circuit-board (PCB) as the device. Using long, thin traces or vias
to connect the device to external components is highly discouraged because this practice leads to parasitic
inductances, which in turn degrade noise, PSRR, and transient response. For an example layout, refer to the
TPS7A3501EVM-547 Evaluation Module User Guide ( SLVU921).
10.2 Layout Example
GND PLANE
COUT
CIN
TPS7A3501
VOUT
VIN
1
2
3
IN
EN
6
5
4
OUT
SENSE
NR
GND
GND PLANE
CNR
Figure 25. PCB Layout Example (DRV Package)
10.3 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to avoiding thermal shutdown and ensuring reliable operation. Device power dissipation depends on input
voltage and load conditions and can be calculated with Equation 4:
PD = (VIN – VOUT) × IOUT
(4)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest available voltage
drop option of 200 mV. However, keep in mind that higher voltage drops result in better PSRR performance.
On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad to the
PCB. To ensure the device does not overheat, connect the pad to ground with an appropriate amount of copper
PCB area through vias.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 5:
TJ = TA + (θJA × PD)
(5)
Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability of the particular
PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The θJA recorded in the table is determined by the JEDEC standard for PCB and copper-spreading area and is to
be used only as a relative measure of package thermal performance. For a well-designed thermal layout, θJA is
actually the sum of the package junction-to-case (bottom) thermal resistance (θJCbot) plus the thermal resistance
contribution by the PCB copper.
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19
TPS7A3501
ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
www.ti.com.cn
10.4 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the power filter on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of copper-spreading area. The key thermal metrics (ΨJT and ΨJB)
are given in the table and are used in accordance with Equation 6.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in Equation 4,
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge.
(6)
20
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TPS7A3501
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ZHCSBQ0B –JULY 2013–REVISED MARCH 2015
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
评估模块 (EVM) 可与 TPS7A3501 配套使用,帮助评估初始电路性能。 TPS7A3501EVM-547 评估模块(和相关
的用户指南)可在德州仪器 (TI) 网站上的产品文件夹中获取,也可直接从 TI 网上商店购买。
11.1.1.2 Spice 模型
分析模拟电路和系统的性能时,使用 SPICE 模型对电路性能进行计算机仿真非常有用。 您可以从产品文件夹中的
工具和软件下获取 TPS7A3501 的 SPICE 模型。
11.2 文档支持
11.2.1 相关文档
•
《TPS7A3501EVM-547 用户指南》,SLVU921。
11.3 商标
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 ,
可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2013–2015, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A3501DRVR
TPS7A3501DRVT
ACTIVE
ACTIVE
WSON
WSON
DRV
DRV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
SIQ
SIQ
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A3501DRVR
TPS7A3501DRVT
WSON
WSON
DRV
DRV
6
6
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A3501DRVR
TPS7A3501DRVT
WSON
WSON
DRV
DRV
6
6
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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