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TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

TPS7A39 双路、150mA、宽输入电压正负 LDO 稳压器

1 特性

3 说明

1

•

正负 LDO 包含在一个封装中

TPS7A39 器件是双路、单片、高 PSRR、正负极低压

降 (LDO) 稳压器，支持高达 150mA 的拉电流（和灌

电流）。该器件的稳压输出可在外部独立调节为对称或

不对称电压，因此是进行信号调节的理想型双路双极性

电源。

宽输入电压范围：±3.3V 至 ±33V

宽输出电压范围：

–

正压范围：1.2V 至 30V

负压范围：–30V 至 0V

•

输出电流：每通道 150mA

单调启动跟踪

TPS7A39 的正负两种输出在启动期间相互进行比例跟

踪，从而缓解双轨系统中常见的浮动状况和其他电源定

序问题。负输出可调节至最高 0V，从而扩大单电源放

大器的共模范围。TPS7A39 还具有高 PSRR，因此

消除了可能影响信号完整性的电源噪声，例如开关噪

声。

高电源抑制比 (PSRR)：

–

69dB (120Hz)

≥ 50dB（10Hz 至 2MHz）

•

输出电压噪声：21µV_RMS(10Hz–100kHz)

缓冲 1.2V 基准电压输出

两个稳压器采用与标准数字逻辑对接的单个正逻辑使能

引脚即可进行控制。可通过电容器编程的软启动功能将

控制浪涌电流和启动时间。TPS7A39 的内部基准电压

可用外部基准电压覆盖，从而实现精密输出、获得输出

电压裕量或跟踪其他电源。此外，TPS7A39 具有缓冲

基准输出，此输出可用作系统中其他组件的电压基准。

与 10µF 或更大的输出电容器一起工作时保持稳定

单个正逻辑使能引脚

可调软启动浪涌控制

3mm × 3mm 10 引脚 WSON 封装

低热阻：R_θJA= 44.4°C/W

工作温度范围：–40 至 +125°C

这些特性使得 TPS7A39 成为一种为运算放大器、数

模转换器 (DAC) 以及其他精密模拟电路供电的强大而

简化的解决方案。

2 应用

•

用于运算放大器、ADC、DAC 和其他高精度模拟

电路的电源轨

后级直流/直流调节和滤波

模拟 I/O 模块

测试和测量

器件信息⁽¹⁾

封装

•

器件型号

TPS7A39

封装尺寸（标称值）

WSON (10)

3.00mm x 3.00mm

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Rx、Tx 和 PA 电路

工业仪表

医疗成像

为信号链供电

单调启动跟踪

+5 V

25

+15 V

OUTP

INP

EN

V_INP

V_OUTP

V_OUTN

V_INN

20

15

10

5

Feedback

Network

FBP

NR/SS

V_S+

V_S-

œ

TPS7A39

ADC

BUF

FBN

+

Signal In

0

+15 V

-15 V

EN

-5

-10

-15

-20

-25

INN

OUTN

GND

-5 V

0

20

40

60

80 100 120 140 160 180 200

Time (ms)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBVS263

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Startup Characteristics.............................................. 7

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 19

7.1 Overview ................................................................. 19

7.2 Functional Block Diagram ....................................... 19

7.3 Feature Description................................................. 20

7.4 Device Functional Modes........................................ 24

8

9

Application and Implementation ........................ 25

8.1 Application Information............................................ 25

8.2 Typical Applications ................................................ 34

Power-Supply Recommendations...................... 39

10 Layout................................................................... 39

10.1 Layout Guidelines ................................................. 39

10.2 Layout Example .................................................... 40

10.3 Package Mounting ................................................ 40

11 器件和文档支持 ..................................................... 41

11.1 器件支持................................................................ 41

11.2 文档支持................................................................ 41

11.3 接收文档更新通知 ................................................. 41

11.4 社区资源................................................................ 41

11.5 商标....................................................................... 41

11.6 静电放电警告......................................................... 41

11.7 Glossary................................................................ 41

12 机械、封装和可订购信息....................................... 42

7

4 修订历史记录

Changes from Original (July 2017) to Revision A

Page

•

产品投产 ................................................................................................................................................................................. 1

2

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

5 Pin Configuration and Functions

DSC Package

10-Pin WSON

Top View

INP

EN

1

2

3

4

5

10

9

OUTP

FBP

Thermal Pad

NR/SS

GND

INN

8

BUF

FBN

OUTN

7

6

Not to scale

Pin Functions

NAME

I/O

DESCRIPTION

NO.

Positive input. A 10-μF⁽¹⁾or larger capacitor must be tied from this pin to ground to ensure stability.

Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section

for more information.

1

2

INP

I

Enable pin. Driving this pin to logic high (V_EN≥ V_IH(EN)) enables the device; driving this pin to logic low

(V_EN≤ V_IL(EN)) disables the device. If enable functionality is not required, this pin must be connected to

INP; see the Application and Implementation section for more detail. The enable voltage cannot exceed

the input voltage (V_EN≤ V_INP).

EN

I

Noise-reduction, soft-start pin. Connecting an external capacitor between this pin and ground reduces

reference voltage noise and enables soft-start and start-up tracking. A 10-nF or larger capacitor (C_NR/SS

is recommended to be connected from NR/SS to GND to maximize or optimize ac performance and to

ensure start-up tracking. This pin can also be driven externally to provide greater output voltage

accuracy and lower noise, see the User-Settable Buffered Reference section for more information.

)

3

NR/SS

—

Ground pin. This pin must be connected to ground and the thermal pad with a low-impedance

connection.

Negative input. A 10-μF⁽¹⁾or larger capacitor must be tied from this pin to ground to ensure stability.

Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section

for more information.

4

5

GND

INN

—

I

Negative output. A 10-μF⁽¹⁾or larger capacitor must be tied from this pin to ground to ensure stability.

Place the output capacitor as close to the output as possible; see the Capacitor Recommendations

section for more information.

6

7

8

OUTN

FBN

O

I

Negative output feedback pin. This pin is used to set the negative output voltage. Although not required,

a 10-nF feed-forward capacitor from FBN to OUTN (as close to the device as possible) is recommended

to maximize ac performance. Nominally this pin is regulated to V_FBN. Do not connect to ground.

Buffered reference output. This pin is connected to FBN through R₂and the voltage at this node is

inverted and scaled up by the negative feedback network to provide the desired output voltage. The

buffered reference can be used to drive external circuits, and has a 1-mA maximum load.

BUF

O

Positive output feedback pin. This pin is used to set the positive output voltage. Although not required, a

10-nF feed-forward capacitor from FBP to OUTP (as close to the device as possible) is recommended to

maximize ac performance. Nominally this pin is regulated to V_FBP. Do not connect this pin directly to

ground.

9

FBP

I

Positive output. A 10-μF⁽¹⁾or larger capacitor must be tied from this pin to ground to ensure stability.

Place the output capacitor as close to the output as possible; see the Capacitor Recommendations

section for more information.

10

OUTP

O

Pad

Thermal Pad

—

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

(1) The nominal input and output capacitance must be greater than 2.2 µF; throughout this document the nominal derating on these

capacitors is 80%. Take care to ensure that the effective capacitance at the pin is greater than 2.2 µF.

3

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

MAX

36

UNIT

INP

INN

–36

0.3

OUTP

OUTN

–0.3

V_INN– 0.3⁽⁴⁾

V_INP+ 0.3⁽³⁾

0.3

Voltage

FBP

BUF

NR/SS

FBN

EN

–0.3

V_INP+ 0.3⁽⁵⁾

V_INP+ 0.3⁽⁶⁾

0.3

V

–1

–0.3

V_INN– 0.3⁽⁷⁾

–0.3

V_INP+ 0.3⁽⁸⁾

Internally

limited

Output current

Current

Buffer current

2

mA

°C

Operating junction temperature, T_J

Storage, T_stg

–55

–65

150

Temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages with respect to the ground pin, unless otherwise noted.

(3) The absolute maximum rating is V_INP+ 0.3 V or 33 V, whichever is smaller.

(4) The absolute maximum rating is V_INN– 0.3 V or –33 V, whichever is greater.

(5) The absolute maximum rating is V_INP+ 0.3 V or 3 V, whichever is smaller.

(6) The absolute maximum rating is V_INP+ 0.3 V or 2 V, whichever is smaller.

(7) The absolute maximum rating is V_INN– 0.3 V or –3 V, whichever is greater.

(8) The absolute maximum rating is V_INP+ 0.3 V or 36 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_ESD

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.3

NOM

MAX

33

UNIT

V

|V_INx

|

Supply voltage magnitude for either regulator

Enable supply voltage

V_EN

0

V_INP

30

V

V_OUTP

V_OUTN

I_OUTx

I_BUF

Positive regulated output voltage range

Negative regulated output voltage range

Output current for either regulator

V_FBP

–30

0.005⁽¹⁾

0

V

V_FBN

150

1000

V

mA

µA

µF

nF

kΩ

°C

Output current from the BUF pin

120

10⁽²⁾

10

C_INx

Input capacitor for either regulator

4.7

C_OUTx

C_NR/SS

C_FFP

C_FFN

R_2P

Output capacitor for either regulator

4.7

0⁽³⁾

Noise-reduction and soft-start capacitor

Positive channel feed-forward capacitor; connect from V_OUTPto FBP

Negative channel feed-forward capacitor; connect from V_OUTNto FBN

Lower positive feedback resistor

1000

100

240

125

0

10

0

10

R_2N

Lower negative feedback resistor (from FBN to BUF)

Operating junction temperature

10

T_J

–40

(1) Minimum load required when feedback resistors are not used. If feedback resistors are used, keeping R_2xbelow 240 kΩ satisfies this

requirement.

(2) The nominal input and output capacitor value of 10-µF accounts for the derating factors that apply to X5R and X7R ceramic capacitors.

The assumed overall derating is 80%.

(3) For startup tracking to function correctly a minimum 4.7-nF C_NR/SScapacitor must be used.

6.4 Thermal Information

TPS7A39

THERMAL METRIC⁽¹⁾

DSC (WSON)

10 PINS

44.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

33.7

19.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.4

ψ_JB

19.5

R_θJC(bot)

2.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

6.5 Electrical Characteristics

at T_J= –40°C to +125°C, V_INP(nom)= V_OUTP(nom)+ 1 V or V_IN(nom)= 3.3 V (whichever is greater), V_INN(nom)= V_OUTN(nom)– 1 V or

V_INN(nom)= –3.3 V (whichever is less), V_EN= V_INP, I_OUT= 1 mA, C_INx= 2.2 μF, C_OUTx= 10 μF, C_FFx= C_NR/SS= open, R_1N= R_2N

10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at T_J= 25°C

=

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_INP

V_INN

Input voltage range, positive channel

Input voltage range, negative channel

3.3

33

V

–33

–3.3

V

Undervoltage lockout threshold,

positive channel

V_{UVLOP(rising)}

V_UVLOP(hys)

V_INPrising, V_INN= –3.3 V

1.4

3.1

V

Undervoltage lockout threshold, positive

channel hysteresis

V_INPfalling, V_INN= –3.3 V

120

70

mV

Undervoltage lockout threshold,

negative channel

V_{UVLON(falling)}

V_UVLON(hys)

V_INNfalling, V_INP= 3.3 V

V_INNrising, V_INP= 3.3 V

–3.1

–1.4

V

Undervoltage lockout threshold, negative

channel, hysteresis

mV

V_NR/SS

V_FBP

Internal reference voltage

Positive feedback voltage

Negative feedback voltage

1.172

1.170

–10

1.19

1.188

3.7

1.208

1.206

10

V

V_FBN

mV

Positive channel

Output voltage range⁽¹⁾

V_FBP

–30

30

V

(2)

Negative channel

V_FBN

V

_INP(nom)≤ V_INP≤ 33 V, 1 mA ≤ I_OUTP≤ 150 mA,

V_OUTPaccuracy

–1.5

–3

1.5 %V_OUT

1.2 V ≤ V_OUTP(nom)≤ 30 V

–33 V ≤ V_INN≤ V_INN(nom), –150 mA ≤ I_OUTN

–1 mA, –30 V ≤ V_OUTN(nom)≤ –1.2 V

≤

V_OUTNaccuracy⁽³⁾

3

36

12

%V_OUT

mV

V_OUT

–33 V ≤ V_INN≤ V_INN(nom), –150 mA ≤ I_OUTN

1 mA, –1.2 V < V_OUTN(nom)< 0 V

≤

–36

–12

Negative V_OUTchannel accuracy

–33 V ≤ V_INN≤ V_INN(nom), –150 mA ≤ I_OUTN

1 mA, V_OUTN(nom)= 0 V

≤

Line regulation, positive channel

Line regulation, negative channel

Load regulation, positive channel

Load regulation, negative channel

V

_INP(nom)≤ V_INP≤ 33 V

0.035

0.125

–0.09

0.715

ΔV_OUT(ΔV_IN) /

V_OUT(NOM)

%V_OUT

–33 V ≤ V_INN≤ V_OUT(nom)+ 1 V

1 mA ≤ I_OUTP≤ 150 mA

ΔV_OUT(ΔI_OUT) /

V_OUT(NOM)

–150 mA ≤ I_OUTN≤ –1 mA

I_OUTP= 50 mA, 3.3 V ≤ V_INP(nom)≤ 33.0 V,

V_FBP= 1.070 V

175

300

500

Positive channel

I_OUTP= 150 mA, 3.3 V ≤ V_INP(nom)≤ 33.0 V,

V_FBP= 1.070 V

V_DO

Dropout voltage

mV

I_OUTN= –50 mA, –3.3 V ≤ V_INN(nom)≤ –33.0 V,

V_FBN= 0.0695 V

–250

–400

–145

–275

Negative channel

I_OUTN= –150 mA, –3.3 V ≤ V_INN(nom)≤ –33.0 V,

V_FBN= 0.0695 V

V_BUF

Buffered reference output voltage

Buffered reference load regulation

Output buffer offset voltage

V_NR/SS

V

V_BUF/I_BUF

V_BUF– V_NR/SS

I_BUF= 100 µA to 1 mA

V_NR/SS= 0.25 V to 1.2 V

1

3

mV/mA

mV

–4

8

DC output voltage difference with a forced

REF voltage

V_OUTP–V_OUTN

V_NR/SS= 0.25 V to 1.2 V

V_OUTP= 90% V_OUTP(nom)

–10

10 %V_NR/SS

500

Positive channel

Current limit

200

330

–300

75

I_LIM

mA

µA

Negative channel V_OUTN= 90% V_OUTN(nom)

–500

–200

150

I_OUTP= 0 mA, R_2N= open, V_INP= 33 V

I_OUTP= 150 mA, R_2N= open, V_INP= 33 V

Positive channel

904

I_SUPPLY

Supply current

I_OUTN= 0 mA, V_OUTN(nom)= 0 V, R_2N= open, V_INN

–33 V

=

–150

–4.5

–60

Negative channel

I_OUTN= 150 mA, R_2N= open, V_INN= –33 V

V_EN= 0.4 V, V_INP= 33 V

–1053

3.75

Positive channel

6.5

I_SHDN

Shutdown supply current

Negative channel V_EN= 0.4 V, V_INN= –33 V

–2.25

(1) To ensure V_OUTdoes not drift up while the device is disabled, a minimum load current of 5 µA is required.

(2) V_OUT(target)= 0 V, R_1N= 10 kΩ, R_2N= open.

(3) The device is not tested under conditions where the power dissipated across the device, P_D, exceeds 2 W.

6

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

Electrical Characteristics (continued)

at T_J= –40°C to +125°C, V_INP(nom)= V_OUTP(nom)+ 1 V or V_IN(nom)= 3.3 V (whichever is greater), V_INN(nom)= V_OUTN(nom)– 1 V or

V_INN(nom)= –3.3 V (whichever is less), V_EN= V_INP, I_OUT= 1 mA, C_INx= 2.2 μF, C_OUTx= 10 μF, C_FFx= C_NR/SS= open, R_1N= R_2N

10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at T_J= 25°C

=

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Positive channel

Negative channel

5.5

100

Feedback pin leakage

current

I_FBx

nA

–100

3

–9.7

5.1

I_NR/SS

I_EN

V_IH(EN)

V_IL(EN)

Soft-start charging current

Enable pin leakage current

Enable high-level voltage

Enable low-level voltage

V_NR/SS= 0.9 V

6.7

1

µA

V

V_EN= V_INP= 33 V

0.02

2.2

0

V_INP

0.4

V

|V_IN| = 6 V, |V_OUT(nom)| = 5 V, C_OUT= 10 μF,

C_NR/SS= C_FF= 10 nF, f = 120 Hz

PSRR

Power-supply rejection ratio

69

20.63

26.86

22.13

28.68

dB

V_INP= 3.3 V, V_OUTP(nom)= V_NR/SS, C_OUTP= 10 μF,

C_NR/SS= 10 nF, BW = 10 Hz to 100 kHz

Positive channel

Negative channel

V_INP= 6 V, V_OUTP(nom)= 5 V, C_OUTP= 10 μF,

C_NR/SS= C_FF= 10 nF, BW = 10 Hz to 100 kHz

V_n

Output noise voltage

µV_RMS

V_INN= –3 V, V_OUTN(nom)= –V_NR/SS, C_OUTP= 10 μF,

C_NR/SS= 10 nF, BW = 10 Hz to 100 kHz

V_INN= –6 V, V_OUTN(nom)= –5 V, C_OUTP= 10 μF,

C_NR/SS= C_FF= 10 nF, BW = 10 Hz to 100 kHz

R_NR/SS

T_sd

Filter resistor from band gap to NR pin

Thermal shutdown temperature

350

175

160

kΩ

Shutdown, temperature increasing

Reset, temperature decreasing

°C

6.6 Startup Characteristics

at T_J= –40°C to +125°C, V_INP(nom)= V_OUTP(nom)+ 1 V or V_IN(nom)= 3.3 V (whichever is greater), V_INN(nom)= V_OUTN(nom)– 1 V or

V_INN(nom)= –3.3 V (whichever is less), V_EN= V_INP, I_OUT= 1 mA, C_INx= 2.2 μF, C_OUTx= 10 μF, C_FFx= C_NR/SS= 4.7nF, R_1N= R_2N

= 10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Delay time from EN low-to-high transition to 2.5%

V_OUTP

From EN low-to-high transition to V_OUTP= 2.5% ×

V_OUTP(nom)

t_EN(delay)

t_start-up

300

µs

Delay time from EN low-to-high transition to both

outputs reaching 95% of final value

From EN low-to-high transition to V_OUTP

=

1.1

ms

V_OUTP(nom)× 95% and V_OUTN= V_OUTN(nom)× 95%

Delay time from V_OUTPleaving a high-impedance

state to V_OUTNleaving a high-impedance state

From V_OUTP= V_OUTP(nom)× 2.5% to V_OUTN

V_OUTN(nom)× 2.5%

=

t_{Pstart-Nstart}

–40

–17

75

40

µs

Δ|V_OUTP

V_OUTN

–

Voltage difference between the positive and

negative output

During t_{Pstart-Nstart}

300

mV

|

7

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

V_EN

V_IH(EN)

Tt_start-up

t

90%

V_OUTP

t_EN(delay)

V_OUTN

t_{Pstart-Nstart}

90%

NOTE: Slow ramps (t_rise(VINx)> 10 ms typically) on V_INxwith EN tied to V_INPdoes not meet the tracking specification. Use a

resistor divider from V_INPto EN for these applications.

图 1. Start-Up Characteristics

8

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

6.7 Typical Characteristics

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

100

80

60

40

20

0

100

80

60

40

20

0

V_IN= 5.5 V

V_IN= 5.6 V

V_IN= 5.7 V

V_IN= 5.8 V

V_IN= 5.9 V

V_IN= 6.0 V

V_INN= -5.5 V

V_INN= -5.6 V

V_INN= -5.7 V

V_INN= -5.8 V

V_INN= -5.9 V

V_INN= -6.0 V

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, I_OUTP= 150 mA, V_OUTN= –5 V, I_OUTN= 0 mA,

C_NR/SS= C_FFx= 10 nF

V_OUTP= 5 V, I_OUTP= 0 mA, V_OUTN= –5 V, I_OUTN= 150 mA,

C_NR/SS= C_FFx= 10 nF

图 2. Positive PSRR vs Frequency and V_INP

图 3. Negative PSRR vs Frequency and V_INN

100

80

60

40

80

60

40

I_OUT= 1 mA

I_OUT= 10 mA

I_OUT= 50 mA

I_OUT= 10 mA

I_OUT= 50 mA

20

I_OUT= 100 mA

I_OUT= 150 mA

0

I_OUT= 150 mA

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, V_INP= V_EN= 6 V, V_OUTN= –5 V, I_OUTN= 0 mA,

C_NR/SS= C_FFx= 10 nF

V_OUTP= 5 V, I_OUTP= 0 mA, V_INN= –6 V, V_OUTN= –5 V,

C_NR/SS= C_FFx= 10 nF

图 4. Positive PSRR vs Frequency and I_OUTP

图 5. Negative PSRR vs Frequency and I_OUTN

100

80

60

80

60

40

C_OUT= 4.7 mF

20

C_OUT= 10 mF

C_OUT= 22 mF

C_OUT= 47 mF

C_OUT= 22 mF

C_OUT= 47 mF

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, V_INP= V_EN= 6 V, V_OUTN= –5 V, I_OUTN= 0 mA,

C_NR/SS= C_FFx= 10 nF

V_OUTP= 5 V, I_OUTP= 0 mA, V_INN= –6 V, V_OUTN= –5 V,

C_NR/SS= C_FFx= 10 nF, C_OUTP= 10 µF

图 6. Positive PSRR vs Frequency and C_OUTP

图 7. Negative PSRR vs Frequency and C_OUTN

9

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

100

80

60

40

20

0

100

80

60

40

20

0

C_FF= 0 nF

C_FF= 10 nF

C_FF= 100 nF

C_FFN= 0 nF

C_FFN= 10 nF

C_FFN= 100 nF

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, V_INP= V_EN= 6 V, V_OUTN= –5 V, I_OUTN= 0 mA,

C_NR/SS= 10 nF

V_OUTP= 5 V, I_OUTP= 0 mA, V_INN= –6 V, V_OUTN= –5 V,

C_NR/SS= C_FFP= 10 nF

图 8. Positive PSRR vs Frequency and C_FFP

图 9. Negative PSRR vs Frequency and C_FFN

100

80

60

80

60

40

C_NR/SS= 0 nF

C_NR/SS= 10 nF

C_NR/SS= 0 nF

C_NR/SS= 10 nF

20

C_NR/SS= 100 nF

C_NR/SS= 1000 nF

0

C_NR/SS= 1000 nF

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, V_INP= V_EN= 6 V, V_OUTN= –5 V, I_OUTN= 0 mA,

C_FFx= 10 nF

V_OUTP= 5 V, I_OUTP= 0 mA, V_INN= –6 V, V_OUTN= –5 V,

C_FFx= 10 nF

图 10. Positive PSRR vs Frequency and C_NR/SS

图 11. Negative PSRR vs Frequency and C_NR/SS

100

80

60

40

20

80

60

40

20

I_OUT= 150 mA

0

I_OUT= 150 mA

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

图 12. Crosstalk Positive to Negative

图 13. Crosstalk Negative to Positive

10

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

10

5

10

5

V_OUT

1.188 V, 20.63 mV_RMS

5 V, 26.86 mV_RMS

15 V, 63.88 mV_RMS

-1.188 V, 22.13 mV_RMS

-5 V, 28.68 mV_RMS

-15 V, 47.10 mV_RMS

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

I_OUTP= 150 mA, V_INP= V_EN, V_OUTN= –V_OUTP, I_OUTN= 0 mA,

C_NR/SS= C_FFx= 10 nF

I_OUTN= –150 mA, V_INP= V_EN, V_OUTN= –V_OUTP, I_OUTP= 0 mA,

C_NR/SS= C_FFx= 10 nF

图 14. Positive Spectral Noise Density vs Frequency and

图 15. Negative Spectral Noise Density vs Frequency and

V_OUTP

V_OUTN

10

C_NR/SS

5

0 nF, 68.08 mV_RMS

10 nF, 26.86 mV_RMS

100 nF, 21.74 mV_RMS

1000 nF, 21.56 mV_RMS

0 nF, 53.32 mV_RMS

10 nF, 26.68 mV_RMS

100 nF, 23.21 mV_RMS

1000 nF, 23.06 mV_RMS

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, I_OUTP= 150 mA, V_INP= V_EN= 6 V, V_OUTN= –5 V,

I_OUTN= 0 mA, C_FFx= 10 nF

V_OUTN= –5 V, I_OUTN= –150 mA, V_INP= V_EN= 6 V, V_OUTN= –5 V,

I_OUTP= 0 mA, C_FFx= 10 nF

图 16. Positive Spectral Noise Density vs Frequency and

图 17. Negative Spectral Noise Density vs Frequency and

C_NR/SS

10

C_FF

5

0 nF, 37.77 mV_RMS

10 nF, 26.86 mV_RMS

100 nF, 22.95 mV_RMS

0 nF, 45.08 mV_RMS

10 nF, 26.68 mV_RMS

100 nF, 23.53 mV_RMS

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, I_OUTP= 150 mA, V_INP= V_EN= 6 V, V_OUTN= –5 V,

I_OUTN= 0 mA, C_NR/SS= 10 nF

V_OUTN= –5 V, I_OUTN= –150 mA, V_INP= V_EN= 6 V, V_OUTN= –5 V,

I_OUTP= 0 mA, C_NR/SS= 10 nF

图 18. Positive Spectral Noise Density vs Frequency and C_FF

图 19. Negative Spectral Noise Density vs Frequency and

C_FF

11

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

10

5

10

5

C_OUT

4.7 mF, 27.33 mV_RMS

10 mF, 26.86 mV_RMS

22 mF, 27.47 mV_RMS

47 mF, 27.64 mV_RMS

4.7 mF, 28.43 mV_RMS

10 mF, 26.68 mV_RMS

22 mF, 26.67 mV_RMS

47 mF, 28.70 mV_RMS

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, I_OUTP= 150 mA, V_INP= V_EN= 6 V, V_OUTN= –5 V,

I_OUTN= 0 mA, C_NR/SS= C_FFx= 10 nF

V_OUTN= –5 V, I_OUTN= –150 mA, V_INP= V_EN= 6 V, V_OUTN= –5 V,

I_OUTP= 0 mA, C_NR/SS= C_FFx= 10 nF

图 20. Positive Spectral Noise Density vs Frequency and

图 21. Negative Spectral Noise Density vs Frequency and

C_OUT

10

I_OUT

5

1 mA, 29.88 mV_RMS

10 mA, 27.07 mV_RMS

50 mA, 26.66 mV_RMS

100 mA, 26.77 mV_RMS

150 mA, 26.86 mV_RMS

1 mA, 29.72 mV_RMS

10 mA, 28.42 mV_RMS

50 mA, 28.59 mV_RMS

100 mA, 28.47 mV_RMS

150 mA, 26.68 mV_RMS

2

1

2

1

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

0.002

0.001

0.002

0.001

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_OUTP= 5 V, V_INP= V_EN= 6 V, V_OUTN= –5 V, I_OUTN= 0 mA,

C_NR/SS= C_FFx= 10 nF

V_OUTN= –5 V, V_INP= V_EN= 6 V, V_OUTN= –5 V, I_OUTP= 0 mA,

C_NR/SS= C_FFx= 10 nF

图 22. Positive Spectral Noise Density vs Frequency and

图 23. Negative Spectral Noise Density vs Frequency and

I_OUT

20

25

V_INP

V_INN

V_OUTP

V_OUTN

EN

V_INP

V_OUTP

V_OUTN

V_INN

16

12

8

20

15

10

5

4

0

-4

-5

-8

-10

-15

-20

-25

-12

-16

-20

0

20

40

60

80 100 120 140 160 180 200

Time (ms)

0

20

40

60

80 100 120 140 160 180 200

Time (ms)

V_OUTP= –V_OUTN= 5 V, V_INP= –V_INN= 12 V

V_OUTP= –V_OUTN= 5 V, V_INP= –V_INN= 15 V

图 24. Startup (V_INP= V_EN

)

图 25. Startup With EN

12

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

12

11

10

9

5.065

5.06

-4

-5

-4.9

V_INP

V_OUTP

-4.925

-4.95

-4.975

-5

5.055

5.05

-6

-7

8

5.045

5.04

-8

7

-9

-5.025

-5.05

-5.075

-5.1

6

5.035

5.03

-10

-11

-12

5

V_INN

V_OUTN

4

5.025

0

20

40

60

80

100

0

20

40

60

80 100 120 140 160 180 200

Time (ms)

V_INP= 5.5 V to 10 V at 1 V/µs, V_OUTP= –V_OUTN= 5 V,

I_OUTN= 0 mA, I_OUTP= 150 mA

V_INN= –5.5 V to –10 V at 1 V/µs, V_OUTP= –V_OUTN= 5 V,

I_OUTN= –150 mA, I_OUTP= 0 mA

图 26. Line Transient Positive Regulator

图 27. Line Transient Negative Regulator

12

11

10

9

5.2

-4

-4.9

V_INP

V_OUTP

5.15

5.1

-5

-6

-4.925

-4.95

-4.975

-5

5.05

5

-7

8

-8

7

4.95

4.9

-9

-5.025

-5.05

-5.075

-5.1

6

-10

-11

-12

5

4.85

4.8

V_INN

V_OUTN

4

0

20

40

60

80

100

0

20

40

60

80 100 120 140 160 180 200

Time (ms)

V_INP= 5.5 V to 10 V at 4 V/µs, V_OUTP= –V_OUTN= 5 V,

I_OUTN= 0 mA, I_OUTP= 150 mA

V_INN= –5.5 V to –10 V at 4 V/µs, V_OUTP= –V_OUTN= 5 V,

I_OUTN= –150 mA, I_OUTP= 0 mA

图 28. Line Transient Positive Regulator

图 29. Line Transient Negative Regulator

5.1

0.2

-4.9

0

V_OUTP

I_OUTP

V_OUTP

I_OUTP

-4.925

-4.95

-4.975

-5

-0.025

-0.05

-0.075

-0.1

5.075

5.05

5.025

5

0.15

0.1

0.05

0

-5.025

-5.05

-5.075

-5.1

-0.125

-0.15

-0.175

-0.2

0

20

40

60

80 100 120 140 160 180 200

0

20

40

60

80 100 120 140 160 180 200

Time (ms)

V_INP= 6 V, V_OUTP= –V_OUTN= 5 V, I_OUTN= 0 mA,

I_OUTP= 1 mA to 150 mA at 1 A/µs

V_INN= –6 V, V_OUTP= –V_OUTN= 5 V, I_OUTN= 0 mA,

I_OUTN= –1 mA to –150 mA at 1 A/µs

图 30. Load Transient Positive Regulator

图 31. Load Transient Negative Regulator

13

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

0.0075

0.006

0.0045

0.003

0.0015

0

0.01

0.005

0

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

-0.005

-0.01

-33 -30 -27 -24 -21 -18 -15 -12

Input Voltage (V)

-9

-6

-3

0

15

30

45

60

75

90 105 120 135 150

Output Current (mA)

V_OUTN= 0 V

V_OUTN= 0 V, V_INN= –3.3 V

图 32. Negative Line Regulation

图 33. Negative Load Regulation

2

1.5

1

2

1.5

1

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

-33 -30 -27 -24 -21 -18 -15 -12

-9

-6

-3

-33

-30

-27

-24

-21

-18

-15

Input Voltage (V)

V_OUTN= –1.19 V

V_OUTN= –15 V

图 34. Negative Line Regulation

图 35. Negative Line Regulation

2

1.5

1

2

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

1.5

1

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

0

30

60

90

120

150

-33

-31

-29

-27

-25

-23

Output Current (mA)

Input Voltage (V)

V_OUTN= –1.2 V, V_INN= –3.3 V

图 37. Negative Load Regulation

V_OUTN= –24 V

图 36. Negative Line Regulation

14

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

2

1.5

1

2

1.5

1

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

0

30

60

90

120

150

0

30

60

90

120

150

Output Current (mA)

V_OUTN= –15 V, V_INN= –16 V

V_OUTN= –30 V, V_INN= –33 V

图 38. Negative Load Regulation

图 39. Negative Load Regulation

2

1.5

1

2

1.5

1

-40èC

0èC

85èC

-40èC

0èC

85èC

125èC

25èC

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

30

60

90

120

150

0

30

60

90

120

150

Output Current (mA)

V_OUTP= 1.188 V, V_INP= 3.3 V

V_OUTP= 15 V, V_INP= 16 V

图 41. Positive Load Regulation

图 40. Positive Load Regulation

2

1.5

1

-40èC

0èC

25èC

85èC

-40èC

0èC

25èC

85èC

125èC

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

3

6

9

12

15

18

21

24

27

30

33

30

60

90

120

150

Input Voltage (V)

Output Current (mA)

V_OUTP= 1.188 V

图 43. Positive Line Regulation

V_OUTP= 30 V, V_INP= 33 V

图 42. Positive Load Regulation

15

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

1

0.5

0

1

0.5

0

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

-0.5

-1

15

18

21

24

27

30

33

23

25.5

28

30.5

33

Input Voltage (V)

V_OUTP= 15 V

V_OUTP= 24 V

图 44. Positive Line Regulation

图 45. Positive Line Regulation

1.25

1

0

-0.25

-0.5

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

0.75

0.5

0.25

0

-0.75

-1

-1.25

0

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

0

50 100 150 200 250 300 350 400 450 500

Output Current (mA)

V_OUTN= –1.19 V

V_OUTP= 1.188 V

图 47. Negative Regulator Current Limit

图 46. Positive Regulator Current Limit

500

450

400

350

300

250

200

150

100

500

450

400

350

300

250

200

150

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

100

3

6

9

12

15

18

21

24

27

30

33

6

9

12

15

18

21

24

27

30

33

Input Voltage (V)

图 48. Positive Regulator Dropout Voltage vs

图 49. Negative Regulator Dropout Voltage vs

Input Voltage

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Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

550

500

450

400

350

300

250

200

150

100

50

550

500

450

400

350

300

250

200

150

100

50

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

0

30

60

90

120

150

0

30

60

90

120

150

Output Current (mA)

V_INP= 3.3 V

V_OUTN= –3.3 V

图 50. Positive Regulator Dropout Voltage vs

图 51. Negative Regulator Dropout Voltage vs

Output Current

2

1.75

1.5

10

8

-40èC

0èC

25èC

85èC

125èC

6

4

1.25

2

Enable Falling

-25

Enable Rising

50

1

-50

0

25

75

100

125

0

0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5

NR/SS Voltage (V)

Temperature (èC)

图 52. Enable Threshold vs Temperature

图 53. I_NR/SSvs V_NR/SS

6

5

4

3

2

1

0

-1

-2

-3

-4

-5

-40èC

0èC

25èC

85èC

125èC

-40èC

0èC

25èC

85èC

125èC

0

5

10

15

20

25

30

35

-35

-30

-25

-20

-15

-10

-5

0

Output Voltage (V)

图 54. Positive Output Discharge Current vs

图 55. Negative Output Discharge Current vs

Output Voltage

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Typical Characteristics (接下页)

at T_J= 25°C, V_INP= V_OUTP(nom)+ 1.0 V or V_IN= 3.3 V (whichever is greater), V_INN= V_OUTN(nom)– 1 V or –3.3 V (whichever is

less), V_EN= V_IN, I_OUT= 1 mA, C_IN= 10-μF ceramic, C_OUT= 10-μF ceramic, and C_FFP= C_FFN= C_NR/SS= 10 nF (unless otherwise

noted)

2000

1600

1200

800

400

0

-400

-40èC

0èC

25èC

85èC

125èC

-800

-1200

-1600

-2000

-40èC

0èC

25èC

85èC

125èC

0

30

60

90

120

150

0

15

30

45

60

75

90 105 120 135 150

Output Current (mA)

V_OUTP= 1.188 V

V_OUTN= –1.19 V

图 56. Positive Supply Current vs Output Current

图 57. Negative Supply Current vs Output Current

2

-40èC

0èC

25èC

85èC

125èC

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (mA)

1

V_OUTN= –1.19 V

图 58. Buffer Accuracy vs Buffer Current

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7 Detailed Description

7.1 Overview

The TPS7A39 is an innovative linear regulator (LDO) targeted at powering the signal chain, capable of up to

±33 V on the inputs and regulating up to ±30 V on the outputs at up to 150 mA of load current. The device uses

an LDO topology that, by design, delivers ratiometric start-up tracking in most applications. The TPS7A39 has

several other features, as listed in 表 1, that simplify using the device in a variety of applications.

注

Throughout this document, x is used to designate that the condition or component applies

to both the positive and negative regulators (for example, C_FFxmeans C_FFPand C_FFN).

表 1. TPS7A39 Features

VOLTAGE REGULATION

Reference input/output

High-PSRR output

SYSTEM START-UP

Ratiometric start-up tracking

Programmable soft-start

Sequencing controls

INTERNAL PROTECTION

Current limit

Thermal shutdown

Fast transient response

7.2 Functional Block Diagram

Positive LDO

INP

+

UVLO P

+

œ

2.6 V

OUTP

Internal

Enable

Current

Limit

FBP

350 kꢀ

Bandgap

INP

Reference

NR/SS

BUF

x1

UVLO P

Internal Enable

EN

UVLO N

FBN

Current

Limit

Thermal

Shutdown

OUTN

Internal

Enable

œ

+

UVLO N

- 2.6 V

+

œ

INN

Negative LDO

GND

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7.3 Feature Description

7.3.1 Voltage Regulation

7.3.1.1 DC Regulation

An LDO functions as a buffered op-amp in which the input signal is the internal reference voltage (V_NR/SS), as

shown in 图 59, and in normal regulation V_FBP= V_NR/SS. Sharing a single reference ensures that both channels

track each other during start-up.

V_NR/SSis designed to have a very low-bandwidth at the input to the error amplifier through the use of a low-pass

filter. As such, the reference can be considered as a pure dc input signal.

As 图 60 shows, the negative LDO on the device regulates with a V_FBN= 0 V and inverts the positive reference

(V_BUF). This topology allows the negative regulator to regulate down to 0 V.

V_OUTP= V_NR/SS× (1+R_1P/R_2P

)

V_INP

To Load

R_1P

NR/SS

V_FBP

R_2P

C_NR/SS

GND

Bandgap

GND

Reference

GND

图 59. Simplified Positive Regulation Circuit

V_OUTN= V_BUF× (-R_1N/R_2N

)

V_INN

To Load

R_1N

V_FBN

GND

R_2N

V_BUF

图 60. Simplified Negative Regulation Circuit

7.3.1.2 AC and Transient Response

Each LDO responds quickly to a transient on the input supply (line transient) or the output current (load

transient). This LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a low internal noise-

floor (V_n), the LDO approximates an ideal power supply in ac and large-signal conditions.

The performance and internal layout of the device minimizes the coupling of noise from one channel to the other

channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.

The noise-reduction and soft-start capacitor (C_NR/SS) and feed-forward capacitor (C_FFx) easily reduce the device

noise floor and improve PSRR; see the Optimizing Noise and PSRR section for more information on optimizing

the noise and PSRR performance.

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Feature Description (接下页)

7.3.2 User-Settable Buffered Reference

As 图 61 shows, the device internally generated band-gap voltage outputs at the NR/SS pin. An internal resistor

(R_NR) and an external capacitor (C_NR/SS) control the rise time of the voltage at the V_NR/SSpin, setting the soft-start

time. This network also filters out noise from the band gap, reducing the overall noise floor of the device.

Driving the NR/SS pin with an external source can improve the device accuracy and can reduce the device noise

floor, along with enabling the device to regulate the positive channel to voltages below the device internal

reference.

+

SW

V_FBN

œ

x1

R_2N*

V_BUF

I_NR/SS

R_NR/SS

V_NR/SS

C_NR/SS

V_Bandgap

+

*

œ

V_FBP

GND

Note: * Denotes external components

NOTE: * denotes external components.

图 61. Simplified Reference Circuit

7.3.3 Active Discharge

When either EN or UVLOx are low, the device connects a resistance from V_OUTxto GND, discharging the output

capacitance. The active discharge circuit requires |V_OUTx| ≥ 0.6 V (typ) to discharge the output because the NPN

pulldown has a minimum V_CErequirement.

Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops

below the targeted output voltage. The TPS7A39 is a bipolar device, and as such, reverse voltage conditions

(|V_OUTx| ≥ |V_INX| + 0.3 V) can breakdown the emitter to base diode and also cause a breakdown of the parasitic

bipolar formed in the substrate; see the Reverse Current section for more details.

When either EN or UVLOx are low, the device outputs a small amount of leakage current. The leakage current is

typically handled by the maximum R_2xresistor value of 240 kΩ. However, if the device is placed in unity gain (no

R_2xresistor) this leakage current causes the output to slowly rise until the discharge circuit (as shown in 图 62)

has enough headroom to clamp the output voltage (typically ±0.6 V).

UVLOP

Internal Enable

EN

UVLON

GND

图 62. Simplified Active Discharge Circuit

7.3.4 System Start-Up Controls

In many different applications, the power-supply output must turn-on within a specific window of time because of

sequencing requirements, ensuring proper operation of the load, or to minimize the loading on the input supply.

Both LDOs start-up are well-controlled and user-adjustable through the C_NR/SScapacitor, solving the demanding

requirements faced by many power-supply design engineers in a simple fashion. For start-up tracking to work

correctly. a minimum 4.7-nF C_NR/SScapacitor is required. For more information on startup tracking, see the

Noise-Reduction and Soft-Start Capacitor (C_NR/SS) section.

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Feature Description (接下页)

7.3.4.1 Start-Up Tracking

图 63 shows how both regulators use a common reference, which enables start-up tracking. Using the same

reference voltage for both the positive and negative regulators ensures that the regulators start-up together in a

controlled fashion; see 图 24 and 图 25.

Ramps on V_INxwith EN = V_INPthat are slower than the soft-start time do not have start-up tracking. If ramps

slower than the soft-start time are used then enable should be used to start the device to ensure start-up

tracking. A small mismatch between the positive and negative internal enable thresholds means that one channel

turns on at a slightly lower input voltage than the other channel. This mismatch is typically not a problem in most

applications and is easily solved by controlling the start-up with enable. The external signal can come from the

input power supply power-good indicator, a voltage supervisor output such as the TPS3701, or from another

source.

V_OUTN= V_BUF× (-R_1N/R_2N

)

V_OUTP= V_NR/SS× (1+R_1P/R_2P

)

V_INN

V_INP

R_1N

R_1P

V_NR/SS

GND

R_2N

R_2P

GND

V_BUF

x1

图 63. Simplified Regulation Circuit

7.3.4.2 Sequencing

图 64 and 表 2 describe how the turn-on and turn-off times of both LDOs (respectively) is controlled by setting

the enable circuit (EN) and undervoltage lockout circuit (UVLOP and UVLON).

UVLOP

Internal

Enable

EN

UVLON

图 64. Simplified Turn-On Control

表 2. Sequencing Functionality Table

POSITIVE INPUT VOLTAGE NEGATIVE INPUT VOLTAGE

(V_INP(V_INN

LDO

STATUS

ACTIVE

DISCHARGE

ENABLE STATUS

)

EN = 1

On

Off

V_INP≥ V_UVLOP

V_INN≤ V_UVLON

EN = 0

On⁽¹⁾

V_INP≥ V_UVLOP

V_INP< V_UVLOP

V_INN> V_UVLON

_INN≤ V_UVLON

V_INN> V_UVLON– V_HYSN

EN = don't care

V

V_INP< V_UVLOP– V_HYSP

(1) The active discharge remains on as long as V_INxand V_OUTxprovide enough headroom for the discharge circuit to function.

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7.3.4.2.1 Enable (EN)

The enable signal (V_EN) is an active-high digital control that enables the LDO when the enable voltage is past the

rising threshold (V_EN≥ V_IH(EN)) and disables the LDO when the enable voltage is below the falling threshold (V_EN

≤ V_IL(EN)). The exact enable threshold is between V_IH(EN)and V_IL(EN)because EN is a digital control. In

applications that do not use the enable control, connect EN to V_INP

.

A slow V_INxramp directly connecting EN to V_INPcan cause the start-up tracking to move out of specification.

Under slow ramp conditions, use a resistor divider from V_INPto ensure start-up tracking.

7.3.4.2.2 Undervoltage Lockout (UVLO) Control

The UVLO circuit responds quickly to glitches on the input supplies and attempts to disable the output of the

device if either of these rails collapse.

As a result of the fast response time of the input supply UVLO circuit, fast and short line transients well below the

input supply UVLO falling threshold (brownouts) can cause momentary glitches during the edges of the transient.

These glitches are typical in most LDOs. The local input capacitance prevents severe brown-outs in most

applications; see the Undervoltage Lockout (UVLOx) Control section for more details. Fast line transients can

cause the outputs to momentarily shut off, and can be mitigated through using the recommended 10-µF input

capacitor. If this becomes a problem in the system, increasing the input capacitance prevents these glitches from

occurring.

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7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

•

The input voltage is at least as high as |V_INx(min)

The input voltage is greater than the nominal output voltage added to the dropout voltage

The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased

below the enable falling threshold

|

•

The output current is less than the current limit

The device junction temperature is less than T_SD

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the

output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the

device is significantly degraded because the pass device (as a bipolar junction transistor, or BJT) is in saturation

and no longer controls the current through the LDO. Line or load transients in dropout can result in large output

voltage deviations.

7.4.3 Disabled

The device is disabled under the following conditions:

•

The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising

threshold

•

The device junction temperature is greater than the thermal shutdown temperature

表 3 shows the conditions that lead to the different modes of operation.

表 3. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

|V_INx| > |V_OUT(nom)| + |V_DOx| and

Normal mode

Dropout mode

V_EN> V_IH

|I_OUTx| < |I_LIMx

|

T _J< 125°C

|V_INx| > |V_INx(min)

|

|V_INx(min)| < |V_INx| < |V_OUTx(nom)| +

V_EN> V_IH

V_EN< V_IL

—

T_J< 125°C

T_J> T_SD

|V_DOx

|

Disabled mode

(any true condition disables the device)

—

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement the LDO to achieve a reliable design.

8.1.1 Setting the Output Voltages on Adjustable Devices

图 65 shows that each LDO resistor feedback network sets its output voltage. The positive LDO output voltage

range is V_NR/SSto 30 V and the negative LDO output voltage range is 0 V to –30 V.

OUTP

C_OUTP

INP

C_INP

C_FFP

R_1P

FBP

R_2P

NR/SS

C_NR/SS

TPS7A39

BUF

FBN

3mm x 3mm

R_2N

C_FFN

EN

R_1N

OUTN

INN

C_INN

C_OUTN

GND

图 65. Adjustable Operation

公式 1 relates the values of R_1Pand R_2Pto V_OUTP(NOM)and V_NR/SSto set the positive output voltage. 公式 2

relates the values of R_1Nand R_2Nto V_OUTN(NOM)and V_NR/SSto set the negative output voltage.

The positive LDO is configured as a noninverting op amp, whereas the negative LDO is an inverting op amp.

V_OUTP= V_NR/SS× (1 + R_1P/ R_2P

)

(1)

(2)

V_OUTN= V_NR/SS× (–R_1N/ R_2N

)

Substituting V_NR/SSwith V_FBPon the positive channel and V_NR/SSwith V_BUFon the negative channel gives a more

accurate relationship.

公式 3 and 公式 2 are rearranged versions of 公式 1 and 公式 2, with the above substitutions made.

R_1P= (V_OUTP/ V_FBP– 1) × R_2P

R_1N= –(V_OUTN× R_2P) / V_BUF

(3)

(4)

The minimum bias current through both feedback networks is 5 µA to ensure accuracy.

For even tighter accuracy, take into account the input bias current into the error amplifiers (I_FBPand I_FBN) and use

0.1% resistors. Overriding the internal reference with a high accuracy external reference can also improve the

accuracy of the device.

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Application Information (接下页)

表 4 and 表 5 show the resistor combinations for several common output voltages using commercially available,

1% tolerance resistors.

表 4. Recommended Feedback-Resistor Values for the Positive LDO

FEEDBACK RESISTOR VALUES⁽¹⁾

TARGETED OUTPUT

VOLTAGE (V)

CALCULATED OUTPUT

VOLTAGE (V)

R_1P(kΩ)

2.67

5.23

11.0

15.4

17.8

32.4

66.5

90.9

115

R_2P(kΩ)

10.0

1.5

1.8

1.50

1.80

2.49

3.00

3.29

5.02

9.07

12.0

14.8

23.8

29.8

2.5

3.0

3.3

5.0

9.0

12.0

15.0

24.0

30.0

191

243

(1) R_1Pis connected from OUTP to FBP, R_2Pis connected from FBP to GND; see the Setting the Output Voltages on Adjustable Devices

section.

表 5. Recommended Feedback-Resistor Values for the Negative LDO

FEEDBACK RESISTOR VALUES⁽¹⁾

TARGETED OUTPUT

VOLTAGE (V)

CALCULATED OUTPUT

VOLTAGE (V)

R_1N(kΩ)

2.55

12.7

15.0

21.0

25.5

28.0

42.2

75.0

100

R_2N(kΩ)

10.0

-0.3

-1.5

-0.303

-1.51

-1.78

-2.49

-3.03

-3.33

-5.04

-8.91

-11.9

-15.1

-23.8

-30.3

-1.8

-2.5

-3.0

-3.3

-5.0

-9.0

-12.0

-15.0

-24.0

-30.0

127

200

255

(1) R_1Nis connected from OUTN to FBN, R_2Nis connected from FBN to BUF; see the Setting the Output Voltages on Adjustable Devices

section.

8.1.2 Capacitor Recommendations

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input

and output pins. The device is also designed to be stable with aluminum polymer and tantalum polymer

capacitors with ESR < 75 mΩ.

Electrolytic capacitors (along with higher ESR polymer capacitors) can also be used if capacitors (meeting the

minimum capacitance and ESR requirements ) are used in parallel.

Take the effective ESR for stability when the impedance of the capacitor is at its minimum. At the minimum level,

the capacitance and parasitic inductance cancel each other and provides the DC ESR.

Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good

capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large

variations in capacitance.

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Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors

recommended herein account for an effective capacitance derating of approximately 50%, but at higher V_INand

V_OUTconditions (that is, V_IN= 5.5 V to V_OUT= 5.0 V) the derating can be greater than 50% and must be taken

into consideration.

For high performance applications polymer capacitors are ideal as they do not experience the large deratings of

ceramic capacitors.

8.1.3 Input and Output Capacitor (C_INxand C_OUTx

)

The device is designed and characterized for operation with ceramic capacitors of 10 µF or greater (2.2 µF or

greater of effective capacitance) at each input and output.

Locate the input and output capacitors as near as practical to the respective input and output pins to minimize

the trace inductance from the capacitor to the device. If the LDO is used to produce low output voltages (below

5 V), a 4.7-µF output capacitor can be used. If a 4.7-µF output capacitor is used, be sure to account for the

derating of the capacitors during design.

Large, fast line transients on the input supplies can cause the device output to momentarily turn off. Typically

these transients do not occur in most applications, but when these transients do occur use a larger input

capacitor to slow down the line transient. If the system has input line transients that are faster than 0.5 V/µs,

increase the input capacitance.

8.1.4 Feed-Forward Capacitor (C_FFx

)

Although a feed-forward capacitor (C_FFx) from the FBx pin to the OUTx pin is not required to achieve stability, a

10-nF external C_FFxcapacitor optimizes the transient, noise, and PSRR performance. The maximum

recommended value for C_FFxis 100 nF.

A larger C_FFxcan dominate the start-up time set by C_NR/SS, for more information see the Pros and Cons of Using

a Feed-Forward Capacitor with a Low Dropout Regulator application report.

8.1.5 Noise-Reduction and Soft-Start Capacitor (C_NR/SS

)

Although a noise-reduction and soft-start capacitor (C_NR/SS) from the NR/SS pin to GND is not required, C_NR/SSis

highly recommended to control the start-up time and reduce the noise-floor of the device. For start-up tracking to

function correctly, a minimum 4.7-nF capacitor is required. As the time constant formed by the feedback resistors

and feed-forward capacitors increases, the value of the C_NR/SScapacitor must also be increased for startup

tracking to work correctly. To figure out how to calculate the time constant of the feedback network see the Pros

and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report.

8.1.6 Buffered Reference Voltage

The voltage at the NR/SS pin, whether driven internally or externally, is buffered with a high-bandwidth, low-noise

op amp. The BUF pin can be used as a voltage reference in many signal chain applications.

8.1.7 Overriding Internal Reference

The internal reference of the LDO can be overridden using an external source to increase the accuracy of the

LDO and lower the output noise. To override the internal reference connect the external source to the NR/SS pin

of the LDO. In order to overdrive the internal reference the external source must be able to source or sink 100 µA

or greater.

The internal reference achieves a 2% accuracy from –40°C to +125°C; using an external reference can help

achieve better accuracy over temperature.

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8.1.8 Start-Up

8.1.8.1 Soft-Start Control (NR/SS)

Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an

external capacitor (C_NR/SS). This soft-start eliminates power-up initialization problems.

The output voltage (V_OUTx) rises proportionally to V_NR/SSduring start-up. As such, the time required for V_NR/SSto

reach its nominal value determines the rise time of V_OUTx(start-up time).

The soft-start ramp time depends on the soft-start charging current (I_NR/SS), the soft-start capacitance (C_NR/SS),

and the internal reference (V_NR/SS). 公式 5 calculates the approximate soft-start ramp time (t_SS):

t_SS= R_NR/SS× C_NR/SS× ln [(V_NR/SS+ I_NR/SS× R_NR/SS) / (I_NR/SS×R_NR/SS)]

(5)

Values for the soft-start charging currents, R_NR/SS, and the device internal C_NR/SSare provided in the table.

8.1.8.1.1 In-Rush Current

In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists

primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to

measure because the input capacitor must be removed, which is not recommended. However, the in-rush current

can be estimated by 公式 6:

C

_OUTx´ dV_OUTx(t)

V_OUTx(t)

R_LOAD

I_OUTx(t) =

+

dt

where:

•

V_OUTx(t) is the instantaneous output voltage of the turn-on ramp

dV_OUTx(t) / dt is the slope of the V_OUTxramp

R_LOADis the resistive load impedance

(6)

8.1.8.2 Undervoltage Lockout (UVLOx) Control

The UVLOx circuit ensures that the device stays disabled before its input or bias supplies reach the minimum

operational voltage range, and ensures that the device properly shuts down when the input supply collapses.

图 66 and 表 6 explain the UVLOx circuit response to various input voltage events, assuming V_EN≥ V_IH(EN)

.

The positive and negative UVLO circuits are internally ANDed together. As such, if either supply collapses, both

outputs turn-off and V_NR/SSis pulled low internally.

UVLOx Rising Threshold

UVLOx Hysteresis

V_INx

C

V_OUTx

tAt

tBt

tDt

tEt

tFt

tGt

图 66. Typical UVLOx Operation

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表 6. Typical UVLOx Operation Description

REGION

EVENT

V_OUTxSTATUS

COMMENT

A

B

Turn-on, |V_INx| ≤ |V_UVLOx

Regulation

|

0

1

Start-up

Regulates to target V_OUTx

Brownout,|V_INx| ≥ |V_UVLOx

–

C

D

1

The output can fall out of regulation but the device is still enabled

Regulates to target V_OUTx

V_HYSx

|

Regulation

The device is disabled and the output falls because of the load and

active discharge circuit. The device is reenabled when the UVLOx

rising threshold is reached by the input voltage and a normal start-

up then follows.

Brownout, |V_INx| < |V_UVLOx

V_HYSx

–

E

0

|

F

Regulation

1

0

Regulates to target V_OUTx

Turn-off, |V_INx| < |V_UVLOx

–

G

The output falls because of the load and active discharge circuit

V_HYSx

|

Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During

this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time;

however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of

the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs

are not fully disabled.

The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall

time of the input supply when operating near the minimum V_INx

.

8.1.9 AC and Transient Performance

LDO ac performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output

isolation, output current transient response, and output noise. These metrics are primarily a function of open-loop

gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The

output noise is primarily a result of the band-gap reference and error amplifier noise.

8.1.9.1 Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control-loop rejects signals from V_INxto V_OUTxacross the frequency

spectrum (usually 10 Hz to 10 MHz). 公式 7 gives the PSRR calculation as a function of frequency for the input

signal [V_INx(f)] and output signal [V_OUTx(f)].

≈

∆

«

’

÷

◊

V

_INx(f)

PSRR (dB) = 20 Log₁₀

V_OUTx(f)

(7)

Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for

convenience.

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图 67 shows a simplified diagram of PSRR versus frequency.

Bandgap RC

Filter

Error Amplifier, Flat-Gain

Region

Error Amplifier,

Gain Roll-off

Output Capacitor

|Z_COUT| Decreasing

Output Capacitor

|Z_COUT| Increasing

Bandgap

10 Hz œ 1 MHz

Sub 10 Hz

100 kHz +

Frequency (Hz)

图 67. Power-Supply Rejection Ratio Diagram

An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply

voltages that exhibit ultra-low noise and ripple to sensitive system components.

8.1.9.2 Channel-to-Channel Output Isolation and Crosstalk

Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting

the other output. This attenuation appears in load transient tests on the other output; however, to numerically

quantify the rejection, the output channel isolation is expressed in decibels (dB).

Output isolation performance is a strong function of the PCB layout. See the Layout Guidelines section on how to

best optimize the isolation performance.

8.1.9.3 Output Voltage Noise

The TPS7A39 is designed for system applications where minimizing noise on the power-supply rail is critical to

system performance. For example, the TPS7A39 can be used in a phase-locked loop (PLL)-based clocking

circuit that can be used for minimum phase noise, or in test and measurement systems where even small power-

supply noise fluctuations reduce system dynamic range.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This

noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions,

thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower

frequencies as a function of 1/f). 图 68 shows a simplified output voltage noise density plot versus frequency.

Wide-band Noise

Integrated Noise

From Bandgap and Error Amplifier

Measurement Noise Floor

Frequency (Hz)

图 68. Output Voltage Noise Diagram

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For further details, see the How to Measure LDO Noise white paper.

8.1.9.4 Optimizing Noise and PSRR

表 7 describes how the ultra-low noise floor and PSRR of the device can be improved in several ways.

表 7. Effect of Various Parameters on AC Performance⁽¹⁾⁽²⁾

NOISE

PSRR

PARAMETER

LOW-

MID-

HIGH-

LOW-

MID-

HIGH-

FREQUENCY

C_NR/SS

C_FFx

+++

No effect

+++

++

+

No effect

+

++

No effect

+

+++

+

+++

+

+++

+

C_OUTx

No effect

+++

++

|V_INx| – |V_OUTx

|

+

+++

PCB layout

++

+

+++

(1) The number of +s indicates the improvement in noise or PSRR performance by increasing the parameter value.

(2) Shaded cells indicate the easiest improvement to noise or PSRR performance.

The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that

filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the

output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with 公式 8.

The effect of the C_NR/SScapacitor increases when V_OUTx(NOM)increases because the noise from the reference is

gained up when the output voltage increases. For low-noise applications, a 10-nF to 1-µF C_NR/SSis

recommended.

f_cutoff= 1 / (2 × π × R_NR/SS× C_NR/SS

)

(8)

The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-

forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing

out the loop bandwidth, thus improving mid-band PSRR.

A larger C_OUTxor multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing

the high-frequency output impedance of the power supply.

Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the

internal circuits. However, a high power dissipation across the die increases the output noise because of the

increase in junction temperature.

Good PCB layout improves the PSRR and noise performance by providing heatsinking at low frequencies and

isolating V_OUTxat high frequencies.

8.1.9.5 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions illustrated in 图

69 are broken down in this section and are described in 表 8. Regions A, E, and H are where the output voltage

is in steady-state. Increasing the output capacitance improves the transient response (less dip); however, the

transient takes longer to recover when using a large output capacitor.

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V_OUTx

B

F

A

C

D

E

G

H

I_OUTx

图 69. Load Transient Waveform

表 8. Load Transient Waveform Description

REGION

DESCRIPTION

COMMENT

A

B

Regulation

Output current ramping

Initial voltage dip is a result of the depletion of the output capacitor charge.

Recovery from the dip results from the LDO increasing its sourcing current, and leads

to output voltage regulation.

C

LDO responding to transient

At high load currents the LDO takes some time to heat up. During this time the output

voltage changes slightly.

D

E

F

Reaching thermal equilibrium

Regulation

Initial voltage rise results from the LDO sourcing a large current, and leads to the

output capacitor charge to increase.

Output current ramping

Recovery from the rise results from the LDO decreasing its sourcing current in

combination with the load discharging the output capacitor.

G

H

LDO responding to transient

Regulation

8.1.10 DC Performance

8.1.10.1 Output Voltage Accuracy (V_OUTx

)

The device features an output voltage accuracy that includes the errors introduced by the internal reference, load

regulation, line regulation, process variation, and operating temperature as specified by the table. Output voltage

accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage

stated as a percent (for very low output voltages this specification is in mV).

8.1.10.2 Dropout Voltage (V_DO

)

Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and

output voltage (|V_DO| = |V_INx| – |V_OUTx|) that is required for regulation. When V_INxdrops below the required V_DOx

for the given load current, the device functions as a resistive switch and does not regulate output voltage.

Dropout voltage is proportional to the output current because the device is operating as a resistive switch.

8.1.11 Reverse Current

As with most LDOs, this device can be damaged by excessive reverse current.

Reverse current is current that flows through the substrate of the device instead of the normal conducting

channel of the pass element. This current flow, at high enough magnitudes, degrades long-term reliability of the

device resulting from risks of electromigration and excess heat being dissipated across the device.

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Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the

absolute maximum rating of V_OUTP> V_INP+ 0.3 V and V_OUTN< V_INN– 0.3 V:

•

If the device has a large C_OUTxand the input supply collapses quickly with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

If excessive reverse current flow is expected in the application, then external protection must be used to protect

the device. 图 70 shows one approach of protecting the device.

Schottky Diode

INP

C_INP

OUTP

Device

C_OUTP

GND

图 70. Example Circuit for Reverse Current Protection Using a Schottky Diode On Positive Rail

8.1.12 Power Dissipation (P_D)

Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on

the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must

be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. Use 公式 9 to approximate P_D:

P_D= (V_INP– V_OUTP) × I_OUTP+ (|V_INN– V_OUTN|) × |I_OUTN

|

(9)

Careful selection of the system voltage rails minimizes power dissipation and improves system efficiency. Proper

selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the device

allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to 公式 10, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (θ_JA) of the combined PCB, device package, and the temperature of the ambient air

(T_A).

T_J= T_A+ θ_JA× P_D

(10)

Unfortunately, this thermal resistance (θ_JA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The θ_JArecorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and

copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-

designed thermal layout, θ_JAis actually the sum of the WSON package junction-to-case (bottom) thermal

resistance (θ_JCbot) plus the thermal resistance contribution by the PCB copper.

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8.1.12.1 Estimating Junction Temperature

The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of

the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are given in the Electrical Characteristics table and are used in accordance with 公式 11.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

where:

•

P_Dis the power dissipated as explained in 公式 9

T_Tis the temperature at the center-top of the device package

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(11)

8.2 Typical Applications

8.2.1 Design 1: Single-Ended to Differential Isolated Supply

TP1

OUTP

FBP

GND

EN

D2

INP

Diode1

Diode3

Diode2

Diode4

10 nF

C_OUTP

+5V

V_INP

SN6505B

VCC

10 …F 0.1 …F

NR/SS

CLK

D1

TPS7A39

3mm x 3mm

10 nF

BUF

FBN

TP2

10 …F 0.1 …F

To

Signal

EN

10 nF

OUTN

INN

C_OUTN

GND

图 71. Single-Ended to Differential Isolated Supply Schematic

8.2.1.1 Design Requirements

表 9. Design Requirements

PARAMETER

Input supply

DESIGN REQUIREMENT

DESIGN RESULT

Must operate off of 5-V input

5-V input supply

Output supply

Positive output

Must have a 5-V and –5-V output

±5-V output, ±2% accuracy

Capable of sourcing 50 mA on positive output

Capable of sinking 50 mA on negative output

Must be isolated from input supply

50 mA (sourcing)

current

Negative output

current

50 mA (sinking)

Isolation from 5-V

supply

Isolated through center tapped transformer

85% efficiency when I_OUTN= –50 mA and I_OUTP

50 mA

=

Efficiency

Must have > 80% efficiency at 100 mA⁽¹⁾

(1) |I_OUTN| = I_OUTP= 50 mA.

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8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Switcher Choice

This design incorporates a push-pull driver for center-tapped transformers that takes a single-ended supply and

converts the supply to an isolated split rail design. The SN6505B provides a simple small-form factor isolated

supply. The input voltage of the SN6505B can vary from 2.25 V to 5 V, which allows for use with a wide range of

input supplies. The output voltage can be adjusted through the turns ratio of the transformer. Based on the

choice of the transformer this design can be used to create output voltages from ±3.3 V to ±15 V. In this design

the SN6505B was paired with the 750315371 center-tapped transformer from Wurth Electronics™. This

transformer has a turns ratio of 1:1.1 and an isolation rating of 2500 V_RMS(the total system isolation was never

tested).

8.2.1.2.2 Full Bridge Rectifier With Center-Tapped Transformer

To create the isolated supply, the SN6505B uses a center-tapped transformer. A full bridge rectifier and

capacitors are required to regulate the signal before reaching the LDO because of the alternating nature of the

input signal. TI recommends having a fast switching and low forward voltage diode to improve efficiency because

of how fast the SN6505 switches; Schottky diodes work well. 图 73 shows the switching nodes of the SN6505 D1

and D2 and also shows where the transformer connects to the full bridge rectifier TP1 and TP2. 图 73 shows the

switching waveforms across the rectifier diodes.

n

V

OUT+

= n·V

IN

V

IN

V

OUT-

= n·V

IN

图 72. Bridge Rectifier With Center-Tapped Secondary Enables Bipolar Outputs

8.2.1.2.3 Total Solution Efficiency

公式 12 shows how the efficiency of the system can be measured by taking the output power and dividing by the

input power. I_OUTP= |I_OUTN| = I_OUT/ 2 because this system has two output rails to simplify the efficiency

measurement. When the necessary parameters are measured, and by using 公式 12, the overall system

efficiency can be plotted as in 图 74. 图 74 shows the overall system efficiency for this design, at the maximum

output current of 100 mA (I_OUTP= 50 mA, I_OUTN= –50 mA) the efficiency of the system is 85%.

η = (I_OUTP× V_OUTP+ I_OUTN× V_OUTN) / (I_IN× V_IN)

(12)

8.2.1.2.4 Feedback Resistor Selection

公式 13 and 公式 14 calculate the values of the feedback resistors.

V_OUTP= V_FBP× (1 + R_1P/ R_2P

)

(13)

(14)

V_OUTN= V_BUF× (–R_1N/ R_2N

)

For this design the recommended 10-kΩ resistors are used for R_2Pand R_2N. R_1Pand R_1Ncan be calculated by

substituting R_2Pand R_2Ninto 公式 15 and 公式 16 because R_2Pand R_2Nare already selected

R_1P= [(V_OUTP/ V_FBP) – 1] × R_2P= [(5 V / 1.188 V) – 1] × 10 kΩ = 32.2 kΩ

R_1N= –V_OUTN× R_2N/ V_BUF= –(–5 V) × 10 kΩ / 1.19 V = 42 kΩ

(15)

(16)

After solving for 公式 15 and 公式 16, the closest one percent resistors are selected, R_1N= 42.2 kΩ and R_1P

32.4 kΩ.

=

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8.2.1.3 Application Curves

100

90

80

70

60

50

40

30

20

10

0

20

D1

D2

TP1

TP2

16

12

8

4

0

-4

-8

-12

-16

-20

0

5

10

15

20

25

Time (ms)

30

35

40

45

50

0

10

20

30

40

50

60

70

80

90 100

I_OUT(mA)

I_OUT= I_OUTP+ |I_OUTN|, I_OUTP= |I_OUTN

|

图 73. Switching Node of the SN6505B

图 74. Efficiency vs Output Current

10

5

V_CC

V_INP

V_OUTP

V_INN

V_OUTN

I_OUT= 50 mA

8

6

2

1

4

0.5

2

0.2

0.1

0

0.05

-2

-4

-6

-8

-10

0.02

0.01

0.005

0.002

0.001

10

100

1k

10k

100k

1M

10M

0

10

20

30

40

50

60

70

80

90 100

Frequency (Hz)

Time (ms)

图 76. OUTP Noise

图 75. System Startup

10

5

I_OUT= 50 mA

2

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

0.001

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

图 77. OUTN Noise

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8.2.2 Design 2: Getting the Full Range of a SAR ADC

OUTP

FBP

V_OUTP= 5.2 V

C_OUTP

INP

C_INP

C_FFP

R_1P

+

6 V

œ

R_2P

NR/SS

C_NR/SS

TPS7A39

BUF

FBN

3mm x 3mm

R_1N

+

3.3 V

œ

C_FFN

EN

R_2N

V_OUTN= -0.2 V

OUTN

INN

C_INN

C_OUTN

GND

1 nF

1 kΩ

Positive

Differential Input

V_OUTP

œ

2.2 Ω

AINP

OPA625

+

10 nF

V_OUTN

+

Vin

œ

OPA625_CM

ADC

10 nF

V_OUTP

+

OPA625

AINN

Negative

Differential Input

2.2 Ω

œ

V_OUTN

1 kΩ

1 nF

图 78. Creating Power Rails for an Analog Front-End of an ADC

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8.2.2.1 Design Requirements

A common problem in analog-to-digital converters (ADCs) is that as the input signal approaches the edge of the

range of the ADC, the signal begins to become distorted. Often times this is not because of a limitation of the

ADC, but is a result of the analog front-end (AFE). In the AFE, the signal begins to approach the rails of the op

amp and the signal begins to lose linearity and becomes distorted. This distortion is because when the rail-to-rail

op amp begins to enter the nonlinear region of operation within 100 mV of the rail, the signal-to-noise ratio (SNR)

starts to degrade and the total harmonic distortion (THD) of the ADC increases. To prevent the op amp from

exiting the linear region of operation, the design must use a power supply that can generate rails 200 mV above

and below the input range of the ADC.

8.2.2.2 Detailed Design Procedure

In this design, the ADS8900B is used as the ADC. This ADC features a differential input, so from a 5-V reference

the ADC is able to encode values between ±5 V. In many applications, single-supply op amps are powered with

rails from 0 V to 5 V, which causes the input signal to become distorted when the full range signal is applied. The

FFT of a 10-V_PP(peak-to-peak) sine wave using a single 5-V rail to bias the amplifiers is illustrated in 图 79. In

this test the SNR was calculated to be 54.89 dB and the THD was calculated to be –40.68 dB.

There is a simple solution to improve the SNR and THD of the ADC: bias the amplifiers in the analog front end

with a 5.2-V rail and a –0.2-V rail. Using these rails allows the amplifier to operate in the linear region in the 0-V

to 5-V range needed by the ADC. The FFT of a 10-V_PPsine wave using a 5.2-V rail and a –0.2-V rail is illustrated

in 图 80. In this test the SNR was calculated to be 102.535 dB and the THD was calculated to be –121.66 dB.

Using –0.2-V and 5.2-V rail voltages still allows for common 5-V (5.5 V max) op amps to be used in the design.

8.2.2.3 Detailed Design Description

8.2.2.3.1 Regulation of –0.2 V

The TPS7A39 has an innovative feature of regulating the negative rail down to zero volts. This regulation is

achieved by using an inverting amplifier and using the positive-buffered reference as the input signal to the

amplifier. Regulating to –0.2 V eliminates the nonlinearity and distortion present when using the full rail range of

the amplifiers.

8.2.2.3.2 Feedback Resistor Selection

Use 公式 17 and 公式 18 to calculate the values of the feedback resistors:

V_OUTP= V_FBP× (1 + R_1P/ R_2P

)

(17)

(18)

V_OUTN= V_BUF× (–R_1N/ R_2N

)

For this design the recommended 10-kΩ resistors are used for R_2Pand R_2N. R_1Pand R_1Ncan be calculated by

substituting R_2Pand R_2Ninto 公式 19 and 公式 20 because R_2Pand R_2Nare already selected.

R_1P= [(V_OUTP/ V_FBP) – 1] × R_2P= [(5.2 V / 1.188 V) – 1] × 10 kΩ = 33.8 kΩ

R_1N= –V_OUTN× R_2N/ V_BUF= –(–5 V) × 10 kΩ / 1.19 V = 1.68 kΩ

(19)

(20)

After solving for 公式 19 and 公式 20, the closest one percent resistors are selected, R_1N= 1.69 kΩ and R_1P= 34

kΩ.

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8.2.2.4 Application Curves

0

-20

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

-100

-120

-140

-160

-180

-200

100

1k

10k

100k

100

1k

10k

100k

Frequency (Hz)

f_IN= 1 kHz, V_PP= 10.0 V

图 79. FFT Using 5-V and 0-V Supply Rails

图 80. FFT Using 5.2-V and –0.2-V Supply Rails

9 Power-Supply Recommendations

The input supply for the LDO must be within the recommended operating conditions. The input voltage must

provide adequate headroom in order for the device to have a regulated output. Place the 10-µF input capacitors

as close to the device as possible. If the input supply is noisy, additional input capacitors can help improve the

output noise performance.

10 Layout

10.1 Layout Guidelines

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing

currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade

the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with capacitors.

Tie the GND pin directly to the thermal pad under the device. The thermal pad must be connected to any internal

PCB ground planes using multiple vias directly under the device.

Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the

regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use

of vias and long traces is strongly discouraged because these circuits can impact system performance

negatively, and even cause instability.

10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the

board be designed with separate ground planes for V_INand V_OUT, with each ground plane star connected only at

the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to

the GND pin of the device.

39

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

10.2 Layout Example

图 81. Layout Example for Adjustable Option

10.3 Package Mounting

Solder pad footprint recommendations for the TPS7A39 are available at the end of this document and at

www.ti.com.

40

TPS7A39

www.ti.com.cn

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

我们提供了一款评估模块 (EVM)，可与 TPS7A39 配套使用，帮助评估初始电路性能。TPS7A39EVM-865 评估模

块（和相关的用户指南）可在德州仪器 (TI) 网站上的产品文件夹中获取，也可直接从 TI 网上商店购买。

11.1.1.2 Spice 模型

分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从产品文件夹中的

工具和软件下获取 TPS7A39 的 SPICE 模型。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

《用于过压和欠压检测且具有内部基准电压的 TPS3701 36V 窗口比较器》

《适用于隔离式电源的 SN6505 低噪声 1A 变压器驱动器》

《具有集成式基准缓冲器和增强性能特性的 ADS890xB 20 位、高速 SAR ADC》

《使用前馈电容器和低压降稳压器的优缺点》

《使用新的热指标》

《TPS7A39EVM-865 用户指南》

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

E2E is a trademark of Texas Instruments.

Wurth Electronics is a trademark of Würth Elektronik GmbH and Co.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

41

TPS7A39

ZHCSGP0A –JULY 2017–REVISED SEPTEMBER 2017

www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

42

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS7A3901DSCR

TPS7A3901DSCT

WSON

DSC

10

3000

250

330.0

180.0

12.4

3.3

1.0

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS7A3901DSCR

TPS7A3901DSCT

WSON

DSC

10

3000

250

367.0

213.0

367.0

191.0

38.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DSC0010J

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

C

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

EXPOSED

THERMAL PAD

4X (0.25)

5

6

2X

2

11

SYMM

2.4 0.1

10

1

8X 0.5

0.30

0.18

10X

SYMM

PIN 1 ID

0.1

C A B

C

(OPTIONAL)

0.05

0.5

0.3

10X

4221826/D 08/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSC0010J

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

1

10

10X (0.24)

11

(2.4)

(3.4)

SYMM

(0.95)

8X (0.5)

6

5

(R0.05) TYP

(

0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221826/D 08/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSC0010J

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

11

10X (0.6)

1

10

(1.53)

10X (0.24)

2X

(1.06)

SYMM

(0.63)

8X (0.5)

6

5

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4221826/D 08/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款

的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	TPS7A3901DSCT
厂家：	TEXAS INSTRUMENTS
描述：	150mA、33V、低噪声、高 PSRR、双通道、正负电压范围、低压降稳压器 \| DSC \| 10 \| -40 to 125 光电二极管输出元件稳压器调节器
文件：	总51页 (文件大小：3999K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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