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TPS65321A-Q1

SLVSE55 –NOVEMBER 2017

TPS65321A-Q1 36-V Step-Down Converter With Eco-mode™ and LDO Regulator

1 Features

2 Applications

1

•

Qualified for Automotive Applications

•

Automotive Infotainment and Cluster

Advanced Driver Assistance System (ADAS)

Automotive Telematics, eCall

•

AEC-Q100 Qualified with the Following Results:

–

Device Temperature Grade 1: –40°C to

+125°C Ambient Operating Temperature

3 Description

–

Device HBM ESD Classification Level 2

Device CDM ESD Classification Level C4B

The TPS65321A-Q1 device is a combination of a

high-VIN DC-DC step-down converter, referred to as

the buck regulator, with an adjustable switch-mode

frequency from 100-kHz to 2.5-MHz, and a high-VIN

280-mA low-dropout (LDO) regulator. The input range

is 3.6 V to 36 V for the buck regulator, and 3 V to

36 V for the LDO regulator. The buck regulator has

an integrated high-side MOSFET with an active-low,

open-drain power-good output-pin (nRST). The LDO

regulator features a low-input supply current of 45-μA

typical in no-load, also has an integrated MOSFET.

Low-voltage tracking feature enables TPS65321A-Q1

to track the input supply during cold-crank conditions.

•

One High-VIN Step-Down DC-DC Converter

–

Input Range of 3.6 V to 36 V

250-mΩ High-Side MOSFET

Maximum Load Current 3.2 A, Output

Adjustable 1.1 V to 20 V

–

Adjustable Switching Frequency 100 kHz to

2.5 MHz

–

Synchronizes to External Clock

High Efficiency at Light Loads With Pulse-

Skipping Eco-mode™ Control Scheme

The buck regulator provides a flexible design to fit

system needs. The external loop compensation circuit

allows for optimization of the converter response for

the appropriate operating conditions. A low-ripple

pulse-skip mode reduces the no-load input-supply

current to maximum 140 μA.

–

Maximum 140-µA Operating Quiescent

Current

Reset Output-Pin (Active Low, Open-Drain)

•

One High-VIN Low-Dropout (LDO) Voltage

Regulator

–

Input Range of 3 V to 36 V

The device has built-in protection features such as

soft start, current-limit, thermal sensing and shutdown

due to excessive power dissipation. Furthermore, the

device has an internal undervoltage-lockout (UVLO)

function that turns off the device when the supply

voltage is too low.

280-mA Current Capability With Typical 35-µA

Quiescent Current in No-Load Condition

–

Low-Dropout Voltage of 300 mV at

I_O= 200 mA (Typical)

•

Overcurrent Protection for Both Regulators

Overtemperature Protection

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

14-Pin HTSSOP Package With PowerPAD™

Integrated Circuit Package

TPS65321A-Q1

HTSSOP (14)

5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Schematic

Buck Efficiency Versus Output Current

V_I= 3.6 V to 36 V

Supply

1.1 V to 20 V,

3.2 A

BOOT

SW

VIN

100

90

80

70

60

50

40

30

20

EN1

Buck

Regulator

Control

FB1

RT/CLK

SS

COMP

RST

1.1 V to 5.5 V,

280 mA

V_I= 3 V to 36 V

Supply

LDO_OUT

VIN_LDO

f_s= 300 kHz

10

f_s= 2 MHz

0

GND

EN2

LDO

Regulator

Control

PowerPAD

0

1

2

3

4

FB2

Load Current (A)

D001

TPS65321-Q1

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65321A-Q1

SLVSE55 –NOVEMBER 2017

www.ti.com

Table of Contents

7.4 Device Functional Modes........................................ 21

Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Application .................................................. 22

Power Supply Recommendations...................... 33

1

2

3

4

5

6

Features.................................................................. 1

8

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 8

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 11

9

10 Layout................................................................... 33

10.1 Layout Guidelines ................................................. 33

10.2 Layout Example .................................................... 34

11 Device and Documentation Support ................. 35

11.1 Documentation Support ........................................ 35

11.2 Receiving Notification of Documentation Updates 35

11.3 Community Resources.......................................... 35

11.4 Trademarks........................................................... 35

11.5 Electrostatic Discharge Caution............................ 35

11.6 Glossary................................................................ 35

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 35

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

November 2017

*

Initial release.

2

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5 Pin Configuration and Functions

PWP Package

14-Pin HTSSOP With Thermal Pad

Top View

BOOT

VIN

1

14

13

12

11

10

9

SW

2

3

4

5

6

7

GND

COMP

FB1

VIN_LDO

LDO_OUT

FB2

Thermal

Pad

SS

nRST

RT/CLK

EN1

EN2

8

Pin Functions

I/O

DESCRIPTION

NAME

NO.

A bootstrap capacitor is required between the BOOT and SW pins to supply the bias voltage for the integrated

high-side MOSFET.

BOOT

1

O

I

The COMP pin is the error-amplifier output of the buck regulator, and the input to the output switch-current

comparator of the buck regulator. Connect frequency-compensation components to the COMP pin.

COMP

EN1

12

8

The EN1 pin is the enable and disable input for the buck regulator (high-voltage tolerant) and is internally

pulled to ground. Pull this pin up externally to enable the buck regulator.

The EN2 pin is the enable and disable input for the LDO regulator (high-voltage tolerant) and is internally

pulled to ground. Pull this pin up externally to enable the LDO regulator.

EN2

7

I

The FB1 pin is the feedback pin of the buck regulator. Connect an external resistive divider between the buck

regulator output, the FB2 pin, and the GND pin to set the desired output voltage of the buck regulator.

FB1

11

5

I

The FB2 pin is the feedback pin of the LDO regulator. Connect an external resistive divider between the

LDO_OUT pin, the FB2 pin, and the GND pin to set the desired output voltage of the LDO regulator.

FB2

I

GND

13

4

—

O

This pin is the ground pin.

LDO_OUT

This pin is the LDO regulator output.

The nRST pin is the active low, open drain reset output of the buck regulator. Connect this pin with an external

bias voltage through an external resistor. This pin is asserted high after the buck regulator begins regulating.

nRST

6

O

Connect this pin to an external resistor to ground to program the switching frequency of the buck regulator. An

alternative option is to feed an external clock to provide a reference for the switching frequency of the buck

regulator.

RT/CLK

9

I

SS

10

14

2

I

Connect this pin to an external capacitor to ground which sets the soft-start time of the buck regulator.

The SW pin is the source node of the internal high-side MOSFET of the buck regulator.

The VIN pin is the input supply pin for the internal biasing and high-side MOSFET of the buck regulator.

The VIN_LDO pin is the input supply pin for the LDO regulator.

SW

I

VIN

—

VIN_LDO

3

Exposed

PowerPAD

Electrically connect the PowerPAD to ground and solder to the ground plane of the PCB for thermal

performance.

—

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6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature (unless otherwise noted)

MIN

–0.3

MAX

40

UNIT

VIN

Supply inputs

V

VIN_LDO

40

EN1, EN2

Control

40

V

EN1-VIN, EN2-VIN

1

FB1

–0.3

3.6

V

–0.3

–2 V for 30 ns

SW

40

BOOT

–0.3

46

8

V

BOOT-SW

COMP

Buck converter

LDO regulator

–0.3

-40

3.6

7

V

SS

V

RT/CLK, SS

nRST

V

LDO_OUT

FB2

7

V

7

V

Operating ambient temperature, T_A

Operating junction temperature, T_J

Storage temperature, T_stg

125

150

165

°C

–40

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

Electrostatic

discharge

V_(ESD)

All pins

V

Corner pins (1, 7, 8, and 14)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

4

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.6

3

MAX

36

42

36

0.8

3

UNIT

VIN

Supply inputs

V

VIN_LDO

BOOT

SW1

FB1

3.6

–1

0

Buck regulator

LDO regulator

SS

0

V

COMP

0

3

RT/CLK

0

3

nRST

0

5.25

5.5

0.8

36

150

LDO_OUT

1.1

0

FB2

EN1

0

Control

V

EN2

0

Temperature

Operating junction temperature range, T_J

–40

°C

6.4 Thermal Information

TPS65321A-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

14 PINS

41.0

33.1

25.4

1.6

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

25.1

2.7

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

V_I= 6 V to 27 V, EN1 = EN2 = V_I, over-operating free-air temperature range T_A= –40°C to 125°C and maximum operating

junction temperature T_J= –150°C, unless otherwise noted. V_Iis the voltage on the battery-supply pins, VIN and VIN_LDO.

PARAMETER

TEST CONDITIONS

MIN

3.6

6

TYP

MAX

UNIT

VIN (INPUT POWER SUPPLY)

Operating input voltage

Normal mode, after initial start-up

V_(EN1)= V_(EN2)= 0 V, 25°C

12

2

36

7

V

μA

V

Shutdown supply current

Initial start-up voltage

36

ENABLE AND UVLO (EN1 AND EN2 PINS)

Enable low level

0.7

V

Enable high level

2.5

1.8

2.2

V_(VIN)(f)

V_(VIN)(r)

Internal UVLO falling threshold

Internal UVLO rising threshold

Ramp V_(VIN)down until output turns OFF

Ramp V_(VIN)up until output turns ON

2.6

2.8

3

3.2

BUCK REGULATOR

Measured at the VIN pin

V_(FB1)= 0.83 V, V_(VIN)= 12 V, 25°C

I_(Qon)

Operating: non-switching supply

110

140

μA

μF

ESR = 0.001 Ω to 0.1 Ω, large output

capacitance may be required for load

transient

Output capacitance

10

Buck regulator output: 1.1 V to 20 V.

Buck regulator in Continuous Conducting

Mode without Pulse-Skipping

V_(ref1)

Voltage reference for FB1 pin

DC output voltage accuracy

0.788

-2

0.8

0.812

2

V

Includes voltage references, DC load and

line regulation, process and temperature

%

DC_(LDR)

T_(LDSR)

DC Load regulation, ΔV_OUT/ V_OUTI_OUT= 0 to I_OUTmax

V_(VIN)= 12V, I_OUT= 200 mA to 3A, T_R

T_F= 1 µs, Buck Output Voltage = 5V, ƒ_S

0.5

5

=

Transient load step response

%

= 2 MHz

BUCK REGULATOR: HIGH-SIDE MOSFET

r_{(DS(on) HS}

FET)

On-resistance

V_(VIN)= 12 V, V_(SW)= 6 V

ƒ_S= 2.5 MHz

127

115

250

mΩ

t_onmin

Minimum on-time

ns

BUCK REGULATOR: CURRENT-LIMIT

Current-limit threshold

V_(VIN)= 12 V, T_J= 25°C

4

6

A

BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

Under RT mode

100

523

300

2500

640

kHz

Under fixed-frequency PWM mode, with

ƒ_S

Switching-frequency range

200 kΩ connected between RT/CLK and

585

GND pins

Under CLK mode

2200

kHz

ns

V

Minimum CLK input pulse width

High threshold

Measures at CLK input = 2.2 MHz

30

1.9

0.7

RT/CLK

2.2

Low threshold

0.5

V

Falling edge to SW rising edge

delay

Measured at 500 kHz with external clock

connected to RT/CLK pin

RT/CLK

PLL

60

ns

Lock-in time

Measured at 500 kHz

100

μs

BUCK REGULATOR: INTERNAL SOFT START TIMER

V_(SS)= 1 V, EN1=0, T_A= 25°C

50

33

400

μA

I_{Discharge(SS)}Soft-start Pin Discharge Current

V_(SS)= 1 V, EN1=0, T_A= 125°C

LDO REGULATOR

V_{(VIN_LDO)}= 6 V to 30 V,

I_{(LDO_OUT)}= 10 mA,

V_{(LDO_OUT)}= 3.3 V

ΔV_O(ΔVI)

Line regulation

20

mV

6

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Electrical Characteristics (continued)

V_I= 6 V to 27 V, EN1 = EN2 = V_I, over-operating free-air temperature range T_A= –40°C to 125°C and maximum operating

junction temperature T_J= –150°C, unless otherwise noted. V_Iis the voltage on the battery-supply pins, VIN and VIN_LDO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{(LDO_OUT)}= 10 mA to 200 mA,

V_{(VIN_LDO)}= 12 V,

ΔV_O(ΔIL)

Load regulation

35

mV

V_{(LDO_OUT)}= 3.3 V

Dropout voltage

(V_{(VIN_LDO)}– V_{(LDO_OUT)}

V_DROPOUT

I_{(LDO_OUT)}

V_{I(VIN_LDO)}

V_(ref2)

I_{(LDO_OUT)}= 200 mA

300

450

280

mV

mA

V

)

Output current

V_{(LDO_OUT)}in regulation, V_(VIN)≥ 4V

V_{(LDO_OUT)}in regulation

Operating input voltage on

VIN_LDO pin

3

0.788

280

36

Voltage reference at FB2 pin

V_{(LDO_OUT)}= 1.1 V to 5.5 V

0.8

35

0.812

1000

V

V_{(LDO_OUT)}= 0 V (the LDO_OUT pin is

shorted to ground)

I_{CL(LDO_OUT)}Output current-limit

mA

V(VIN) = 12 V

Measured at VIN pin

V_(EN1)= 0 V, V_(EN2)= 5 V, I_{(LDO_OUT)}

0.01 mA to 0.75 mA

I_Q(LDO)

Quiescent current

50

μA

=

V_{(VIN_LDO)(rip)}= 0.5 V_PP

,

I_{(LDO_OUT)}= 200 mA,

frequency (ƒ) = 100 Hz,

V_{(LDO_OUT)}= 5 V and V_{(LDO_OUT)}= 3.3 V

60

30

dB

μF

PSRR

Power supply ripple rejection

V_{(VIN_LDO)(rip)}= 0.5 V_PP, I_{(LDO_OUT)}= 200

mA, ƒ = 150 kHz,

V_{(LDO_OUT)}= 5 V and V_{(LDO_OUT)}= 3.3 V

ESR = 0.001 Ω to 100 mΩ, large output

capacitance may be required for load

transient

C_{(LDO_OUT)}Output capacitor

1

40

V_{(LDO_OUT)}≥ 3.3 V

ESR = 0.001 Ω to 100 mΩ, large output

capacitance may be required for load

transient

20

μF

1.2 V ≤ V_{(LDO_OUT)}< 3.3 V

BUCK REGULATOR: RESET (nRST Pin)

RESET threshold

V_(FB1)decreasing

85%

90%

0.045

14

95%

0.4

21

nRST pin asserted low due to falling

V_(FB1), < 1-mA sinking current into nRST

V_OL

Output low

Filter time

0

7

V

Delay before asserting nRST low

μs

OVER TEMPERATURE PROTECTION

T_SD

T_hys

Thermal-shutdown trip point

Hysteresis

175

10

ºC

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6.6 Typical Characteristics

6

5.5

5

100

90

80

70

60

50

40

30

20

10

0

4.5

4

3.5

3

2.5

2

No Load

100-mA Load

1-A Load

1.5

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

3.6

4

4.4

4.8

5.2

5.6

6

Input Voltage (V)

C004

V_FB1(V)

C002

ƒ_S= 2 MHz

3.6 V ≤ V_(VIN)≤ 6 V

V_(VIN)= 12 V

Figure 1. Maximum-Possible Buck-Regulator Output Voltage

Figure 2. Buck-Regulator Switching Frequency vs V_(FB1)

Feedback Voltage

3000

2500

2000

1500

1000

500

0.802

0.8

0.798

0.796

0.794

0

200

400

600

800 1000 1200 1400 1600

-50

-25

0

25

50

75

100

125

150

Junction Temperature (°C)

C003

RT/CLK Resistance (kꢀ)

C007

V_(VIN)= 12 V

T_J= 25°C

No Load

V_(VIN)= 12 V

Figure 3. Buck-Regulator Switching Frequency vs RT_CLK

Resistance

Figure 4. Buck-Regulator Feedback-Voltage Reference

(V_(FB1)) vs Junction Temperature

500

3.302

3.3

450

400

350

300

250

200

150

100

50

3.298

3.296

3.294

3.292

3.29

3.288

3.286

3.284

3.282

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0

50

100

150

200

250

300

350

400

LDO Load Current (A)

LDO Load Current (mA)

C008

C009

V_{(VIN_LDO)}= 5 V

V_{(LDO_OUT)}= 3.3 V

V_{(LDO_OUT)}= 5 V

Figure 5. LDO-Regulator Load Regulation

Figure 6. LDO-Regulator Dropout Voltage vs Load Current

8

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Typical Characteristics (continued)

0.7995

0.799

0.7985

0.798

0.7975

0.797

0.7965

0.796

-50

-25

0

25

50

75

100

125

150

Junction Temperature (°C)

C010

I_{(LDO_OUT)}= 100 mA

V_{(VIN_LDO)}= 12 V

Figure 7. LDO-Regulator Feedback-Voltage Reference (V_(FB2)) vs Junction Temperature

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7 Detailed Description

7.1 Overview

The TPS65321A-Q1 device is a 36-V, 3.2-A, DC-DC step-down converter (also referred to as a buck regulator)

with a 280-mA low-dropout (LDO) linear regulator. Both of these regulators have low quiescent consumption

during a light load to prolong battery life.

The buck regulator improves performance during line and load transients by implementing a constant-frequency

and current-mode control (CCM) that reduces output capacitance which simplifies external frequency-

compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size

optimization when selecting the output-filter components. The switching frequency is adjusted by using a resistor

to ground on the RT/CLK pin. The buck regulator has an internal phase-locked loop (PLL) on the RT/CLK pin

that synchronizes the power-switch turnon to the falling edge of an external system clock.

The TPS65321A-Q1 device reduces the external component count by integrating the boot recharge diode. A

capacitor between the BOOT pin and the SW pin supplies the bias voltage for the integrated high-side MOSFET.

The TPS65321A-Q1 device can operate at high duty cycles under the dropout mode operation. The output

voltage can step-down to as low as the 0.8-V reference. The soft start minimizes inrush currents and provides

power-supply sequencing during power up. Connect a small-value capacitor to the pin to adjust the soft-start

time. For critical power-supply sequencing requirements couple a resistor divider to the pin.

The LDO regulator consumes only about a 35-µA current in light load. The LDO regulator also tracks the battery

when the battery voltage is low (in a cold-crank condition).

The buck regulator of the TPS65321A-Q1 device has a power-good open-drain output (nRST) that asserts low

when the regulated output voltage is less than 90% (typical) of the nominal output voltage.

10

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7.2 Functional Block Diagram

EN1

EN2

VIN

Shutdown

PWRGD

Thermal

UVLO

Shutdown

Logic

UV

OV

Shutdown

Logic

Enable

Threshold

Boot

Charge

Boot

UVLO

Current

Sense

Voltage

Reference

Minimum

Clamp

Pulse Skip

Error

Amplifier

BOOT

PWM

Comparator

FB1

SS

PWM Latch

+

R

Q

SS/TR

Logic

S

SW

Shutdown

Slope

Compensation

ꢀ

OVTO

COMP

Frequency

Shift

Overload

Recovery

Maximum

Clamp

Linear Regulator

Control

LDO_OUT

RST

Oscillator

with PLL

FB1

Voltage

Supervisor

0.8 V

GND

PowerPAD

RT/CLK

VIN_LDO FB2

7.3 Feature Description

7.3.1 Buck Regulator

7.3.1.1 Fixed-Frequency PWM Control

The TPS65321A-Q1 buck regulator uses an adjustable, fixed-frequency peak current-mode control. An internal

voltage reference compares the output voltage through external resistors on the FB1 pin to an error amplifier

which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The device

compares the error amplifier output to the high-side power-switch current. When the power-switch current

reaches the level set by the COMP voltage, the power switch turns off. The COMP pin voltage increases and

decreases as the output current increases and decreases. The device implements a current-limit by clamping the

COMP pin voltage to a maximum level.

7.3.1.2 Slope Compensation Output

The TPS65321A-Q1 buck regulator adds a compensating ramp to the switch-current signal. This slope

compensation prevents sub-harmonic oscillations. The available peak-inductor current remains constant over the

full duty-cycle range.

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Feature Description (continued)

7.3.1.3 Pulse-Skip Eco-mode™ Control Scheme

The TPS65321A-Q1 buck regulator operates in a pulse-skip mode at light load currents to improve efficiency by

reducing switching and gate-drive losses. The design of the TPS65321A-Q1 buck regulator is such that if the

output voltage is within regulation and the peak switch current at the end of any switching cycle is below the

pulse-skipping-current threshold, the buck regulator enters pulse-skip mode. This current threshold is the current

level corresponding to a nominal COMP voltage, or 720 mV. The current at which entry to the pulse-skip mode

occurs depends on switching frequency, inductor selection, output-capacitor selection, and compensation

network.

In pulse-skip mode, the buck regulator clamps the COMP pin voltage at 720 mV, inhibiting the high-side

MOSFET. Further decreases in load current or in output voltage cannot drive the COMP pin below this clamp-

voltage level. Because the buck regulator is not switching, the output voltage begins to decay. As the voltage-

control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the

high-side MOSFET turns on and a switching pulse initiates on the next switching cycle. The peak current is set

by the COMP pin voltage. The output current recharges the output capacitor to the nominal voltage, then the

peak switch current begins to decrease, and eventually falls below the pulse-skip-mode threshold, at which time

the buck regulator enters Eco-mode again.

For pulse-skip-mode operation, the TPS65321A-Q1 buck regulator senses the peak current, not the average or

load current. Therefore, the load current where the buck regulator enters pulse-skip mode is dependent on the

output inductor value. When the load current is low and the output voltage is within regulation, the buck regulator

enters a sleep mode and draws only 140-µA input quiescent current. The internal PLL remains operating when

the buck regulator is in sleep mode.

7.3.1.4 Dropout Mode Operation and Bootstrap Voltage (BOOT)

The TPS65321A-Q1 buck regulator has an integrated boot regulator and requires a small ceramic capacitor

between the BOOT pin and the SW pin to provide the gate-drive voltage for the high-side MOSFET. The BOOT

capacitor recharges when the high-side MOSFET is off and the low-side diode conducts. The value of this

ceramic capacitor must be 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric and

a voltage rating of 10 V or higher because of the stable characteristics over temperature and over voltage.

To improve drop out, the high-side MOSFET of the TPS65321A-Q1 buck regulator remains on for 7 consecutive

switching cycles, and is forced off during the 8th switching cycle to allow the low-side diode to conduct and

refresh the charge on the BOOT capacitor. Because the current supplied by the BOOT capacitor is low, the high-

side MOSFET can remain on before it is required to refresh the BOOT capacitor. The effective duty cycle of the

switching regulator under this operation can be higher than the fixed-frequency PWM operation through skipping

switching cycles.

7.3.1.5 Error Amplifier

The buck converter of the TPS65321A-Q1 buck regulator has a transconductance amplifier acting as the error

amplifier. The error amplifier compares the FB1 voltage to the lower of the internal soft-start (SS) voltage or the

internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 310 µS during normal

operation. During the soft-start operation, the transconductance is a fraction of the normal operating gm. When

the voltage of the voltage on the FB1 pin is below 0.8 V and the buck regulator is regulating using an internal SS

voltage, the gm is 70 µS. For frequency compensation, external compensation components (capacitor with series

resistor and an optional parallel capacitor) must be connected between the COMP pin and the GND pin.

7.3.1.6 Voltage Reference

The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output

of a temperature stable band-gap circuit.

7.3.1.7 Adjusting the Output Voltage

A resistor divider from the output node to the FB1 pin sets the output voltage. TI recommends using 1%

tolerance or better divider resistors. Start with 10 kΩ for the R2 resistor and use Equation 1 to calculate R1. To

improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is

more susceptible to noise, and voltage errors from the FB1 input current are noticeable.

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Feature Description (continued)

V_O- 0.8 (V)

R1= R2 ´

0.8 (V)

where

•

V_O= buck regulator output voltage

(1)

7.3.1.8 Soft-Start Pin (SS)

The TPS65321A-Q1 buck regulator regulates the output voltage by referencing the lower of either the internal

voltage reference or the SS pin voltage. A capacitor on the SS pin to ground implements a soft-start time. The

TPS65321A-Q1 buck regulator has an internal pullup current source of 2 μA that charges the external soft-start

capacitor. Equation 2 shows the calculations for the soft-start time (10% to 90%). The voltage reference (V_ref) is

0.8 V and the soft-start current (I_ss) is 2 μA. The soft-start capacitor must remain lower than 10 nF and greater

than 1 nF.

t_ss(ms) ´ I_ss(µA)

C_ss(nF) =

V

(V) ´ 0.8

ref

where

•

The voltage reference (V_ref) is 0.8 V.

The soft-start current (I_SS) is 2 µA.

(2)

To secure a smooth power up with effective soft-start, the delay between a shutdown event and a consecutive

power-up event (such as recovering from a UVLO event or from a thermal shutdown event) must be long enough

to allow a complete discharge of the soft-start capacitor. The soft-start capacitor is discharged through an internal

FET when the buck is disabled (EN1 = low). Because the FET has a finite resistance, a minimum disable time is

required to allow discharge of the capacitor. In either case, the buck must be disabled for at least 100 μs. For

soft-start capacitance with values higher than 1.5 nF, the discharge time of the capacitor increases linearly as

shown in Figure 8.

600

500

400

300

200

100

0

2

4

6

8

10

12

Soft-Start Capacitance (nF)

D007

Figure 8. Soft-Start Capacitance Value versus Discharge Time

7.3.1.9 Reset Output, nRST

The nRST pin pf the TPS65321A-Q1 is a open-drain output between the nRST pin and the GND pin. The power-

on-reset output asserts low until the output voltage on the FB1 pin exceeds the setting thresholds (91%) and the

deglitch timer has expired. Additionally, whenever the EN1 pin is low or open, nRST immediately asserts low

regardless of the output voltage. If a thermal shutdown occurs because of excessive thermal conditions, this pin

also asserts low. When the nRST is released (not asserted low) an external resistor connected to any external

bias voltage pulls up this nRST pin.

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Feature Description (continued)

7.3.1.10 Overload-Recovery Circuit

The TPS65321A-Q1 buck regulator has an overload recovery (OLR) circuit. The OLR circuit soft-starts the output

from the overload voltage to the nominal regulation voltage on removal of the fault condition. The OLR circuit

discharges the SS pin to a voltage slightly greater than the FB1 pin voltage using an internal pulldown of 382 μA

when the error amplifier changes to a high voltage from a fault condition. On removal of the fault condition, the

output soft starts from the fault voltage to nominal output voltage.

7.3.1.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS65321A-Q1 buck regulator is adjustable over a wide range from

approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is 0.5 V

(typical) and must have a resistor to ground to set the switching frequency. To determine the timing resistance

for a given switching frequency, use Equation 3 or the curves in Figure 2. To reduce the solution size, the user

typically sets the switching frequency as high as possible. However, consider tradeoffs of the supply efficiency,

maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is 100 ns (typical)

and limits the maximum operating input voltage. The frequency-shift circuit also limits the maximum switching

frequency. The following sections discuss more details of the maximum switching frequency.

206033

1.0888

R_T(kW) =

ƒ_S

(kHz)

(3)

7.3.1.12 Overcurrent Protection and Frequency Shift

The TPS65321A-Q1 buck regulator implements current-mode control, which uses the COMP pin voltage to turn

off the high-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch current and COMP pin

voltage are compared. When the peak-switch current intersects the COMP voltage, the high-side switch turns off.

During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP

pin high, increasing the switch current. Internal clamping of the error-amplifier output functions as a switch

current-limit.

The TPS65321A-Q1 buck regulator also implements a frequency shift. The switching frequency is divided by 8,

4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the FB1 pin. During short-circuit events (particularly with

high-input-voltage applications), the control loop has a finite minimum controllable on-time, and the output has a

low voltage. During the switch on-time, the inductor current ramps to the peak current-limit because of the high

input voltage and minimum on-time. During the switch off-time, the inductor typically does not have enough off-

time and output voltage for the inductor to ramp down by the ramp-up amount. The frequency shift effectively

increases the off-time which allows the current to ramp down.

7.3.1.13 Selecting the Switching Frequency

The switching frequency that is selected must be the lower value of the two equations, Equation 4 and

Equation 5. Equation 4 is the maximum switching-frequency limitation set by the minimum controllable on-time.

Setting the switching frequency above this value causes the regulator to skip switching pulses. The device

maintains regulation, but pulse-skipping leads to high inductor current and a significant increase in output ripple

voltage.

Use Equation 5 to calculate the maximum switching frequency limit set by the frequency-shift protection. For

adequate output short-circuit protection at high input voltages, set the switching frequency to a value less than

the ƒ_S(maxshift) frequency. In Equation 5, to calculate the maximum switching frequency one must take into

account that the output voltage decreases from the nominal voltage to 0 volts, and the ƒ_divinteger increases from

1 to 8 corresponding to the frequency shift.

æ

ö æ

ö

÷

ø

(I_L´ R_dc+ V_O+ V_d)

1

ƒ (max skip) =

´

÷ ç

ç

S

t

(V -I_L´ R_hs+ V_d)

è ^onø è

I

where

•

I_L= inductor current

R_dc= inductor resistance

V_I= maximum input voltage

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Feature Description (continued)

•

V_O= buck regulator output voltage

V_d= diode voltage drop

R_hs= FET on resistance (127 mΩ, trypical)

t_on= controllable on-time (100 ns, typical)

(4)

(5)

(I ´ R + V_O(SC)+ V )

æ

ö

æ

ç

è

ö

ƒ_div

L

dc

d

ƒ (shift) =

´

ç

÷

S

ç

÷

t_{on ø}

(V -I_L´ R_hs+ V_d)

I

è

ø

where

•

V_O(SC)= buck regulator output voltage during short-circuit condition

ƒ_div= frequency divide factor (equals 1, 2, 4 or 8)

In Figure 9 the solid line illustrates a typical safe operating area regarding frequency shift and assumes the

output voltage is 0 V, the resistance of the inductor is 0.13 Ω, the FET on-resistance is 0.127 Ω, and the diode

voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping.

2500

2000

1500

1000

500

fsw (Max Skip)

ƒ_S(max skip)

ƒ

(shift)

fsw (Shift)

S

0

10

20

30

40

50

60

C012

Input Voltage (V)

V_O= 3.3 V

I_L= 1 A

Figure 9. Maximum Switching Frequency Versus Input Voltage

7.3.1.14 How to Interface to RT/CLK Pin

The RT/CLK pin synchronizes the buck regulator to an external system clock. To implement the synchronization

feature, connect a square wave to the RT/CLK pin through the circuit network shown in Figure 10. The square-

wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and must have an on-

time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to

2200 kHz. The rising edge of the SW pin synchronizes with the falling edge of the RT/CLK pin signal. Design the

external synchronization circuit in such a way that the device has the default frequency-set resistor connected

from the RT/CLK pin to ground if the synchronization signal turns off. TI recommends using a frequency-set

resistor connected as shown in Figure 10 through a 50-Ω resistor to ground. The resistor must set the switching

frequency close to the external CLK frequency. TI also recommends AC-coupling the synchronization signal

through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces SW

jitter in heavy-load applications when synchronizing to an external clock, and in applications that transition from

synchronizing to RT mode. The first time CLK is pulled above the CLK threshold, the device switches from the

RT resistor frequency to PLL mode. Along with the resulting removal of the internal 0.5-V voltage source, the

CLK pin becomes high-impedance as the PLL starts to lock onto the external signal. Because there is a PLL on

the buck regulator, the switching frequency can be higher or lower than the frequency set with the external

resistor. The buck regulator transitions from the resistor mode to the PLL mode and then increases or decreases

the switching frequency until the PLL locks onto the CLK frequency within 100 ms.

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Feature Description (continued)

When the buck regulator transitions from the PLL mode to the resistor mode, the switching frequency slows

down from the CLK frequency to 150 kHz, then reapplies the 0.5-V voltage. The resistor then sets the switching

frequency. The switching-frequency divisor changes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the

FB1 pin. The buck regulator implements a digital frequency shift to enable synchronizing to an external clock

during standard start-up and fault conditions.

10 …F

4 kꢀ

R

fset

RT/CLK

PLL

External

Clock

50 ꢀ

Source

Figure 10. Synchronizing to a System Clock

7.3.1.15 Overvoltage Transient Protection

The TPS65321A-Q1 buck regulator incorporates an overvoltage transient protection (OVTP) circuit to minimize

voltage overshoot when recovering from output fault conditions or strong unload transients on power-supply

designs with low-value output capacitance. For example, with the buck regulator output overloaded, the error

amplifier compares the actual output voltage to the internal reference voltage. If the FB1 pin voltage is lower than

the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the

error amplifier output to a high voltage, thus requesting the maximum output current. On removal of the condition,

the buck regulator output rises and the error-amplifier output transitions to the steady-state duty cycle. In some

applications, the buck regulator output voltage can respond faster than the error-amplifier output can respond

which leads to possible output overshoot. The OVTP feature minimizes the output overshoot when using a low-

value output capacitor by implementing a circuit to compare the FB1-pin voltage to the OVTP threshold (which is

109% of the internal voltage reference). The FB1 pin voltage exceeding the OVTP threshold disables the high-

side MOSFET, preventing current from flowing to the output and minimizing output overshoot. The FB1 voltage

dropping lower than the OVTP threshold allows the high-side MOSFET to turn on at the next clock cycle.

7.3.1.16 Small-Signal Model for Loop Response

Figure 11 shows an equivalent model for the buck-regulator control loop which can be modeled in a circuit-

simulation program to check frequency response and dynamic load response. The error amplifier is a

transconductance amplifier with a gm_eaof 310 μS. Model the error amplifier using an ideal voltage-controlled

current source. Resistor, R_O, and capacitor, C_O, model the open-loop gain and frequency response of the

amplifier. The 1-mV AC-voltage source between nodes a and b effectively breaks the control loop for the

frequency-response measurements. Plotting c versus a shows the small-signal response of the frequency

compensation. Plotting a versus b shows the small-signal response of the overall loop. Check the dynamic loop

response by replacing R_Lwith a current source that has the appropriate load-step amplitude and step rate in a

time-domain analysis. This equivalent model is only valid for continuous-conduction-mode designs.

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Feature Description (continued)

SW

V_O

Power Stage

gm = 10.5 A/V

ps

a

b

R1

R

ESR

FB1

R

L

œ

C

O

COMP

Error

c

R1

Amplifier

C2

R3

C

O_ea

V

= 0.8 V

ref

+

R

O_ea

C1

gm

ea

310 µA/V

Figure 11. Small-Signal Model for Loop Response

7.3.1.17 Simple Small-Signal Model for Peak-Current Mode Control

Figure 12 shows a simple small-signal model that can be used to understand how to design the frequency

compensation. A voltage-controlled current source (duty cycle modulator) supplying current to the output

capacitor and load resistor can approximate the TPS65321A-Q1 buck regulator power stage. Equation 6 shows

the control-to-output transfer function, which consists of a DC gain, one dominant pole, and one ESR zero. The

quotient of the change in switch current divided by the change in COMP pin voltage (node c in Figure 11) is the

power-stage transconductance. The gm_psfor the TPS65321A-Q1 buck regulator power-stage is 10.5 A/V. Use

Equation 7 to calculate the low-frequency gain of the power stage which is the product of the transconductance

and the load resistance.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This

variation with the load seems problematic at first, but the dominant pole moves with the load current (see

Equation 8). The dashed line in the right half of Figure 12 highlights the combined effect. As the load current

decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same

for the varying load conditions, which makes designing the frequency compensation easier. The type of output

capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation

design. Using high-ESR aluminum-electrolytic capacitors can reduce the number of frequency-compensation

components required to stabilize the overall loop because the phase margin increases from the ESR zero at the

lower frequencies (see Equation 9).

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Feature Description (continued)

V_O

R_ESR

V_C

A_dc

ƒ_P

R_L

gm_ps= 10.5 A/V

C_O

ƒ_Z

Figure 12. Simple Small-Signal Model and Frequency Response for Peak-Current Mode

æ

ç

è

ö

s

1+

÷

2π ´ ƒ_{Z ø}

V_O

V_C

= A_dc

´

æ

ç

è

ö

÷

s

2π ´ ƒ_{P ø}

(6)

(7)

A_dc= gm_ps´ R_L

1

ƒ_{P _mod}

=

2π ´ R_L´ C_O

(8)

(9)

1

ƒ_{Z _mod}

=

2π ´ R_ESR´ C_O

7.3.1.18 Small-Signal Model for Frequency Compensation

The buck regulator of the TPS65321A-Q1 device uses a transconductance amplifier as the error amplifier.

Figure 13 shows compensation circuits. Implementation of Type 2 circuits is most likely in high-bandwidth power-

supply designs. The purpose of loop compensation is to ensure stable operation while maximizing dynamic

performance. Use of the Type 1 circuit is with power-supply designs that have high-ESR aluminum electrolytic or

tantalum capacitors. Equation 10 and Equation 11 show how to relate the frequency response of the amplifier to

the small-signal model in Figure 13. Modeling of the open-loop gain and bandwidth uses R_Oand C_Oshown in

Figure 13. See the Typical Application section for a design example with a Type 2A network that has a low-ESR

output capacitor. For stability purposes, the target must have a loop-gain slope that is –20 dB/decade at the

crossover frequency. Also, the crossover frequency must not exceed one-fifth of the switching frequency (120

kHz in the case of a 600-kHz switching frequency).

For dynamic purposes, the higher the bandwidth, the faster the load-transient response. A large DC gain means

high DC-regulation accuracy (DC voltage changes little with load or line variations). To achieve this loop gain, set

the compensation components according to the shape of the control-output bode plot.

Equation 10 through Equation 20 serve as a reference to calculate the compensation components. R_Oand C1

form the dominant pole (P1). A resistor (R3) and a capacitor (C1) in series to ground work as zero (Z1). In

addition, add a lower-value capacitor (C2) in parallel with R3 to work as an optional pole. This capacitor can filter

noise at switching frequency, and is also required if the output capacitor has high ESR.

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Feature Description (continued)

V_O

R1

FB1

œ

Type 2B

Type 1

Type 2A

gm

ea

COMP

Error

Amplifier

R2

V

= 0.8 V

ref

+

R3

C1

R3

C1

R_O

C2

C_O

Inside TPS65321-Q1

Figure 13. Types of Frequency Compensation

P0

A_ol

P1

A0

Z1

P2

A1

BW

Figure 14. Frequency Response of the Type 2 Frequency Compensation

A_ol(V/V)

R_{O _ ea}

C_{O _ ea}

P0 =

=

gm_ea

(10)

(11)

=

2π ´ BW (Hz)

1

2π ´ R_{O _ ea}´ C_{O _ ea}

(12)

æ

ç

è

ö

2

1+

÷

2π ´ ƒ_{Z1 ø}

EA = A0´

æ

ç

è

ö æ

ö

2

1+

´ 1+

÷ ç

÷

2π ´ ƒ_{P1 ø è}2π ´ ƒ_{P2 ø}

(13)

R2

A0 = gm_ea´ R_{O _ ea}

´

R

1

+

R2

(14)

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Feature Description (continued)

R2

A1= gm_ea´ R_{O _ ea}|| R3 ´

R

1

+

R2

(15)

1

P1=

2π ´ R_{O _ ea}´ C1

(16)

(17)

(18)

1

Z1=

P2 =

2π ´ R3 ´ C1

1

Type 2A

Type 2B

2π ´ R3 ´ C2

1

2π ´ R3 ´ C_{O _ ea}

(19)

(20)

1

P2 =

Type 1

2π ´ R_{O _ ea}´ C2

7.3.2 LDO Regulator

The LDO regulator on the TPS65321A-Q1 device can be used to supply low power consumption rails. The

quiescent current in standby mode is about 35 µA under typical operating condition.

The LDO regulator require both supplies from VIN and VIN_LDO to function. The current capability of the LDO

regulator is 280 mA under the full VIN_LDO input range, while V_(VIN)≥ 4 V. When VIN becomes less than 4 V,

the current capability of the LDO regulator decreases.

7.3.2.1 Charge-Pump Operation

The LDO regulator has an internal charge-pump that turns on or off depending on the input voltage. The charge-

pump switching circuitry does not cause conducted emissions to exceed required thresholds on the input voltage

line. The charge-pump switching thresholds are hysteretic. Figure 15 shows the typical switching thresholds for

the charge pump.

ON

Hysteresis

OFF

8.5

9

V_I(V)

Figure 15. Charge-Pump Switching Thresholds

Table 1. Typical Quiescent Current Consumption

CHARGE PUMP ON

CHARGE PUMP OFF

LDO I_Q

300-µA

35 µA

7.3.2.2 Low-Voltage Tracking

At low input voltages, the regulator drops out of regulation, and the output voltage tracks input minus a drop out

voltage (V_DROPOUT). This feature allows for a smaller input capacitor and can possibly eliminate the need to use a

boost convertor during cold-crank conditions.

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7.3.2.3 Adjusting the Output Voltage

A resistor divider from the output node to the FB2 pin sets the output voltage. TI recommends using 1%

tolerance or better divider resistors. Referring to the schematics in Figure 16, begin with 10 kΩ as the selected

value for the R6 resistor and use Equation 21 to calculate the value of the R5 resistor.

V

- 0.8 (V)

(LDO _ OUT)

R5 = R6 ´

0.8 (V)

(21)

To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator

is more susceptible to noise, and voltage errors from the FB2 input current are noticeable.

7.3.3 Thermal Shutdown

The device implements an internal thermal shutdown as protection if the junction temperature exceeds 170°C

(typical). The thermal shutdown forces the buck regulator to stop switching and disables the LDO regulator when

the junction temperature exceeds the thermal trip threshold. Once the junction temperature decreases below

160°C (typical), the device re-initiates the power-up sequence.

7.3.4 Enable and Undervoltage Lockout

The TPS65321A-Q1 device enable pins (EN1 and EN2) are high-voltage-tolerant input pins with an internal

pulldown circuit. A high input activates the device and turns on the regulators.

The TPS65321A-Q1 device has an internal UVLO circuit to shut down the output if the input voltage falls below

an internally-fixed UVLO-falling threshold level. This UVLO circuit ensures that both regulators are not latched

into an unknown state during low-input-voltage conditions. The regulators power up when the input voltage

exceeds the UVLO-rising threshold level.

7.4 Device Functional Modes

The device has two hardware-enable pins as listed in Table 2. The EN1 pin enables and disables the buck

regulator, and the EN2 pin enables and disables the LDO regulator.

Table 2. Device Operation Modes

BUCK

LDO

REGULATOR

DESCRIPTION

EN1

EN2

0

1

0

1

0

1

Both the buck regulator and the LDO regulator are disabled.

The buck regulator is disabled. The LDO regulator is enabled.

The buck regulator is enabled and the LDO regulator is disabled.

Both the buck regulator and the LDO regulator are enabled.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65321A-Q1 buck regulator operates with a supply voltage of 3.6 V to 36 V. The TPS65321A-Q1 LDO

regulator operates with a supply voltage of 3 V to 36 V V. To reduce power dissipation, TI recommends to use

the output voltage of the buck regulator as the input supply for the LDO regulator. To use the output voltage of

the buck regulator in this way, the selected buck-regulator output voltage must be higher than the selected LDO-

regulator output voltage.

To optimize the switching performance (such as low jitter) in automotive applications with input voltages that

have wide ranges, TI recommends to operate the device at higher frequencies, such as 2 MHz, which also helps

achieve AM-band compliance requirements (that extends until 1.7 MHz).

8.2 Typical Application

8.2.1 2-MHzSwitching Frequency, 9-V to 16-V Input, 3.3-V Output Buck Regulator, 5-V Output LDO

Regulator

This example details the design of a high-frequency switching regulator and linear regulator using ceramic output

capacitors.

V_I= 6 V to 36 V

Supply

L1

3.3 ꢀH

BOOT

SW

C3

0.1 ꢀF

VIN

C8

3.3 V

100 ꢀF

C4

47 ꢀF

C5

47 ꢀF

D1

R1

31.6 kꢁ

EN1

EN2

FB1

R2

10 kꢁ

RT/CLK

SS

R4

47 kꢁ

C1

4.7 nF

R3

22 kꢁ

C6

3.3 nF

COMP

LDO_OUT

FB2

C2 (Optional)

12 pF

V_I= 6 V to 36 V

Supply

5 V

C7

10 ꢀF

VIN_LDO

GND

R5

95.3 kꢁ

C9

4.7 ꢀF

VIO

R6

18 kꢁ

R7

TPS65321-Q1

10 kꢁ

RST

PowerPAD

Figure 16. TPS65321A-Q1 Design Example With 2-MHz Switching Frequency

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Typical Application (continued)

8.2.1.1 Design Requirements

A few parameters must be known to begin the design process. The determination of these parameters is typically

at the system level. This example begins with the parameters listed in Table 3.

Table 3. Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage, VIN1

6 V to 36 V, nominal 12 V

Output voltage, VREG1 (buck regulator)

Maximum output current, I_{O_max1}

Minimum output current, I_{O_min1}

Transient response, 0.01 A to 0.8 A

Output ripple voltage

3.3 V ± 2%

3 A

0.01 A

3%

1%

Switching frequency, ƒ_SW

2 MHz

Input voltage, VIN_LDO

6 V to 36 V, nominal 12 V

5 V ± 2%

Output voltage, VREG2 (LDO regulator)

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Switching Frequency Selection for the Buck Regulator

The first step is to decide on a switching frequency for the regulator. Typically, the user selects the highest

switching frequency possible because this produces the smallest solution size. The high switching frequency

allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a

lower frequency. The selectable switching frequency is limited by the minimum on-time of the internal power

switch, the input voltage, the output voltage, and the frequency-shift limitation.

Consider minimum on-time and frequency-shift protection as calculated with Equation 4 and Equation 5. To find

the maximum switching frequency for the regulator, select the lower value of the two results. Switching

frequencies higher than these values result in pulse skipping or the lack of overcurrent protection during a short

circuit. The typical minimum on-time, t_ON-min, is 100 ns for the TPS65321A-Q1 device. For this example, where

the output voltage is 3.3 V and the maximum input voltage is 36 V, use a switching frequency of 2200 kHz. Use

Equation 3 to calculate the timing resistance for a given switching frequency. The R4 resistor sets the switching

frequency. A 2-MHz switching frequency requires a 47-kΩ resistor (see R4 in Figure 16).

8.2.1.2.2 Output Inductor Selection for the Buck Regulator

Use Equation 22 to calculate the minimum value of the output inductor. The output capacitor filters the inductor

ripple current. Therefore, selecting high inductor-ripple currents impacts the selection of the output capacitor

because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple

current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines

can be used to select this value. K_INDis a coefficient that represents the amount of inductor ripple current relative

to the maximum output current.

V max - V_O

V_O

I

L_Omin =

´

I_O´ K_IND

V max ´ ƒ_S

I

(22)

For designs using low-ESR output capacitors such as ceramics, use a value as high as K_IND= 0.3. When using

higher-ESR output capacitors, K_IND= 0.2 yields better results. In a wide-input voltage regulator, selecting an

inductor ripple current on the larger side is best because it allows the inductor to still have a measurable ripple

current with the input voltage at a minimum.

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For this design example, use K_IND= 0.2 and the minimum inductor value which is calculated as 2.27 µH. For this

design, select standard value which is 3.3 µH (see L1 in Figure 16). Use Equation 23 to calculate the inductor

ripple current (I_ripple). For the output filter inductor, do not to exceed the RMS-current and saturation-current

ratings. Use Equation 24 and Equation 25 to calculate the RMS current (I_L-RMS) and the peak inductor (I_L-peak).

V ´ V max- V

O

(

V max ´ L_o´ ƒ_S

)

O

I

I_ripple

=

I

(23)

1

2

I_L-RMS

=

I_O

+

I_ripple

12

(24)

(25)

I_ripple

2

I_L-peak= I_O+

For this design, the RMS inductor current is 3 A, the peak inductor current is 3.21 A, and the inductor ripple

current is 0.41 A. The selected inductor is a Coilcraft XAL4030-332ME, which has a saturation-current rating of

5.5 A and an RMS-current rating of 5 A. As the equation set demonstrates, lower ripple current reduces the

output ripple voltage of the buck regulator but requires a larger value of inductance. Selecting higher ripple

currents increases the output ripple voltage of the buck regulator but allows for a lower inductance value.

8.2.1.2.3 Output Capacitor Selection for the Buck Regulator

Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines

the modulator pole, the output ripple voltage, and how the buck regulator responds to a large change in load

current. Select the output capacitance based on the most stringent of these three criteria. The desired response

to a large change in the load current is the first criterion. The output capacitor must supply the load with current

when the regulator cannot. This situation occurs if the desired hold-up times are present for the buck regulator. In

this case, the output capacitor must hold the output voltage above a certain level for a specified amount of time

after the input power is removed. The regulator is also temporarily unable to supply sufficient output current if a

large, fast increase occurs affecting the current requirements of the load, such as a transition from no load to full

load. The buck regulator usually requires two or more clock cycles for the control loop to notice the change in

load current and output voltage, and to adjust the duty cycle to react to the change. Size the output capacitor to

supply the extra current to the load until the control loop responds to the load change. The output capacitance

must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable

amount of droop in the output voltage. Use Equation 26 to calculate the minimum output capacitance required to

supply the difference in current.

2 ´ DI_O

C_O

>

ƒ_S´ DV_O

where

•

ΔI_Ois the change in the buck-regulator output current

ƒ_Sis the switching frequency of the buck regulator

ΔV_Ois the allowable change in the buck-regulator output voltage

(26)

For this example, the specified transient load response is a 3% change in V_Ofor a load step from 0.01 A to 0.8

A. For this example, ΔI_O= 0.8 – 0.01 = 0.79 A and ΔV_O= 0.03 × 3.3 = 0.1 V. Using these numbers results in a

minimum capacitance of 7.2 µF. This value does not consider the ESR of the output capacitor in the output

voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum

electrolytic and tantalum capacitors have higher ESR that must be take into consideration.

The catch diode of the regulator cannot sink current. Therefore any stored energy in the inductor produces an

output-voltage overshoot when the load current rapidly decreases. Also, size the output capacitor to absorb the

energy stored in the inductor when transitioning from a high load current to a lower load current. The excess

energy that is stored in the output capacitor increases the voltage on the capacitor. Size the capacitor to maintain

the desired output voltage during these transient periods.

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Use Equation 27 to calculate the minimum capacitance to keep the output voltage overshoot to a desired value.

2

(I_OH-I_OL

2

)

C_O> L_O

´

(V_f²- V²)

i

where

•

L_Ois the output inductance of the buck regulator

I_OHis the output current of the buck regulator under heavy load

I_OLis the output current of the buck regulator under light load

V_fis the final peak output voltage of the buck regulator

V_iis the initial capacitor voltage of the buck regulator

(27)

For this example, the worst-case load step is from 3 A to 0.01 A. The output voltage increases during this load

transition, and the stated maximum in the specification is 3% of the output voltage (see the Electrical

Characteristics table). This makes V_f= 1.03 × 3.3 = 3.4 V_iis the initial capacitor voltage, which is the nominal

output voltage of 3.3 V. Using these numbers in Equation 27 yields a minimum capacitance of 30 µF.

Equation 28 calculates the minimum output capacitance needed to meet the output ripple-voltage specification.

Equation 28 yields 0.8 µF.

1

C_O

>

´

V_O-ripple

8´ ƒ_S

I_L-ripple

where

•

V_O-rippleis the maximum allowable output ripple voltage of the buck regulator

I_L-rippleis the inductor ripple current of the buck regulator

(28)

Use Equation 29 to calculate the maximum ESR required for the output capacitor to meet the output voltage

ripple specification. As a result of Equation 29, the ESR should be less than 80 mΩ.

V_O-ripple

R_ESR<

I_L-ripple

(29)

The most stringent criterion for the output capacitor is 30 µF of capacitance to keep the output voltage in

regulation during a load transient.

Factor in additional capacitance deratings for aging, temperature, and DC bias which increase this minimum

value. For this example, two 47-µF, 25-V ceramic capacitors with 3 mΩ of ESR are used (see C4 and C5 in

Figure 16). Capacitors generally have limits to the amount of ripple current they can handle without failing or

producing excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor

data sheets specify the root-mean-square (RMS) value of the maximum ripple current.

Use Equation 30 to calculate the RMS ripple current that the output capacitor must support. For this application,

Equation 30 yields 119 mA.

V_O´ (V max - V_O)

I

I_CO(RMS)

<

12 ´ V max ´ L_O´ ƒ_S

I

(30)

8.2.1.2.4 Catch Diode Selection for the Buck Regulator

The TPS65321A-Q1 device requires an external catch diode between the SW pin and GND (see D1 in

Figure 16). The selected diode must have a reverse voltage rating equal to or greater than V_Imax. The peak

current rating of the diode must be greater than the maximum inductor current. The diode should also have a low

forward voltage. Schottky diodes are typically a good choice for the catch diode because of low forward voltage

of these diodes. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage is. Although the

design example has an input voltage up to 36 V, select a diode with a minimum of 40-V reverse voltage to allow

input voltage transients up to the rated voltage of the TPS65321A-Q1 device.

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For the example design, the selection of a Schottky diode is SL44-E3/57 based on the low forward voltage of this

diode. This diode is also available in a larger package size, which has better thermal characteristics. The typical

forward voltage of the SL44-E3/57 is 0.44 V.

Also, select a diode with an appropriate power rating. The diode conducts the output current during the off-time

of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the

output voltage, and the switching frequency. The output current during the off-time, multiplied by the forward

voltage of the diode, equals the conduction losses of the diode. At higher switching frequencies, consider the AC

losses of the diode. The AC losses of the diode are because the charging and discharging of the junction

capacitance and reverse recovery.

8.2.1.2.5 Input Capacitor Selection for the Buck Regulator

The TPS65321A-Q1 device requires a high-quality ceramic input decoupling capacitor (type X5R or X7R) of at

least 3 µF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance

includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input

voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the

TPS65321A-Q1 device. Use Equation 31 to calculate the input ripple current (I_CI(RMS)).

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. Minimize the capacitance variations because of temperature by selecting a dielectric material that is

stable over temperature. Designers usually select X5R and X7R ceramic dielectrics for power regulator

capacitors because these capacitors have a high capacitance-to-volume ratio and are fairly stable over

temperature. Also, select the output capacitor with the DC bias taken into consideration. The capacitance value

of a capacitor decreases as the DC bias across a capacitor increases.

This design requires a capacitor with at least a 40-V voltage rating to support the maximum input voltage.

Common standard capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, 63V, or 100 V. For this

design example. The selection for this example is a 100-µF, 50-V capacitor (see C8 in Figure 16).

V_O

(V min- V_O)

I

I_CI(RMS)= I_Omax ´

´

V min

I

(31)

The input-capacitance value determines the input ripple voltage of the regulator. Use Equation 32 to calculate the

input ripple voltage (ΔV_I).

I_Omax ´ 0.25

DV =

I

C_I´ ƒ_S

(32)

Using the design example values, I_Omax= 3 A, C_I= 100 µF, ƒ_S= 2200 kHz, yields an input ripple voltage of 3.4

mV and an RMS input ripple current of 1.49 A.

8.2.1.2.6 Soft-Start Capacitor Selection for the Buck Regulator

The soft-start capacitor determines the minimum amount of time required for the output voltage to reach the

nominal programmed value during power up which is useful if a load requires a controlled-voltage slew rate. This

feature is also useful if the output capacitance is large and requires large amounts of current to charge the

capacitor quickly to the output voltage level. The large currents required to charge the capacitor may make the

TPS65321A-Q1 device reach the current limit, or excessive current draw from the input power supply may cause

the input voltage rail to sag. Limiting the output voltage-slew rate solves both of these problems.

The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output

voltage without drawing excessive current. Use Equation 33 to calculate the minimum soft-start time, t_ss, required

to charge the output capacitor, C_O, from 10% to 90% of the output voltage, V_O, with an average load current of

I_o(avg)

.

C_O´ V_O´ 0.8

>

I_O(avg)

t_ss

(33)

In the example, to charge the effective output capacitance of 94 µF up to 3.3 V while allowing the average output

current to be 3 A requires a 0.083 ms soft-start time.

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When the soft-start time is known, use Equation 2 to calculate the soft-start capacitor. For the example circuit,

the soft-start time is not too critical because the output-capacitor value is 2 × 47 µF, which does not require much

current to charge to 3.3 V. The example circuit has the soft-start time set to an arbitrary value of 1 ms, which

requires a 3.125 nF soft-start capacitor. This design uses the next-larger standard value of 3.3 nF.

8.2.1.2.7 Bootstrap Capacitor Selection for the Buck Regulator

Connect a 0.1-µF ceramic capacitor between the BOOT and SW pins for proper operation. TI recommends using

a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage

rating.

8.2.1.2.8 Output Voltage and Feedback Resistor Selection for the Buck Regulator

The voltage divider of R1 and R2 sets the output voltage. For the design example, the selected value of R2 is 10

kΩ, and the calculated value of R1 is 32.1 kΩ. Because of current leakage of the FB1 pin, the current flowing

through the feedback network should be greater than 1 μA to maintain the output-voltage accuracy. Selecting

higher resistor values decreases the quiescent current and improves efficiency at low output currents, but can

introduce noise immunity problems.

8.2.1.2.9 Frequency Compensation Selection for the Buck Regulator

Several possible methods exist to design closed loop compensation for DC-DC converters. The method

presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the buck

regulator. Ignoring the slope compensation usually causes the actual crossover frequency to be lower than the

crossover frequency used in the calculations. This method assumes the crossover frequency is between the

modulator pole and the ESR zero, and that the ESR zero is at least 10 times greater than the modulator pole.

To begin, use Equation 34 to calculate the modulator pole, ƒ_{P_mod}, and Equation 35 to calculate the ESR zero,

ƒ_{z_mod}

.

I_max

1

ƒ_{P _mod}

=

2π ´ R_L´ C_O2π ´ V_O´ C_O

(34)

(35)

1

ƒ_{Z _mod}

=

2π ´ R_ESR´ C_O

Use Equation 36 and Equation 37 to calculate an estimate starting point for the crossover frequency, ƒ_CO, to

design the compensation.

ƒ_CO

=

ƒ_{P _mod}´ ƒ_{Z _mod}

(36)

ƒ_S

´

ƒ_CO

=

ƒ_{P _mod}

2

(37)

For the example design, ƒ_{P_mod}is 1.54 kHz and ƒ_{Z_mod}is 564 kHz. Equation 36 is the geometric mean of the

modulator pole and the ESR zero and Equation 37 is the mean of the modulator pole and the switching

frequency. Equation 36 yields 29.5 kHz and Equation 37 results 41.1 kHz. Use the lower value of Equation 36 or

Equation 37 for an initial crossover frequency.

For this example, the target ƒ_COvalue is 29.5 kHz. Next, calculate the compensation components. Use a resistor

in series with a capacitor to create a compensating zero. A capacitor in parallel to these two components forms

the compensating pole.

The total loop gain, which consists of the product of the modulator gain, the feedback voltage-divider gain, and

the error amplifier gain at ƒ_COequal to 1. Use Equation 38 to calculate the compensation resistor, R3 (see the

schematic in Figure 16).

æ

ç

è

ö

÷

ø

æ

ç

è

ö

2π ´ ƒ_CO´ C_O

V_O

R3 =

´

÷

gm_ps

V

ref

´ gm_{ea ø}

(38)

Assume the power-stage transconductance, gm_ps, is 10.5 S. The output voltage (V_O), reference voltage (V_ref),

and amplifier transconductance, (gm_ea) are 3.3 V, 0.8 V, and 310 μS, respectively. The calculated value for R3 is

22.1 kΩ. For this design, use a value of 22 kΩ for R3. Use Equation 39 to set the compensation zero to the

modulator pole frequency.

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1

C1=

2π ´ R3 ´ ƒ_{P _mod}

(39)

Equation 37 yields 4.69 nF for compensating capacitor C1 (see the schematic in Figure 16). For this design,

select a value of 4.7 nF for C1.

To implement a compensation pole as needed, use an additional capacitor, C2, in parallel with the series

combination of R3 and C1. Use Equation 40 and Equation 41 to calculate the value of C2 and select the larger

resulting value to set the compensation pole. Type 2B compensation does not use C2 because it would demand

a low ESR of the output capacitor.

C_O´ R_ESR

C2 =

R3

(40)

(41)

1

C2 =

π ´ R3 ´ ƒ_S

8.2.1.2.10 LDO Regulator

Depending on the end application, use different values of external components can be used. To program the

output voltage, carefully select the feedback resistors, R5 and R6 (see the schematic in Figure 16). Using smaller

resistors results in higher current consumption, whereas using very large resistors impacts the sensitivity of the

regulator. Therefore selecting feedback resistors such that the sum of R5 and R6 is between 20 kΩ and 200 kΩ

is recommended.

If the desired regulated output voltage is 5 V on selecting R6, the value of R5 can be calculated. With V_ref= 0.8 V

(typical), V_O= 5 V, and selecting R6 = 18 kΩ, the calculated value of R5 is 95.3 kΩ.

An output capacitor for the LDO regulator is required (see C10 in Figure 16) to prevent the output from

temporarily dropping down during fast load steps. TI recommends a low-ESR ceramic capacitor with dielectric of

type X5R or X7R. Additionally, a bypass capacitor can be connected at the output to decouple high-frequency

noise based on the requirements of the end application.

8.2.1.2.11 Power Dissipation

8.2.1.2.11.1 Power Dissipation Losses of the Buck Regulator

Use the following equations to calculate the power dissipation losses for the buck regulator. These losses are

applicable for continuous-conduction-mode (CCM) operation.

1. Conduction loss:

P_CON= I_O²× r_DS(on)× (V_O/ V_I)

where

•

I_Ois the buck regulator output current

V_Ois the buck regulator output voltage

V_Iis the input voltage

(42)

(43)

2. Switching loss:

P_SW= ½ × V_I× I_O× (t_r+ t_f) × f_S

where

•

t_ris the FET switching rise time (t_rmaximum = 20 ns)

t_fis the FET switching fall time (t_fmaximum = 20 ns)

ƒ_Sis the switching frequency of the buck regulator

3. Gate drive loss:

P_Gate= V_drive× Q_g× ƒ_sw

where

•

V_driveis the FET gate-drive voltage (typically V_drive= 6 V)

Q_g= 1 × 10^–9(nC, typical)

(44)

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8.2.1.2.12 Power Dissipation Losses of the LDO Regulator

P_LDO= (V_{VIN_LDO}– V_{(LDO_OUT)}) × I_{(LDO_OUT)}

(45)

8.2.1.2.13 Total Device Power Dissipation Losses and Junction Temperature

1. Supply loss:

P_IC= V_I× I_Q-normal

(46)

(47)

2. Total power loss:

P_Total= P_CON+ P_SW+ P_Gate+ P_LDO+ P_IC

For a given operating ambient temperature T_A:

T_J= T_A+ R_th× P_Total

where

•

T_Jis the junction temperature in °C

T_Ais the ambient temperature in °C

R_this the thermal resistance of package in (°C/W)

P_Totalis the total power dissipation (W)

(48)

For a given maximum junction temperature T_J-max= 150°C, the allowed Total power dissipation is given as:

T_A-max= T_J-max-R_th× P_Total

(49)

where

•

T_A-maxis the maximum ambient temperature in °C

T_J-maxis the maximum junction temperature in °C

(50)

Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the Schottky

diode, and trace resistance that impact the overall efficiency of the regulator.

Figure 17 shows the thermal derating profile of the 14-pin HTSSOP Package With PowerPAD™ . It is important

to consider additional cooling strategies if necessary to maintain the junction temperature of the device below the

maximum junction temperature of 150 °C.

3

2.5

2

1.5

1

0.5

0

25

50

75

100

125

150

Ambient Temperature (èC)

Figure 17. Thermal Derating Profile ofTPS65321A-Q1 in 14-pin HTSSOP Package With PowerPAD

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8.2.1.3 Application Curves

EN1

Buck_out

SS

Buck_out

5 V/div

1 V/div

200 mV/div

I_load

1 V/div

200 mA/div

I_load

1 A/div

100 µs/div

ƒ_S= 2 MHz Buck Output Voltage = 5 V

1 ms/div

Figure 19. Buck-Regulator Startup Operation

Figure 18. Buck Regulator Output at Load Transient

(200 mA to 3 A)

EN2

50 mV/div

LDO_out

5 V/div

2 V/div

LDO_out

I_load

200 mA/div

I_load

200 mA/div

400 µs/div

Figure 20. LDO Regulator Startup Operation

10 µs/div

V_{(LDO_OUT)}= 5 V

Figure 21. LDO-Regulator Output at Load Transient

(50 mA to 300 mA)

100

90

80

70

60

50

40

30

20

10

0

f = 300 kHz

sw = 300kHz

S

f = 2 MHz

sw = 2MHz

S

0.0

1.0

2.0

3.0

4.0

C001

Output Current (A)

Figure 22. Buck Efficiency Versus Output Current

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8.2.2 Design Example With 500-kHz Switching Frequency

C51

0.1 ꢀF

U01

TPS65321QPWPRQ1

TP_SW

6V5

L04 33 …F

VIO

10 kꢁ

VIN

D800

B340A-13-F

6.5 V at 1 A

1

2

3

4

5

6

7

14

13

12

11

10

9

BOOT

VIN

SW

MSS1048-103MLB

C57

9 V to 18 V (40 V PK)

J2

GND

J1

C60

1 ꢀF

C59

22 ꢀF

C63

22 ꢀF

2

1

V_CAM

GND

220 pF

2

1

R55

49.9 ꢁ

C50

47 …F

C1

0.1 …F

GND

VBATT

VIN_LDO COMP

TP_PM1

LDO_OUT

FB2

FB1

SS

FB1

R57

10 ꢁ

C58

22 ꢀF

C62

22 ꢀF

GND

C52

47 nF

GND

R48

240 kꢁ

RST

RT/CLK

EN1

8

R54

360 kꢁ

EN2

C53

3V3

56 pF

C54

0.01 …F

FB1

VFB 800 mV

R62

240 kꢁ

J3

2

1

F_CO8.7 kHz

PM > 80 Degs

GM < œ15 dB

R50

75 kꢁ

C61

10 …F

3.3 V at 250 mA

R56

12 kꢁ

R53

51 kꢁ

VIN

GND1

GND2

F_SW500 kHz

GND

R55 is for test purposes only.

Figure 23. TPS65321A-Q1 Design Example With 500-kHz Switching Frequency

8.2.2.1 Design Requirements

This example begins with the parameters listed in Table 4.

Table 4. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

9 V to 18 V, typical 12 V

6.5 V ± 2%

Input voltage, VIN1

Output voltage, VREG1 (buck regulator)

Maximum output current I_{O_max1}

Minimum output current I_{O_min1}

Transient response 0.01 A to 1 A

Output ripple voltage

1 A

0.01 A

3%

1%

Switching frequency ƒ_SW

500 kHz

Output voltage, VREG2 (LDO regulator)

Overvoltage threshold

3.3 V ± 2%

106% of output voltage

91% of output voltage

Undervoltage threshold

8.2.2.2 Detailed Design Procedure

For the 500-kHz switching-frequency design, make the adjustments as outlined in the following sections. For

sections such as LDO-component calculations, bootstrap-capacitor selection, and others that are not listed in this

section, see the 2-MHzSwitching Frequency, 9-V to 16-V Input, 3.3-V Output Buck Regulator, 5-V Output LDO

Regulator section.

8.2.2.2.1 Selecting the Switching Frequency

For 500-kHz operation, use a 240-kΩ resistor which is calculated using Equation 3. The R62 resistor sets this

switching frequency.

8.2.2.2.2 Output Inductor Selection

Using Equation 22, the inductor value is calculated as 27.7 μH with K_IND= 0.3. This design example can allow for

a higher ripple current, therefore, select the nearest standard value of 33 µH. The RMS and peak inductor-

current ratings are calculated using Equation 24 and Equation 25 which result in 1.00 A and 1.13 A, respectively.

The value of the output-filter inductor must not exceed the RMS-current and saturation-current ratings.

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8.2.2.2.3 Output Capacitor

For this example, the specified transient load response is a 3% change in V_Ofor a load step from 0.01 A to 1 A

(full load). For this example, ΔI_O= 1 – 0.01 = 0.99 A and ΔV_O= 0.03 × 6.5 = 0.195 V. Using these numbers

results in a minimum capacitance of 20.31 μF. This value does not consider the ESR of the output capacitor in

the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Aluminum electrolytic and tantalum capacitors have higher ESR that should be considered. The catch diode of

the regulator cannot sink current, so any stored energy in the inductor produces an output-voltage overshoot

when the load current rapidly decreases. Also, size the output capacitor to absorb the energy stored in the

inductor when transitioning from a high load current to a lower load current. The excess energy that is stored in

the output capacitor increases the voltage on the capacitor. Size the capacitor to maintain the desired output

voltage during these transient periods. Use Equation 27 to calculate the minimum capacitance to keep the output

voltage overshoot to a desired value.

For this example, the worst-case load step is from 1 A to 0.01 A. The output voltage increases during this load

transition, and the stated maximum in our specification is 3% of the output voltage resulting in V_f= 1.03 × 6.5 =

6.7. The initial capacitor voltage, V_i, is the nominal output voltage of 5 V. Using these values, Equation 27 yields

a minimum capacitance of 3.88 μF. Equation 28 calculates the minimum output capacitance required to meet the

output ripple-voltage specification. Equation 28 yields 10.6 μF. Equation 29 calculates the maximum ESR an

output capacitor can have to meet the output ripple-voltage specification. Equation 29 indicates the ESR should

be less than 60.2 mΩ.

The most stringent criterion for the output capacitor is 20.31 μF of capacitance to keep the output voltage in

regulation during a load transient.

Factor in additional capacitance deratings for aging, temperature, and DC bias which increase this minimum

value. For this example, four 22-μF, 25-V and one 1-µF, 25-V ceramic capacitors with 10 mΩ of ESR are used.

Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the

RMS value of the maximum ripple current. Use Equation 30 to calculate the RMS ripple current that the output

capacitor must support. For this design example, Equation 30 yields 240 mA.

8.2.2.2.4 Compensation

This design example use a different approach for calculating compensation values, beginning with the desired

crossover frequency. Ensure that the crossover frequency is maintained at 10 kHz to provide reasonable phase

margin (PM). To achieve circuit stability, a phase margin greater than 60 degrees and a gain margin less than 15

dB is required. Next, place the zero close to the load pole. The zero is determined using C52 and R56. For this

example, select a value of 10 kΩ for R56 which results in a value of approximately 4.7 nF for C52. The pole,

resulting from C53 and R56, can be placed between 10 times the crossover frequency and 1/3 of the switching

frequency. The gain is adjusted to be maintained over 60 degrees of phase margin and –15 dB of gain margin.

The resulting value of C53 is approximately 100 pF for a pole frequency of 159 kHz.

Use the following component values:

R56 = 12 kΩ

C53 = 56 pF

C52 = 47 nF

32

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SLVSE55 –NOVEMBER 2017

8.2.2.3 Application Curve

98

96

94

92

90

88

86

84

82

80

V_IN= 9 V

V_IN= 13.8 V

V_IN= 18 V

0

0.2

0.4

0.6

0.8

1

Output Current (A)

D001

Figure 24. Efficiency vs Output Current

9 Power Supply Recommendations

The buck regulator is designed to operate from an input voltage supply range between 3.6 V and 36 V. The

linear regulator is designed to operate from an input supply voltage up to 36 V. Both input supplies must be well

regulated. If the input supply connected to the VIN pin is located more than a few inches from the TPS65321A-

Q1 converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An

electrolytic capacitor with a value of 100 μF is a typical choice.

10 Layout

10.1 Layout Guidelines

TI recommends the guidelines that follow for PCB layout of the TPS65321A-Q1 device.

•

Inductor

Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors can also be used, however,

these inductors must have low-EMI characteristics and be located away from the low-power traces and

components in the circuit.

•

Input Filter Capacitors

Locate input ceramic filter capacitors close to the VIN pin. TI recommends surface-mount capacitors to

minimize lead length and reduce noise coupling.

Feedback

Route the feedback trace for minimum interaction with any noise sources associated with the switching

components. TI recommends to place the inductor away from the feedback trace to prevent creating an EMI

noise source.

•

Traces and Ground Plane

All power (high-current) traces must be as thick and short as possible. The inductor and output capacitors

must be as close to each other as possible to reduce EMI radiated by the power traces because of high

switching currents. In a two-sided PCB, TI recommends using ground planes on both sides of the PCB to

help reduce noise and ground loop errors. The ground connection for the input capacitors, output capacitors,

and device ground should connect to this ground plane, where the connection between input capacitors and

the catch-diode is the most critical. In a multi-layer PCB, the ground plane separates the power plane (where

high switching currents and components are) from the signal plane (where the feedback trace and

components are) for improved performance. Also, arrange the components such that the switching-current

loops curl in the same direction. Place the high-current components such that during conduction the current

path is in the same direction. This placement prevents magnetic field reversal caused by the traces between

the two half-cycles, and helps reduce radiated EMI.

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10.2 Layout Example

Buck Regulator

Output Capacitor

V_O(BUCK)

Power

Ground

Buck Regulator

Output Inductor

Buck Regulator

Catch Diode

V_I

Input Capacitors

Buck

Regulator

BOOT

Capacitor

14

BOOT

SW

1

2

3

4

5

6

7

Buck

Regulator

Resistor

Feedback

Network

Analog Ground Trace

VIN

GND

COMP

FB1

13

12

Exposed

Thermal Pad

Area

VIN_LDO

LDO_OUT

FB2

V_O(LDO)

11

10

Buck Regulator

Soft-Start Capacitor

SS

LDO

LDO Regulator

Regulator

RT/CLK

EN1

9

8

RST

EN2

Buck Regulator

Compensation Components

Output Capacitor

Resistor

Feedback

Network

Buck Regulator Switching

Frequency Resistor

Analog Ground Trace

Figure 25. TPS65321A-Q1 Layout Example

Figure 26. TPS65321A-Q1 Layout Example

Top Side

Figure 27. TPS65321A-Q1 Layout Example

Bottom Side

34

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Interfacing TPS57xxx-Q1,TPS65320-Q1 Family, and TPS65321-Q1 Devices With Low

Impendence External Clock Drivers application report

•

Texas Instruments, Low Quiescent Current with Asynchronous Buck Converters at High Temperatures

application report

•

Texas Instruments, TPS65321EVM (HVL125A) User Guide

Texas Instruments, TPS65321-Q1 Design Checklist

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following packaging information and addendum reflect the most current data available for the designated

devices. This data is subject to change without notice and revision of this document.

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Product Folder Links: TPS65321A-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65321AQPWPRQ1 HTSSOP PWP

14

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 14

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TPS65321AQPWPRQ1

2000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

PWP 14

4.4 x 5.0, 0.65 mm pitch

PowerPAD TSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224995/A

www.ti.com

PACKAGE OUTLINE

PWP0014G

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

12X 0.65

14

1

2X

5.1

4.9

3.9

NOTE 3

7

8

0.30

14X

0.19

4.5

4.3

B

0.1

C A B

SEE DETAIL A

(0.15) TYP

4X (0.4)

NOTE 5

4X (0.05)

NOTE 5

8

7

THERMAL

PAD

0.25

GAGE PLANE

2.548

1.708

15

1.2 MAX

0.15

0.05

0 - 8

14

1

0.75

0.50

DETAIL A

(1)

TYPICAL

2.558

1.718

4223314/A 09/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ and may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0014G

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(2.56)

SYMM

SEE DETAILS

14X (1.5)

1

14

14X (0.45)

(1.1)

TYP

15

SYMM

(2.55)

(5)

NOTE 9

12X (0.65)

8

7

(

0.2) TYP

VIA

(R0.05) TYP

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-14

4223314/A 09/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0014G

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(2.56)

BASED ON

0.125 THICK

STENCIL

14X (1.5)

(R0.05) TYP

1

14

14X (0.45)

15

(2.55)

SYMM

BASED ON

0.125 THICK

STENCIL

12X (0.65)

8

7

SEE TABLE FOR

METAL COVERED

BY SOLDER MASK

SYMM

(5.8)

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.86 X 2.85

2.56 X 2.55 (SHOWN)

2.34 X 2.33

0.125

0.15

0.175

2.16 X 2.16

4223314/A 09/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

PWP0014K

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX

AREA

SEATING

PLANE

12X 0.65

14

1

2X

5.1

4.9

3.9

NOTE 3

7

8

0.30

14X

0.19

4.5

4.3

B

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X (0.6)

NOTE 5

2X (0.4)

NOTE 5

THERMAL

PAD

7

8

0.25

1.2 MAX

GAGE PLANE

2.59

1.89

15

0.15

0.05

0.75

0.50

0 -8

A

20

1

14

DETAIL A

TYPICAL

2.6

1.9

4229706/A 06/2023

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0014K

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(2.6)

METAL COVERED

BY SOLDER MASK

SYMM

14X (1.5)

(1.2) TYP

14

14X (0.45)

1

(5)

NOTE 9

(R0.05) TYP

SYMM

(0.6)

15

(2.59)

12X (0.65)

7

8

(

0.2) TYP

VIA

SEE DETAILS

(1.1) TYP

SOLDER MASK

DEFINED PAD

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4229706/A 06/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0014K

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(2.6)

BASED ON

0.125 THICK

STENCIL

METAL COVERED

BY SOLDER MASK

14X (1.5)

14X (0.45)

14

1

(R0.05) TYP

(2.59)

SYMM

15

BASED ON

0.125 THICK

STENCIL

12X (0.65)

7

8

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 12X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.91 X 2.90

2.60 X 2.59 (SHOWN)

2.37 X 2.36

0.125

0.15

0.175

2.20 X 2.19

4229706/A 06/2023

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65321AQPWPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	采用宽输入电压范围、280mA LDO 稳压器的汽车类 3.6V 至 36V 3.2A 降压转换器 \| PWP \| 14 \| -40 to 125 开关光电二极管输出元件转换器稳压器
文件：	总46页 (文件大小：4910K)
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