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TPS65311-Q1

SLVSCA6C –OCTOBER 2013–REVISED OCTOBER 2017

TPS65311-Q1 High-Voltage Power-Management IC for Automotive Applications

1 Features

2 Applications

1

•

Qualified for Automotive Applications

•

Multi-Rail DC Power Distribution Systems

Safety-Relevant Automotive Applications

•

AEC-Q100 Test Guidance With the Following

Results:

–

Advanced Driver Assistance Systems

–

Device Temperature Grade 1: –40°C to

+125°C Ambient Operating Temperature

3 Description

The TPS65311-Q1 device is a power-management IC

(PMIC), meeting the requirements of digital-signal-

processor (DSP) controlled-automotive systems (for

example, advanced driver-assistance systems). With

the integration of commonly used supply rails and

features, the TPS65311-Q1 device significantly

reduces board space and system costs.

–

Device HBM ESD Classification Level H1B

Device CDM ESD Classification Level C4B

•

Input Voltage Range: 4 V to 40 V, Transients up

to 60 V; 80 V When Using External PMOS-FET

Single-Output Synchronous-Buck Controller

–

Peak Gate-Drive Current 0.6 A

The device is capable of providing stable output

voltages to the application, including a typical 5-V

CAN-supply, from a varying input power supply (such

as an automotive car battery) from 4 V to 40 V. The

device includes one synchronous buck controller as a

pre-regulator that offers flexible output power to the

application. For post-regulation, the device includes

two synchronous buck and one asynchronous boost

converter, working at a switching frequency of 2.45

MHz to allow for a smaller inductor which requires

less board space. The two buck converters also offer

internal loop compensation which eliminates the need

for external compensation components. Furthermore,

the device includes a low-noise linear regulator.

490-kHz Fixed Switching Frequency

Pseudo Random Frequency-Hopping Spread

Spectrum or Triangular Mode

•

Dual-Synchronous Buck Converter

–

Designed for Output Currents up to 2 A

Out of Phase Switching

Switching Frequency: 2.45 MHz

•

Adjustable 350-mA Linear Regulator

Adjustable Asynchronous-Boost Converter

–

1-A Integrated Switch

Switching Frequency: 2.45 MHz

•

Soft-Start Feature for All Regulator Outputs

Independent Voltage Monitoring

Device Information⁽¹⁾

DEVICE NAME

PACKAGE

VQFN (56)

VQFNP (56)

BODY SIZE

Undervoltage (UV) Detection and Overvoltage

(OV) Protection

8.00 mm × 8.00 mm

TPS65311-Q1

•

Short Circuit, Overcurrent, and Thermal Protection

on all supply output rails

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Serial-Peripheral Interface (SPI) for Control and

Diagnostic

Simplified Schematic

•

Integrated Window Watchdog (WD)

Reference Voltage Output

V_BAT

High-Side (HS) Driver for Use with External

PMOS-FET for driving an LED

V_Buck1

V_Boost

•

Input for External Temperature Sensor for

Shutdown at T_A< –40°C

TPS65311-Q1

V_Buck1

Thermally Enhanced Packages With Exposed

Thermal Pad

V_Buck3

V_Buck2

–

56-Pin VQFN (RVJ) or 56-Pin VQFNP (RWE)

V_LDO

Logic I/O

(SPI, Watchdog, Reset)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65311-Q1

SLVSCA6C –OCTOBER 2013–REVISED OCTOBER 2017

www.ti.com

Table of Contents

8.4 Device Functional Modes........................................ 30

8.5 Programming........................................................... 34

8.6 Register Map........................................................... 35

Application and Implementation ........................ 41

9.1 Application Information............................................ 41

9.2 Typical Applications ................................................ 41

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (continued)......................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 8

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 9

7.6 Timing Requirements.............................................. 13

7.7 Switching Characteristics........................................ 15

7.8 Typical Characteristics............................................ 16

Detailed Description ............................................ 19

8.1 Overview ................................................................. 19

8.2 Functional Block Diagram ....................................... 20

8.3 Feature Description................................................. 21

9

10 Power Supply Recommendations ..................... 51

11 Layout................................................................... 53

11.1 Layout Guidelines ................................................. 53

11.2 Layout Example .................................................... 54

12 Device and Documentation Support ................. 55

12.1 Documentation Support ........................................ 55

12.2 Receiving Notification of Documentation Updates 55

12.3 Community Resources.......................................... 55

12.4 Trademarks........................................................... 55

12.5 Electrostatic Discharge Caution............................ 55

12.6 Glossary................................................................ 55

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 55

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2014) to Revision C

Page

•

Added the VQFNP (RWE) package option to the data sheet ............................................................................................... 1

Added pin descriptions for the S1 and S2 pins in the Pin Functions table ............................................................................ 5

Deleted the lead temperature (soldering, 10 sec), 260°C parameter from the Absolute Maximum Ratings table ................ 8

Changed the Handling Ratings table to ESD Ratings and moved storage temperature back to the Absolute

Maximum Ratings table .......................................................................................................................................................... 8

•

Changed all the thermal values for the RWE package in the Thermal Information table ...................................................... 8

Added the Receiving Notification of Documentation Updates and Community Resources sections................................... 55

Changes from Revision A (October 2013) to Revision B

Page

•

Changed CDM ESD Classification Level from C3B to C4B in the Features list and ESD ratings ........................................ 1

Added device number to document title................................................................................................................................. 1

Added Device Information table to first page and Table of Contents to second page. Moved Revision History to

second page also ................................................................................................................................................................... 1

•

Added two new paragraphs following the first paragraph in the Description section ............................................................ 1

Deleted simplified block diagram from first page and added new schematic image ............................................................. 1

Moved the pin diagram and function table to before the electrical specifications and change it to the Pin

Configurations and Functions section ................................................................................................................................... 4

•

Added the word range to the Absolute Maximum Ratings..................................................................................................... 7

Moved the electrical specifications tables into the Specifications section ............................................................................. 7

Moved the ESD ratings and storage temperature out of the Absolute Maximum Ratings table and into the Handling

Ratings table. Also added the ESD HBM and CDM notes..................................................................................................... 8

•

Changed both max values for T_Jfrom 125 to 150 in the RECOMMEND OPERATING CONDITIONS table........................ 8

Lowered all thermal values in the Thermal Information table ................................................................................................ 8

Changed condition statement of ELECTRICAL CHARACTERISTICS table from T_J(max)= 125°C to T_J(max)= 150°C ........... 9

2

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•

Added test condition for I_OUT= 350 mA, T_J= 150°C to the V_Dropoutparameter in the ELECTRICAL

CHARACTERISTICS table................................................................................................................................................... 10

•

Changed the min value for the V_{HSSC_HY}parameter from 1.5 to 1 and deleted the typ (2.5) and max (3.5) values ............ 10

Moved all timing specifications from the Electrical Characteristics table into the Timing Requirements table and

added figure references to the timing diagram..................................................................................................................... 13

•

Changed the max value for the t_{VSSENSE_BLK}parameter from 20 to 35................................................................................. 13

Changed the MAX value for the WD filter time parameter from 0.5 µs to 1.2 µs in the Timing Requirements table ......... 14

Changed the min value for the t_GL-BLKparameter from 10 to 5............................................................................................. 14

Moved all switching characteristics out of the Electrical Characteristics and into the new Switching Characteristics

table ..................................................................................................................................................................................... 15

•

Moved all but the first paragraph of the Description into the new Overview section in the Detailed Description section.... 19

Moved the block diagram into the Detailed Description section .......................................................................................... 20

Deleted the Operating Modes table and Normal Mode PWM Operation section title for Buck Controller (BUCK1)............ 21

Changed the resistor name for the resistor next to C₁from R₁to R₃and added R₁and R₂to the Detailed Block

Diagram of Buck 1 Controller image .................................................................................................................................... 21

•

Moved the component selection portion of the Synchronous Buck Converters BUCK2 and BUCK3 section into the

Typical Applications section ................................................................................................................................................ 22

•

Moved the component selection portion of the BOOST Converter section into the Typical Applications section .............. 22

Changed the voltage value that EXTSUP is connected to from 4.6 to 4.8 in the Gate Driver Supply section ................... 23

Moved the SPI section into a Programming section ........................................................................................................... 34

Added the Design Parameters tables for each of the Typical Application sections............................................................. 42

Added the Adjusting the Output Voltage for the BUCK1 Controller section to the Buck Controller (BUCK1)

application section ................................................................................................................................................................ 42

•

Moved the component selection portion of the Buck Controller (BUCK1) section into the Typical Applications section ... 42

Changed R1 to R3 in the Compensation of the Buck Controller section ............................................................................. 43

Added the Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter to the Detailed Design Procedure in

the Synchronous Buck Converters BUCK2 and BUCK3 section ......................................................................................... 45

•

Changed the inductance, capacitance and FLC values from 3.3 µH, 20 µF, and 12.9 kHz to 1.5 µH, 39 µF, and 13.7

kHz (respectively) in the For example: section of the Compensation of the BOOST Converter section............................. 49

•

Added the Linear Regulator application section .................................................................................................................. 50

Added the Device and Documentation Support and Mechanical, Packaging, and Orderable Information sections.

The Device and Documentation Support now includes the electrostatic discharge caution, trademark information,

and a link to the TI Glossary................................................................................................................................................. 55

Changes from Original (October 2013) to Revision A

Page

•

Changed document status from Product Preview to Production Data................................................................................... 1

Deleted both min values (–44°C and –55°C) for T_Jin the RECOMMENDED OPERATING CONDITIONS table................. 8

Changed both max values for T_Jfrom 150°C to 125°C in the RECOMMENDED OPERATING CONDITIONS table........... 8

Changed condition statement of ELECTRICAL CHARACTERISTICS table from T_Jtemperature range to T_J(max)= 125°C . 9

Changed one test condition for the V_Droupoutparameter in the ELECTRICAL CHARACTERISTICS table from T_J=

150°C to T_J= 125°C............................................................................................................................................................. 10

•

Deleted the T_Jtemperature range from SHUTDOWN COMPARATOR subheader row in the ELECTRICAL

CHARACTERISTICS table................................................................................................................................................... 11

Changed one test condition for the I_{VT_leak}parameter in the ELECTRICAL CHARACTERISTICS table from T_J=

–20°C to 150°C to T_J= –20°C to 125°C............................................................................................................................... 11

Changed the T_Jtemperature range to T_J(max)= 125°C for the INTERNAL VOLTAGE REGULATORS subheader row

in the ELECTRICAL CHARACTERISTICS table.................................................................................................................. 12

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5 Description (continued)

To help support system safety, the device includes voltage monitoring on all supply rails and a window-watchdog

to monitor the MCU and DSP. Other features include a high-side driver which drives a warning-lamp LED, a

reference voltage which is used as ADC reference in the MCU, DSP, and a shutdown comparator which, in

combination with external NTC-resistor, switches off the device at too-low ambient temperature.

6 Pin Configuration and Functions

56-Pin VQFN and VQFNP

RVJ and RWE Package With Exposed Thermal Pad

Top View

VSSENSE

VIN

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

BOOT3

VSUP3

PH3

2

GPFET

VINPROT

HSCTRL

HSSENSE

WAKE

EXTSUP

VREG

3

4

PGND3

VMON3

COMP3

VSENSE3

VSENSE2

COMP2

VMON2

PGND2

PH2

5

6

7

Thermal

Pad

8

9

BOOT1

GU

10

11

12

13

14

PH1

GL

VSUP2

BOOT2

PGND1

Not to scale

Pin Functions

PULLUP OR

PULLDOWN

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

The capacitor on this pin acts as the voltage supply for the BUCK1 high-side MOSFET gate-drive

circuitry.

BOOT1

10

I

—

The capacitor on this pin acts as the voltage supply for the BUCK2 high-side MOSFET gate drive

circuitry.

BOOT2

BOOT3

COMP1

29

42

18

The capacitor on this pin act as the voltage supply for the BUCK3 high-side MOSFET gate drive

circuitry.

I

Error amplifier output for the switching controller. External compensation network is connected to this

pin.

O

COMP2

COMP3

34

37

I

—

Compensation selection for the BUCK2 switching converter

Compensation selection for the BUCK3 switching converter.

Error amplifier output for the boost switching controller. External compensation network is connected

to this pin.

COMP5

CSN

20

44

O

I

—

Pullup

SPI – Chip select

(1) Description of pin type: I = Input; O = Output; OD = Open-drain output

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Pin Functions (continued)

PULLUP OR

PULLDOWN

TYPE⁽¹⁾

DESCRIPTION

NAME

DVDD

EXTSUP

GL

NO.

55

8

O

I

—

Internal DVDD output for decoupling

Optional LV input for gate driver supply

Gate driver – low-side FET

—

13

56

3

O

I

—

GND

—

Analog GND, digital GND and substrate connection

Gate driver external protection PMOS FET.

Gate driver – high-side FET

GPFET

GU

—

11

5

—

HSCTRL

HSPWM

HSSENSE

IRQ

—

High-side gate driver output

49

6

Pulldown

High side and LED PWM input

I

—

Sense input high side and LED

28

51

14

32

39

22

12

31

40

23

26

27

15

16

46

45

47

24

OD

O

OD

I

—

Low battery interrupt output in operating mode

Linear regulated output (connect a low ESR ceramic output capacitor to this pin)

Ground for low-side FET driver

LDO_OUT

PGND1

PGND2

PGND3

PGND5

PH1

—

Power ground of synchronous converter BUCK2

Power ground of synchronous converter BUCK3

Power ground boost converter

—

Switching node - BUCK1 (floating ground for high-side FET driver)

Switching node BUCK2

PH2

—

PH3

—

Switching node BUCK3

PH5

—

Switching node boost

PRESN

RESN

S1

Peripherals reset

—

System reset

—

Differential current sense input for BUCK1

Differential current sense input for BUCK1, pulldown only active in RAMP and ACTIVE state

SPI – Clock

S2

I

Pulldown

—

SCK

I

SDI

I

SPI – Master out, slave in

SDO

O

I

SPI – Master in, slave out - push-pull output supplied by VIO

Booster output voltage

VBOOST

—

Unprotected supply input for the base functionality and band-gap 1. Supplied blocks are: RESET, WD,

wake, SPI, temp sensing, voltage monitoring and the logic block.

VIN

2

4

I

—

VINPROT

VIO

Main input supply (gate drivers and bandgap2)

Supply input for the digital interface to the MCU. Voltage on this input is monitored. If VIO falls below

UV threshold a reset is generated and the part enters error mode.

48

VMON1

VMON2

VMON3

VREF

17

33

38

53

9

I

—

Input for the independent voltage monitor at BUCK1

Input for the independent voltage monitor at BUCK2

I

Input for the independent voltage monitor at BUCK3

O

Accurate reference voltage output for peripherals on the system (for example, ADC)

Internal regulator for gate driver supply (decoupling) and VREF

VREG

Input for externally sensed voltage of the output using a resistor divider network from their respective

output line to ground.

VSENSE1

VSENSE2

VSENSE3

VSENSE4

VSENSE5

19

35

36

52

21

I

—

Input for externally sensed voltage of the output using a resistor divider network from their respective

output line to ground

Input for externally sensed voltage of the output using a resistor divider network from their respective

output line to ground

Input for externally sensed voltage of the output using a resistor divider network from their respective

output line to ground.

Input for externally sensed voltage of the boost output using a resistor divider network from their

respective output line to ground.

VSSENSE

VSUP2

1

I

—

Input to monitor the battery line for undervoltage conditions. UV is indicated by the IRQ pin.

Input voltage supply for switch mode regulator BUCK2

30

41

50

VSUP3

Input voltage supply for switch mode regulator BUCK3

VSUP4

Input voltage supply for linear regulator LDO

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Pin Functions (continued)

PULLUP OR

PULLDOWN

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Input for the comparator with shutdown functionality. This input can be used to sense an external NTC

resistor to shutdown the IC in case the ambient temperature is too high or too low. Tie to GND if not

in use.

VT

54

I

—

Shutdown comparator reference output. Internally connected to DVDD, current-limited. When not in

use can be connected to DVDD or left open.

VT_REF

25

O

WAKE

WD

7

I

Pulldown

Wake up input

43

Watchdog input. WD is the trigger input coming from the MCU.

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

80

UNIT

VIN

VINPROT

60

VSUP2, 3 (BUCK2 and 3)

20

Supply inputs

VSUP4 (Linear Regulator)

20

V

VBOOST

EXTSUP

VIO

20

13

5.5

60

–1

PH1

–2 for 100 ns

VSENSE1

–0.3

–2

20

8

COMP1

GU-PH1, GL-PGND1, BOOT1-PH1

Buck controller

V

S1, S2

20

2

S1-S2

BOOT1

–0.3

–1

68

20

20⁽²⁾

VMON1

BOOT2, BOOT3

–1⁽²⁾

PH2, PH3

–2 for 10 ns

VSENSE2, VSENSE3

COMP2, COMP3

VMON2, VMON3

BOOTx – PHx

LDO_OUT

–0.3

–1⁽³⁾

–0.3

–1⁽³⁾

20

8

Buck controller

V

8

Linear regulator

Boost converter

V

VSENSE4

20

5.5

20

60

80

20

VSENSE5

PH5

COMP5

CSN, SCK, SDO, SDI, WD, HSPWM

RESN, PRESN, IRQ

WAKE

Digital interface

Wake input

V

GPFET

Protection FET

VIN – GPFET

60

Battery sense input

Temperature sense

VSSENSE

V

Transients up to 80 V⁽⁴⁾

VT

–0.3

5.5

20

VT_REF

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum 3.5 A

(3) I_max= 100 mA

(4) Internally clamped to 60-V, 20-kΩ external resistor required, current into pin limited to 1 mA.

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Absolute Maximum Ratings (continued)

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–55

MAX

5.5

60

UNIT

Reference voltage

VREF

V

HSSENSE

High-side and LED driver

HSCTRL

60

V

VINPROT-HSSENSE, VINPROT-HSCTRL

VREG

20

Driver supply decoupling

Supply decoupling

8

V

DVDD

3.6

150

125

165

Junction temperature range, T_J

Operating temperature range, T_A

Storage temperature, T_stg

Temperature ratings

–55

°C

–55

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

±1000

±150

VT pin

Electrostatic

V_(ESD)

V

Charged-device model (CDM), per AEC

Q100-011

Corner pins (1, 14, 15, 28, 29, 42, 43,

and 56)

discharge

±750

±500

All other pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage at VIN, VINPROT, VSSENSE

All electrical characteristics in specification

4.8

40

V

–40

125

T_AOperating free air temperature

°C

Shutdown comparator and internal voltage regulators in

specification

–55

125

150

All electrical characteristics in specification

Operating virtual junction

T_J

°C

Shutdown comparator and internal voltage regulators in

specification

temperature

7.4 Thermal Information

TPS65311-Q1

RWE (VQFNP) RVJ (VQFN)

THERMAL METRIC⁽¹⁾

UNIT

56 PINS

22.1

9.6

56 PINS

22.3

9.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

6.2

6.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

6.2

R_θJC(bot)

0.4

0.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8

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7.5 Electrical Characteristics

VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, T_J(max)= 150°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE-CURRENT CONSUMPTION

Buck regulator operating range, Voltage on VIN and

VINPROT pins

V_IN

Device operating range

Power-on reset threshold

4

50

V

Falling VIN

Rising VIN

3.5

3.9

3.6

4.2

0.6

3.8

4.3

V_POR

V_{POR_hyst}

I_LPM0

Power-on reset hysteresis on VIN

LPM0 current consumption⁽¹⁾⁽²⁾

0.47

0.73

V

All off, wake active, V_IN= 13 V

Total current into VSSENSE, VIN and VINPROT

44

60

μA

LPM0 current (commercial vehicle All off, wake active, V_IN= 24.5 V

I_LPM0

μA

application) consumption⁽³⁾⁽²⁾

Total current into VSSENSE, VIN and VINPROT

BUCK1 = on, V_IN= 13 V, EXTSUP = 0 V,

Q_gof BUCK1 FETs = 15 nC.

Total current into VSSENSE, VIN and VINPROT

ACTIVE total current

consumption⁽¹⁾⁽⁴⁾

I_ACTIVE1

32

40

mA

BUCK1/2/3 = on, V_IN= 13 V,

Q_gof BUCK1 FETs = 15 nC.

Total current into VSSENSE, VIN and VINPROT

ACTIVE total current

consumption⁽¹⁾⁽⁴⁾

I_ACTIVE123

mA

BUCK1/2/3, LDO, BOOST, high-side switch = on,

V_IN= 13 V, Q_gof BUCK1 FETs = 15 nC.

EXTSUP = 5 V from BOOST

I_ACTIVE1235

ACTIVE current consumption⁽¹⁾⁽⁴⁾

31

53

Total current into VSSENSE, VIN and VINPROT

BUCK1/2/3, LDO, BOOST, high-side switch = on,

V_IN= 13 V, Q_gof BUCK1 FETs = 15 nC,

EXTSUP = open

I_{ACTIVE1235_noEXT}ACTIVE current consumption⁽¹⁾⁽⁴⁾

mA

V

Total current into VSENSE, VIN and VINPROT

BUCK CONTROLLER (BUCK1)

V_BUCK1

Adjustable output voltage range

3

11

Internal reference voltage in

operating mode

VSENSE1 pin, load = 0 mA,

Internal REF = 0.8 V

V_{Sense1_NRM}

–1%

1%

Maximum sense voltage VSENSE1 = 0.75 V (low

duty cycle)

60

75

90

V_S1-2

VS1-2 for forward OC in CCM

mV

Minimum sense voltage VSENSE 1 = 1 V (negative

current limit)

–65

4

–37.5

–23

12

A_CS

Current sense voltage gain

Gate driver peak current

∆VCOMP1 / ∆ (VS1 - VS2)

8

V/V

A

I_Gpeak

VREG = 5.8 V

0.6

I_Gcurrent for external MOSFET = 200 mA,

VREG = 5.8 V, V_BOOT1-PH1= 5.8 V

R_{DSON_DRIVER}

V_DIO1

Source and sink driver

5

10

Ω

Bootstrap diode forward voltage

I_BOOT1= –200 mA, VREG-BOOT1

0.8

60

1.1

V

ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BOOST CONVERTER

COMP1/2/3/5 = 0.8 V; source/sink = 5 µA,

Test in feedback loop

gm_EA

A_EA

Forward transconductance

Error amplifier DC gain

0.9

mS

dB

SYNCHRONOUS BUCK CONVERTER BUCK2 AND BUCK3 (BUCK2/3)

VSUP2/3

V_BUCK2/3

Supply voltage

3

11

V

I_load= 0…2 A

VSUPx = V_BUCK2/3+ I_load× 0.2 Ω

Regulated output voltage range

0.8

5.5

R_DSON-HS

R_DSON-LS

R_DSONhigh-side switch

R_DSONlow-side switch

V_{BOOTx –PHx}= 5.8 V

VREG = 5.8 V

0.20

Ω

Static current limit test.

I_HS-Limit

High-side switch current-limit

Low-side switch current-limit

In application L > 1 µH at

I_HS-Limitand I_LS-Limitto limit dI / dt

2.5

2

2.9

2.5

3.3

3

A

Static current limit test.

In application L > 1 µH at

I_HS-Limitand I_LS-Limitto limit dI / dt

I_LS-Limit

(1) T_A= 25°C

(2) Quiescent Current Specification does not include the current flow through the external feedback resistor divider. Quiescent Current is

non-switching current, measured with no load on the output with VBAT = 13 V.

(3) T_A= 130°C

(4) Total current consumption measured on EVM includes switching losses.

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Electrical Characteristics (continued)

VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, T_J(max)= 150°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VSUP = 10 V for high side, controller disabled,

T_J= 100°C

VSUP_Lkg

VSUP leakage current

1

2

µA

V_Sense2/3

Feedback voltage

With respect to the 800-mV internal reference

–1%

0.9

1%

1.5

COMP2/3_HTH

COMP2/3 Input threshold low

V

VREG –

0.3

COMP2/3_LTH

COMP2/3 Input threshold high

VREG – 1.2

70

BUCK2/3 enabled. Resistor to VREG and GND,

each

R_{TIEOFF COMP23}COMP2/3 internal tie-off

100

1.1

130

1.2

kΩ

V_{DIO2 3}

BOOST CONVERTER

Boost adjustable output voltage

Bootstrap diode forward voltage

I_BOOT1= –200 mA, VREG-BOOT2, VREG-BOOT3

V

V_Boost

Using 3.3-V input voltage, Ieak_switch ≤ 1 A

4.5

15

V

range

Boost adjustable output voltage

range

Using 3.3-V input voltage I_loadmax= 20 mA,

I_{peak_switch}= 0.3 A

V_Boost

18.5

V

R_{DS-ON_BOOST}

V_Sense5

Internal switch on-resistance

Feedback voltage

VREG = 5.8 V

0.3

0.5

1%

1.5

Ω

With respect to the 800-mV internal reference

–1%

1

I_CLBOOST

Internal switch current-limit

A

LINEAR REGULATOR LDO

VSUP4

V_LDO

Device operating range for LDO

Recommended operating range

I_OUT= 1 mA to 350 mA

3

7

V

Regulated output range

0.8

5.25

DC output voltage tolerance at

VSENSE4

VSENSE4 = 0.8 V (regulated at internal ref)

VSUP4 = 3 V to 7 V, I_OUT= 1 mA to 350 mA

V_RefLDO

–2%

2%

VSENSE4 = 0.8 V (regulated at internal ref)

I_OUT= 1 mA to 101 mA,

C_LDO= 6 to 50 µF, t_rise= 1 µs

V_step1

Load step 1

–2%

–1%

V_Sense4

Feedback voltage

With respect to the 800-mV internal reference

I_OUT= 350 mA, T_J= 25°C

I_OUT= 350 mA, T_J= 125°C

I_OUT= 350 mA, T_J= 150°C

V_OUTin regulation

1%

143

180

335

–1

127

156

275

V_Dropout

Drop out voltage

mV

I_OUT

Output current

–350

mA

I_LDO-CL

Output current limit

V_OUT= 0 V, VSUP4 = 3 V to 7 V

–1000

–400

Freq = 100 Hz

V_ripple= 0.5 V_PP, I_OUT= 300 mA,

Freq = 4 kHz

60

50

25

PSRR_LDO

Power supply ripple rejection

dB

C_LDO= 10 µF

Freq = 150 kHz

LDOns_10-100

LDOns_100-1k

Output noise 10 Hz – 100 Hz

Output noise 100 Hz – 10 kHz

10-µF output capacitance, V_LDO= 2.5 V

20 µV/√(Hz)

10-µF output capacitance, V_LDO= 2.5 V

6

µV/√(Hz)

Ceramic capacitor with ESR range, C_{LDO_ESR}= 0 to

100 mΩ

C_LDO

Output capacitor

6

50

µF

LED AND HIGH-SIDE SWITCH CONTROL

VINPROT – HSSENSE, high-side switch in current

limit

V_HSSENSE

Current sense voltage

370

4

400

430

60

mV

V

Common mode range for current

sensing

VCM_HSSENSE

See VINPROT

Ramping negative

Ramping positive

5

26

20

38

35

50

28

VINPROT – HSSENSE open load

threshold

V_{HSOL_TH}

V_{HSOL_HY}

mV

Open load hysteresis

10

18

Ramping positive

88%

92.5%

96% V_HSSENSE

VINPROT – HSSENSE load short

detection threshold

V_{HS SC}

% of

93

Ramping negative from load short condition

87

1

90

V_HSSENSE

VINPROT – HSSENSE short

circuit hysteresis

% of

V_HSSENSE

V_{HSSC_HY}

VHSCTRL_OFF

V_GS

VINPROT

– 0.5

Voltage at HSCTRL when OFF

VINPROT

8.5

V

Clamp voltage between

HSSENSE – HSCTRL

6.1

7.7

10

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Electrical Characteristics (continued)

VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, T_J(max)= 150°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

400

5

UNIT

mV

V_{OS_HS}

Overshoot during turn-on

HSCTRL current-limit

V_{OS_HS}= VINPROT - HSSENSE

I_{CL_HSCTRL}

R_{PU_HSCTRL}

2

4.1

mA

Between VINPROT and HSCTRL

Between HSCTRL and HSSENSE

70

100

130

Internal pullup resistors

kΩ

R_{PU_HSCTRL-}

70

2

100

130

HSSENSE

V_{I_high}

V_{I_low}

High level input voltage

Low level input voltage

Input voltage hysteresis

External sense resistor

HSPWM, VIO = 3.3 V

V

HSPWM, VIO = 3.3 V

0.8

500

50

V_{I_hys}

HSPWM, VIO = 3.3 V

150

1.5

mV

Ω

R_SENSE

Design info, no device parameter

External MOSFET gate source

capacitance

C_GS

C_GD

100

2000

500

pF

External MOSFET gate drain

capacitance

REFERENCE VOLTAGE

V_REF

Reference voltage

3.3

V

V_REF-tol

Reference voltage tolerance

Reference voltage current-limit

Capacitive load

I_VREF= 5 mA

–1%

10

1%

25

5

I_REFCL

mA

µF

C_VREF

0.6

REFns_10-100

REFns_100-1k

Output noise 10 Hz–100 Hz

Output noise 100 Hz–10 kHz

2.2 µF output capacitance, I_VREF= 5 mA

Threshold, V_REFfalling

20 µV/√(Hz)

6

3.12

140

µV/√(Hz)

2.91

14

3.07

70

V

V_{REF_OK}

Reference voltage OK threshold

Hysteresis

mV

SHUTDOWN COMPARATOR

I_{VT_REF}= 20 µA. Measured as drop voltage with

respect to VDVDD

10

17

420

1

500

Shutdown comparator reference

voltage

VT_REF

mV

mA

I_{VT_REF}= 600 µA. Measured as drop voltage with

respect to VDVDD. No VT_REF short-circuit

detection.

200

1100

Shutdown comparator reference

current limit

I_{VT_REFCL}

VT_REF = 0

0.6

0.9

1.4

1.8

Threshold, VT_REF falling. Measured as drop

voltage with respect to VDVDD

1.2

130

V

V_{VT_REF SH}

VT_REF short circuit detection

Hysteresis

mV

Input voltage threshold on VT,

rising edge triggers shutdown

This feature is specified by design to work down to

–55°C.

VT_TH-H

VT_TH-L

0.48

0.46

0.50

0.52 VT_REF

Input voltage threshold on VT,

falling voltage enables device

operation

This feature is specified by design to work down to

–55°C.

0.48

VT_TOL

I_{VT_leak}

Threshold variation

VT_TH-H– VT_REF / 2, VT_TH-L– VT_REF / 2

T_J: –20°C to 125°C

–20

–400

–200

20

–50

mV

nA

Leakage current

T_J: –55°C to –20°C

Threshold, VT_REF rising. Measured as drop

voltage with respect to VDVDD

0.42

0.9

1.2

V

VT_REF_OV

VT_REF overvoltage threshold

Hysteresis

100

mV

WAKE INPUT

V_{WAKE_ON}

Voltage threshold to enable device WAKE pin is a level sensitive input

3.3

3.7

V

VBAT UNDERVOLTAGE WARNING

V_{SSENSETH_L}

V_{SSENSETH_H}

V_SSENSE-HY

I_VSLEAK

VSSENSE falling threshold low

SPI selectable, default after reset

SPI selectable

4.3

6.2

4.7

6.8

V

VSSENSE falling threshold high

VSSENSE hysteresis

0.2

V

Leakage current at VSSENSE

LPM0 mode, VSSENSE 55 V

LPM0 mode, VSSENSE 60 V

LPM0 mode, VSSENSE 80 V

1

100

25

µA

mA

I_VSLEAK60

I_VSLEAK80

5

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Electrical Characteristics (continued)

VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, T_J(max)= 150°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal resistance from VSSENSE

to GND

R_VSSENSE

VSSENSE = 14 V, disabled in LPM0 mode

0.7

1

1.3

MΩ

VIN OVERVOLTAGE PROTECTION

VIN overvoltage shutdown

threshold 1 (rising edge)

V_{OVTH_H}

V_{OVTH_L}

Selectable with SPI

50

36

60

38

V

VIN overvoltage shutdown

threshold 2 (rising edge)

Selectable with SPI, default after reset

Threshold 1

0.2

1.5

1.7

2

3

V_OVHY

VIN overvoltage hysteresis

V

Threshold 2 - default after reset

2.5

WINDOW WATCHDOG

V_{I_high}

V_{I_low}

V_{I_hys}

High level input voltage

WD, VIO = 3.3 V

2

V

Low level input voltage

Input voltage hysteresis

0.8

150

500

mV

RESET AND IRQ BLOCK

Low level output voltage at RESN,

PRESN and IRQ

V_RESL

I_RESLeak

N_RES

VIN ≥ 3 V, IxRESN = 2.5 mA

VIN = 0 V, VIO = 1.2 V, IxRESN = 1 mA

V_test= 5.5 V

0

0.4

1

V

Low level output voltage at RESN

and PRESN

Leakage current at RESN, PRESN

and IRQ

µA

Number of consecutive reset

events for transfer to LPM0

7

EXTERNAL PROTECTION

VCLAMP

Gate to source clamp voltage

VIN - GPFET, 100 µA

VIN = 14 V, GPFET = 2 V

VIN = 14 V, turn off

14

15

20

25

V

µA

Ω

IGPFET

Gate turn on current

Gate driver strength

RDSONGFET

THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION

T_SDTH

T_SDHY

Thermal shutdown

Hysteresis

Junction temperature

160

150

175

20

°C

Overtemperature flag is implemented as local temp

sensors and expected to trigger before the thermal

shutdown

T_OTTH

Overtemperature flag

165

20

°C

T_OTHY

Hysteresis

VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER

V_{MONTH_L}

V_{MONTH_H}

V_{MON_HY}

Voltage monitor reference

Voltage monitor hysteresis

REF = 0.8 V – falling edge

REF = 0.8 V – rising edge

90%

92%

108%

2%

94%

106%

110%

Undervoltage monitoring at VIO –

falling edge

V_{VIOMON_TH}

3

3.13

V

V_{VIOMON_HY}

GND LOSS

V_GLTH-low

UV_VIO hysteresis

0.05

GND loss threshold low

GND loss threshold high

GND to PGNDx

–0.31

0.19

–0.25

0.25

–0.19

0.31

V

V_GLTH-high

INTERNAL VOLTAGE REGULATORS

I_VREG= 0 mA to 50 mA, VINPROT = 6.3 V to 40 V

and EXTSUP = 6.3 V to 12 V

V_REG

Internal regulated supply

5.5

5.8

6.1

V

I_VREG= 0 mA to 50 mA and EXTSUP ramping

positive, ACTIVE mode

V_EXTSUP-TH

V_EXTSUP-HY

Switch over voltage

4.4

4.6

4.8

V

Switch over hysteresis

100

200

300

mV

I_VREG= 50 mA,

V_REGDROP

Drop out voltage on VREG

EXTSUP = 5 V / VINPROT = 5 V and

EXTSUP = 0 V / VINPROT = 4 V

200

mV

I_{REG_CL}

EXTSUP = 0 V, VREG = 0 V

–250

1.2

–50

3.3

mA

µF

Current limit on VREG

Capacitive load

I_{REG_EXTSUP_CL}

C_VREG

EXTSUP ≥ 4.8 V, VREG = 0 V

2.2

12

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Electrical Characteristics (continued)

VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, T_J(max)= 150°C, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

4.2

UNIT

V

VREG rising

Hysteresis

3.8

4

V_REG-OK

VDVDD

VREG undervoltage threshold

350

420

490

mV

Internal regulated low voltage

supply

3.15

2.1

3.3

3.45

3.8

V

VDVDD UV

VDVDD OV

SPI

DVDD undervoltage threshold

DVDD overvoltage threshold

DVDD falling

DVDD rising

V

V_{I_high}

High level input voltage

Low level input voltage

Input voltage hysteresis

SDO output high voltage

SDO output low voltage

SDO capacitance

CSN, SCK, SDI; VIO = 3.3 V

VIO = 3.3 V I_SDO= 1 mA

2

V

V_{I_low}

0.8

V_{I_hys}

150

3

500

mV

V

V_{O_high}

V_{O_low}

VIO = 3.3 V I_SDO= 1 mA

0.2

50

V

CSDO

pF

GLOBAL PARAMETERS

R_PU

R_PD

Internal pullup resistor at CSN pin

70

100

130

kΩ

Internal pulldown resistor at pins:

HSPWM , SDI, SCK, WD, S2⁽⁵⁾

Internal pulldown resistor at WAKE

R_PD-WAKE

140

200

260

–50

kΩ

Input pullup current at pins:

- VSENSE1–5

I_LKG

V_TEST= 0.8 V

–200

–100

nA

- VMON1–3

(5) RAMP and ACTIVE only

7.6 Timing Requirements

MIN

TYP

MAX UNIT

BUCK CONTROLLER (BUCK1)

t_{OCBUCK1_BLK}

RSTN and ERROR mode transition, when over current detected for > t_{OCBUCK1_BLK}

1

ms

LED AND HIGH-SIDE SWITCH CONTROL

t_{HSOL_BLK}

t_{HSS CL}

t_{S HS}

Open load blanking time

70

4

100

5

140

6

µs

ms

µs

Net time in current limit to disable driver

Current-limit sampling interval

100

Time from rising HSPWM till high-side

switch in current limitation, ±5% settling

30

µs

Time from rising HSPWM till high-side

switch till voltage-clamp between

HSSENSE – HSCTRL active (within V_GS

limits)

t_ON

Turnon time

30

60

500

20

µs

Hz

µs

f_{HS_IN}

HSPWM input frequency

Design information, no device parameter

100

10

REFERENCE VOLTAGE

T_{REF_OK}

Reference voltage OK deglitch time

SHUTDOWN COMPARATOR

T_{VT_REF_FLT}

VT_REF fault deglitch time

Overvoltage or short condition on VT_REF

10

20

WAKE INPUT

V_WAKE= 4 V to suppress short spikes at

WAKE pin

t_WAKE

Min. pulse width at WAKE to enable device

10

20

35

µs

VBAT UNDERVOLTAGE WARNING

t_{VSSENSE_BLK}Blanking time

VIN OVERVOLTAGE PROTECTION

V_VSENSE< V_{SSENSETH_xx}→ IRQ asserted

t_{OFF BLK-H}

t_{OFF BLK-L}

OV delay time

VIN > V_{OVTH_H}→ GPFET off

VIN > V_{OVTH_L}→ GPFET off

1

µs

OV blanking time

10

20

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MAX UNIT

Timing Requirements (continued)

MIN

TYP

WINDOW WATCHDOG

TESTSTART, TESTSTOP, VTCHECK ,

and RAMP mode:

Starts after entering each mode.

ACTIVE mode:

t_timeout

Timeout

230

300

370

ms

WD timeout starts with rising edge of

RESN

Spread spectrum disabled

Spread spectrum enable

18

20

22

t_WD

Watchdog window time

ms

µs

19.8

24.2

t_{WD_FAIL}

t_{WD_BLK}

Closed window time

WD filter time

t_WD/ 4

1.2

RESET AND IRQ BLOCK

t_RESNHOLD

RESN hold time

1.8

10

2

2.2

20

ms

µs

t_IRQHOLD

IRQ hold time

After V_VSENSE< V_SSENSETHfor t_{VSSENSE_BLK}

t_{DR IRQ PRESN}

t_{DF RESN_PRESN}

Rising edge delay of IRQ to rising edge of PRESN

Falling edge delay of RESN to PRESN / IRQ

2

THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION

t_SD-BLK

t_{OT_BLK}

Blanking time before thermal shutdown

10

20

µs

Blanking time before thermal over temperature

VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER

t_{VMON_BLK}

Blanking time between UV/OV condition to RESN low UV/OV: BUCK1/2/3 UV: VIO

10

20

µs

Blanking time between undervoltage condition to

ERROR mode transition or corresponding SPI bit

BUCK1/2/3 → ERROR mode LDO or

BOOST → SPI bit set or turn off

t_{VMONTHL_BLK}

1

ms

Blanking time between undervoltage condition to

ERROR mode transition

t_{VMONTHL_BLK1}

t_{VMONTHH_BLK1}

VIO only

10

20

µs

Blanking time between overvoltage condition to

ERROR mode transition

BUCK1/2/3 → ERROR mode VIO has no

OV protection

LDO or BOOST (ACTIVE mode) → SPI bit

set or turn off LDO (VTCHECK or RAMP

mode) → ERROR mode

Blanking time LDO and BOOST overvoltage condition

to corresponding SPI bit or ERROR mode

t_{VMONTHH_BLK2}

20

5

40

20

µs

GND LOSS

t_GL-BLK

Blanking time between GND loss condition and transition to ERROR state

POWER-UP SEQUENCING

From start till exceeding V_{MONTH_L}

V_{MON_HY}Level

+

t_START1

t_START2

t_START

t_SEQ2

Soft start time of BOOST

0.7

0.5

2.7

2

ms

From start till exceeding V_{MONTH_L}

V_{MON_HY}Level

Soft start time of BUCK1/2/3 and LDO

Startup DVDD regulator

From start till exceeding V_{MONTH_L}

V_{MON_HY}Level

3

Sequencing time from start of BUCK1 to BUCK2 and

BOOST

Internal SSDONE_BUCK1 signal

3

t_WAKE-RES

t_SEQ1

INTERNAL VOLTAGE REGULATORS

Startup time from entering TESTSTART to RESN high GPFET = IRFR6215

14

4

ms

Sequencing time from start of BOOST to BUCK3 Internal SSDONE_BOOST signal

1

t_{DVDD OV}

Blanking time from DVDD overvoltage condition to shutdown mode transition

10

20

µs

SPI INTERFACE

t_SPI

SCK period

240

100

ns

t_SCKL

t_SCKH

SCK low time

SCK high time

See Figure 1

Time between falling edge of CSN and SDO output

valid (FSI bit)

Falling SDO < 0.8 V; Rising SDO > 2 V,

See Figure 1

t_FSIV

80

55

ns

Falling SDO < 0.8 V; Rising SDO > 2 V,

See Figure 1

t_SDOV

Time between rising edge of SCK and SDO data valid

t_SDIS

t_SDOH

t_HCS

Setup time of SDI before falling edge of SCK

Hold time of SDO after rising edge of SCK

Hold time of CSN after last falling edge of SCK

Delay between rising edge of CSN and SDO 3-state

See Figure 1

20

5

ns

50

See Figure 1

t_SDOtri

80

14

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Timing Requirements (continued)

MIN

TYP

MAX UNIT

t_min2SPI

Minimum time between two SPI commands

10

µs

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BUCK CONTROLLER (BUCK1)

f_SWBUCK1

Switching frequency

f_OSC/ 10

100

High-side minimum on time

Maximum duty cycle

ns

DC

Duty cycle

98.75%

25

t_{DEAD_BUCK1}

Shoot-through delay, blanking time

SYNCHRONOUS BUCK CONVERTER BUCK2/3

f_SWLBuck2/3

Buck switching frequency

f_OSC/ 2

50

High-side minimum on time

Maximum duty cycle

ns

DC_BUCK2/3

Duty cycle

99.8%

20

t_{DEAD_BUCK2/3}Shoot-through delay

BOOST CONVERTER

f_SWLBOOST

Boost switching frequency

f_OSC/ 2

75%

Maximum internal MOSFET duty cycle

at f_SWLBOOST

DC_BOOST

GLOBAL PARAMETERS

Internal oscillator used for Buck or

Boost switching frequency

f_OSC

4.6

4.9

5.2

MHz

f_spread

Spread spectrum frequency range

0.8 × f_OSC

f_OSC

CSN

T_SPI

t_Hcs

SCK

t_FSIV

t_SDOV

t_SCKL

t_SCKH

t_SDOtri

FSI

Bit15

Bit14

Bit0

SDO

t_SDIS

t_SDIH

Bit15

Bit14

Bit0

SDI

Figure 1. SPI Timing

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7.8 Typical Characteristics

All parameters are measured on a TI EVM, unless otherwise specified.

7.8.1 BUCK 1 Characteristics

Figure 2. Reduction of Current-Limit vs Duty Cycle

7.8.2 BUCK 2 and BUCK3 Characteristics

810

VSUP3 = 3.8 V, 25°C

804

VSUP3 = 3.3 V, 25°C

VSUP3 = 5 V, 25°C

VSUP2 = 3.8 V, 25°C

808

VSUP2 = 5 V, 25°C

VSUP3 = 3.8 V, 140°C

VSUP3 = 3.8 V, -40°C

802

800

798

796

794

792

790

806

804

802

800

798

796

794

792

790

VSUP2 = 3.8 V, 140°C

VSUP2 = 3.8 V, -40°C

0

0.5

1

1.5

2

0

0.5

1

1.5

2

Load Current (A)

Figure 3. Load Regulation BUCK2 = 3.3 V

EXTSUP Pin Open

Figure 4. Load Regulation BUCK3 = 1.2 V

EXTSUP Pin Open

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BUCK 2 and BUCK3 Characteristics (continued)

805

804

803

802

801

800

799

798

797

796

795

25°C

804

803

802

801

800

799

798

797

796

795

25°C

-40°C

140°C

-40°C

140°C

2

4

6

8

10

12

2

4

6

8

10

12

VSUP2 (V)

VSUP3 (V)

Figure 5. Open-Load Line Regulation BUCK2 = 3.3 V

EXTSUP Pin Open

Figure 6. Open-Load Line Regulation BUCK3 = 1.2 V

EXTSUP Pin Open

10

6

5.5

5

9

8

7

6

5

4

3

2

1

0

4.5

4

3.5

3

2.5

2

25°C

1.5

1

-40°C

125°C

-40°C

140°C

0.5

0

3

5

7

9

11

2

4

6

8

10

12

VSUP2 (V)

VSUP3 (V)

Figure 7. Open-Load Supply Current BUCK2 = 3.3 V

EXTSUP Pin Open

Figure 8. Open-Load Supply Current BUCK3 = 1.2 V

EXTSUP Pin Open

801

802

801.5

801

800.5

800

799.5

799

800.5

800

799.5

799

798.5

798

VSUP2 = 3.8 V, NO LOAD

VSUP3 = 3.8 V, NO LOAD

-50

-30

-10

10

30

50

70

90

110

130

150

798.5

-50

-30

-10

10

30

50

70

90

110

130

150

Temperature (°Celcius)

Figure 9. BUCK2 = 3.3-V VSENSE2 vs Temperature

EXTSUP Pin Open

Figure 10. BUCK3 = 1.2-V VSENSE3 vs Temperature

EXTSUP Pin Open

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7.8.3 BOOST Characteristics

0.81

0.805

0.8

0.805

0.8

0.795

0.79

0.795

0.79

3

3.2

3.4

3.6

3.8

4

0

0.1

0.2

0.3

0.4

0.5

VSUP5 (V)

Load Current (A)

Figure 11. Open-Load Line Regulation BOOST = 5 V, AT

25°C, EXTSUP Pin Open, BOOST Supply Input = 3.8 V

Figure 12. Load Regulation BOOST = 5 V AT 25°C

EXTSUP Pin Open, BOOST Supply Input = 3.8 V

805

804

803

802

801

800

799

798

797

796

795

-50

0

50

100

150

Temperature (°Celcius)

Figure 13. BOOST = 5-V VSENSE5 vs Temperature

EXTSUP Pin Open, Input Supply = 3.8-V, 0.4-A Load

7.8.4 LDO Noise Characteristics

(2 × 3.3-µF output capacitance, LDO output = 2.5 V, VSUP4 = 3.8 V)

10

9

8

7

6

5

4

3

2

1

0

Noise [LDO ON]

Noise [LDO OFF]

(Noisefloor)

10

100

1000

10000

Frequency (Hz)

Figure 14. LDO Noise Density

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8 Detailed Description

8.1 Overview

The device includes one high-voltage buck controller for pre-regulation combined with a two-buck and one-boost

converter for post regulation. A further integrated low-dropout (LDO) regulator rounds up the power-supply

concept and offers a flexible system design with five independent-voltage rails. The device offers a low power

state (LPM0 with all rails off) to reduce current consumption in case the system is constantly connected to the

battery line. All outputs are protected against overload and over temperature.

An external PMOS protection feature makes the device capable of sustaining voltage transients up to 80 V. This

external PMOS is also used in safety-critical applications to protect the system in case one of the rails shows a

malfunction (undervoltage, overvoltage, or overcurrent).

Internal soft-start ensures controlled startup for all supplies. Each power-supply output has an adjustable output

voltage based on the external resistor-network settings.

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8.2 Functional Block Diagram

VBAT

VINPROT

IRQ

UV

OV

Protection

Warning

DVDD

+ POR

V_EXTSUP-TH

V_BUCK1

5.8V

VREG

VIO

UV

Bandgap1

Bandgap2

Monitoring

VREG

RESN

PRESN

WD

BOOT1

RESET

/

Window

Watchdog

Digital

Logic

GU

PH1

WAKE

Wake Up

circuit

GL

PGND1

CSN

SCK

SDO

SDI

COMP1

S1

SPI

V_BUCK1

S2

+

-

Bandgap3

VREF

VSENSE1

VMON1

Voltage

Monitoring

DVDD

Short

VT_REF

VT

V_BUCK1

Sync. Buck Converter

BUCK2

VSUP2

BOOT2

Protection

(low voltage)

+

-

GND

LT

V_Buck2

VINPROT

PH2

Shutdown

Comparator

GND

COMP2

PGND2

HSSENSE

HSCTRL

HSPWM

VSENSE2

VMON2

LED Driver

Booster

Voltage

Monitoring

V_BUCK1

Sync. Buck Converter

BUCK3

COMP5

VSUP3

BOOT3

(low voltage)

LDO

(Low voltage)

PH5

V_Buck3

PH3

Charge

Pump

PGND5

COMP3

PGND3

SMPS

Voltage

Mode

VBOOST

+

-

V_Booster

VSENSE3

VMON3

VSENSE5

Control

Voltage

Monitoring

Voltage

Monitoring

Voltage

Monitoring

V_LDO

Figure 15. Detailed Block Diagram

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8.3 Feature Description

8.3.1 Buck Controller (BUCK1)

The main buck controller operates using constant frequency peak current mode control. The output voltage is

programmable with external resistors.

The switching frequency is set to a fixed value of f_SWBUCK1. Peak current-mode control regulates the peak current

through the inductor such that the output voltage VBUCK1 is maintained to its set value. Current mode control

allows superior line-transient response. The error between the feedback voltage VSENSE1 and the internal

reference produces an error signal at the output of the error amplifier (COMP1) which serves as target for the

peak inductor current. At S1–S2, the current through the inductor is sensed as a differential voltage and

compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at

VSENSE1, which causes COMP1 to rise or fall respectively, thus increasing or decreasing the current through

the inductor until the average current matches the load. In this way the output voltage VBUCK1 is maintained in

regulation.

Sense Resistor

V

INPROT

L

R

S

GU

HS DCR Sensing

L

R

L

PH

V

PWM

BUCK1

Gate

Drivers

Logic

GL

LS

R

DCR

C

DCR

Current

Comparator

S1

S2

Current

Sensing

V_S1-S2,INT

V

S1-S2, EXT

V_SLOPE

Slope

Compensation

R

1

VSENSE1

COMP1

gm

C

2

Error

Amp

R

2

Current Loop

(Inner Loop)

R

C

1

3

Voltage Loop (Outer Loop)

Figure 16. Detailed Block Diagram of Buck 1 Controller

The high-side N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the

inductor current reaches its peak value as set by the voltage loop. Once the high external FET is turned OFF,

and after a small delay (shoot-through delay), the lower N-channel MOSFET is turned on until the start of the

next clock cycle. In dropout operation the high-side MOSFET stays on 100%. In every fourth period the duty

cycle is limited to 95% in order to charge the bootstrap capacitor at BOOT1. This allows a maximum duty cycle

of 98.75%.

The maximum value of COMP1 is clamped so that the maximum current through the inductor is limited to a

specified value. The BUCK1 controller output voltage is monitored by a central independent voltage-monitoring

circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In addition, BUCK1

is thermally protected with a dedicated temperature sensor.

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Feature Description (continued)

8.3.2 Synchronous Buck Converters BUCK2 and BUCK3

Both regulators are synchronous converters operating with a fixed switching frequency ƒ_sw= 2.45 MHz. For each

buck converter, the output voltage is programmable with external resistors. The synchronous operation mode

improves the overall efficiency. BUCK3 switches in phase with BUCK1, and BUCK2 switches at a 216-degree

shift to BUCK3 to minimize input current ripple.

Each buck converter can provide a maximum current of 2 A and is protected against short circuits to ground. In

case of a short circuit to ground, the integrated cycle-by-cycle current limit turns off the high-side FET when its

current reaches I_HS-Limitand the low-side FET is turned on until the end of the given cycle. When the current limit

is reached in the beginning of the cycle for five consecutive cycles, the pulse-width modulation (PWM) is forced

low for sixteen cycles to prevent uncontrolled current build-up. In case the low-side current limit of I_LS-Limitis

reached, for example, because of an output short to the VSUP2 and VSUP23 pins, the low-side FET is turned off

until the end of the cycle. If this is detected shortly after the high-low PWM transition (immediately after the low-

side overcurrent comparator blanking time), both FETs are turned off for sixteen cycles.

The output voltages of the BUCK2 and BUCK3 regulators are monitored by a central independent voltage-

monitoring circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In

addition BUCK2 and BUCK3 are thermally protected with a dedicated temperature sensor.

8.3.3 BOOST Converter

The BOOST converter is an asynchronous converter operating with a fixed switching frequency ƒ_sw= 2.45 MHz.

It switches in phase with BUCK1. At low load, the boost regulator switches to pulse skipping.

The output voltage is programmable with external resistors.

The internal low-side switch can handle maximum 1-A current, and is protected with a current limit. In case of an

overcurrent, the integrated cycle-by-cycle current limit turns off the low-side FET when its current reaches

I_CLBOOSTuntil the end of the given cycle. When the current limit is reached in the beginning of the cycle for five

consecutive cycles, the PWM is forced low for sixteen cycles to prevent uncontrolled current build-up.

The BOOST converter output voltage is monitored by a central independent voltage-monitoring circuit, which has

an independent voltage-monitoring bandgap reference for safety reasons. If the V_{MONTH_L}> V_SENSE5or V_SENSE5

>

V_{MONTH_H}, the output is switched off and the BOOST_FAIL bit in the SPI PWR_STAT register is set. The BOOST

can be reactivated by setting BOOST_EN bit in the PWR_CONFIG register.

In addition, the BOOST converter is thermally protected with a dedicated temperature sensor. If T_J> T_OTTH, the

BOOST converter is switched off and bit OT_BOOST in PWR_STAT register is set. Reactivation of the booster is

only possible if the OT_BOOST bit is 0, and the booster enable bit in the PWR_CONFIG register is set to 1.

8.3.4 Frequency-Hopping Spread Spectrum

The TPS65311-Q1 features a frequency-hopping pseudo-random spectrum or triangular spreading architecture.

The pseudo-random implementation uses a linear feedback shift register that changes the frequency of the

internal oscillator based on a digital code. The shift register is designed in such a way that the frequency shifts

only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies. The triangular

function uses an up-down counter. Whenever spread spectrum is enabled (SPI command), the internal oscillator

frequency is varied from one BUCK1 cycle to the next within a band of 0.8 x f_OSC... f_OSCfrom a total of 16

different frequencies. This means that BUCK3 and BOOST also step through 16 frequencies. The internal

oscillator can also change its frequency during the period of BUCK2, yielding a total of 31 frequencies for

BUCK2.

8.3.5 Linear Regulator LDO

The LDO is a low drop out regulator with an adjustable output voltage through an external resistive divider

network. The output has an internal current-limit protection in case of an output overload or short circuit to

ground. In addition, the output is protected against overtemperature. If T_J> T_OTTH, the LDO is switched off and bit

OT_LDO in PWR_STAT register is set. Reactivation of the LDO is only possible through the SPI by setting the

LDO enable bit in the PWR_CONFIG register to 1 if the OT_LDO bit is 0.

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Feature Description (continued)

The LDO output voltage is monitored by a central independent voltage-monitoring circuit, which has an

independent voltage-monitoring bandgap reference for safety reasons. If the V_{MONTH_L}> V_SENSE4or V_SENSE4

>

V_{MONTH_H}, the output is switched off and the LDO_FAIL bit in the SPI PWR_STAT register is set. The LDO can

be reactivated through the SPI by setting the LDO_EN bit in the PWR_CONFIG register. In case of overvoltage

in VTCHECK and RAMP mode, the GPFET is turned off and the device changes to ERROR mode.

8.3.6 Gate Driver Supply

The gate drivers of the BUCK1 controller, BUCK2 and BUCK3 converters and the BOOST converter are supplied

from an internal linear regulator. The internal linear regulator output (5.8-V typical) is available at the VREG pin

and must be decoupled using a typical 2.2-μF ceramic capacitor. This pin has an internal current-limit protection

and must not be used to power any other circuits.

The VREG linear regulator is powered from VINPROT by default when the EXTSUP voltage is less than 4.6 V

(typical).

If the VINPROT is expected to go to high levels, there can be excessive power dissipation in this regulator when

using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin,

which can be connected to a supply less than VINPROT but high enough to provide the gate drive. When

EXTSUP is connected to a voltage greater than 4.8 V, the linear regulator automatically switches to EXTSUP as

its input to provide this advantage. This automatic switch-over to EXTSUP can only happen once the TPS65311-

Q1 device reaches ACTIVE mode. Efficiency improvements are possible when one of the switching regulator

rails from the TPS65311-Q1, or any other voltage available in the system is used to power EXTSUP. The

maximum voltage that must be applied to EXTSUP is 12 V.

8.3.7 RESET

RESN and PRESN are open drain outputs which are active if one or more of the conditions listed in Table 1 are

valid. RESN active (low) is extended for t_RESNHOLDafter a reset is triggered. RESN is the main processor reset

and also asserts PRESN as a slave signal.

PRESN is latched and is released when window trigger mode of the watchdog is enabled (first rising edge at the

WD pin).

RESN and PRESN must keep the main processor and peripheral devices in a defined state during power up and

power down in case of improper supply voltages or a critical failure condition. Therefore, for low supply voltages

the topology of the reset outputs specify that RESN and PRESN are always held at a low level when RESN and

PRESN are asserted, even if V_INfalls below V_PORor the device is in SHUTDOWN mode.

Loss of LPM clock

Thermal Shutdown

RESN

Mono

Flop

WD_RESET

Loss of GND

POR

≥1

Voltage Monitor Buck1-3 fail

Voltage Monitor VIO fail

Over Temperature BUCK1-3, VREG

Over Voltage LDO

PRESN

RESET

≥1

S

R

Q

WD Trigger

Over-Current BUCK1

Figure 17. RESET Functionality

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Feature Description (continued)

Table 1. Reset Conditions

RESET CONDITION

CONSEQUENCE FOR DEVICE

The device reinitializes all registers with their default values. Error counter

is cleared.

POR, Loss of LPM Clock, and Thermal Shutdown

Input voltage at V_MON1-3pin out-of-bounds:

V_VMON1-3< V_{MONTH_L}or V_VMON1-3> V_{MONTH_H}

Voltage Monitor BUCK 1-3

Over Voltage LDO

Voltage Monitor VIO

Loss of GND

V_sense4> V_{MONTH_H}

Input voltage at VIO pin out-of-bounds: V_VIO< V_{VIOMON TH}

Open at PGNDx or GND pin

OT BUCK1, BUCK2, BUCK3, VREG

WD_RESET

Overtemperature on BUCK1–3 or VREG

Watchdog window violation

Any reset event (without POR, thermal shutdown, or loss of LPM clock) increments the error counter (EC) by

one. After a reset is consecutively triggered N_REStimes, the device transfers to the LPM0 state, and the EC is

reset to 0. The counter is decremented by one if an SPI LPM0_CMD is received. Alternatively, the device can be

put in LOCK state once an SPI LOCK_CMD is received. Once the device is locked, it cannot be activated again

by a wake condition. The reset counter and lock function avoid cyclic start-up and shut-down of the device in

case of a persistent fault condition. The reset counter content is cleared with a POR condition, a thermal

shutdown or a loss of LPM clock. Once the device is locked, a voltage below V_PORat VIN pin or a thermal

shutdown condition are the only ways to unlock the device.

8.3.8 Soft Start

The output voltage slopes of BUCK, BOOST and LDO regulators are limited during ramp-up (defined by t_STARTx).

During this period the target output voltage slowly settles to its final value, starting from 0 V. In consequence,

regulators that offer low-side transistors (BUCK1, BUCK2 and BUCK3) actively discharge their output rails to the

momentary ramp-value if previously charged to a higher value.

8.3.9 Power-on Reset Flag

The POR flag in the SYS_STAT SPI register is set:

•

When V_INis below the V_PORthreshold

System is in thermal shutdown

Over or undervoltage on DVDD

Loss of low power clock

8.3.10 WAKE Pin

Only when the device is in LPM0 mode, it can be activated by a positive voltage on the WAKE pin with a

minimum pulse width t_WAKE. A valid wake condition is latched. Normal deactivation of the device can only occur

through the SPI Interface by sending an SPI command to enter LMP0. Once in LMP0, the device stays in LPM0

when the WAKE pin is low, or restarts to TESTSTART when the WAKE pin is high.

The WAKE pin has an internal pulldown resistance R_PD-WAKE, and the voltage on the pin is not allowed to exceed

60 V. A higher voltage compliance level in the application can be achieved by applying an external series resistor

between the WAKE pin and the external wake-up signal.

The device cannot be re-enabled by toggling the WAKE pin when the device is in LOCKED state (by SPI

command).

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PowerOn

Reset

VIN > V_POR

(EC==0)

VT>VT_TH-H_{(if enabled)}

VT_ref_ok = ”1‘

AND VT<VT_TH-L

AND vreg_ok = ”1‘

AND SMPS clock O.K.

VTCHECK

RAMP

no OV (BUCK1, LDO)

Independent voltage monitors

(IVM)

OV (BUCK1, LDO)

OR OV (BUCK2,

BUCK3 if enabled)

AND T < T_OTTH

J

Timeout**

AND WAKE

terminal low

INIT

OR T > T_OTTH

J

OV (BUCK1, LDO)

(BUCK1-3,VREG)

OR vreg_ok = ”0‘

OR VT_ref_ok = ”0‘

OR no SMPS clock

OR BUCK1 OC

OR GND LOSS

(EC++)

OR Tj > T_OTTH

(BUCK1-3,VREG)

OR GND LOSS

(EC++)

TESTSTOP

CRC=O.K.

AND EE ready

AND Vreg_ok = 0

READY****

UV and OV

Independent voltage

monitors

Timeout**

AND WAKE

terminal low

and VIO

Timeout**

AND WAKE

terminal low

Voltage Monitors < V_MONTHL

AND T < T_OTTH

J

TESTSTART

ERROR

EC=N_RES(ECã0, EC_OFã1)

Timeout**

AND WAKE

terminal low

VT>VT_TH-H

(if enabled)

WD Reset

(EC++)

All RESET events*** (w/o WD)

OR vreg_ok = ”0‘

Wake

(WAKE

OR vref_ok = ”0‘

OR VT_REF_ok = ”0‘

OR no SMPS clock

(EC++)

terminal high)

EC=N_RES

(ECã0, EC_OFã1)

OR SPI LPM0 CMD

(EC--)

ACTIVE

LPM0

SPI LOCK CMD

LOCKED

T

>T_SDTHOR VIN < V_POR

OR DVDD UV/OV

* GPFET is turned on in VTCHECK, RAMP, ACTIVE and if

VIN<VIN_OV

J

OR loss of low power clock

** TIMEOUT counter is reset with every state transition

*** RESET EVENTS : WD, GROUND LOSS, VOLTAGE

MONITOR BUCK1, MONITOR BUCK2-3(if enabled), Over

Voltage LDO (if enabled), VOLTAGE MONITOR VIO,

OVERTEMPERATURE BUCK1-3 OR VREG, BUCK1

OVERCURRENT

SHUTDOWN

Generation of

POR

**** READY = VREF_OK and not BUCK1_UV and Power Up

Sequence completed

Figure 18. Operating Mode Transitions

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8.3.11 IRQ Pin

The IRQ pin has two different functions. In OPERATING mode, the pin is forced low when the voltage on the

battery line is below the V_SSENSETHxthreshold. The IRQ pin is low as long as PRESN is low. If PRESN goes high

and the battery line is already below the V_SSENSETHxthreshold, the IRQ pin is forced high for t_{VSSENSE_BLK}

.

8.3.12 VBAT Undervoltage Warning

•

Low battery condition on VSSENSE asserts IRQ output (interrupt for µC, open drain output)

Sense input can be directly connected to VBAT through the resistor

Detection threshold for undervoltage warning can be selected through the SPI.

An integrated filter time avoids false reaction due to spikes on the VBAT line.

8.3.13 VIN Over or Undervoltage Protection

•

Undervoltage is monitored on the V_INline, for POR generation.

Two V_INovervoltage shutdown thresholds (V_OVTH) can be selected through the SPI. After POR, the lower

threshold is enabled.

•

During LPM0, only the POR condition is monitored.

An integrated filter time avoids false reaction due to spikes on the V_INline.

In case of overvoltage, the external PMOS is switched off to protect the device. The BUCK1 controller is not

switched off and it continues to run until the undervoltage on VREG or BUCK1 output is detected.

VINPROT

VBAT

VSSENSE

VIN

GPFET

IRQ

UV

OV

LOCKED

ERROR

LPM0

PWR_CMD

Bit0

LV_THRES

=

≥1

INIT

TESTSTART

TESTSTOP

DVDD

+ POR

Figure 19. Overvoltage or Undervoltage Detection Circuitry

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8.3.14 External Protection

The external PMOS switch is disabled if:

•

The device detects V_INovervoltage

The device is in ERROR, LOCKED, POR, INIT, TESTSTART, TESTSTOP or LPM0 mode

NOTE

Depending on the application, the external PMOS may be omitted as long as

VBAT < 40 V

VSSENSE

VIN

PCH

GPFET

VINPROT

20µA

50 œ 60V

GND

Figure 20. PMOS Control Circuitry

8.3.15 Overtemperature Detection and Shutdown

There are two levels of thermal protection for the device.

Overtemperature is monitored locally on each regulator.

OT for BUCK1, BUCK2, and BUCK3 If a thermal monitor on the buck rails reaches a threshold higher than

T_OTTH, the device enters ERROR mode. Leaving ERROR mode is only possible if the temperature

is below T_OTTH–T_OTHY

.

OT for BOOST and LDO If the temperature monitor of the boost or the LDO reaches the T_OTTHthreshold, the

corresponding regulator is switched off.

Overtemperature Shutdown is monitored on a central die position. In case the T_SDTHis reached, the device

enters shutdown mode. It leaves shutdown when the TSD sensor is below T_SDTH– T_SDHY. This

event internally generates a POR.

8.3.16 Independent Voltage Monitoring

The device contains independent voltage-monitoring circuits for BUCK1–3, LDO, VIO and BOOST. The

reference voltage for the voltage monitoring unit is derived from an independent bandgap. BUCKs 1–3 use

separate input pins for monitoring. The monitoring circuit is implemented as a window comparator with an upper

and lower threshold.

If there is a violation of the upper (only LDO [RAMP, VTCHECK], or BUCK1–3) or lower threshold (only

BUCK1–3, or VIO), the device enters ERROR mode, RESN and PRESN are asserted low, the external PMOS

(main system switch) is switched off, and the EC is incremented.

In TESTSTART mode, a self-test of the independent voltage monitors is performed.

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In case any of the supply rails for BUCK2, BUCK3, LDO or BOOST are not used in the application, the

respective VMON2 and VMON3 or VSENSE4 and VSENSE5 pin of the unused supply must be connected to

VMON1. Alternatively, the VSENSE4 pin can also be connected directly to ground in case the LDO is not used.

8.3.17 GND Loss Detection

All power grounds PGNDx are monitored. If the voltage difference to GND exceeds V_GLTH-lowor V_GLTH-high, the

device enters ERROR mode. RESN and PRESN are asserted low, the external PMOS (main system switch) is

switched off, and the EC is incremented.

8.3.18 Reference Voltage

The device includes a precise voltage reference output to supply a system ADC. If this reference voltage is used

in the application, a decoupling capacitor between 0.6 and 5 µF must be used. If this reference voltage is not

used in the application, this decoupling capacitor can be left out. The VREF output is enabled in RAMP state.

The output is protected against a short to GND.

8.3.19 Shutdown Comparator

An auxiliary, short circuit protected output supplied from DVDD is provided at the VT_REF pin. This output is

used as a reference for an external resistive divider to the VT pin. In case a voltage > VTTH is detected on the

VT pin, the main switch (external PMOS driven by GPFET) is switched off. This functionality can be used to

monitor over and under temperature (using a NTC resistor) to avoid operation below or above device

specifications.

If the voltage at VT_REF falls below V_{VT_REF SH}while the shutdown comparator is enabled, an ERROR transition

occurs. The shutdown comparator is enabled in VTCHECK state, and can be turned off by SPI. Disabling the

comparator saves power by also disabling the VT_REF output.

8.3.20 LED and High-Side Switch Control

This module controls an external PMOS in current-limited high-side switch.

The current levels can be adjusted with an external sense resistor. Enable and disable is done with the HS_EN

bit. The switch is controlled by the HSPWM input pin. Driving HSPWM high turns on the external FET.

The device offers an open load diagnostic indicated by the HS_OL flag in the SPI register PWR_STAT. Open

load is also indicated in case the voltage on VINPROT–VSSENSE does not drop below the threshold when PWM

is low (self-test).

A counter monitors the overcurrent condition to detect the risk of overheating. While HSPWM = high and HS_EN

= high the counter is incremented during overcurrent conditions, and decremented if the current is below the

overcurrent threshold at a sampling interval of t_{S HS}(see Figure 22). When reaching a net current limit time of t_HSS

_CL, the driver is turned off and the HS_EN bit is cleared. This feature can be disabled by SPI bit HS_CLDIS.

When HS_EN is cleared, the counter is reset.

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VINPROT

HSPWM

V_{HSOL_TH}

V_HSSENSE

OL

HSSENSE

HSCTRL

V_{HS_SC}

SC

ECU

Connector

Figure 21. High-Side Control Circuit

V_HSPWM

PWM

V_VINPROT- V_HSSENSE

V_HSSENSE

V_{HS_SC}

counter_max) t_{HSS_CL}

HS_EN

HS_CLDIS

Figure 22. HS Overcurrent Counter

NOTE

In case the LED or high-side switch control is not used in the application, HSSENSE must

be connected to VINPROT.

8.3.21 Window Watchdog

The WD is used to detect a malfunction of the MCU and DSP. Description:

•

Timeout trigger mode with long timing starts on the rising edge at RESN

Window trigger mode with fixed timing after the first and each subsequent rising edge at the WD pin

Watchdog is triggered by rising edge at the WD pin

A watchdog reset happens by:

•

A trigger pulse outside the WD trigger open window

No trigger pulse during window time

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After the RESN pin is released (rising edge) the DSP and MCU must trigger the WD by a rising edge on the WD

pin within a fixed time t_timeout. With this first trigger, the window watchdog functionality is released.

Start of t_WDtime with a

rising edge of WD

V_WD

WD Trigger fail

WD Trigger open window

t_{WD_FAIL_min}

t_{WD_FAIL_max}

t

t_{WD1_min}

t_{WD_min}

t_{WD_max}

Figure 23. WD Window Description

8.3.22 Timeout in Start-Up Modes

A timer is used to limit the time during which the device can stay in each of the start-up modes: TESTSTART,

TESTSTOP, VTCHECK and RAMP. If the device enters one of these start-up modes and V_INor VT is not in a

proper range, the part enters LPM0 after t_timeoutis elapsed and the WAKE pin is low.

8.4 Device Functional Modes

8.4.1 Operating Modes

8.4.1.1 INIT

Coming from a power-on reset the device enters INIT mode. The configuration data from the EEPROM is loaded

in this mode. If the checksum is valid and the internal VREG monitor is indicating an undervoltage condition (self-

test VREG comparator), the device enters TESTSTART.

8.4.1.2 TESTSTART

TESTSTART mode is entered:

•

After the INIT state (coming from power on)

After detecting that VT > VT_TH-H

After ERROR mode and the fail condition is gone

After a wake command in LPM0

In this mode the OV and UV comparators of BUCK1, BUCK2, BUCK3, BOOST, LDO and VIO are tested. The

test is implemented in such a way that during this mode all comparators have to deliver a 1 (fail condition). If this

is the case the device enters TESTSTOP mode.

If this is not the case, the device stays in TESTSTART. If the WAKE pin is low, the device enters LPM0 after

t_timeout. If the pin WAKE is high, the part stays in TESTSTART.

8.4.1.3 TESTSTOP

In this mode the OV and UV comparators are switched to normal operation. It is expected that only the UV

comparators give a fail signal. In case there is an OV condition on any rail or one of the rails has an

overtemperature the device stays in TESTSTOP. If the WAKE pin is low the device enters LPM0 mode after

t_timeout. If the WAKE pin is high, the part stays in TESTSTOP. If there is no overvoltage and overtemperature

detected, the part enters VTCHECK mode.

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Device Functional Modes (continued)

8.4.1.4 VTCHECK

VTCHECK mode is used to:

1. Switch on external GPFET in case VIN < V_{OVTH_L}

2. Turn on VREG regulator and VT_REF

3. Check if voltage on pin VT < VT_TH-L

4. Check if SMPS clock is running correctly

5. Check if VREG,VT_REF exceed the minimum voltage

If all checks are valid the part enters the RAMP state. In case the device is indicating a malfunction and the

WAKE pin is low, the device enters LPM0 after t_timeoutto reduce current consumption.

In case the voltage monitors detect an overvoltage condition on BUCK1, BUCK2, BUCK3, or LDO, a loss of GND

or an overtemperature condition on BUCK1, BUCK2, BUCK3, or VREG the device enters ERROR mode and the

error counter is increased.

8.4.1.5 RAMP

In this mode the device runs through the power-up sequencing of the SMPS rails (see Figure 24).

8.4.1.5.1 Power-Up Sequencing

After the power-up sequence (see Figure 24), all blocks are fully functional. BUCK1 starts first. After t_SEQ2

elapses and BUCK1 is above the undervoltage threshold, BUCK2 and BOOST start. BUCK3 and VREF start one

t_SEQ1after BUCK2. After the release of RESN pin, the µC can enable the LDO per SPI by setting bit 4 LDO_EN

in PWR_CONFIG register to 1 (per default, this LDO_EN is set to 0 after each reset to the µC).

In case any of the following conditions occurduring power-up sequencing, the device enters ERROR mode and

the error counter (EC) is increased:

•

Overtemperature on BUCK1, BUCK2, BUCK3 or VREG

Overvoltage on BUCK1, BUCK2, BUCK3 or LDO

Overcurrent on BUCK1

SMPS clock fail

VT_REF and VREG undervoltage

Loss of GND

In case VT > VT_TH-H, the device transitions to TESTSTART.

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Device Functional Modes (continued)

WakeUp event through WAKE terminal

V_POR

VIN

t_START

VINPROT

V_REG-OK/ V_{VT_REF_SH}

VREG/

VT_REF

V_{MONTH_L}+ V_{MON_HY}

BUCK1

BUCK1 > V_{MONTH_L}+ V_{MON_HY}AND t_SEQ2elapsed before BUCK2 and BOOST are enabled

t_START2

t_SEQ2

V_{MONTH_L}+ V_{MON_HY}

BOOSTER

t_START1

V_{MONTH_L}+ V_{MON_HY}

BUCK2

VREF

t_START2

V_{REF_OK}

V_{MONTH_L}+ V_{MON_HY}

BUCK3

LDO

LDO enabled through SPI by mC

t_SEQ1

t_START2

V_{MONTH_L}+ V_{MON_HY}

t_START2

t_RESNHOLD

RESN

t_WAKE-RES

WD

Only when device

is in ACTIVE state

PRESN

In case of permanent supply with the device in LPM0 mode, the start point of VREG-VT_REF is with the rising

edge of WAKE. In case of non-permanent supply, the rising edge of the VSSENSE and VIN terminals initiates

the start-up sequence

Figure 24. Power-up Sequencing

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Device Functional Modes (continued)

After the power-up sequence is completed (except LDO) without detecting an error condition, the device enters

ACTIVE mode.

8.4.1.5.2 Power-Down Sequencing

There is no dedicated power-down sequencing. All rails are switched off at the same time. The external FETs of

BUCK1 are switched off and the outputs of BUCK2, BUCK3, BOOST (PHx) and the LDO are switched in a high-

impedance state.

8.4.1.6 ACTIVE

This is the normal operating mode of the device. Transitions to other modes:

→ ERROR

The device is forced to go to ERROR in case of:

•

Any RESET event (without watchdog reset)

VREG, VREF, or VT_REF below undervoltage threshold

SMPS clock fail

During the transition to ERROR mode the EC is incremented.

→ LOCKED

In case a dedicated SPI command (SPI_LOCK_CMD) is issued.

→ TESTSTART

The device moves to TESTSTART after detecting that VT < VT_TH-L

.

→ LPM0

The device can be forced to enter LPM0 with a SPI LPM0 command. During this transition the EC is

decremented.

If the EC reaches the N_RESvalue, the device transitions to LPM0 mode and EC is cleared. Depending on the

state of the WAKE pin, the device remains in LMP0 (WAKE pin low) or restart to TESTSTART (WAKE pin high).

To indicate the device entered LPM0 after EC reached N_RESvalue, a status bit EC_OF (error counter overflow,

SYS_STAT bit 3) is set. The EC_OF bit is cleared on read access to the SYS_STAT register.

A watchdog reset in ACTIVE mode only increases the EC, but it does not change the device mode.

8.4.1.7 ERROR

In this mode all power stages and the GPFET are switched off. The devices leave ERROR mode and enter

TESTSTART if:

•

All rails indicate an undervoltage condition

No GND loss is detected

No overtemperature condition is detected

When the EC reaches the N_RESvalue, the device transitions to LPM0 and the EC is cleared. To indicate the

device entered LPM0 after EC reached N_RES, a status bit EC_OF (error counter overflow, SYS_STAT bit 3) is

set. The EC_OF bit is cleared on read access to the SYS_STAT register.

8.4.1.8 LOCKED

Entering this mode disables the device. The only way to leave this mode is through a power-on reset, thermal

shutdown, or the loss of an LPM clock.

8.4.1.9 LPM0

Low-power mode 0 is used to reduce the quiescent current of the system when no functionality is needed. In this

mode the GPFET and all power rails except for DVDD are switched off.

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Device Functional Modes (continued)

In case a voltage > V_{WAKE_ON}longer than t_WAKEis detected on the WAKE pin, the part switches to TESTSTART

mode.

8.4.1.10 SHUTDOWN

The device enters and stays in this mode, as long as T_J> T_SDTH- T_SDHYor V_IN< V_PORor DVDD under or

overvoltage, or loss of low power clock is detected. Leaving this mode and entering INIT mode generates an

internal POR.

8.5 Programming

8.5.1 SPI

The SPI provides a communication channel between the TPS65311-Q1 and a controller. The TPS65311-Q1 is

always the slave. The controller is always the master. The SPI master selects the TPS65311-Q1 by setting CSN

(chip select) to low. SDI (slave in) is the data input, SDO (slave out) is the data output, and SCK (serial clock

input) is the SPI clock provided by the master. If chip select is not active (high), the data output SDO is high

impedance. Each communication consist of 16 bits.

1 bit parity (odd) (parity is built over all bits including: R/W, CMD_ID[5:0], DATA[7:0])

1 bit R/W; read = 0 and write = 1

6 bits CMD identifier

8 bits data

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10

Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Parity

R/W

CMD_ID5 CMD_ID4 CMD_ID3 CMD_ID2 CMD_ID1 CMD_ID0 DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Figure 25. SPI Bit-Frame

Each command is valid if:

•

A valid CMD_ID is sent

The parity bit (odd) is correct

Exactly 16 SPI clocks are counted between falling and rising edge of CSN

The response to each master command is given in the following SPI cycle. The response address is the CMD_ID

of the previous sent message and the corresponding data byte. The response data is latched with the previous

cycle such that a response to a write command is the status of the register before the write access. (Same

response as a read access.) The response to an invalid command is the original command with the correct parity

bit. The response to an invalid number of SPI clock cycles is a SPI_SCK_FAIL communication (CMD_ID = 0x03).

Write access to a read-only register is not reported as an SPI error and is treated as a read access. The initial

answer after the first SPI command sent is: CMD_ID[5:0] = 0x3F and Data[7:0] 0x5A.

8.5.1.1 FSI Bit

The slave transmits an FSI bit between the falling edge of CSN and the rising edge of SCK. If the SDO line is

high during this time, a failure occurred in the system and the MCU must use the PWR_STAT to get the root

cause. A low level of SDO indicates normal operation of the device.

The FSI bit is set when: PWR_STAT ! = 0x00, or (SYS_STAT and 0x98) ! = 0x00, or SPI_STAT ! = 0x00. The

FSI is cleared when all status flags are cleared.

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8.6 Register Map

CMD_ID

0x00

0x03

0x11

0x12

0x21

0x22

0x23

0x24

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x31

0x32

0x33

NAME

Bit7

Bit6

Bit5

Bit4

Bit3

0x00

SCK[3]

0xAA

Bit2

Bit1

Bit0

NOP

SPI_SCK_FAIL

LPM0_CMD

LOCK_CMD

PWR_STAT

SYS_STAT

SPI_STAT

1

0

SCK_OF

SCK[2]

SCK[1]

SCK[0]

0x55

BUCK_FAIL

WD

VREG_FAIL

POR

OT_BUCK

TestMode

OT_LDO

OT_BOOST

EC_OF

LDO_FAIL

EC2

BOOST_FAIL

EC1

HS_OL

EC0

SMPCLK_FAIL

CLOCK_FAIL

BUCK3-0

CMD_ID FAIL

BUCK2-1

PARITY FAIL

BUCK2-0

COMP_STAT

Serial Nr 1

Serial Nr 2

Serial Nr 3

Serial Nr 4

Serial Nr 5

Serial Nr 6

DEV_REV

BUCK3-1

Bit [7:0]

Bit [15:8]

Bit [23:16]

Bit [31:24]

Bit [39:32]

Bit [47:40]

Minor3

Major3

F_EN

Major2

Major1

Major0

Minor2

HS_EN

VT_EN

F2

Minor1

Minor0

IRQ_THRES

RSV

PWR_CONFIG

DEV_CONFIG

CLOCK_CONFIG

BUCK2_EN

BUCK3_EN

LDO_EN

BOOST_EN

HL_CLDIS

F3

GPFET_OV_HIGH

RSV

F1

SS_EN

SS_MODE

F4

F0

8.6.1 Register Description

NOP 0x00

Bit7

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

After RESET

Read

0

Write

d.c.

SPI_SCK_FAIL 0x03

Bit7

1

Bit6

Bit5

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

Default after

RESET

0

Read

Write

1

0

SCK_OF

d.c.

SCK[3]

d.c.

SCK[2]

d.c.

SCK[1]

d.c.

SCK[0]

d.c.

BIT NAME

BIT NO.

DESCRIPTION

Between a falling and a rising edge of CSN, the number of SCK was greater than 16.

0:

SCK_OF

4

1:

Number of SCK cycles was > 16

Comment: This flag is cleared after its content is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

The number of rising edges on SCK between a falling and a rising edge of CSN minus 1. Saturates at 0xF if

16 or more edges are received.

SCK[3:0]

3:0

Comment: This flag is cleared after its content is transmitted to the master.

LPM0_CMD 0x11

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

After RESET

Read

0

Write

0xAA

This command is used to send the device into LPM0 mode.

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LOCK_CMD 0x12

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

After RESET

Read

0

Write

0x55

Sending a lock command (0x55) brings the device into LOCK mode. Only a POR brings the device out of this state.

PWR_STAT 0x21

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

0

Bit1

0

Bit0

0

Default after

POR

Read

Write

BUCK_FAIL VREG_FAIL

OT_BUCK

d.c.

OT_LDO

d.c.

OT_BOOST

d.c.

LDO_FAIL

d.c.

BOOST_FAIL

d.c.

HS_OL

d.c.

BIT NAME

BIT NO.

DESCRIPTION

BUCK power fail flag

0:

BUCK_FAIL

7

1:

Power stages shutdown detected caused by OC BUCK1, UV, OV, loss of GND (BOOST + all bucks)

BUCK_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

Internal voltage regulator too low

0:

VREG_FAIL

6

1:

VREG fail

VREG_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

BUCK1-3 overtemperature flag

0:

OT_BUCK

5

1:

IC power stages shutdown due to overtemperature

OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

LDO overtemperature flag

0:

OT_LDO

4

1:

LDO shutdown due to overtemperature

OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

Boost overtemperature flag

0:

OT_BOOST

3

1:

BOOST shutdown due to overtemperature

OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

LDO under or overvoltage flag

0:

LDO_FAIL

2

1:

LDO out of regulation

LDO_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag is transmitted to the master.

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BIT NAME

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BIT NO.

DESCRIPTION

Booster under or overvoltage flag or loss of GND

BOOST_FAIL

1

0:

1:

Booster out of regulation

BOOST_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag was transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

High-side switch open load condition

0:

HS_OL

0

1:

Open load at high side

Bit indicates current OL condition of high side (no flag)

SYS_STAT 0x22

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

0

Bit1

0

Bit0

1

Default after

POR

0

Read

Write

WD

d.c.

POR

d.c.

Testmode

d.c.

SMPCLK_FAIL

d.c.

0

EC2

d.c.

EC1

d.c.

EC0

d.c.

BIT NAME

BIT

NO.

DESCRIPTION

Watchdog reset flag

0:

WD

7

1:

Last reset caused by watchdog

Comment: This flag is cleared after its content is transmitted to the master.

BIT NAME

BIT

NO.

Power-on reset flag

0:

POR

6

1:

Last reset caused by a POR condition

Comment: This flag is cleared after its content is transmitted to the master.

BIT NAME BIT NO.

If this bit is set, the device entered test mode

Testmode

5

0:

1:

Device in Testmode

Comment: This flag is cleared after its content is transmitted to the master and the device left the test mode.

BIT NAME BIT NO.

DESCRIPTION

If this bit is set, the clock of the switch mode power supplies is too low.

SMPCLK_

4

0:

1:

Clock OK

Clock fail

FAIL

Comment: This flag is cleared after its content is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

Actual error flag counter

EC [2:0]

0-2

0:

1:

-

*Error Counter is only deleted with a POR

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SPI_STAT 0x23

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

Bit1

Bit0

Default after RESET

0

Read

Write

0

CLOCK_FAIL

d.c.

CMD_ID FAIL

d.c.

PARITY FAIL

d.c.

BIT NAME

BIT NO.

DESCRIPTION

Between a falling and a rising edge of CSN, the number of SCK does not equal 16

0:

CLOCK_FAIL

2

1:

Wrong SCK

Comment: This flag is cleared after its content is transmitted to the master.

BIT NAME

BIT NO.

DESCRIPTION

Last received CMD_ID in a reserved area

0:

CMD_ID FAIL

1

1:

Wrong CMD_ID

Comment: This flag is cleared after its content is transmitted to the master and is not set if the number of SCK cycles is incorrect.

BIT NAME

BIT

DESCRIPTION

NO.

Last received command has a parity bit failure

0:

PARITY_FAIL

0

1:

Parity bit error

Comment: This flag is cleared after its content is transmitted to the master and is not set if the number of SCK cycles is incorrect.

COMP_STAT 0x24

Bit7

0

Bit6

0

Bit5

0

Bit4

0

Bit3

0

Bit2

1

Bit1

1

Bit0

0

Default after

RESET

Read

Write

0

BUCK3-1

d.c.

BUCK3-0

d.c.

BUCK2-1

d.c.

BUCK2-0

d.c.

Register to read back the actual BUCK2/3 compensation settings on COMP2/3. 0x1 ≥ 0 V 0 x 2 ≥ VREG 0 x 3 ≥ open

DEV_REV 0x2F

Bit7

Major3

d.c.

Bit6

Major2

d.c.

Bit5

Major1

d.c.

Bit4

Major0

d.c.

Bit3

Minor3

d.c.

Bit2

Minor2

d.c.

Bit1

Minor1

d.c.

Bit0

Minor0

d.c.

After RESET

Read

Write

Hard coded device revision can be read from this register

PWR_CONFIG 0x31

Bit7

0

Bit6

1

Bit5

1

Bit4

0

Bit3

1

Bit2

Bit1

Bit0

0

Default after RESET

0

Read

Write

0

BUCK2_EN

BUCK3_EN

LDO_EN

BOOST_EN

HS_EN

GPFET_OV_HIGH

IRQ_THRES

0

This register contains all power rail enable bits.

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BIT NAME

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BIT NO.

DESCRIPTION

BUCK2 enable flag

0:

BUCK2_EN

6

1:

After reset, BUCK2 is enabled

Enable BUCK2

BIT NAME

BIT NO.

DESCRIPTION

BUCK3 enable flag

0:

BUCK3_EN

5

1:

After reset, BUCK3 is enabled

Enable BUCK3

BIT NAME

BIT NO.

LDO enable flag

LDO_EN

4

0:

1:

LDO enabled

After reset, LDO is disabled

BIT NAME

BIT NO.

BOOST enable

0:

BOOST_EN

3

1:

After reset, BOOST is enabled

BOOST enabled

BIT NAME

BIT

NO.

LED and high-side switch enable

HS_EN

2

0:

1:

High side disabled

High side enabled

After reset, high side is disabled

BIT NAME

BIT

DESCRIPTION

NO.

Protection FET overvoltage shutdown

GPFET_OV_HIGH

1

0: Protection FET switches off at VIN > V_OVTH-L

1: Protection FET switches off at VIN > V_OVTH-H

After reset, the lower VIN protection threshold is enabled

BIT NAME

BIT NO.

DESCRIPTION

VSSENSE IRQ low voltage interrupt threshold select

IRQ_THRES

0

0:

1:

Low threshold selected (V_{SSENSETH_L}

)

High threshold selected (V_{SSENSETH_H}

)

After reset, the lower VBAT monitoring threshold is enabled

DEV_CONFIG 0x32

Bit7

0

Bit6

0

Bit5

0

Bit4

Bit3

0

Bit2

1

Bit1

1

Bit0

0

Default after RESET

0

Read

Write

0

VT_EN

RSV

1

RSV

0

d.c.

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BIT NAME

BIT NO.

DESCRIPTION

LED and high-side switch current limit counter disable bit

HS_CLDIS

3

0:

1:

LED and high-side switch current limit counter enabled

LED and high-side switch current limit counter disabled

BIT NAME

BIT NO.

DESCRIPTION

VT enable bit

VT_EN

2

0:

1:

VT monitor disabled

VT monitor enabled

The VT monitor cannot be turned on after it was turned off. Turn on only happens during power up in the VTCHECK state.

BIT NAME

BIT NO.

DESCRIPTION

Voltage reference enable bit

RSV

1

0:

1:

not recommended setting

default setting

BIT NAME

BIT NO.

DESCRIPTION

Reserved - keep this bit at 1

RSV

0

0:

1:

default setting

not recommended setting

CLOCK_CONFIG 0x33

Bit7

0

Bit6

0

Bit5

Bit4

Bit3

Bit2

0

Bit1

0

Bit0

0

Default after

RESET

0

1

0

Read

Write

F_EN

SS_EN

SS_MODE

F4

F3

F2

F1

F0

BIT NAME BIT NO.

DESCRIPTION

Frequency tuning enable register

F_EN

7

0:

1:

Off – Setting of Bit4…Bit0 are not effective, setting of Bit6 and Bit5 become effective

On – Setting of Bit4…Bit0 become effective, setting of Bit6 and Bit5 are not effective

BIT NAME BIT NO.

DESCRIPTION

Spread spectrum mode enable

SS_EN

6

0:

1:

Spread spectrum option for all switching regulators disabled

Spread spectrum option for all switching regulators enabled (only when F_EN = 0)

When enabled, the switching frequency of BUCK1/2/3 and BOOST is modulated between 0.8×f_oscand f_osc

BIT NAME BIT NO.

DESCRIPTION

Spread spectrum mode select (effective only when F_EN = 0)

SS_MODE

5

0:

1:

Pseudo random

Triangular

BIT NAME

BIT

DESCRIPTION

NO.

F4, F3, F2, F1,

F0

4-0

Frequency tuning register (effective only when F_EN = 1)

0x10 is default value, trim range is 25% for 0x00 setting to –20% for 0x1F setting. Frequency tuning influences the switching frequency of

BUCK1/2/3 and BOOST as well as the watchdog timing.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS65311-Q1 device is a multi-rail power supply including one buck controller, two buck converters, one

boost converter and one linear regulator (LDO). The buck controller is typically used to convert a higher car

battery voltage to a lower DC voltage which is then used as pre-regulated input supply for the buck converters,

boost converter, and the linear regulator. Use the following design procedure and application example to select

component values for the TPS65311-Q1 device.

9.2 Typical Applications

9.2.1 Buck Controller (BUCK1)

4 V to 40 V

D1

(typ. 12 V)

VBAT

VINPROT

10

BOOT1

Q2

Q3

11

12

13

14

GU

PH1

GL

PGND1

TPS65311-Q1

1.2 nF

C1

24 kꢀ

18

COMP1

R3

C2 33 pF

15

16

S1

S2

V_BUCK1

3.3 V,

2.3 A max

19

17

VSENSE1

VMON1

V_BUCK1

Figure 26. Buck Controller Schematic

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Typical Applications (continued)

9.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

12 V

Input voltage

Output voltage (V_BUCK1

Maximum output current (I_{max_peak_coil}

Load Step ΔI_OUT

)

3.3 V

)

2.3 A

1 A

Output current ripple I_{L_ripple}

Output voltage ripple

500 mA

3 mV

Allowed voltage step on output ΔV_OUT

Switching frequency (f_SWBUCK1

Bandwidth (F_BW

0.198 (or 6%)

490 kHz

≈ 60 kHz

)

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Adjusting the Output Voltage for the BUCK1 Controller

A resistor divider from the output node to the VSENSE1 pin sets the output voltage. TI recommends using 1%

tolerance or better divider resistors. Start with 16 kΩ for the R1 resistor and use Equation 1 to calculate R2 (see

Figure 26).

R1´ (V_BUCK1- 0.8 V)

R2 =

0.8 V

(1)

Therefore, for the value of V_BUCK1to equal to 3.3 V, the value of R2 must be 50 kΩ.

For voltage monitoring of the BUCK1 output voltage, placing an additional resistive divider with the exact same

values from the output node to the VMON1 pin is recommended for safety reasons (see Figure 26). If no safety

standard must be fulfilled in the application, the VMON1 pin can be directly connected to VSENSE1 pin without

the need for this additional resistive divider.

9.2.1.2.2 Output Inductor, Sense Resistor, and Capacitor Selection for the BUCK1 Controller

An external resistor senses the current through the inductor. The current sense resistor pins (S1 and S2) are fed

into an internal differential amplifier which supports the range of VBUCK1 voltages. The sense resistor R_Smust

be chosen so that the maximum forward peak current in the inductor generates a voltage of 75 mV across the

sense pins. This specified typical value is for low duty cycles only. At typical duty-cycle conditions around 28%

(assuming 3.3-V output and 12-V input), 50 mV is a more reasonable value, considering tolerances and

mismatches. The typical characteristics (see Figure 2) provide a guide for using the correct current-limit sense

voltage.

60 mV

R_S=

I_{max_peak}

(2)

Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation

at all conditions. In order to specify optimal performance of this circuit, the following condition must be satisfied in

the choice of inductor and sense resistor:

L = 410´R_s

where

•

L = inductor in µH

R_s= sense resistor in Ω

(3)

The current sense pins S1 and S2 are high impedance pins with low leakage across the entire VBUCK1 range.

This allows DCR current sensing (see Figure 16) using the DC resistance of the inductor for better efficiency.

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For selecting the output capacitance and its ESR resistance, the following set of equations can be used:

2 ´ DI_OUT

C_OUT

R_ESR

>

<

ƒ_SW´ DV_OUT

I_L

_

1

ripple

´

8´ ƒ_SWV_{o _ripple}

V_{o _ripple}

I_L

_

ripple

where

•

ƒ_swis the 490-kHz switching frequency

ΔI_OUTis the worst-case load step from the application

ΔV_OUTis the allowed voltage step on the output

V_{o_ripple}is the allowed output voltage ripple

I_{L_ripple}is the ripple current in the coil

(4)

9.2.1.2.3 Compensation of the Buck Controller

The main buck controller requires external type 2 compensation on pin COMP1 for normal mode operation. The

components can be calculated as follows.

1. Select a value for the bandwidth, F_BW, to be between f_SWBUCK1/ 6 (faster response) and f_SWBUCK1/ 10 (more

conservative)

2. Use Equation 5 to select a value for R3 (see Figure 16).

2p ´ F ´ V_OUT1´ C_OUT1

R3 =

BW

gm ´ K_CFB´ V

refBUCK

where

•

C_OUT1is the load capacitance of BUCK1

gm is the error amplifier transconductance

K_CFB= 0.125 / R_s

V_refBUCKis the internal reference voltage

(5)

3. Use Equation 6 to select a value for C1 (in series with R3, see Figure 16) to set the zero frequency close to

F_BW/ 10.

10

C1=

2p ´ R3´ F

BW

(6)

4. Use Equation 7 to select a value for C2 (parallel with R3, C1, see Figure 16) to set the second pole below

f_SWBUCK1/ 2

1

C2 =

2p ´ R3´ F ´ 3

BW

(7)

For example:

f_SWBUCK1= 490 kHz, V_refBUCK= 0.8 V, F_BW= 60 kHz

V_OUT1= 3.3 V, C_OUT1= 100 µF, R_s= 22 mΩ

Selected values: R3 = 24 kΩ, C1 = 1.2 nF, C2 = 33 pF

Resulting in F_BW: 58 kHz

Resulting in zero frequency: 5.5 kHz

Resulting in second pole frequency: 201 kHz

Stability and load step response must be verified in measurements to fine tune the values of the compensation

components.

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9.2.1.2.4 Bootstrap Capacitor for the BUCK1 Controller

The BUCK1 controller requires a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF. The bootstrap

capacitor is located between the PH1 pin and the BOOT1 pin (see Figure 26). The bootstrap capacitor must be a

high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

9.2.1.3 BUCK 1 Application Curve

100

90

80

70

60

VBAT = 5 V

VBAT = 8.1 V

VBAT = 10 V

VBAT = 14 V

VBAT = 18 V

VBAT = 22 V

VBAT = 26 V

VBAT = 30 V

VBAT = 34 V

50

40

30

20

VBAT = 36 V

VBAT = 37 V

10

0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

Load Current (A)

D001

Figure 27. Efficiency Results of Buck1

9.2.2 Synchronous Buck Converters BUCK2 and BUCK3

TPS65311-Q1

V_BUCK1

30

VSUP2

3.3 V

29

BOOT2

1 µH

V_Buck2

31

PH2

1.2 V, 2 A max

34

COMP2

32

PGND2

35

VSENSE2

33

VMON2

V_BUCK1

41

VSUP3

3.3 V

42

BOOT3

1.2 µH

V_Buck3

40

PH3

1.8 V, 2 A max

37

COMP3

39

PGND3

36

VSENSE3

38

VMON3

Figure 28. Synchronous Buck Converter Schematic

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9.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 3.

Table 3. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage

3.3 V

1.2 V

1.8 V

Output voltage (V_BUCK2/3

)

Maximum output current (I_{max_peak}

)

2 A

Output current ripple ΔI_{L_PP}

300 mA

2.45 MHz

Switching frequency (f_SWBUCK2/3

)

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter

A resistor divider from the output node to the VSENSE2 to ground respectively between the VSENSE3 to ground

pin sets the output voltage (see Figure 28). TI recommends using 1% tolerance or better divider resistors. Start

by selecting 1.6 kΩ for the value of the R_xresistor between the VSENSE2 to ground respectively between the

VSENSE3 to ground pin VSENSE3 pin and use Equation 8 to calculate the value for the R_yresistor between

BUCK2 and BUCK3 output and the VSENSE2 to ground respectively between the VSENSE3 to ground pin.

R_x´ (V_BUCK2/3- 0.8 V)

R_y=

0.8 V

(8)

Therefore, for V_BUCK2to equal to 1.2 V, the value of R_ymust be 0.8 kΩ. For V_BUCK3to equal to 1.8 V, the value of

R_ymust be 2 kΩ.

For voltage monitoring of the BUCK2 and BUCK3 output voltage, placing an additional resistive divider with exact

same values from the output node to the VMON2 and VMON3 pins is recommended for safety reasons (see

Figure 28). If no safety standard must be fulfilled in the application, the VMON2 and VMON3 pins can be directly

connected to VSENSE2 and VSENSE3 pins without the need for this additional resistive divider.

9.2.2.2.2 Output Inductor Selection for the BUCK2 and BUCK3 Converter

The inductor value L depends on the allowed ripple current ΔI_{L_PP}in the coil at chosen input voltage V_INand

output voltage V_OUT, and given switching frequency f_sw:

V

_OUT´(V_IN- V_OUT)

L =

DI_{L _PP}´ V ´ f_sw

IN

(9)

For example:

V_IN= 3.3 V (from BUCK1)

V_OUT= 1.2 V

ΔI_{L_PP}= 300 mA

f_sw= 2.45 MHz

→ L ≈ 1 μH

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9.2.2.2.3 Compensation of the BUCK2 and BUCK3 Converters

The regulators operate in forced continuous mode, and have internal frequency compensation. The frequency

response can be adjusted to the selected LC filter by setting the COMP2 and COMP3 pin low, high, or floating.

After selecting the output inductor value as previously described, the output capacitor must be chosen so that the

L × C_OUT× V_BUCK2/3product is equal to or less than one of the three values, as listed in Table 4.

Table 4. Compensation Settings

COMP 2/3

= 0 V

L × C_OUT× V_BUCK2/3

80 µF × µH × V

EXAMPLE COMPONENTS

30 µF × 2.2 µH × 1.2 V

50 µF × 1.8 µH × 1.8 V

150 µF × 2.2 µH × 1.2 V

= OPEN

= VREG

160 µF × µH × V

320 µF × µH × V

Larger output capacitors can be used if a feed-forward capacitor is placed across the upper resistance, R_y, of the

feedback divider. This works effectively for output voltages > 2 V. With an RC product greater than 10 µs, the

effective V_BUCK2/3at higher frequencies can be assumed as 0.8 V, thus allowing an output capacitor increase by

a factor equal to the ratio of the output voltage to 0.8 V.

9.2.2.2.4 Bootstrap Capacitor for the BUCK2/3 Converters

The BUCK2 and BUCK3 converters require a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF. The

bootstrap capacitor is located between the PH2 pin and the BOOT2 pin and between the PH3 pin and the

BOOT3 pin (see Figure 28). The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade

dielectric for temperature stability.

9.2.2.3 BUCK2 and BUCK3 Application Curves

100

90

80

70

60

50

40

30

20

10

0

1

100

90

80

70

60

50

40

30

20

10

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

EFF VSUP3 = 3.8 V

EFF VSUP3 = 3.3 V

EFF VSUP3 = 5 V

EFF VSUP2 = 3.8 V

EFF VSUP2 = 5 V

LOSS VSUP2 = 3.8 V

LOSS VSUP2 = 5 V

LOSS VSUP3 = 3.8 V

LOSS VSUP3 = 3.3 V

LOSS VSUP3 = 5 V

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Load Current (A)

Buck3 = 1.2 V at 25°C

EXTSUP Pin Open

L = 1.2 μH

C = 30 μF

Buck2 = 3.3 V at 25°C

COMP2 Pin to Ground

L = 1 μH

C = 20 μF

COMP3 Pin to Ground

EXTSUP Pin Open

Figure 30. Efficiency of Buck3, Measured Buck3 Output

Power With Respect to VSUP3 Input Power

Figure 29. Efficiency of Buck2, Measured Buck2 Output

Power With Respect to VSUP2 Input Power

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100

95

90

85

80

75

95

90

85

80

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

L = 1 μH

C = 20 μF

VSUP2 = 3.8 V

L = 1.2 μH

C = 30 μF

VSUP3 = 3.8 V

1-A LOAD

COMP2 Pin to Ground

0.5-A LOAD

EXTSUP Pin Open

COMP3 Pin to Ground

Figure 31. Buck2 = 3.3-V Efficiency at 0.5 A Versus

Temperature, Measured Buck2 Output Power With

Respect to VSUP2 Input Power

Figure 32. Buck3 = 1.2-V Efficiency at 1 A Versus

Temperature, Measured Buck3 Output Power With

Respect to VSUP3 Input Power

100

95

90

85

80

90

85

80

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

L = 1 μH

COMP2 Pin to Ground

C = 20 μF

VSUP2 = 3.8 V

L = 1.2 μH

EXTSUP Pin Open

C = 30 μF

VSUP3 = 3.8 V

EXTSUP Pin Open

COMP3 Pin to Ground

Figure 33. Buck2 = 3.3-V Peak Efficiency Versus

Temperature, Measured Buck2 Output Power With

Respect to VSUP2 Input Power

Figure 34. Buck3 = 1.2-V Peak Efficiency Versus

Temperature, Measured Buck3 Output Power With

Respect to VSUP3 Input Power

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9.2.3 BOOST Converter

V_BUCK1

3.3 V

TPS65311-Q1

5.6 nF

20

COMP5

2.2 kꢀ

23

22

PH5

PGND5

D2

24

21

VBOOST

V_BOOST

8.4 kꢀ

VSENSE5

5 V,

600 mA max

Figure 35. BOOST Converter Schematic

9.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 5.

Table 5. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

3.3 V

Input voltage

Output voltage (V_BOOST

)

5 V

Peak coil current (I_{peak_coil}

)

1 A

Maximum output current I_OUT

Output current ripple ΔI_{L_PP}

Switching frequency (f_SWBOOST

≈ 600 mA

300 mA

2.45 MHz

)

9.2.3.2 Detailed Design Procedure

9.2.3.2.1 Adjusting the Output Voltage for the Boost Converter

A resistor divider from the output node to the VSENSE5 pin sets the output voltage. TI recommends using 1%

tolerance or better divider resistors. Start with a value of 1.6 kΩ for the R_xresistor and use Equation 10 to

calculate R_y(see Figure 35).

R_x´ (V_BOOST- 0.8 V)

R_y=

0.8 V

(10)

Therefore, for the value of V_BOOSTto equal to 5 V, the value of R_ymust be 8.4 kΩ.

9.2.3.2.2 Output Inductor and Capacitor Selection for the BOOST Converter

The inductor value L depends on the allowed ripple current ΔI_{L_PP}in the coil at chosen input voltage V_INand

output voltage V_OUT, and given switching frequency f_sw:

V ´(V_OUT- V )

L =

IN

DI_{L _PP}´ V_OUT´ f_sw

(11)

For example:

V_IN= 3.3 V (from BUCK1)

V_OUT= 5 V

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ΔI_{L_PP}= 300 mA (30% of 1-A peak current)

ƒ_sw= 2.45 MHz

→ L ≈ 1.5 μH

The capacitor value C_OUTmust be selected such that the L-C double-pole frequency F_LCis in the range of

10 kHz–15 kHz. The F_LCis given by Equation 12:

V

IN

F

=

LC

2´ p´ V_OUT´ L ´ C_OUT

(12)

The right half-plane zero F_RHPZ, as given in Equation 13, must be > 200 kHz:

V²

IN

F_RHPZ

=

> 200 kHz

2 ´ p L ´ I_OUT´ V_OUT

where

•

I_OUTrepresents the load current

(13)

If the condition F_RHPZ> 200 kHz is not satisfied, L and therefore C_OUThave to be recalculated.

9.2.3.2.3 Compensation of the BOOST Converter

The BOOST converter requires an external R-C network for compensation (see Figure 15, COMP5). The

components can be calculated using Equation 14 and Equation 15:

æ

ç

è

ö²

F

BW

R = 120´ V ´

÷

IN

F

^LCø

(14)

1

C =

2´ p´R´F

LC

where

•

F_BWrepresents the bandwidth of the regulation loop, and must be set to 30 kHz

F_LCrepresents the L-C double-pole frequency, as mentioned previously

•

(15)

For example:

V_IN= 3.3 V (from BUCK1)

V_OUT= 5 V

L = 1.5 μH

C = 39 μF

→ F_LC= 13.7 kHz

F_BW= 30 kHz

→ R ≈ 2.2 kΩ

→ C ≈ 5.6 nF

Stability and load step response must be verified in measurements to fine tune the values of the compensation

components.

9.2.3.2.4 Output Diode for the BOOST Converter

The BOOST converter requires an external output diode between the PH5 pin and VBOOST pin (see Figure 35,

component D2). The selected diode must have a reverse voltage rating equal to or greater than the V_BOOST

output voltage. The peak current rating of the diode must be greater than the maximum inductor current. The

diode must also have a low forward voltage in order to reduce the power losses. Therefore, Schottky diodes are

typically a good choice for the catch diode.

Also, select a diode with an appropriate power rating, because the diode conducts the output current during the

off-time of the internal power switch.

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9.2.3.3 BOOST Converter Application Curves

100

95

100

90

80

70

60

50

40

30

20

10

0

250

200

150

100

50

Efficiency

90

Power Loss

85

0

80

0.001

0.01

0.1

1

-50

0

50

100

150

Load Current (A)

Temperature (°C)

BOOST Supply Input = 3.8 V

EXTSUP Pin Open

BOOST Supply Input = 3.8 V

EXTSUP Pin Open

Figure 36. Efficiency BOOST = 5 V at 25°C, Measured

BOOST Output Power with respect to Supply Input Power

Figure 37. BOOST = 5-V Peak Efficiency Versus

Temperature, Measured BOOST Output Power with

respect to Supply Input Power

9.2.4 Linear Regulator

TPS65311-Q1

1 µF

V_{LDO_OUT}

1.74 kW

2.5 ë, max 350 m!

Figure 38. Linear Regulator Schematic

9.2.4.1 Design Requirements

For this design example, use the parameters listed in Table 6.

Table 6. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

3.3 V

Input voltage

Output voltage (V_{LDO_OUT}

)

2.5 V

Maximum output current (I_OUT

)

350 mA

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9.2.4.2 Detailed Design Procedure

9.2.4.2.1 Adjusting the Output Voltage for the Linear Regulator

A resistor divider from the output node to the VSENSE4 pin sets the output voltage. TI recommends using 1%

tolerance or better divider resistors. In order to get the minimum required load current of 1 mA for the linear

regulator, start with a value of 820 Ω for the R_xresistor and use Equation 16 to calculate R_y(see Figure 38).

R_x´ (V_{LDO _ OUT}- 0.8 V)

R_y=

0.8 V

(16)

Therefore, for the value of V_{LDO_OUT}to equal to 2.5 V, the value of R_ymust be 1.74 kΩ.

9.2.4.2.2 Output Capacitance for the Linear Regulator

The linear regulator requires and external output capacitance with a value between 6 µF and 50 µF.

9.2.4.3 Linear Regulator Application Curve

10

9

Noise [LDO ON]

8

Noise [LDO OFF]

(Noisefloor)

7

6

5

4

3

2

1

0

10

100

1000

10000

Frequency (Hz)

Figure 39. LDO Noise Density

10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 4 V and 40 V (see Figure 40 for

reference). This input supply must be well regulated. In case the supply voltage in the application is likely to

exceed 40 V, the external PMOS protection device as explained in External Protection must be applied between

VIN and VINPROT pins. Furthermore, if the supply voltage in the application is likely to reach negative voltage

(for example, reverse battery), a forward diode must be placed between the VSSENSE and VIN pins. A ceramic

bypass capacitor with a value of 100 μF (typical) is recommended to be placed close to the VINPROT pin. For

the VIN pin, a small ceramic capacitor of typical 1 µF is recommended. Also place 1-µF (typical) bypass

capacitors to the DVDD and VREF pins, and 100-nF (typical) bypass capacitors to VIO pin. Furthermore, the

VREG pin requires a bypass capacitor of 2.2 µF (typical).

The BUCK1 output voltage is the recommended input supply for the BUCK2, BUCK3, and BOOST regulators.

Place local, 10-µF (typical) bypass capacitors at the VSUP2 and VSUP3 pins and at the supply input of the

BOOST in front of the BOOST-inductor. Also place a local, 1-µF (typical) bypass capacitor at the VSUP4 pin.

The EXTSUP pin can be used to improve efficiency. For the EXTSUP pin to improve efficiency, a voltage of

more than 4.8 V is required in order to have VREG regulator supplied from EXTSUP pin. If the EXSUP pin is not

used, the VINPROT pin supplies the VREG regulator. The EXTSUP pin requires a 100-nF (typical) bypass

capacitor.

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Product Folder Links: TPS65311-Q1

TPS65311-Q1

SLVSCA6C –OCTOBER 2013–REVISED OCTOBER 2017

www.ti.com

D1

VBAT

4 V to 40 V (typ. 12 V)

Q1

VINPROT

28

48

IRQ

VIO

V_BUCK1

10

BOOT1

Q2

Q3

11

12

13

14

GU

PH1

27

26

43

RESN

PRESN

WD

GL

10 kꢀ

WAKE

PGND1

1.2 nF

C1

44

46

47

45

24 kꢀ

18

CSN

SCK

COMP1

R3

SDO

SDI

C2 33 pF

15

16

S1

S2

53

V_BUCK1

VREF

3.3 V, 2.3 A maximum

19

17

VSENSE1

VMON1

25

54

VT_REF

VT

V_BUCK1

30

TPS65311-Q1

VSUP2

VINPROT

29

31

BOOT2

PH2

1 µH

V_Buck2

6

HSSENSE

HSCTRL

HSPWM

1.2 V, 2 A maximum

5

34

32

35

33

COMP2

PGND2

49

VSENSE2

VMON2

V_BUCK1

5.6 nF

V_BUCK1

20

COMP5

41

VSUP3

2.2 kꢀ

23

22

42

40

PH5

BOOT3

PH3

1.2 µH

V_Buck3

PGND5

D2

1.8 V, 2 A maximum

24

21

37

39

36

38

VBOOST

COMP3

PGND3

V_BOOST

5 V,

600 mA max

8.4 kꢀ

VSENSE5

VSENSE3

VMON3

1 µF

V_{LDO_OUT}

2.5 V, maximum 350 mA

1.74 kꢀ

Figure 40. Typical Application Schematic

52

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TPS65311-Q1

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SLVSCA6C –OCTOBER 2013–REVISED OCTOBER 2017

11 Layout

11.1 Layout Guidelines

11.1.1 Buck Controller

•

Connect a local decoupling capacitor between the drain of Q3 and the source of Q2. The length of this trace

loop should be short.

The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel

with each other. Place any filtering capacitor for noise near the S1-S2 pins.

The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor

and the GND pin (IC signal ground). Do not locate these components and their traces near any switching

nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as

possible to the sensing resistor divider, and should be connected to same traces.

•

Connect the boot-strap capacitance between the PH1 and BOOT1 pins, and keep the length of these trace

loops as short as possible.

•

Connect the compensation network between the COMP1 pin and GND pin (IC signal ground).

Connect a local decoupling capacitor between the VREG and PGDN1 pin, and between the EXTSUP and

PGND1 pin. The length of this trace loop should be short.

11.1.2 Buck Converter

•

Connect a local decoupling capacitor between VSUP2 and PGND2 respectively VSUP3 and PGND3 pins.

The length of this trace loop should be short.

•

The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor

and the GND pin (IC signal ground). Do not locate these components and their traces near any switching

nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as

possible to the sensing resistor divider, and should be connected to same traces.

•

Connect the boot-strap capacitance between the PH2 and BOOT2 respectively PH3 and BOOT3 pins, and

keep the length of this trace loop as short as possible.

If COMP2 and/or COMP3 are chosen to be connected to ground, use the signal ground trace connected to

GND pin for this.

11.1.3 Boost Converter

•

The path formed from the input capacitor to the inductor and the PH5 pin should have short trace length. The

same applies for the trace from the inductor to Schottky diode D2 to the output capacitor and the VBOOST

pin. Connect the negative pin of the input capacitor and the PGND5 pin together with short trace lengths.

The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor

and the GND pin (IC signal ground). Do not locate these components and their traces near any switching

nodes or high-current traces.

Connect the compensation network between the COMP5 pin and GND pin (IC signal ground).

11.1.4 Linear Regulator

•

Connect a local decoupling capacitor between VSUP4 and GND (IC signal ground) pins. The length of this

trace loop should be short.

•

The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor

and the GND pin (IC signal ground). Do not locate these components and their traces near any switching

nodes or high-current traces.

11.1.5 Other Considerations

•

Short PGNDx and GND to the thermal pad.

Use a star ground configuration if connecting to a non-ground plane system. Use tie-ins for the

compensation-network ground, voltage-sense feedback ground, and local biasing bypass capacitor ground

networks to this star ground.

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www.ti.com

11.2 Layout Example

Analog Signal Ground trace

Sense resistors LDO

VSSENSE

VIN

BOOT3

VSUP3

PH3

D1

BUCK3 output voltage

Q1

GPFET

VINPROT

HSCTRL

HSSENSE

WAKE

EXTSUP

VREG

Sense and

Monitoring

resistors

BUCK3

PGND3

VMON3

COMP3

VSENSE3

VSENSE2

COMP2

VMON2

PGND2

PH2

Compensation connection BUCK2

(either to Analog Signal Ground, to VREG or leave open)

Exposed Thermal

Pad area

Compensation connection BUCK2

(either to Analog Signal Ground, to VREG or leave open)

BOOT1

GU

Sense and

Monitoring

resistors

BUCK2

Q2

Q3

PH1

BUCK2 output voltage

GL

VSUP2

BOOT2

PGND1

Power

ground

plane

VT_REF

BOOST output

voltage

Sense and

Monitoring

resistors

BUCK1

Sense resistors

BOOST

Analog Signal Ground trace

Figure 41. TPS65311-Q1 Layout Example

54

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SLVSCA6C –OCTOBER 2013–REVISED OCTOBER 2017

12 Device and Documentation Support

12.1 Documentation Support

For related documentation see the following:

•

Texas Instruments, TPS65310A-Q1 Efficiency application report

Texas Instruments, TPS65310AEVM and TPS65311EVM Evaluation Module user's guide

Texas Instruments, TPS65311-Q1 BUCK1 Controller DCR Current Sensing application report

Texas Instruments, TPS65311-Q1/TPS65310A-Q1 GPFET Soft Start Using a Capacitor Between GPFET Pin

and PMOS-Protection Switch Source Pin application report

•

Texas Instruments, TPS65311-Q1/TPS65310A-Q1 Monitoring and Diagnostic Mechanism Definitions

application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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55

Product Folder Links: TPS65311-Q1

PACKAGE OUTLINE

VQFN - 1 mm max height

RVJ0056A

PLASTIC QUAD FLATPACK- NO LEAD

8.1

7.9

A

B

0.1 MIN

8.1

7.9

(0.13)

SECTION A-A

PIN 1 INDEX AREA

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

5.2±0.1

(0.2) TYP

15

28

52X 0.5

(0.16)

14

29

SYMM

A

57

4X

6.5

5.2±0.1

1

42

0.30

56X

0.20

PIN 1 ID

(OPTIONAL)

43

56

0.1

C A B

C

0.55

0.35

56X

SYMM

0.05

4225251/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RVJ0056A

PLASTIC QUAD FLATPACK- NO LEAD

(7.75)

(5.2)

SYMM

56X (0.65)

56

43

1

42

56X (0.25)

52X (0.5)

SYMM

(7.75)

57

(5.2)

8X (1.27)

6X (1.08)

(Ø0.2) VIA

TYP

14

29

(R0.05)

TYP

15

28

8X (1.27)

6X (1.08)

LAND PATTERN EXAMPLE

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225251/A 09/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RVJ0056A

PLASTIC QUAD FLATPACK- NO LEAD

(7.75)

SYMM

56X (0.65)

56

43

1

42

57

16X

SQ (1.07)

56X (0.25)

52X (0.5)

SYMM

(7.75)

8X (0.635)

6X (1.27)

METAL TYP

14

29

(R0.05)

TYP

15

28

8X (0.635)

6X (1.27)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

67% PRINTED COVERAGE BY AREA

SCALE: 10X

4225251/A 09/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65311-Q1
厂家：	TEXAS INSTRUMENTS
描述：	适用于汽车安全应用的汽车类 4V 至 40V、5 稳压输出电源管理 IC
文件：	总62页 (文件大小：1078K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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