TPS65253RHDR [TI]
4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN DUAL BUCK; 4.5 V至16 V输入，大电流，同步降压双降压
| 型号： | TPS65253RHDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN DUAL BUCK |
| 文件： | 总24页 (文件大小：1636K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65253
www.ti.com
SLVSAW8 –JUNE 2011
4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN DUAL BUCK
CONVERTER WITH INTEGRATED FETS
Check for Samples: TPS65253
•
Current-Mode Control With Simple
Compensation Circuit
Power Good and Reset Generator
Low Power Mode Set By External Signal
Supervisory Circuit
1
FEATURES
•
Wide Input Supply Voltage Range:
4.5 V - 16 V
Output Range: 0.8 V to ~VIN-1 V
Fully Integrated Dual Buck, 3.5-A/2.5-A
Continuous Current (4-A/3-A Maximum
Current)
•
•
•
•
•
•
QFN Package, 28-Pin 5 mm x 5 mm RHD
APPLICATIONS
•
•
High Efficiency
300-kHz - 1.2-MHz Switching Frequency Set by
External Resistor
External Eenable/Sequencing Pins
Adjustable Cycle-by-Cycle Current Limit Set
by External Resistor
•
•
•
•
•
•
•
DTV
DSL Modems
Cable Modems
Set Top Boxes
Car DVD Players
Home Gateway and Access Point Networks
Wireless Routers
•
•
•
Soft-Start Pins
DESCRIPTION/ORDERING INFORMATION
The TPS65253 features two synchronous wide input range high efficiency buck converters. The converters are
designed to simplify product application while giving designers the options to optimize their usage according to
the target application.
The converters can operate in 5-, 9- and 12-V systems and have integrated power transistors. The output voltage
can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each
converter features an enable pin that allows a delayed start-up for sequencing purposes, soft-start pin that allows
adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables
designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The CMP pin
allows optimizing transient versus dc accuracy response with a simple RC compensation.
The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching
regulators are designed to operate from 300 kHz to 1.2 MHz. The converters operate with 180° phase between
then to minimize the input filter requirements.
TPS65253 also features a low power mode enabled by an external signal, which allows for a reduction on the
input power supplied to the system when the host processor is in stand-by (low activity) mode.
TPS65253 features a supervisor circuit that monitors both converters and provides a PGOOD signal (End of
Reset) with a 32-ms timer.
TPS65253 is packaged in a small, thermally efficient 28-pin QFN package.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
PART NUMBER
TOP-SIDE MARKING
-40°C to 85°C
28-Pin (QFN) - RHD
TPS65253RHD
TPS65253
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65253
SLVSAW8 –JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
PGOOD
PGOOD
Vpullup
CV7V
GENERATOR
V7V
V3V
REFERENCE
ROSC
ROSC
BST1
OSC
CV3V
VIN1
VIN
RLIM1
RLIM1
CIN1
CBST1
LX1
LX1
FB1
L1
Vout Buck1
Light Load
Power Saving
LOW_P
RFB1U
BUCK1
LOW_P
COUT1
CSS1
SS1
EN1
RFB1L
CC1
RC1
CMP1
EN1
CRoll1
VIN2
BST2
RLIM2
RLIM2
CIN2
CBST2
LX2
LX2
FB2
L2
Vout Buck2
BUCK2
RFB2U
COUT2
CSS2
SS2
EN2
RFB2L
CC2
RC2
CMP2
GND
EN2
CRoll2
2
Copyright © 2011, Texas Instruments Incorporated
TPS65253
www.ti.com
SLVSAW8 –JUNE 2011
TYPICAL APPLICATION
R9
10kΩ
C14
4.7nF
Low Power Mode from HOST
C15
10uF
C13
4.7nF
C12
4.7nF
R8
69.8k
R6
12.7k
C16
4.7uF
C11
47nF
C10
10uF
V3V
BST2
C9
44uF
R10
100kΩ
GND
VIN2
LX2
LX2
LX1
LX1
VIN1
VIN2
R7
40.2k
C8
22nF
PGOOD
GND
3.3V
1.2V
TPS65253
GND
GND
R5
40.2k
C6
22nF
GND
C7
44uF
VIN1
C5
10nF
C4
47nF
R4
80.6k
R1
383k
C2
4.7nF
R3
59k
C3
4.7nF
R2
5k
C1
2.2nF
Copyright © 2011, Texas Instruments Incorporated
3
TPS65253
SLVSAW8 –JUNE 2011
www.ti.com
PIN OUT
RHD PACKAGE
(TOP VIEW)
21 20 19 18 17 16 15
14
13
V3V
BST2
VIN2
22
23
24
25
26
27
28
GND
PGOOD
GND
12 LX2
11 LX2
10 LX1
9 LX1
8 VIN1
PowerPAD
GND
GND
GND
1
2
3
4
5
6
7
4
Copyright © 2011, Texas Instruments Incorporated
TPS65253
www.ti.com
SLVSAW8 –JUNE 2011
TERMINAL FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
Oscillator set. This resistor sets the frequency of internal autonomous
clock.
ROSC
FB1
1
I
I
Feedback pin for Buck 1. Connect a divider set to 0.8 V from the output of
the converter to ground.
2
3
4
5
Compensation pin for Buck 1. Fit a series RC circuit to this pin to
complete the compensation circuit of this converter.
CMP1
SS1
O
I
Soft-start pin for Buck 1. Fit a small ceramic capacitor to this pin to set
the converter soft-start time.
Current limit setting pin for Buck 1. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
RLIM1
I
Enable pin for Buck 1. A high signal on this pin enables the regulator
Buck. For a delayed start-up add a small ceramic capacitor from this pin
to ground.
EN1
6
7
I
I
Bootstrap capacitor for Buck 1. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
BST1
VIN1
LX1
8
I
Input supply for Buck 1. Fit a 10-µF ceramic capacitor close to this pin.
Switching node for Buck 1
9, 10
11, 12
13
O
O
I
LX2
Switching node for Buck 2
VIN2
Input supply for Buck 2. Fit a 10-µF ceramic capacitor close to this pin.
Bootstrap capacitor for Buck 1. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
BST2
14
I
Enable pin for Buck 2. A high signal on this pin enables the regulator
Buck. For a delayed start-up add a small ceramic capacitor from this pin
to ground.
EN2
15
I
Current limit setting pin for Buck 2. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
RLIM2
SS2
16
17
18
I
I
Soft-start pin for Buck 2. Fit a small ceramic capacitor to this pin to set
the converter soft-start time.
Compensation pin for Buck 2. Fit a series RC circuit to this pin to
complete the compensation circuit of this converter.
CMP2
O
Feedback pin for Buck 2. Connect a divider set to 0.8 V from the output of
the converter to ground.
FB2
19
20
21
I
I
LOW_P
V7V
Low power operation mode (active high) input for TPS65253
Internal supply. Connect a 4.7-µF to 10-µF ceramic capacitor from this pin
to ground.
O
Internal supply. Connect a 3.3-µF to 10-µF ceramic capacitor from this pin
to ground.
V3V
22
O
O
GND
23, 25, 26, 27, 28
24
Ground
PGOOD
Open drain power good output
PowerPAD. Connect to system ground for electrical and thermal
connection.
PowerPAD
Copyright © 2011, Texas Instruments Incorporated
5
TPS65253
SLVSAW8 –JUNE 2011
www.ti.com
(1)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Voltage range at VIN1,VIN2, LX1, LX2
–0.3 to 18
–3 to 18
V
V
Voltage range at LX1, LX2 (maximum withstand voltage transient < 20 ns)(2)
Voltage at BST1, BST2, referenced to LX pin
–0.3 to 7
V
Voltage at V7V, CMP1, CMP2
–0.3 to 7
V
Voltage at V3V, RLIM1, RLIM2, EN1, EN2, SS1, SS2, FB1, FB2, PGOOD, ROSC, LOW_P
Voltage at GND
–0.3 to 3.6
–0.3 to 0.3
–40 to 125
–55 to 150
V
V
TJ
Operating virtual junction temperature range
Storage temperature range
°C
°C
TSTG
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) Excessive parasitic inductance may cause deeper negative voltage for less than 20 ns. To minimize this undershoot tight board layout is
recommended.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
16
UNIT
V
VIN
TA
Input operating voltage
Junction temperature
–40
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
2000
500
MAX
UNIT
V
Human body model (HBM)
Charge device model (CDM)
V
PACKAGE DISSIPATION RATINGS(1)
TA = 25°C
POWER RATING (W)
TA = 55°C
POWER RATING (W)
PACKAGE
θJA (°C/W)
RHD
34 (Simulated)
2.9
2
(1) Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x 0.6-mm board with the following layer arrangement:
(a) Top layer: 2 Oz Cu, 6.7% coverage
(b) Layer 2: 1 Oz Cu, 90% coverage
(c) Layer 3: 1 Oz Cu, 90% coverage
(d) Bottom layer: 2 Oz Cu, 20% coverage
6
Copyright © 2011, Texas Instruments Incorporated
TPS65253
www.ti.com
SLVSAW8 –JUNE 2011
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, VIN = 12 V, LO = 2.2 µH, fSW = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN
Input voltage range
Shutdown
4.5
16
V
IDDSDN
EN pin = low for all converters
0.4
40
mA
Converters enabled, no load
Buck 1 = 1.2 V
IDDQ
Quiescent, low power disabled
mA
Buck 2 = 3.3 V
Converters enabled, no load
Buck 1 = 1.2 V
Buck 2 = 3.3 V
IDDQ_LOW_P
Quiescent, low power enabled
VIN under voltage lockout
0.6
mA
V
Rising VIN
Falling VIN
Both edges
4.22
4.1
UVLOVIN
UVLODEGLITCH
110
3.3
µs
Internal supply output voltage
V
V3V
V7V
External load for
3.15 V < V3V < 3.4 V
10
25
mA
V
Internal supply output voltage
6.25
External load for
5.8 V < V3V < 6.56 V
VIN = 12 V
mA
Rising V7V
Falling V7V
Falling edge
3.8
3.6
V7VUVLO
UVLO for internal V7V rail
V
V7VUVLO_DEGLITCH
110
µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT-START, SWITCHING FREQUENCY AND LOW POWER MODE)
V3p3 = 3.2 V - 3.4 V,
VENx rising
0.66 x
V3p3
VIH_ENx
VIL_ENx
Enable threshold high
Enable treshold Low
V
V
V3p3 = 3.2 V - 3.4 V,
VENx falling
0.33 x
V3p3
ICHEN
tD
Pull up current enable pin
Discharge time enable pins
Soft-start pin current source
1.1
10
5
µA
ms
µA
Power-up
ISS
FSW_BK
RFSW
fSW_TOL
Converter switching frequency range Set externally with resistor
Frequency setting resistor
0.3
140
-10
1.2
600
10
MHz
kΩ
Internal oscillator accuracy
fSW = 800 kHz
%
0.66 x
V3p3
VIHLOW_P
VILLOW_P
Low power mode threshold high
V3p3 = 3.3 V
V
V
0.33 x
V3p3
Low power mode treshold Low
V3p3 = 3.3 V
FEEDBACK, REGULATION, OUTPUT STAGE
VIN = 12 V , TA = 25°C
-1%
-2%
0.8
0.8
1%
2%
VFB
Feedback voltage
V
VIN = 4.5 V to 16 V
Minimum on time (current sense
blanking)
tON_MIN
100
135
ns
VIN = 12 V, VOUT = 3.3 V,
TJ = 25°C, LO = 2.2 µH,
RLIM1 = 59 kΩ, RLIM2 = 69.8 kΩ
ILIMIT1
Peak inductor current limit range
Peak inductor current limit range
-10%
-15%
5
10%
A
A
VIN = 12 V, VOUT = 3.3 V,
TJ = 25°C, LO = 2.2 µH,
ILIMIT2
4.25
15%
RLIM1 = 59 kΩ, RLIM2 = 69.8 kΩ
MOSFET (BUCK 1)
On resistance of high side FET on
CH1
H.S. Switch
25°C, BOOT = 6.5 V
25°C, VIN = 12 V
90
45
mΩ
mΩ
On resistance of low side FET on
CH1
L.S. Switch
Copyright © 2011, Texas Instruments Incorporated
7
TPS65253
SLVSAW8 –JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 85°C, VIN = 12 V, LO = 2.2 µH, fSW = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET (BUCK 2)
On resistance of high side FET on
CH2
H.S. Switch
25°C, BOOT = 6.5 V
115
mΩ
mΩ
On resistance of low side FET on
CH2
L.S. Switch
25°C, VIN = 12 V
75
ERROR AMPLIFIER
Error amplifier
transconductance
-2 µA < ICOMP < 2 µA
130
12
µ℧
CMP to ILX gm
ILX = 0.5 A
A/V
POWER GOOD RESET GENERATOR
Output falling
85
90
Threshold voltage for buck under
voltage
VUVBUCKX
%
Output rising (PG will be
asserted)
tUV_deglitch
tON_HICCUP
Deglitch time (both edges)
Hiccup mode ON time
11
12
ms
ms
VUVBUCKX asserted
All converters disabled. Once
tOFF_HICCUP elapses, all
converters will go through
sequencing again.
tOFF_HICCUP
Hiccup mode OFF time
20
ms
Output rising (high side FET will
be forced off)
109
107
Threshold voltage for buck over
voltage
VOVBUCKX
%
Output falling (high side FET will
be allowed to switch )
Measured after the later of
Buck 1 or Buck 2 power-up
successfully
tRP
minimum reset period
32
ms
THERMAL SHUTDOWN
TTRIP
Thermal shut down trip point
Rising temperature
Device re-starts
160
20
°C
°C
µs
THYST
Thermal shut down hysteresis
Thermal shut down deglitch
TTRIP_DEGLITCH
100
120
8
Copyright © 2011, Texas Instruments Incorporated
TPS65253
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SLVSAW8 –JUNE 2011
TYPICAL CHARACTERISTICS
VIN = 12 V, fSW = 500 kHz, LO = 2.2 µH, DCR = 15 mΩ, CO = 44 µF (unless otherwise specified)
Buck 1 Efficiency
Buck 2 Efficiency
vs
vs
VOUT
VOUT
100
100
90
80
70
60
50
40
5V
5V
90
80
70
60
50
40
3.3V
3.3V
1.8V
1.8V
1.2V
1.2V
0
1000
2000
3000
4000
0
1000
2000
3000
Output Current (mA)
Output Current (mA)
Figure 1.
Figure 2.
Buck 1 (1.8 V) Efficiency
. Buck 2 (3.3 V) Efficiency
vs
vs
VIN
VIN
100
100
90
80
70
60
50
40
5V
90
80
70
60
50
40
5V
12V
12V
0
1000
2000
3000
4000
0
1000
Output Current (mA)
2000
3000
Output Current (mA)
Figure 3.
Figure 4.
Buck 1 Load Regulation
Buck 2 Load Regulation
vs
vs
VOUT
VOUT
0.35%
0.30%
0.25%
0.20%
0.15%
0.10%
0.05%
0.00%
-0.05%
-0.10%
-0.15%
0.50%
0.40%
0.30%
0.20%
0.10%
0.00%
-0.10%
-0.20%
1.2V
1.2V
3.3V
5V
3.3V
5V
0
1000
2000
3000
4000
0
1000
Output Current (mA)
2000
3000
Output Current (mA)
Figure 5.
Figure 6.
Copyright © 2011, Texas Instruments Incorporated
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TPS65253
SLVSAW8 –JUNE 2011
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, fSW = 500 kHz, LO = 2.2 µH, DCR = 15 mΩ, CO = 44 µF (unless otherwise specified)
Buck 1 Output Ripple
Buck 2 Output Ripple
vs
vs
VOUT
VOUT
0.04
0.03
0.02
0.01
0.04
0.03
0.02
0.01
5V
5V
3.3V
3.3V
1.2V
1.2V
0
1
2
3
4
4
4
0
1
2
3
Output Current (A)
Output Current (A)
Figure 7.
Figure 8.
Output Voltage (1.2 V)
Output Voltage (1.8 V)
vs
TA
vs
TA
1.225
1.82
Buck1,85°C
1.8
Buck1,85°C
Buck1,25°C
Buck1,25°C
Buck1,-40°C
Buck2,85°C
Buck2,25°C
1.2
Buck2,85°C
Buck2,25°C
Buck1,-40°C
1.78
Buck2,-40°C
Buck2,-40°C
1.175
1.76
0
1
2
3
0
1
2
3
4
Output Current (A)
Output Current (A)
Figure 9.
Figure 10.
Output Voltage (3.3 V)
Output Voltage (5 V)
vs
TA
vs
TA
3.4
3.35
3.3
5.1
5.05
5
Buck2,85°C
Buck2,25°C
Buck1,85°C
Buck1,25°C
Buck1,85°C
Buck1,25°C
Buck2,85°C
Buck2,25°C
Buck2,-40°C
Buck2,-40°C
Buck1,-40°C
4.95
4.9
Buck1,-40°C
0
1
2
3
0
1
2
3
4
Output Current (A)
Output Current (A)
Figure 11.
Figure 12.
10
Copyright © 2011, Texas Instruments Incorporated
TPS65253
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SLVSAW8 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, fSW = 500 kHz, LO = 2.2 µH, DCR = 15 mΩ, CO = 44 µF (unless otherwise specified)
Details on Soft-Start, 1 ms/div
Buck 1 (1.2 V) Ripple at Output Load of 4 A, 20 mV/div
Figure 13.
Figure 14.
Buck 1 Transient Load Response (1-A to 3-A Step),
30 mV/div
Buck 2 (3.3 V) Ripple at Output Load of 3 A, 20 mV/div
Figure 15.
Figure 16.
Buck 2 Transient Load Response (0.75-A to 2.25-A Step),
30 mV/div
Ripple With LOW_P = 1, Each Buck is Loaded With 10 mA,
100 mV/div
Figure 17.
Figure 18.
Copyright © 2011, Texas Instruments Incorporated
11
TPS65253
SLVSAW8 –JUNE 2011
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OVERVIEW
TPS65253 is a power management IC with two step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65253 can support
4.5-V to 16-V input supply, high load current, 300-kHz to 1.2-MHz clocking. The buck converters have an
optional PFM mode, which can improve power dissipation at light loads. Alternatively, the device implements a
constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency of 300 kHz to
1.2 MHz allows for efficiency and size optimization. The switching frequency is adjustable by selecting a resistor
to ground on the ROSC pin. Input ripple is reduced by 180° out-of-phase operation between Buck 1 and Buck 2.
Both buck converters have peak current mode control which simplifies external frequency compensation. A
traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover,
an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and
makes the crossover frequency over 100 kHz.
Each buck converter has an individual current limit, which can be set up by a resistor to ground from the RLIMx
pin. The adjustable current limiting enables high efficiency design with smaller and less expensive inductors.
The device has two built-in LDO regulators. During a standby mode, the 3.3-V LDO and the 6.5-V LDO can be
used to drive MCU and other active loads. By this, the system is able to turn of the two buck converters and
improve the standby efficiency.
The device has a power good comparator monitoring the output voltage. Each converter has its own soft-start
and enable pin, which provide independent control and programmable soft-start.
DETAILED DESCRIPTION
Adjustable Switching Frequency
To select the internal switching frequency, connect a resistor from ROSC to ground. Figure 19 shows the
required resistance for a given switching frequency.
620
520
420
320
220
120
300
400
500
600
700
800
900
1000
1100
1200
fSW (kHz)
Figure 19. ROSC vs Switching Frequency
-1.122
ROSC(kW) = 174 · fSW
(1)
12
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TPS65253
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SLVSAW8 –JUNE 2011
Out-of-Phase Operation
In order to reduce input ripple current, Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system
having less input ripple, then to lower component cost, save board space and reduce EMI.
Startup and Sequencing
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~1.7 ms per nF connected to the pin. Note that the EN pins have a weak 1-MΩ pull-up to the 3V3 rail.
Figure 20 describes startup sequencing and PGOOD generation.
VIN
V7V
V3V
Internal
EN
EN threshold
EN1
EN2
ENx rise time
Dictated by C EN
EN discharge time
10-12 ms
PGOOD asserted
BUCK1
BUCK2
Pre-bias time
4-5 ms
Pre-biased output
Soft-start time
dictated by C ss
Soft-start timer
10ms
PG timer
32ms
PGOOD
Figure 20. Startup Sequence of Dual Bucks
Soft-Start Time
The device has an internal pull-up current source of 5 µA that charges an external soft-start capacitor to
implement a slow start time. Equation 2 shows how to select a soft-start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the soft-start charge current (Iss) is 5 µA. The soft-start
circuit requires 1 nF per around 160 µs to be connected at the SS pin. A 0.8-ms soft-start time is implemented for
all converters fitting 4.7 nF to the relevant SS pin.
Css(nF)
Iss(µA)
Tss(ms) = VREF(V) ·
(
)
(2)
The Power Good circuit for the bucks has a 10-ms watchdog. Therefore the soft-start time should be lower than
this value. It is recommended not to exceed 5 ms.
Copyright © 2011, Texas Instruments Incorporated
13
TPS65253
SLVSAW8 –JUNE 2011
www.ti.com
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with a value close to 40 kΩ
for the R1 resistor and use Equation 3 to calculate R2.
æ
ç
è
ö
÷
ø
0.8V
R2 = R1×
VO - 0.8V
(3)
Vo
FB
TPS65253
R1
R2
-
+
0.8V
Figure 21. Voltage Divider Circuit
14
Copyright © 2011, Texas Instruments Incorporated
TPS65253
www.ti.com
SLVSAW8 –JUNE 2011
Loop Compensation
TPS65253 is a current mode control DC/DC converter. The error amplifier is a transconductance of 130 µA/V. A
typical compensation circuit could be type II (Rc and Cc) to have a phase margin above 45°, or type III (Rc and Cc
and Cff to improve the converter transient response. Optional CRoll adds a high frequency pole to attenuate
high-frequency noise when needed. It may also prevent noise coupling from other rails if there is possibility of
cross coupling in between rails when layout is very compact.
V
o
iL
RL
Co
Gps=12A/V
RESR
R
Cff
1
Current Sense
I/V Gain
FBx
gM = 130u
Vref = 0.8V
R
2
CMPx
Rc
CRoll
C
c
Figure 22. Loop Compensation Scheme
To calculate the external compensation components follow the following steps:
TYPE II CIRCUIT
TYPE III CIRCUIT
Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies around 500 kHz
yield best trade off between performance and cost. When
using smaller L and C, switching frequency can be
increased. To optimize efficiency, switching frequency can
be lowered.
Use type III circuit for switching
frequencies higher than 500 kHz.
Select cross over frequency (fc) to be at least 1/5 to 1/10 of
switching frequency (fs).
Suggested
fc = fs/10
Suggested
fc = fs/10
2p × fc×Vo×Co
gM ×Vref × gmps
2p × fc×Vo×Co
RC =
gM ×Vref × gmps
RC =
Set and calculate Rc.
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
RL ×Co
RL ×Co
Cc =
Cc =
1
fp =
Rc
Rc
CO × RL ×2p
Add CRoll if needed to remove large signal coupling to high
impedance CMP node. Make sure that
Re sr ×Co
Re sr ×Co
1
CRoll
=
CRoll
=
fpRoll
=
RC
RC
2×p × RC ×CRoll
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
that the zero frequency (fzff) is smaller than equivalent
soft-start frequency (1/Tss).
1
Cff =
NA
2×p × fzff × R
1
Copyright © 2011, Texas Instruments Incorporated
15
TPS65253
SLVSAW8 –JUNE 2011
www.ti.com
Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control.
Input Capacitor
Use at least 10-µF X7R/X5R ceramic capacitors at the input of the converter inputs. These capacitors should be
connected as close as physically possible to the input pins of the converters.
Bootstrap Capacitor
The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pins to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.047 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage.
Power Good
The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled up when both buck converters’ outputs are more than
90% of its nominal output voltage.
The default reset time is 32 ms. The polarity of the PGOOD is active high.
Current Limit Protection
The TPS65253 current limit trip is set by the following formula for Buck 1:
252
ILIM1(A) =
+ 0.6
RLIM1(kW)
(4)
(5)
and for Buck 2:
236
RLIM2(kW)
ILIM2(A) =
+ 0.56
All converters operate in hiccup mode: Once an over-current lasting more than 12 ms is sensed in any of the
converters, they will shut down for 20 ms and then the start-up sequencing will be tried again. If the overload has
been removed, the converter will ramp up and operate normally. If this is not the case the converter will see
another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.
If an overload condition lasts for less than 12 ms, only the relevant converter affected will shut-down and re-start
and no global hiccup mode will occur.
Overvoltage Transient Protection
The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The
OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the FB voltage drops lower than the OVTP threshold which is 107%, the high side MOSFET is
allowed to turn on the next clock cycle.
Low Power Mode Operation
By pulling high the Low_P pin all converters will operate in pulse-skipping mode, greatly reducing the overall
power consumption at light and no load conditions. Although each buck converter has a skip comparator that
makes sure regulation is not lost when a heavy load is applied and low power mode is enabled, system design
needs to make sure that the LP pin is pulled low for continuous loading in excess of 100 mA.
16
Copyright © 2011, Texas Instruments Incorporated
TPS65253
www.ti.com
SLVSAW8 –JUNE 2011
When low power is implemented, the peak inductor current used to charge the output capacitor is:
VIN - VOUT
ILIMIT = 0.25 · TSLEEP_CLK
·
L
(6)
Where TSLEEP_CLK is half of the converter switching period, 2/fSW
.
The size of the additional ripple added to the output is:
2
VIN
L · ILIMIT
ILOAD
fSLEEP_CLK
1
C
¾
·
DVOUT
=
-
· VOUT · (VIN - VOUT)
)
(
2
(7)
(8)
And the peak output voltage during low power operation is (see Figure 23):
DVOUT
VOUT_PK = VOUT
+
2
VOUT_PK
VOUT
Figure 23. Peak Output Voltage During Low Power Operation
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
3.3-V and 6.5 LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
•
•
4.7 µF to 10 µF for V7V pin 21
3.3 µF or larger for V3V pin 229
Layout Recommendation
Layout is a critical portion of PMIC designs.
•
•
Place tracing for output voltage and LX on the top layer and an inner power plane for VIN.
For best thermal performance, pins 25, 26, 27, and 28 should be connected to GND on the top PCB layer as
well as inner GND plane by through-hole connections.
•
The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter capacitor and directly under the TPS65253 device to provide a thermal path from
the PowerPad land to ground.
•
•
For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
•
•
The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
The compensation should be as close as possible to the CMPx pins. The CMPx and ROSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
Copyright © 2011, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS65253RHD
PREVIEW
ACTIVE
VQFN
VQFN
RHD
RHD
28
28
50
TBD
Call TI
Call TI
TPS65253RHDR
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS65253RHDT
ACTIVE
VQFN
RHD
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65253RHDR
TPS65253RHDT
VQFN
VQFN
RHD
RHD
28
28
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65253RHDR
TPS65253RHDT
VQFN
VQFN
RHD
RHD
28
28
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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