TPS65258 [TI]

4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE DC-DC CONVERTERS WITH INTEGRATED FET AND 2 USB SWITCHES; 4.5 V至16 V输入，大电流，同步降压THREE DC- DC具有集成FET转换器和2个USB开关系列


型号：	TPS65258
厂家：	TEXAS INSTRUMENTS
描述：	4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE DC-DC CONVERTERS WITH INTEGRATED FET AND 2 USB SWITCHES 4.5 V至16 V输入，大电流，同步降压THREE DC- DC具有集成FET转换器和2个USB开关系列转换器开关输入元件 DC-DC转换器
文件：	总32页 (文件大小：1580K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65258

www.ti.com

SLVSAB31 –SEPTEMBER 2011

4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE DC-DC

CONVERTERS WITH INTEGRATED FET AND 2 USB SWITCHES

Check for Samples: TPS65258

FEATURES

by External Resistor

•

Current-Mode Control With Simple

Compensation Circuit

•

Wide Input Supply Voltage Range:

4.5 V - 16 V

Automatic Low Pulse Skipping (PSM) Power

Mode, Allowing for an Output Ripple Better

than 2%

•

0.8-V, 1% Accuracy Reference

Continuous Loading:

3 A (Buck1), 2 A (Buck2 and 3)

•

Forced PWM Mode

•

Maximum Current:

3.5 A (Buck 1), 2.5 A (Buck2 and 3)

Support Pre-Biased Outputs

Power Good Supervisor and Reset Generator

Synchronous Operation, 300-kHz – 2.2-MHz

Switching Frequency Set By External Resistor

1-A, 2 USB Power Switches With Overcurrent

and Thermal Protection

External Enable Pins With Built-In Current

Source for Easy Sequencing

•

Small, Thermally Efficient 40-Pin 6-mm x 6-mm

RHA (QFN) package

•

External Soft Start Pins

-40°C to 125°C Junction Temperature Range

Adjustable Cycle-by-Cycle Current Limit Set

DESCRIPTION/ORDERING INFORMATION

TPS65258 is a power management IC with three step-down buck converters. Both high-side and low-side

MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. The converters are

designed to simplify its application while giving the designer the option to optimize their usage according to the

target application.

The converters can operate in 5-, 9-, 12- or 15-V systems. The output voltage can be set externally using a

resistor divider to any value between 0.8 V and the input supply minus the resistive drops on the converter path.

Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that

allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIM) pin that enables

designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. All converters

operate in ‘hiccup mode’: Once an over-current lasting more than 10 ms is sensed in any of the converters, they

will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed,

the converter will ramp up and operate normally. If this is not the case the converter will see another over-current

event and shuts down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts

for less than 10 ms, only the relevant converter affected will shut-down and re-start and no global hiccup mode

will occur.

The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching

regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between

then to minimize the input filter requirements. All converters have peak current mode control which simplifies

external frequency compensation.

The device has a built-in slope compensation ramp to prevent sub harmonic oscillations in peak current mode

control. A traditional type II compensation network can stabilize the system and achieve fast transient response.

Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero

and makes the crossover frequency over 100 kHz.

All converters feature an automatic low power pulse PFM skipping mode which improves efficiency during light

loads and standby operation, while guaranteeing a very low output ripple, allowing for a value of less than 2% at

low output voltages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65258

SLVSAB31 –SEPTEMBER 2011

www.ti.com

The device incorporates an overvoltage transient protection circuit to minimize voltage overshoot. The OVP

feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold

which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the

high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot.

When the FB voltage drops lower than the OVP lower threshold which is 107%, the high side MOSFET is

allowed to turn on the next clock cycle.

TPS65258 features a supervisor circuit which monitors each buck’s output and the PGOOD pin is asserted once

sequencing is done. The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck

converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all converter outputs

are more than 90% of its nominal output voltage. The default reset time is 100 ms. The polarity of the PGOOD is

active high.

The 2 USB switches provide up to 1-A of current as required by downstream USB devices. When the output load

exceeds the current-limit threshold or a short is present, the PMU limits the output current to a safe level by

switching into a constant-current mode and pulling the over current logic output low. When continuous heavy

overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise,

a thermal warning protection circuit shuts off the USB switch and allows the buck converters to carry on

operating.

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.

The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip

threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The

thermal shutdown hysteresis is 20°C.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

PART NUMBER

TOP-SIDE MARKING

-40°C to 125°C

40-Pin (QFN) - RHA

Reel of 2500

TPS65258RHAR

TPS65258

(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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TPS65258

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SLVSAB31 –SEPTEMBER 2011

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

V_PULL

USB 1__nFAULT

C_{USB_0}

USB 1__VO

C_{USB_IN}

USB 1__VIN

V_PULL

USB1__EN

12V

C_V3P3

From Host

USB_SWITCHES

USB 2__nFAULT

V_3V

V_7V

C_{USB_0}

C_V7

Biasing

CLOCK

USB 2__VO

CUSB_IN

USB 2__VIN

USB2__EN

ROSC

From Host

R_OSC

BST₁

V_IN1

SS₁

C_SS1

C_BST1

C_IDC1

LX1

LX₁

FB₁

R_ILIM1

R_LIM1

L_DC1

R_FB1U

BUCK1

Forced PWM

C_ODC1

1µA

R_CMP1

C_CMP1

RFB1L

External enable

EN₁

CMP₁

for sequenced

start-up

0.8V

C_CMP11

V_IN2

SS₂

BST ₂

CSS2

C_IDC2

C_BST2

LX₂

FB₂

R_LIM2

R_ILIM2

LDC2

BUCK2

R_FB2U

C_ODC2

1µA

Forced PWM

R_CMP2

C_CMP2

R_FB2L

External enable

EN₂

CMP ₂

0.8V

for sequenced

start-up

CCMP22

V_IN3

SS₃

BST₃

C_SS3

C_IDC3

CBST3

LX₃

R_ILIM3

R_LIM3

L_DC3

R_FB3U

BUCK3

C_ODC3

1µA

FB₃

EN₃

External enable

R_FB3L

R_CMP3

C_CMP3

V_PULL

0.8V

CMP₃

for sequenced

start-up

Forced PWM

C_CMP33

PG&RST

generator

PGOOD

F_PWM

High for forced PWM

Low por autoamtic PFM/PWM mode

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SLVSAB31 –SEPTEMBER 2011

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TYPICAL APPLICATION

V_PULL

EOR

Host

USB_O

FB2

USB1_I

EN2

USB2_VIN

BST2

VIN2

USB1_VIN

USB1_Vo

VIN2

USB_O

Host

LX2

Host

USB1_EN

TPS65258

V_PULL

USB1_nFAULT

LX1

LX3

VIN1

VIN3

BST3

EN3

BST1

EN1

FB1

FB3

Host

Optional

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SLVSAB31 –SEPTEMBER 2011

PIN OUT

USB2_Vin

USB1_Vin

EN2

BST2

VIN2

USB1_Vo

USB1_EN

LX2

LX1

USB1_nFAULT

TPS65258

QFN RHA40

LX3

VIN1

BST1

EN1

VIN3

BST3

EN3

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SLVSAB31 –SEPTEMBER 2011

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TERMINAL FUNCTIONS

NAME

NO.

I/O

DESCRIPTION

Current limit setting for Buck3. Fit a resistor from this pin to ground to set

the peak current limit on the output inductor.

RLIM3

Soft start pin for Buck3. Fit a small ceramic capacitor to this pin to set the

converter soft start time.

SS3

Compensation for Buck3. Fit a series RC circuit to this pin to complete

the compensation circuit of this converter.

COMP3

Feedback pin for Buck3. Connect a divider set to 0.8 V from the output of

the converter to ground.

FB3

USB2_EN

ROSC

Enable input, high turns on the switch

Oscillator set. This resistor sets the frequency of internal autonomous

clock.

Feedback pin for Buck1. Connect a divider set to 0.8 V from the output of

the converter to ground.

FB1

Compensation pin for Buck1. Fit a series RC circuit to this pin to complete

the compensation circuit of this converter.

COMP1

SS1

Soft-start pin for Buck1. Fit a small ceramic capacitor to this pin to set the

converter soft-start time.

Current limit setting pin for Buck1. Fit a resistor from this pin to ground to

set the peak current limit on the output inductor.

RLIM1

Enable pin for Buck1. A high signal on this pin enables the regulator

Buck. For a delayed start-up add a small ceramic capacitor from this pin

to ground.

EN1

Bootstrap capacitor for Buck1. Fit a 47-nF ceramic capacitor from this pin

to the switching node.

BST1

VIN1

LX1

Input supply for Buck1. Fit a 10-µF ceramic capacitor close to this pin.

Switching node for Buck1

14, 15

16, 17

LX2

Switching node for Buck2

VIN2

Input supply for Buck2. Fit a 10-µF ceramic capacitor close to this pin.

Bootstrap capacitor for Buck2. Fit a 47-nF ceramic capacitor from this pin

to the switching node.

BST2

Enable pin for Buck2. A high signal on this pin enables the regulator. For

a delayed start-up add a small ceramic capacitor from this pin to ground.

EN2

Current limit setting pin for Buck2. Fit a resistor from this pin to ground to

set the peak current limit on the output inductor.

RLIM2

SS2

Soft-start pin for Buck2. Fit a small ceramic capacitor to this pin to set the

converter soft-start time.

Compensation pin for Buck2. Fit a series RC circuit to this pin to complete

the compensation circuit of this converter.

COMP2

FB2

Feedback input for Buck2. Connect a divider set to 0.8 V from the output

of the converter to ground.

Forces PWM operation in all converters when set high. If low converters

will operate in automatic PFM/PWM mode.

F_PWM

USB2_nFAULT

USB2 fault flag output, open drain, active low. Asserted when overcurrent

or over temperature condition is detected in the switch.

Power good. Open drain output asserted low after all converters and

sequenced and within regulation. Polarity is factory selectable (active high

default).

PGOOD

Internal supply. Connect a 10-µF ceramic capacitor from this pin to

ground.

V7V

V3V

Internal supply. Connect a 10-µF ceramic capacitor from this pin to

ground.

USB2_Vo

USB2_VIN

USB1_VIN

USB1_Vo

USB switch output

USB switch input supply

USB switch output

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SLVSAB31 –SEPTEMBER 2011

TERMINAL FUNCTIONS (continued)

NAME

NO.

I/O

DESCRIPTION

Enable input, high turns on the switch

USB1_EN

USB1 fault flag output, open drain, active low. Asserted when overcurrent

or overtemperature condition is detected in the switch.

USB1_nFAULT

LX3

36, 37

Switching node for Buck3

VIN3

Input supply for Buck3. Fit a 10-µF ceramic capacitor close to this pin.

Bootstrap capacitor for Buck3. Fit a 47-nF ceramic capacitor from this pin

to the switching node.

BST3

Enable pin for Buck3. A high signal on this pin enables the converter. For

a delayed start-up add a small ceramic capacitor from this pin to ground.

EN3

PowerPAD. Connect to system ground for electrical and thermal

connection.

PowerPAD

(1)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND)

Voltage range at VIN1,VIN2, VIN3, LX1, LX2, LX3

–0.3 to 18

Voltage range at LX1, LX2, LX3 (maximum withstand voltage transient < 10 ns)

Voltage at BST1, BST2, BST3 referenced to LX pin

–3 to 18

–0.3 to 7

Voltage at V7V, COMP1, COMP2, COMP3, USB1_Vin, USB1_Vo, USB2_Vin, USB2_Vo

Voltage at V3V, RLIM1, RLIM2, RLIM3, EN1,EN2, EN3, SS1, SS2, SS3, FB1, FB2,FB3 ,

PGOOD, ROSC, USB1_EN, USB1_nLIMx, USB2_EN, USB2_nLIMx,

–0.3 to 3.6

T_J

Operating junction temperature range

Storage temperature range

–40 to 125

–55 to 150

°C

T_STG

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

MAX

UNIT

VIN

T_A

Input operating voltage

Junction temperature

–40

°C

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN

2000

500

MAX

UNIT

Human body model (HBM)

Charge device model (CDM)

PACKAGE DISSIPATION RATINGS⁽¹⁾

T_A= 25°C

POWER RATING (W)

T_A= 55°C

POWER RATING (W)

T_A= 85°C

POWER RATING (W)

PACKAGE

θ_JA(°C/W)

RHA

3.33

2.3

1.3

(1) Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x 0.6-mm board with the following layer arrangement:

(a) Top layer: 2 Oz Cu, 6.7% coverage

(b) Layer 2: 1 Oz Cu, 90% coverage

(d) Bottom layer: 2 Oz Cu, 20% coverage

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SLVSAB31 –SEPTEMBER 2011

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ELECTRICAL CHARACTERISTICS

T_J= –40°C to 125°C, V_IN= 12 V, f_SW= 500 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE

V_IN

Input voltage range

Shutdown

4.5

IDD_SDN

EN pin = low for all converters

170

600

µA

Converters enabled, no load

Buck1 = 1.2 V

Buck2 = 1.8 V

Buck3 = 3.3 V

T_A= 25°C, F_PWM = Low

Quiescent (push-button pull-up

current not included)

µA

IDD_Q

Converters enabled, no load

F_PWM = High

Quiescent, forced PWM

V_INunder voltage lockout

Rising V_IN

Falling V_IN

Both edges

4.22

4.1

UVLO

UVLO_DEGLITCH

V3p3

110

3.3

µs

Internal biasing supply

V7V

6.25

3.8

Rising V7V

Falling V7V

Falling edge

V7V_UVLO

UVLO for internal V7V rail

3.6

V7V_{UVLO_DEGLITCH}

110

µs

BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT-START AND SWITCHING FREQUENCY)

V3p3 = 3.2 V - 3.4 V,

V_ENxrising

0.66 x

V3p3

V_{IH_ENx}

Enable threshold high

Enable treshold low

Enable threshold high

Enable treshold low

V3p3 = 3.2 V - 3.4 V,

V_ENxfalling

0.33 x

V3p3

V_{IL_ENx}

V3p3 = 3.2 V - 3.4 V,

V_ENxrising

0.66 x

V3p3

V_{IH_F_PWM}

V_{IL_F_PWM}

V3p3 = 3.2 V - 3.4 V,

V_ENxfalling

0.33 x

V3p3

ICH_EN

t_D

Pull up current enable pin

Discharge time enable pins

Soft-start pin current source

µA

Power-up

I_SS

F_{SW_BK}

R_FSW

f_{SW_TOL}

Converter switching frequency range Set externally with resistor

Frequency setting resistor

0.3

2.2

600

MHz

kΩ

Internal oscillator accuracy

f_SW= 800 kHz

-10

FEEDBACK, REGULATION, OUTPUT STAGE

V_IN= 12 V , T_A= 25°C

-1%

-2%

0.8

V_FB

Feedback voltage

V_IN= 4.5 V to 16 V

Minimum on time (current sense

blanking)

t_{ON_MIN}

135

I_LIMIT1

Peak inductor current limit range

0.75

I_LIMIT2

I_LIMIT3

MOSFET (BUCK 1)

On resistance of high side FET on

CH1

H.S. Switch

25°C, BOOT = 6.5 V

25°C, VIN = 12 V

mΩ

On resistance of low side FET on

CH1

L.S. Switch

MOSFET (BUCK 2)

H.S. Switch

On resistance of high side FET on

CH2

25°C, BOOT = 6.5 V

25°C, VIN = 12 V

120

mΩ

On resistance of low side FET on

CH2

L.S. Switch

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SLVSAB31 –SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS (continued)

T_J= –40°C to 125°C, V_IN= 12 V, f_SW= 500 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MOSFET (BUCK 3)

On resistance of high side FET on

CH3

H.S. Switch

25°C, BOOT = 6.5 V

25°C, VIN = 12 V

120

mΩ

On resistance of low side FET on

CH3

L.S. Switch

ERROR AMPLIFIER

g_M

Error amplifier transconductance

COMP to ILX gm

-2 µA < ICOMP < 2 µA

130

µ℧

gm_PS

I_LX= 0.5 A

A/V

POWER GOOD RESET GENERATOR

Output falling

Threshold voltage for buck under

voltage

VUV_BUCKX

Output rising (PG will be

asserted)

t_{UV_deglitch}

t_{ON_HICCUP}

Deglitch time (both edges)

Hiccup mode ON time

VUV_BUCKXasserted

All converters disabled. Once

t_{OFF_HICCUP}elapses, all

converters will go through

sequencing again.

t_{OFF_HICCUP}

Hiccup mode OFF time

Output rising (high side FET will

be forced off)

109

107

Threshold voltage for buck over

voltage

VOV_BUCKX

Output falling (high side FET will

be allowed to switch )

Measured after the later of

Buck1 or Buck3 power-up

successfully

t_RP

minimum reset period

100

THERMAL SHUTDOWN

T_TRIP

Thermal shut down trip point

Rising temperature

Device re-starts

160

°C

µs

T_HYST

Thermal shut down hysteresis

Thermal shut down deglitch

T_{TRIP_DEGLITCH}

USB SWITCHES

VIN_USB

110

USB input voltage range

0.66 x

V3p3

V_{IH_USB_EN}

V_{IL_USB_EN}

R_{DS_USB}

USB_EN high level input voltage

V3p3 = 3.2-3.4 V, V_{USB_EN}rising

V3p3 = 3.2-3.4 V, V_{USB_EN}falling

0.33 x

V3p3

USB_EN low level input voltage

mΩ

Static drain-source on-state

resistance

USB_VIN = 5 V and Io_USB =

0.5 A, T_J= 25°C

120

1.2

Increasing USB_Vo current

di/dt<1 A/s

I_{CS_USB}

USB current limit

Increasing USB_Vo current di/dt<

1A/s

VIN_USB= 5 V

Overcurrent detection factor

Ratio of I_{LIM_START}/I_{CS_USB}

K_OVERCURRENT

1.5

V_{USBx_nFAULT}

T_{CS_USB}

USBx_nFAULT output voltage low

USB over current fault deglitch

I_{USB_ILIM}= 3 mA

0.4

Fault assertion due to Over

current protection

T_{USB_TRIP}

T_{USB_HYST}

USB thermal trip point

Rising temperature

Falling temperature

130

°C

USB thermal trip hysteresis

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SLVSAB31 –SEPTEMBER 2011

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TYPICAL CHARACTERISTICS

Load Regulation: Buck1 @ 1.2V, 1% Resistor Feedback

Load Regulation: Buck2 @ 1.8V, 1% Resistor Feedback

1.225

1.825

I_buck2 = 2 A,

I_buck3 = 2 A

I_buck2 = 1 A,

I_buck3 = 1 A

I_buck2 = 2 A,

I_buck3 = 2 A

I_buck1 = 1 A,

I_buck3 = 1 A

1.22

1.82

1.815

1.81

1.215

1.21

I_buck2 = 0.25 A,

I_buck3 = 0.25 A

I_buck1 = 0.25 A,

I_buck3 = 0.25 A

1.205

1.2

1.805

1.8

0.5

1.5

2.5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

I_BUCK1 - A

I_BUCK2 - A

Figure 1.

Figure 2.

Buck1 Temp Variation @ 1.2V, 1%Resistor

-40°C to 75°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A

Load Regulation: Buck3 @ 3.3V, 1% Resistor Feedback

3.385

1.23

3.38

1.225

I_buck1 = 2 A,

I_buck2 = 2 A

I_buck1 = 1 A,

I_buck2 = 1 A

1.22

3.375

1.215

3.37

I_buck1 = 0.25 A,

I_buck2 = 0.25 A

3.365

1.21

-40

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-20

I_BUCK3 - A

Temperature - °C

Figure 3.

Figure 4.

Current Limit Variation 25°C,

Buck1 1.2V Efficiency, Forced PWM

RLIM1 = 100kΩ, RLIM2&3 = 120kΩ

L = 4.7µH, 20mΩ, f_SW= 500KHz

3.9

3.8

3.7

3.6

3.5

3.4

3.3

buck2 = 0 A,

buck3 = 0 A

V = 12 V

V = 15 V

V = 4.5 V

buck2 = 2 A,

buck3 = 2 A

3.2

3.1

-40

-20

0.5

1.5

2.5

Temperature - °C

Current - A

Figure 5.

Figure 6.

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SLVSAB31 –SEPTEMBER 2011

TYPICAL CHARACTERISTICS (continued)

Buck1 1.2V Efficiency, Forced PWM and PFM

Buck2 1.8V Efficiency, Forced PWM

L = 4.7µH, 20mΩ, f_SW= 500KHz

PFM

V = 12 V

V = 15 V

PWM

V = 4.5 V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Current - A

Current - mA

Figure 7.

Figure 8.

Buck2 1.8V Efficiency, Forced PWM and PFM

Buck3 3.3V Efficiency, Forced PWM

L = 4.7µH, 20mΩ, f_SW= 500KHz

V = 4.5 V

V = 15 V

PFM

V = 12 V

PWM

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Current - A

Current - mA

Figure 9.

Figure 10.

Buck3 3.3V Efficiency, Forced PWM and PFM

L = 4.7µH, 20mΩ, f_SW= 500KHz

Power-Up All Converters, No Load V_IN= 12V (Green)

PFM

PWM

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Current - mA

Figure 11.

Figure 12.

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TYPICAL CHARACTERISTICS (continued)

Power-Up All Converters and PGOOD (Green), No Load

Detail of Start-Up 4.7nF Fitted to All Enable Pins

Figure 13.

Figure 14.

Ripple T_A= 25°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A

Ripple T_A= 70°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A

Figure 15.

Figure 16.

Ripple T_A= 10°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A

Ripple T_A= 40°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A

Figure 17.

Figure 18.

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TYPICAL CHARACTERISTICS (continued)

Transient Response Buck1

Transient Response Buck2

1.2V, 1-3A Step, Co = 22µF,L = 4.7µH, f_SW= 500KHz

1.8V, 1-2A Step, Co = 22µF,L = 4.7µH, f_SW= 500KHz

Figure 19.

Figure 20.

Buck3 3.3V Efficiency Measured With L = 4.7µH, 20mΩ,

f_SW= 500kHz

PFM Operation 1.2V, 1.8V, 3.3V

Figure 21.

Figure 22.

PFM/PWM Transition (Pin 25 Pulled High)

PFM/PWM Transition (Pin 25 Pulled Low)

Figure 23.

Figure 24.

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TYPICAL CHARACTERISTICS (continued)

Buck1 Dynamic Transition from PFM to PWM

Buck2 Dynamic Transition from PFM to PWM

4.7µH, 44µF, 500 kHz

Figure 25.

Figure 26.

Buck3 Dynamic Transition from PFM to PWM

4.7µH, 22µF, 500 kHz

USB Switch Start-Up No Load

Figure 27.

Figure 28.

USB Switch Start-Up No Load

USB Current Limit Operation (3.3 V)

Figure 29.

Figure 30.

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TYPICAL CHARACTERISTICS (continued)

USB Current Limit Recovery (3.3 V)

USB Current Limit Operation (5 V)

Figure 31.

Figure 32.

USB Current Limit Recovery (5 V)

Bucks Operation (Top 3 Traces) and USB Alarm Operation

Figure 33.

Figure 34.

T_A= 25°, V_IN= 12V, f_SW= 500kHz

EVM Layout

B1 = 3A, B2 = 2A, B3 = 2A

Figure 35.

Figure 36.

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TYPICAL CHARACTERISTICS (continued)

T_A= 25°, V_IN= 5V, f_SW= 500kHz

T_A= 25°, V_IN= 5V, f_SW= 1000kHz

B1 = 3A, B2 = 2A, B3 = 2A

Figure 37.

Figure 38.

DETAILED DESCRIPTION

Adjustable Switching Frequency

To select the internal switching frequency, connect a resistor from ROSC to ground. Figure 39 shows the

required resistance for a given switching frequency.

700

650

600

550

500

450

400

350

300

250

200

150

100

0.3

0.8

1.3

1.8

- Switching Frequency - MHz

Figure 39. ROSC vs Switching Frequency

-1.122

R_OSC(kW) = 174 · f_SW

(1)

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Output Inductor Selection

To calculate the value of the output inductor, use Equation 2.

Vin -Vout Vout

Lo =

Io× K_indVin× fsw

(2)

K_indis a coefficient that represents the amount of inductor ripple current relative to the maximum output current.

In general, K_indis normally from 0.1 to 0.3 for the majority of applications. A value of 0.1 will improve the

efficiency at light load, while a value of 0.3 will provide the lowest possible cost solution. The ripple current is:

Vin -Vout Vout

Iripple =

Vin× fsw

(3)

Output Capacitor

There are two primary considerations for selecting the value of the output capacitor. The output capacitors are

selected to meet load transient and output ripple’s requirements. If a minimum transient specification is required

use the following equation:

DI_OUT²× L_o

Co >

V_out×DVout

(4)

The following equation calculates the minimum output capacitance needed to meet the output voltage ripple

specification.

Co >

V_RIPPLE

8× fsw

V_RIPPLE

(5)

Where f_SWis the switching frequency, V_RIPPLEis the maximum allowable output voltage ripple, and V_RIPPLEis the

inductor ripple current.

Input Capacitor

A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND of

each converter. The input capacitor must handle the RMS ripple current shown in the following equation.

Vinmin-Vout

(

)

Vout

Icirms = Iout ×

Vinmin

(6)

Bootstrap Capacitor

The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX

pins to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be

0.047 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable

characteristics over temperature and voltage.

Soft-Start Time

The device has an internal pull-up current source of 5 µA that charges an external soft-start capacitor to

implement a slow start time. Equation 7 shows how to select a soft-start capacitor based on an expected slow

start time. The voltage reference (V_REF) is 0.8 V and the soft-start charge current (I_ss) is 5 µA. The soft-start

circuit requires 1 nF per around 167 µs to be connected at the SS pin. A 0.8-ms soft-start time is implemented for

all converters fitting 4.7 nF to the relevant SS pin.

C_ss(nF)

I_ss(µA)

T_ss(ms) = V_REF(V) ·

(

)

(7)

The Power Good circuit for the bucks has a 10-ms watchdog. Therefore the soft-start time should be lower than

this value. It is recommended not to exceed 5 ms.

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Delayed Start-Up

If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay

added is ~1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1-MΩ pull-up to the 3V3 rail.

VIN

V7V

V3V

PB_in

De-bouncing

20mS

De-bouncing

20mS

200mS

1024 mS

INT

Internal EN

EN treshold

Enx rise time

dictated by C_EN

EN1

EN2

EN3

All bucks are disabled

20-22 mS

Enable discharge

10-12mS

Pre-bias timing

4-5mS

PG asserted

BUCK1

BUCK2

BUCK3

Pre-biased output

Soft star rise time

dictated by C_SS

Soft start timer

10ms watchdog

PGOOD

PG timer

100 ms

Figure 40. Delayed Start-Up

Out-of-Phase Operation

In order to reduce input ripple current, Buck1 and Buck2 operate 180° out-of-phase. This enables the system

having less input ripple, then to lower component cost, save board space and reduce EMI.

Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%

tolerance or better divider resistors. In order to improve efficiency at light load, start with a value close to 40 kΩ

for the R1 resistor and use Equation 8 to calculate R2.

0.8V

R2 = R1×

V_O- 0.8V

(8)

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TPS652510

0.8V

Figure 41. Voltage Divider Circuit

Loop Compensation

TPS65258 is a current mode control DC/DC converter. The error amplifier is a transconductance amplifier with a

g_Mof 130 µA/V. A typical compensation circuit could be type II (R_cand C_c) to have a phase margin between 60°

and 90°, or type III (R_cand C_cand C_ffto improve the converter transient response. C_Rolladds a high frequency

pole to attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there

is possibility of cross coupling in between rails when layout is very compact.

Gm = 10 A/V

ESR

Current Sense

I/V Gain

FBx

=130m

= 0.8 V

COMPx

REF

Roll

Figure 42. Loop Compensation Scheme

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To calculate the external compensation components follow the following steps:

TYPE II CIRCUIT

TYPE III CIRCUIT

Select switching frequency that is appropriate for

application depending on L, C sizes, output ripple, EMI

concerns and etc. Switching frequencies around 500 kHz

yield best trade off between performance and cost. When

using smaller L and C, switching frequency can be

increased. To optimize efficiency, switching frequency can

be lowered.

Use type III circuit for switching

frequencies higher than 500 kHz.

Select cross over frequency (f_c) to be at least 1/5 to 1/10 of

switching frequency (f_s).

Suggested

f_c= f_s/10

Suggested

f_c= f_s/10

2p × fc×Vo×Co

g_M×Vref × gm_ps

2p × fc×Vo×Co

R_C=

g_M×Vref × gm_ps

R_C=

Set and calculate R_c.

Calculate C_cby placing a compensation zero at or before

the converter dominant pole

R_L×Co

C_c=

fp =

R_c

C_O× R_L×2p

Add C_Rollif needed to remove large signal coupling to high

impedance CMP node. Make sure that

Re sr ×Co

C_Roll

fp_Roll

R_C

2×p × R_C×C_Roll

is at least twice the cross over frequency.

Calculate C_ffcompensation zero at low frequency to boost

the phase margin at the crossover frequency. Make sure

that the zero frequency (fz_ff) is smaller than equivalent

soft-start frequency (1/T_ss).

C_ff=

2×p × fz_ff× R

Slope Compensation

The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic

oscillations in peak current mode control.

Power Good

The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below

85% of the nominal output voltage. The PGOOD is pulled up when both buck converters’ outputs are more than

90% of its nominal output voltage.

The default reset time is 100 ms. The polarity of the PGOOD is active high.

Current Limit Protection

The TPS65258 current limit trip is set by the following formulae:

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TYPE II CIRCUIT

4.5

4.3

3.8

3.5

3.3

2.8

2.5

2.3

267

_LIM1(A) =

_{LIM 2}(A) =

_{LIM 3}(A) =

+1.77

+1.72

+ 0.97

RLIM1(kW)

(9)

(10)

(11)

1.8

1.5

1.3

100 175 250 325 400 475 550 625 700 775 850 925 1000

RLIM1 - kW

4.5

4.3

3.8

3.5

3.3

2.8

2.5

2.3

256

RLIM1(kW)

1.8

1.5

1.3

100 175 250 325 400 475 550 625 700 775 850 925 1000

RLIM2 - kW

3.5

3.3

2.8

2.5

2.3

253

1.8

1.5

1.3

RLIM 2(kW)

0.8

0.5

100 175 250 325 400 475 550 625 700 775 850 925 1000

RLIM3 - kW

All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the

converters, they will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has

been removed, the converter will ramp up and operate normally. If this is not the case the converter will see

another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.

If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start

and no global hiccup mode will occur.

Overvoltage Transient Protection

The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The

OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVTP

threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP

threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output

overshoot. When the FB voltage drops lower than the OVTP threshold which is 107%, the high side MOSFET is

allowed to turn on the next clock cycle.

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Low Power/Pulse Skipping Operation

When a buck synchronous converter operates at light load or standby conditions, the switching losses are the

dominant source of power losses. Under these load conditions, TPS65258 uses a pulse skipping modulation

technique to reduce the switching losses by keeping the power transistors in the off-state for several switching

cycles, while maintaining a regulated output voltage. Figure 43 shows the output voltage and load plus the

inductor current.

OUT

Skipping

Burst

OUT

Figure 43. Low Power/Pulse Skipping

During the burst mode, the converter continuously charges up the output capacitor until the output voltage

reaches a certain limit threshold. The operation of the converter in this interval is equivalent to the peak inductor

current mode control. In each switch period, the main switch is turned on until the inductor current reaches the

peak current limit threshold. As the load increases the number of pulses increases to make sure that the output

voltage stays within regulation limits. When the load is very light the low power controller has a zero crossing

detector to allow the low side mosfet to operate even in light load conditions. The transistor is not disabled at

light loads. A zero crossing detection circuit will disable it when inductor current reverses. During the whole

process the body diode does not conduct but is used as blocking diode only.

During the skipping interval, the upper and lower transistors are turned off and the converter stays in idle mode.

The output capacitors are discharged by the load current until the moment when the output voltage drops to a

low threshold.

The choice of output filter will influence the performance of the low power circuit. The maximum ripple during low

power mode can be calculated as:

K_RIPT_S

V_{OUT _ RIPPLE}

C_OUT

(12)

(13)

Where K_RIPis 1.4 for Buck1 and 0.7 for Buck2 and Buck3. TS can be calculated as:

0.35

T_S=

-V_OUT

OUT

V_{IN û}

USB Switches

The USB switches are enabled (active high) with the USB_ENx pin. The switches have a typical resistance of

120 mΩ and has a fold-back current limit that is typically 25% lower than the overcurrent detection point. If a

continuous short-circuit condition is applied to one USB switch output, the USB switches will shut-down once its

temperature reaches 130°C, allowing for the buck converters to operate unaffected. Once the USB switch cools

down it will restart automatically.

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USB_Vin

USB_EN

USB_Vo

OVERCURRENT DETECTED

USB_LOAD

ICS_USB

OVERCURRENT IS CLEARED

USB_I

Overcurrent at the out.put Alarm

is asserted after 5 ms

Normal operation is restor.ed

Alarm is cleare.d

Normal operation

USB_nFAULT

T_{CS_USB}

Figure 44. USB Switches

The USB switches are single sided without back-fed protection but the 2 USB switches of TPS65258 can be

configured as a back to back switch.

Switch 1

Switch2

VOUT

VIN

VOUT

VIN

VOUT

Figure 45. Back to Back Switch

Power Dissipation

The total power dissipation inside TPS65258 should not to exceed the maximum allowable junction temperature

of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (R_JA)

and ambient temperature. To calculate the temperature inside the device under continuous loading use the

following procedure:

1. Define the set voltage for each converter.

2. Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading..

3. Determine from the graphs below the expected losses in watts per converter inside the device. The losses

depend on the input supply, the selected switching frequency, the output voltage and the converter chosen.

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1.6

1.4

1.6

1.4

1.2

0.8

0.6

0.8

0.6

0.4

0.2

2.2 2.4 2.6 2.8

1.2 1.4 1.6 1.8

2.2 2.4 2.6 2.8

3.2 3.4 3.6

1.2 1.4 1.6 1.8

3.2 3.4 3.6

Current - A

Buck1 Vin = 12 V, fsw = 500 kHz,

Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V

Buck1 Vin = 12 V, fsw = 1.1 MHz,

Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.6

1.5

1.4

1.3

1.2

1.1

0.9

0.8

0.7

0.6

0.7

0.6

0.5

0.4

0.3

0.2

0.5

0.4

0.3

0.2

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

1.2

1.4

1.6

1.8

Current - A

Buck2&3 Vin = 12 V, fsw = 500 kHz,

Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V

2.2

2.4

2.6

2.8

Current - A

Buck2&3 Vin = 12 V, fsw = 1.1 MHz,

Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V

Figure 46. Power Dissipation Curves

4. Add additional losses due to the operation of the USB switches.

5. To calculate the maximum temperature inside the IC use the following formula:

T_{HOT_SPOT}= T_A+ P_DISx Ѳ_JA

(14)

Where:

T_Ais the ambient temperature

P_DISis the sum of losses in all converters

Ѳ_JAis the junction to ambient thermal impedance of the device and it is heavily dependant on board layout

Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.

The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip

threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The

thermal shutdown hysteresis is 20°C.

3.3-V and 6.5 LDO Regulators

The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:

•

4.7 µF to 10 µF for V7V pin 28

3.3 µF or larger for V3V pin 29

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Layout Recommendation

Layout is a critical portion of PMIC designs.

•

Place tracing for output voltage and LX on the top layer and an inner power plane for VIN.

Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with

ground.

•

The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass

capacitor, the output filter capacitor and directly under the TPS65258 device to provide a thermal path from

the PowerPad land to ground.

•

For operation at full rated load, the top side ground area together with the internal ground plane, must provide

adequate heat dissipating area.

There are several signals paths that conduct fast changing currents or voltages that can interact with stray

inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help

eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass

capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass

capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching

node, the output inductor should be located close to the LX pins, and the area of the PCB conductor

minimized to prevent excessive capacitive coupling.

•

The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.

Try to minimize this conductor length while maintaining adequate width.

The compensation should be as close as possible to the CMPx pins. The CMPx and ROSC pins are sensitive

to noise so the components associated to these pins should be located as close as possible to the IC and

routed with minimal lengths of trace.

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PACKAGE OPTION ADDENDUM

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30-Sep-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS65258RHAR

TPS65258RHAT

ACTIVE

VQFN

RHA

2500

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65258RHAR

TPS65258RHAT

VQFN

RHA

2500

250

330.0

180.0

16.4

6.3

1.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS65258RHAR

TPS65258RHAT

VQFN

RHA

2500

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

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TPS65258 [TI]

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TPS65258RHAR

TPS65258RHAT

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TPS65261-1RHBR

TPS65261-1RHBT

TPS65261RHBR

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TPS65262

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TPS65262-1RHBR

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