TPS65257RHAT [TI]
4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE DC-DC CONVERTER WITH INTEGRATED FET, USB SWITCH AND PUSH BUTTON CONTROL; 4.5 V至16 V输入,大电流,同步降压DC THREE -DC转换器,集成FET , USB开关和按钮控制型号: | TPS65257RHAT |
厂家: | TEXAS INSTRUMENTS |
描述: | 4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE DC-DC CONVERTER WITH INTEGRATED FET, USB SWITCH AND PUSH BUTTON CONTROL |
文件: | 总34页 (文件大小:2046K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS65257
www.ti.com
SLVSB32 –SEPTEMBER 2011
4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE DC-DC
CONVERTER WITH INTEGRATED FET, USB SWITCH AND PUSH BUTTON CONTROL
Check for Samples: TPS65257
1
FEATURES
•
•
Current-Mode Control With Simple
Compensation Circuit
•
Wide Input Supply Voltage Range:
4.5 V - 16 V
Automatic Low Pulse Skipping (PSM) Power
Mode, Allowing for an Output Ripple Better
than 2%
•
•
0.8-V, 1% Accuracy Reference
Continuous Loading:
3 A (Buck1), 2 A (Buck2 and 3)
•
•
•
Support Pre-Biased Outputs
Power Good Supervisor and Reset Generator
•
•
•
Maximum Current:
3.5 A (Buck 1), 2.5 A (Buck2 and 3)
1-A USB Power Switch With Overcurrent and
Thermal Protection
Synchronous Operation, 300-kHz – 2.2-MHz
Switching Frequency Set By External Resistor
•
Push Button (10-kV ESD Rated Pin for PB_IN)
Control for Intelligent System
Power-On/Power-Off Operation
External Enable Pins With Built-In Current
Source for Easy Sequencing
•
•
Small, Thermally Efficient 40-Pin 6-mm x 6-mm
RHA (QFN) package
•
•
External Soft Start Pins
Adjustable Cycle-by-Cycle Current Limit Set
by External Resistor
-40°C to 125°C Junction Temperature Range
DESCRIPTION/ORDERING INFORMATION
TPS65257 is a power management IC with three step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. The converters are
designed to simplify its application while giving the designer the option to optimize their usage according to the
target application.
The converters can operate in 5-, 9-, 12- or 15-V systems. The output voltage can be set externally using a
resistor divider to any value between 0.8 V and the input supply minus the resistive drops on the converter path.
Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that
allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIM) pin that enables
designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. All converters
operate in ‘hiccup mode’: Once an over-current lasting more than 10 ms is sensed in any of the converters, they
will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed,
the converter will ramp up and operate normally. If this is not the case the converter will see another over-current
event and shuts down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts
for less than 10 ms, only the relevant converter affected will shut-down and re-start and no global hiccup mode
will occur.
The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching
regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between
then to minimize the input filter requirements.
All converters have peak current mode control which simplifies external frequency compensation. The device has
a built-in slope compensation ramp. The slope compensation can prevent sub harmonic oscillations in peak
current mode control. A traditional type II compensation network can stabilize the system and achieve fast
transient response. Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider
provides one more zero and makes the crossover frequency over 100 kHz.
All converters feature an automatic low power pulse PFM skipping mode which improves efficiency during light
loads and standby operation, while guaranteeing a very low output ripple, allowing for a value of less than 2% at
low output voltages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65257
SLVSB32 –SEPTEMBER 2011
www.ti.com
The device incorporates an overvoltage transient protection circuit to minimize voltage overshoot. The OVP
feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold
which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the
high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot.
When the FB voltage drops lower than the OVP lower threshold which is 107%, the high side MOSFET is
allowed to turn on the next clock cycle.
TPS65257 features a supervisor circuit which monitors each buck’s output and the PGOOD pin is asserted once
sequencing is done. The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck
converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all converter outputs
are more than 90% of its nominal output voltage. The default reset time is 100 ms. The polarity of the PGOOD is
active high.
The push button operation has been designed to allow for automatic system start when the input supply is
applied or to provide an integrated ON/OFF system management without the need of additional external
components. The behavior of the device will depend on the status of the INT pin (see start-up signals).
The USB switch provides up to 1-A of current as required by downstream USB devices. When the output load
exceeds the current-limit threshold or a short is present, the PMU limits the output current to a safe level by
switching into a constant-current mode and pulling the over current logic output low. When continuous heavy
overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise,
a thermal warning protection circuit shuts off the USB switch and allows the buck converters to carry on
operating.
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
PART NUMBER
TPS65257RHAR
TPS65257RHAT
TOP-SIDE MARKING
Reel of 2500
Reel of 250
-40°C to 125°C
40-Pin (QFN) - RHA
TPS65257
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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TPS65257
www.ti.com
SLVSB32 –SEPTEMBER 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
V3V
PB_IN
VPULL
Debounce
P_OFF
INT
USB_nFAULT
USB_VO
+
12V
CV3P3
V3V
V7V
CUSB_0
CV7
Biasing
USB_SWITCH
USB_VIN
USB_EN
USB supply
+
CLOCK
CUSB_IN
ROSC
ROSC
BST1
VIN1
SS1
CSS1
CBST1
CIDC1
LX1
LX1
FB1
RILIM1
RLIM1
LDC1
RFB1U
BUCK1
Low Power mode
CODC1
1µA
RFB1L
EN1
External enable
CMP1
0.8V
for sequenced
start-up
RCMP1
CCMP1
VIN2
SS2
BST2
CCMP11
CSS2
CIDC2
CBST2
LX2
LX2
RLIM2
RILIM2
LDC2
BUCK2
RFB2U
CODC2
FB2
1µA
Low Power mode
RFB2L
External enable
EN2
CMP2
0.8V
for sequenced
start-up
RCMP2
CCMP2
CCMP22
VIN3
SS3
BST3
CSS3
CIDC3
CBST3
LX3
LX3
RILIM3
RLIM3
LDC3
RFB3U
BUCK3
CODC3
1µA
FB3
EN3
External enable
RFB3L
RCMP3
CCMP3
VPULL
0.8V
CMP3
for sequenced
start-up
Low Power mode
CCMP33
PG&RST
generator
PGOOD
F_PWM
High for forced PWM
Low por autoamtic PFM/PWM mode
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TPS65257
SLVSB32 –SEPTEMBER 2011
www.ti.com
TYPICAL APPLICATION
VPULL
EOR
HOST
FB2
V7V
IC
EN2
USB_I
USB_VIN
BST2
USB_O
VIN2
USB_Vo
VIN2
LX2
LX2
V2
V1
Host
USB_EN
VPULL
USB_nFAULT
TPS65257
V3
LX1
LX1
LX3
LX3
VIN3
VIN1
VIN1
VIN3
BST3
EN3
BST1
EN1
FB1
FB3
Optional
V3V3
4
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SLVSB32 –SEPTEMBER 2011
PIN OUT
30
29
28
27
26
25
24
23
22
21
IC
USB_Vin
USB_Vo
31
32
20
19
EN2
BST2
VIN2
LX 2
LX2
33
34
35
18
17
16
USB_EN
USB_nFAULT
LX3
TPS65257
QFN RHA40
LX1
36
37
38
15
14
13
LX1
LX3
VIN1
VIN3
BST3
EN3
39
40
BST1
EN1
12
11
1
2
3
4
5
6
7
8
9
10
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SLVSB32 –SEPTEMBER 2011
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TERMINAL FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
Current limit setting for Buck3. Fit a resistor from this pin to ground to set
the peak current limit on the output inductor.
RLIM3
1
I
I
Soft start pin for Buck3. Fit a small ceramic capacitor to this pin to set the
converter soft start time.
SS3
2
3
Compensation for Buck3. Fit a series RC circuit to this pin to complete
the compensation circuit of this converter.
COMP3
O
Feedback pin for Buck3. Connect a divider set to 0.8 V from the output of
the converter to ground.
FB3
4
5
6
I
I
I
PB_IN
ROSC
Push button input (active low)
Oscillator set. This resistor sets the frequency of internal autonomous
clock.
Feedback pin for Buck1. Connect a divider set to 0.8 V from the output of
the converter to ground.
FB1
7
8
I
O
I
Compensation pin for Buck1. Fit a series RC circuit to this pin to complete
the compensation circuit of this converter.
COMP1
SS1
Soft-start pin for Buck1. Fit a small ceramic capacitor to this pin to set the
converter soft-start time.
9
Current limit setting pin for Buck1. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
RLIM1
10
I
Enable pin for Buck1. A high signal on this pin enables the regulator
Buck. For a delayed start-up add a small ceramic capacitor from this pin
to ground.
EN1
11
I
Bootstrap capacitor for Buck1. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
BST1
12
VIN1
LX1
13
I
Input supply for Buck1. Fit a 10-µF ceramic capacitor close to this pin.
Switching node for Buck1
14, 15
16, 17
18
O
O
I
LX2
Switching node for Buck2
VIN2
Input supply for Buck2. Fit a 10-µF ceramic capacitor close to this pin.
Bootstrap capacitor for Buck2. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
BST2
EN2
19
20
21
22
23
24
Enable pin for Buck2. A high signal on this pin enables the regulator. For
a delayed start-up add a small ceramic capacitor from this pin to ground.
I
I
Current limit setting pin for Buck2. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
RLIM2
SS2
Soft-start pin for Buck2. Fit a small ceramic capacitor to this pin to set the
converter soft-start time.
I
Compensation pin for Buck2. Fit a series RC circuit to this pin to complete
the compensation circuit of this converter.
COMP2
FB2
O
I
Feedback input for Buck2. Connect a divider set to 0.8 V from the output
of the converter to ground.
Forces PWM operation in all converters when set high. If low converters
will operate in automatic PFM/PWM mode.
F_PWM
INT
25
26
O
O
Open drain interrupt output
Power good. Open drain output asserted low after all converters and
sequenced and within regulation. Polarity is factory selectable (active high
default).
PGOOD
27
Internal supply. Connect a 10-µF ceramic capacitor from this pin to
ground.
V7V
V3V
28
29
O
O
Internal supply. Connect a 10-µF ceramic capacitor from this pin to
ground.
GND
30
31
32
33
34
Ground
IC
I
I
This pin should be connected to V7V pin
USB switch Input supply
USB switch output
USB_VIN
USB_Vo
USB_EN
I
Enable input, high turns on the switch
6
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SLVSB32 –SEPTEMBER 2011
TERMINAL FUNCTIONS (continued)
NAME
NO.
I/O
DESCRIPTION
USB1 fault flag output, open drain, active low. Asserted when overcurrent
or overtemperature condition is detected in the switch.
USB_nFAULT
35
I
LX3
36, 37
38
O
I
Switching node for Buck3
VIN3
Input supply for Buck3. Fit a 10-µF ceramic capacitor close to this pin.
Bootstrap capacitor for Buck3. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
BST3
39
40
I
I
Enable pin for Buck3. A high signal on this pin enables the converter. For
a delayed start-up add a small ceramic capacitor from this pin to ground.
EN3
PowerPAD. Connect to system ground for electrical and thermal
connection.
PowerPAD
(1)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND)
Voltage range at VIN1,VIN2, VIN3, LX1, LX2, LX3
–0.3 to 18
V
V
V
V
Voltage range at LX1, LX2, LX3 (maximum withstand voltage transient < 10 ns)
Voltage at BST1, BST2, BST3 referenced to LX pin
–3 to 18
–0.3 to 7
–0.3 to 7
Voltage at V7V, COMP1, COMP2, COMP3, USB_Vin, USB_Vo
Voltage at V3V, RLIM1, RLIM2, RLIM3, EN1,EN2, EN3, SS1, SS2, SS3, FB1, FB2,FB3 ,
PGOOD, ROSC, PB_IN INT, USB_EN, USB_ILIM
–0.3 to 3.6
V
Voltage at GND
–0.3 to 0.3
–40 to 125
–55 to 150
V
TJ
Operating junction temperature range
Storage temperature range
°C
°C
TSTG
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
16
UNIT
V
VIN
TA
Input operating voltage
Junction temperature
–40
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
UNIT
Human body model (HBM), PB_IN pin to ground
Any other pin
10000
V
2000
500
Charge device model (CDM)
V
PACKAGE DISSIPATION RATINGS(1)
TA = 25°C
POWER RATING (W)
TA = 55°C
POWER RATING (W)
TA = 85°C
POWER RATING (W)
PACKAGE
θJA (°C/W)
RHA
30
3.33
2.3
1.3
(1) Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x 0.6-mm board with the following layer arrangement:
(a) Top layer: 2 Oz Cu, 6.7% coverage
(b) Layer 2: 1 Oz Cu, 90% coverage
(c) Layer 3: 1 Oz Cu, 90% coverage
(d) Bottom layer: 2 Oz Cu, 20% coverage
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SLVSB32 –SEPTEMBER 2011
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN
Input voltage range
Shutdown
4.5
16
V
IDDSDN
EN pin = low for all converters
170
600
µA
Converters enabled, no load
Buck1 = 1.2 V
Buck2 = 1.8 V
Buck3 = 3.3 V
TA = 25°C, F_PWM = Low
Quiescent (push-button pull-up
current not included)
µA
IDDQ
Converters enabled, no load
F_PWM = High
Quiescent, forced PWM
VIN under voltage lockout
18
mA
V
Rising VIN
Falling VIN
Both edges
4.22
4.1
UVLO
UVLODEGLITCH
V3p3
110
3.3
µs
V
Internal biasing supply
Internal biasing supply
V7V
6.25
3.8
V
Rising V7V
Falling V7V
Falling edge
V7VUVLO
UVLO for internal V7V rail
V
3.6
V7VUVLO_DEGLITCH
110
µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT-START AND SWITCHING FREQUENCY)
V3p3 = 3.2 V - 3.4 V,
VENx rising
0.66 x
V3p3
VIH_ENx
Enable threshold high
Enable treshold low
Enable threshold high
Enable treshold low
V
V
V
V
V3p3 = 3.2 V - 3.4 V,
VENx falling
0.33 x
V3p3
VIL_ENx
V3p3 = 3.2 V - 3.4 V,
VENx rising
0.66 x
V3p3
VIH_F_PWM
VIL_F_PWM
V3p3 = 3.2 V - 3.4 V,
VENx falling
0.33 x
V3p3
ICHEN
tD
Pull up current enable pin
Discharge time enable pins
Soft-start pin current source
1
10
5
µA
ms
µA
Power-up
ISS
FSW_BK
RFSW
fSW_TOL
Converter switching frequency range Set externally with resistor
Frequency setting resistor
0.3
50
2.2
600
10
MHz
kΩ
Internal oscillator accuracy
fSW = 800 kHz
-10
%
FEEDBACK, REGULATION, OUTPUT STAGE
VIN = 12 V , TA = 25°C
-1%
-2%
0.8
0.8
1%
2%
VFB
Feedback voltage
V
VIN = 4.5 V to 16 V
Minimum on time (current sense
blanking)
tON_MIN
135
ns
ILIMIT1
Peak inductor current limit range
Peak inductor current limit range
Peak inductor current limit range
0.75
0.75
0.75
4
3
3
A
A
A
ILIMIT2
ILIMIT3
MOSFET (BUCK 1)
On resistance of high side FET on
CH1
H.S. Switch
25°C, BOOT = 6.5 V
25°C, VIN = 12 V
95
mΩ
mΩ
On resistance of low side FET on
CH1
L.S. Switch
50
MOSFET (BUCK 2)
H.S. Switch
On resistance of high side FET on
CH2
25°C, BOOT = 6.5 V
25°C, VIN = 12 V
120
80
mΩ
mΩ
On resistance of low side FET on
CH2
L.S. Switch
8
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SLVSB32 –SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET (BUCK 3)
On resistance of high side FET on
CH3
H.S. Switch
25°C, BOOT = 6.5 V
25°C, VIN = 12 V
120
mΩ
mΩ
On resistance of low side FET on
CH3
L.S. Switch
80
ERROR AMPLIFIER
gM
Error amplifier transconductance
COMP to ILX gm
-2 µA < ICOMP < 2 µA
130
10
µ℧
gmPS
ILX = 0.5 A
A/V
POWER GOOD RESET GENERATOR
Output falling
85
90
Threshold voltage for buck under
voltage
VUVBUCKX
%
Output rising (PG will be
asserted)
tUV_deglitch
tON_HICCUP
Deglitch time (both edges)
Hiccup mode ON time
11
12
ms
ms
VUVBUCKX asserted
All converters disabled. Once
tOFF_HICCUP elapses, all
converters will go through
sequencing again.
tOFF_HICCUP
Hiccup mode OFF time
20
ms
Output rising (high side FET will
be forced off)
109
107
Threshold voltage for buck over
voltage
VOVBUCKX
%
Output falling (high side FET will
be allowed to switch )
Measured after the later of
Buck1 or Buck3 power-up
successfully
tRP
minimum reset period
100
ms
PB_IN
0.33x
V3p3
Low, V3p3 = 3.2-3.4V
High, V3p3 = 3.2-3.4V
VPB
PB_IN, P_OFF , threshold
V
0.66x
V3p3
POFF Internal de-bounce time turn_on
and turn_off
TPB_DEGLITCH
20
ms
USB SWITCH
VINUSB
USB input voltage range
3
6
V
V
0.66x
V3p3
VIH_USB_EN
VIL_USB_EN
RDS_USB
USB_EN high level input voltage
V3p3 = 3.2-3.4 V, VUSB_EN rising
V3p3 = 3.2-3.4 V, VUSB_EN falling
0.33x
V3p3
USB_EN low level input voltage
V
mΩ
A
Static drain-source on-state
resistance
USB_VIN = 5 V and Io_USB =
0.5 A, TJ = 2 5°C
120
1.2
Increasing USB_Vo current
di/dt<1 A/s
ICS_USB
USB current limit
-20%
20%
0.4
Increasing USB_Vo current di/dt<
1A/s, VINUSB = 6 V
VINUSB = 5 V
Overcurrent detection factor
Ratio of ILIM_START/ICS_USB
KOVERCURRENT
1.5
VUSBx_nFAULT
TCS_USB
USBx_nFAULT output voltage low
USB over current fault deglitch
IUSB_ILIM = 3 mA
V
Fault assertion due to over
current protection
5
ms
TUSB_TRIP
TUSB_HYST
USB thermal trip point
Rising temperature
Falling temperature
130
20
°C
°C
USB thermal trip hysteresis
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
PARAMETER
THERMAL SHUTDOWN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TTRIP
Thermal shut down trip point
Thermal shut down hysteresis
Thermal shut down deglitch
Rising temperature
Device re-starts
160
20
°C
°C
µs
THYST
TTRIP_DEGLITCH
110
10
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SLVSB32 –SEPTEMBER 2011
TYPICAL CHARACTERISTICS
Load Regulation: Buck1 @ 1.2V, 1% Resistor Feedback
Load Regulation: Buck2 @ 1.8V, 1% Resistor Feedback
1.225
1.825
I_buck2 = 2 A,
I_buck3 = 2 A
I_buck2 = 1 A,
I_buck3 = 1 A
I_buck2 = 2 A,
I_buck3 = 2 A
I_buck1 = 1 A,
I_buck3 = 1 A
1.22
1.82
1.815
1.81
1.215
1.21
I_buck2 = 0.25 A,
I_buck3 = 0.25 A
I_buck1 = 0.25 A,
I_buck3 = 0.25 A
1.205
1.2
1.805
1.8
0
0.5
1
1.5
2
2.5
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
I_BUCK1 - A
I_BUCK2 - A
Figure 1.
Figure 2.
Buck1 Temp Variation @ 1.2V, 1%Resistor
-40°C to 75°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A
Load Regulation: Buck3 @ 3.3V, 1% Resistor Feedback
3.385
1.23
3.38
1.225
I_buck1 = 2 A,
I_buck2 = 2 A
I_buck1 = 1 A,
I_buck2 = 1 A
1.22
3.375
1.215
3.37
I_buck1 = 0.25 A,
I_buck2 = 0.25 A
3.365
1.21
-40
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-20
0
20
40
60
I_BUCK3 - A
Temperature - °C
Figure 3.
Figure 4.
Buck1 1.2V Efficiency, Forced PWM
Buck1 1.2V Efficiency, Forced PWM and PFM
L = 4.7µH, 20mΩ, fSW = 500KHz
L = 4.7µH, 20mΩ, fSW = 500KHz
3.9
3.8
3.7
3.6
3.5
3.4
3.3
90
80
buck2 = 0 A,
buck3 = 0 A
V = 12 V
I
V = 15 V
I
70
60
50
V = 4.5 V
I
buck2 = 2 A,
buck3 = 2 A
40
30
20
3.2
3.1
3
20
40
60
1
-40
-20
0
0
0.5
1.5
2
2.5
3
Temperature - °C
Current - A
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
Buck2 1.8V Efficiency, Forced PWM
Buck2 1.8V Efficiency, Forced PWM and PFM
L = 4.7µH, 20mΩ, fSW = 500KHz
L = 4.7µH, 20mΩ, fSW = 500KHz
90
80
90
80
PFM
V = 12 V
I
70
60
70
60
V = 15 V
I
PWM
V = 4.5 V
I
50
40
30
50
40
20
10
0
30
20
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
Current - A
Current - mA
Figure 7.
Figure 8.
Buck3 3.3V Efficiency, Forced PWM
Buck3 3.3V Efficiency, Forced PWM and PFM
L = 4.7µH, 20mΩ, fSW = 500KHz
L = 4.7µH, 20mΩ, fSW = 500KHz
90
80
90
80
V = 4.5 V
I
70
60
V = 15 V
I
PFM
70
60
V = 12 V
I
PWM
50
40
30
50
40
30
20
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
Current - A
Current - mA
Figure 9.
Figure 10.
Push-Button Operation Power-Up
Power-Up All Converters, No Load VIN = 12V (Green)
90
80
70
60
PFM
50
40
30
PWM
20
10
0
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
Current - mA
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
Push-bButton Operation Power-Down
Power-Up All Converters and PGOOD (Green), No Load
Figure 13.
Figure 14.
Ripple TA = 25°C Buck1 = 3A, Buck2 = 2A, Buck3 = 2A
Ripple TA = 70°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A
Figure 15.
Figure 16.
Ripple TA = 10°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A
Ripple TA = 40°C, Buck1 = 3A, Buck2 = 2A, Buck3 = 2A
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
Transient Response Buck1
Transient Response Buck2
1.2V, 1-3A Step, Co = 22µF,L = 4.7µH, fSW = 500KHz
1.8V, 1-2A Step, Co = 22µF,L = 4.7µH, fSW = 500KHz
Figure 19.
Figure 20.
Buck3 3.3V Efficiency Measured With
L = 4.7µH, 20mΩ, fSW = 500kHz
PFM Operation 1.2V, 1.8V, 3.3V
Figure 21.
Figure 22.
PFM/PWM Transition (Pin 25 Pulled High)
PWM/PFM Transition (Pin 25 Pulled Low)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
Buck1 Dynamic Transition from PFM to PWM
Buck2 Dynamic Transition from PFM to PWM
4.7µH, 68µF, 500 kHz
4.7µH, 44µF, 500 kHz
Figure 25.
Figure 26.
Buck3 Dynamic Transition from PFM to PWM
4.7µH, 22µF, 500 kHz
USB Switch Start-Up, No Load
Figure 27.
Figure 28.
USB Switch Start-Up, No Load
USB Current Limit Operation (3.3V)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
USB Current Limit Recovery (3.3V)
USB Current Limit Operation (5V)
Figure 31.
Figure 32.
Bucks Operation (Top 3 Traces) and USB Alarm Operation
USB Current Limit Recovery (5V)
Figure 33.
Figure 34.
TA = 25°, VIN = 12V, fSW = 500kHz
EVM Layout
B1 = 3A, B2 = 2A, B3 = 2A
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
TA = 25°, VIN = 5V, fSW = 500kHz
TA = 25°, VIN = 5V, fSW = 1000kHz
B1 = 3A, B2 = 2A, B3 = 2A
B1 = 3A, B2 = 2A, B3 = 2A
Figure 37.
Figure 38.
DETAILED DESCRIPTION
Adjustable Switching Frequency
To select the internal switching frequency, connect a resistor from ROSC to ground. Figure 39 shows the
required resistance for a given switching frequency.
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0.3
0.8
f
1.3
1.8
- Switching Frequency - MHz
s
Figure 39. ROSC vs Switching Frequency
-1.122
ROSC(kW) = 174 · fSW
(1)
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Output Inductor Selection
To calculate the value of the output inductor, use Equation 2.
Vin -Vout Vout
Lo =
×
Io× Kind Vin× fsw
(2)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
In general, KIND is normally from 0.1 to 0.3 for the majority of applications. A value of 0.1 will improve the
efficiency at light load, while a value of 0.3 will provide the lowest possible cost solution. The ripple current is:
Vin -Vout Vout
×
Iripple =
Lo
Vin× fsw
(3)
Output Capacitor
There are two primary considerations for selecting the value of the output capacitor. The output capacitors are
selected to meet load transient and output ripple’s requirements. If a minimum transient specification is required
use the following equation:
DIOUT 2 × Lo
Co >
Vout ×DVout
(4)
The following equation calculates the minimum output capacitance needed to meet the output voltage ripple
specification.
1
1
Co >
×
VRIPPLE
8× fsw
VRIPPLE
(5)
Where fSW is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and VRIPPLE is the
inductor ripple current.
Input Capacitor
A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND of
each converter. The input capacitor must handle the RMS ripple current shown in the following equation.
Vinmin-Vout
(
)
Vout
Icirms = Iout ×
×
Vinmin
Vinmin
(6)
Bootstrap Capacitor
The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pins to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.047 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage.
Push Button
The push button control is an optional feature. The user can power on and off the PMU without push button by
connecting the PB pin to GND. Alternatively, the user can power on and off the PMU by using a push button
on/off controller. When the 3.3V LDO’s output is more than 2.6V, the internal logic will detect the voltage at PB to
determine whether the PB pin is used. When the voltage at PB is zero, the PMU will be activated after detecting
PB staying low for at least 20ms. On the other hand, if the voltage at PB is high, the PMU will keep off until the
first solid push button signal. After a valid push button signal is asserted, the PMU will follow each dc/dc
converter’s EN and power up from a valid push button signal.
During power off, once the PB has been pressed, INT is switched low. This warns the system to shut down all
housekeeping tasks. During the off period, the PMU will keep off until a new PB signal is received. This “off”
state can be overridden by recycling the input power.
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Turn On Through Push Button
When the PB pin is not tied to GND, a high to low transition on PB initiates the power on sequence. PB must
stay low for a period of 20ms. Once completing this 20mS, the internal EN is asserted and the PMU is turned on.
PB
De-bouncing
20 mS
Internal
EN
Figure 40. Push Button Turn On
Turn Off Through Push Button
A high to low transition on PB initiates the power off sequence. PB must stay low for a period of 20ms. After
completing 20ms, the PMU pulls down the INT to alert the system that the PMU will be shut down within
1024ms. After 1024ms, the PMU will be disabled through an internal EN, which can override the individual EN of
each power converter. The PMU will keep off unless there is another from high to low transition on PB or the
input power is recycled.
De-bouncing
PB
20 mS
200 mS
1024 mS
INT
Internal
EN
Figure 41. Push Button Trun Off
Delayed Start-Up After pb_in
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1 MΩ pull-up to the 3V3 rail.
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VIN
V
V
V7
V3
PB_in
De-bouncing
20mS
De-bouncing
20 mS
200mS
1024 mS
INT
Internal EN
EN treshold
Enx rise time
dictated by C
EN
1
EN
2
EN
All bucks are disabled
3
EN
Enable discharge
10-12 mS
Pre-bias timing
4-5 mS
PG asserted
BUCK1
BUCK2
BUCK3
-biased output
Pre
Soft star rise time
dictated by C
SS
Soft start timer
ms watchdog
10
PGOOD
PG timer
100ms
Figure 42. Delayed Start-Up
Out-of-Phase Operation
In order to reduce input ripple current, buck 1 and buck 2 operate 180 degree out-of-phase. This enables the
system having less input ripple, then to lower component cost, save board space and reduce EMI.
Soft-Start Time
The device has an internal pull-up current source of 5 µA that charges an external soft-start capacitor to
implement a slow start time. Equation 7 shows how to select a soft-start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the soft-start charge current (Iss) is 5 µA. The soft-start
circuit requires 1 nF per around 167 µs to be connected at the SS pin. A 0.8-ms soft-start time is implemented for
all converters fitting 4.7 nF to the relevant SS pin.
Css(nF)
Iss(µA)
Tss(ms) = VREF(V) ·
(
)
(7)
The Power Good circuit for the bucks has a 10-ms watchdog. Therefore the soft-start time should be lower than
this value. It is recommended not to exceed 5 ms.
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Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with a value close to 40 kΩ
for the R1 resistor and use Equation 8 to calculate R2.
æ
ç
è
ö
÷
ø
0.8V
R2 = R1×
VO - 0.8V
(8)
Vo
FB
TPS65257
R1
R2
-
+
0.8V
Figure 43. Voltage Divider Circuit
Loop Compensation
TPS65257 is a current mode control DC/DC converter. The error amplifier is a transconductance amplifier with a
gM of 130 µA/V. A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60°
and 90°, or type III (Rc and Cc and Cff to improve the converter transient response. CRoll adds a high frequency
pole to attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there
is possibility of cross coupling in between rails when layout is very compact.
V
O
i
L
C
O
R
L
R
Gm = 12 A/V
ESR
C
R
ff
1
Current Sense
I/V Gain
FBx
g
=130m
M
R
V
= 0.8 V
COMPx
2
REF
R
C
C
Roll
C
C
Figure 44. Loop Compensation Scheme
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To calculate the external compensation components follow the following steps:
TYPE II CIRCUIT
TYPE III CIRCUIT
Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies around 500 kHz
yield best trade off between performance and cost. When
using smaller L and C, switching frequency can be
increased. To optimize efficiency, switching frequency can
be lowered.
Use type III circuit for switching
frequencies higher than 500 kHz.
Select cross over frequency (fc) to be at least 1/5 to 1/10 of
switching frequency (fs).
Suggested
fc = fs/10
Suggested
fc = fs/10
2p × fc×Vo×Co
gM ×Vref × gmps
2p × fc×Vo×Co
RC =
gM ×Vref × gmps
RC =
Set and calculate Rc.
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
RL ×Co
RL ×Co
Cc =
Cc =
1
fp =
Rc
Rc
CO × RL ×2p
Add CRoll if needed to remove large signal coupling to high
impedance CMP node. Make sure that
Re sr ×Co
Re sr ×Co
1
CRoll
=
CRoll
=
fpRoll
=
RC
RC
2×p × RC ×CRoll
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
that the zero frequency (fzff) is smaller than equivalent
soft-start frequency (1/Tss).
1
Cff =
NA
2×p × fzff × R
1
Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control.
Power Good
The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled up when both buck converters’ outputs are more than
90% of its nominal output voltage.
The default reset time is 100 ms. The polarity of the PGOOD is active high.
Current Limit Protection
The TPS65257 current limit trip is set by the following formulae:
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TYPE II CIRCUIT
4.5
4.3
4
3.8
3.5
3.3
3
2.8
2.5
2.3
2
267
I
I
I
LIM1(A) =
LIM 2 (A) =
LIM 3(A) =
+1.77
+1.72
+ 0.97
RLIM1(kW)
(9)
(10)
(11)
1.8
1.5
1.3
1
100 175 250 325 400 475 550 625 700 775 850 925 1000
RLIM1 - kW
4.5
4.3
4
3.8
3.5
3.3
3
2.8
2.5
2.3
2
256
RLIM1(kW)
1.8
1.5
1.3
1
100 175 250 325 400 475 550 625 700 775 850 925 1000
RLIM2 - kW
3.5
3.3
3
2.8
2.5
2.3
2
253
1.8
1.5
1.3
1
RLIM 2(kW)
0.8
0.5
100 175 250 325 400 475 550 625 700 775 850 925 1000
RLIM3 - kW
All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the
converters, they will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has
been removed, the converter will ramp up and operate normally. If this is not the case the converter will see
another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.
If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start
and no global hiccup mode will occur.
Overvoltage Transient Protection
The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The
OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the FB voltage drops lower than the OVTP threshold which is 107%, the high side MOSFET is
allowed to turn on the next clock cycle.
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Low Power/Pulse Skipping Operation
When a buck synchronous converter operates at light load or standby conditions, the switching losses are the
dominant source of power losses. Under these load conditions, TPS65257 uses a pulse skipping modulation
technique to reduce the switching losses by keeping the power transistors in the off-state for several switching
cycles, while maintaining a regulated output voltage. Figure 45 shows the output voltage and load plus the
inductor current.
V
OUT
I
L
Skipping
Burst
I
OUT
Figure 45. Low Power/Pulse Skipping
During the burst mode, the converter continuously charges up the output capacitor until the output voltage
reaches a certain limit threshold. The operation of the converter in this interval is equivalent to the peak inductor
current mode control. In each switch period, the main switch is turned on until the inductor current reaches the
peak current limit threshold. As the load increases the number of pulses increases to make sure that the output
voltage stays within regulation limits. When the load is very light the low power controller has a zero crossing
detector to allow the low side mosfet to operate even in light load conditions. The transistor is not disabled at
light loads. A zero crossing detection circuit will disable it when inductor current reverses. During the whole
process the body diode does not conduct but is used as blocking diode only.
During the skipping interval, the upper and lower transistors are turned off and the converter stays in idle mode.
The output capacitors are discharged by the load current until the moment when the output voltage drops to a
low threshold.
The choice of output filter will influence the performance of the low power circuit. The maximum ripple during low
power mode can be calculated as:
KRIPTS
=
VOUT _ RIPPLE
COUT
(12)
(13)
Where KRIP is 1.4 for Buck1 and 0.7 for Buck2 and Buck3. TS can be calculated as:
0.35
TS =
é
ù
ú
V
-VOUT
V
OUT
æ
ö
IN
ê
ç
÷
L
VIN û
è
ø
ë
USB Switch
The USB switch is enabled (active high) with the USB_EN pin. The switch has a typical resistance of 100mΩ and
has a fold-back current limit that is typically 25% lower than the overcurrent detection point. If a continuous
short-circuit condition is applied to the USB switch output, the USB switch will shut-down once its temperature
reaches 130°C, allowing for the buck converters to operate unaffected. Once the USB switch cools down it will
restart automatically.
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USB_Vin
0
USB_EN
USB_Vo
OVERCURRENT DETECTED
USB_LOAD
ICS_USB
OVERCURRENT IS CLEARED
USB_I
Overcurrent at the out.put Alarm
is asserted after 5 ms
Normal operation is restor.ed
Alarm is cleare.d
Normal operation
USB_nFAULT
TCS_USB
Figure 46. USB Switch
Power Dissipation
The total power dissipation inside TPS65257 should not to exceed the maximum allowable junction temperature
of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (RJA)
and ambient temperature. To calculate the temperature inside the device under continuous loading use the
following procedure:
1. Define the set voltage for each converter.
2. Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading..
3. Determine from the graphs below the expected losses in watts per converter inside the device. The losses
depend on the input supply, the selected switching frequency, the output voltage and the converter chosen.
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1.6
1.4
1.6
1.4
1.2
1.2
1
1
0.8
0.6
0.8
0.6
0.4
0.2
0.4
0.2
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6
Current - A
Current - A
Buck1 Vin = 12 V, fsw = 500 kHz,
Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
Buck1 Vin = 12 V, fsw = 1.1 MHz,
Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
1.7
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.6
1.5
1.4
1.3
1.2
1.1
1
1
0.9
0.9
0.8
0.8
0.7
0.6
0.7
0.6
0.5
0.4
0.3
0.2
0.5
0.4
0.3
0.2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
1
1.2
1.4
1.6
1.8
Current - A
Buck2&3 Vin = 12 V, fsw = 500 kHz,
Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
2
2.2
2.4
2.6
2.8
3
Current - A
Buck2&3 Vin = 12 V, fsw = 1.1 MHz,
Vo (from top to bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
Figure 47. Power Dissipation Curves
4. To calculate the maximum temperature inside the IC use the following formula:
THOT_SPOT = TA + PDIS x ѲJA
(14)
Where:
TA is the ambient temperature
PDIS is the sum of losses in all converters
ѲJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
3.3-V and 6.5 LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
•
•
4.7 µF to 10 µF for V7V pin 28
3.3 µF or larger for V3V pin 29
26
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TPS65257
TPS65257
www.ti.com
SLVSB32 –SEPTEMBER 2011
Layout Recommendation
Layout is a critical portion of PMIC designs.
•
•
Place tracing for output voltage and LX on the top layer and an inner power plane for VIN.
Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
ground.
•
The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter capacitor and directly under the TPS65257 device to provide a thermal path from
the PowerPad land to ground.
•
•
For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
•
•
The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
The compensation should be as close as possible to the CMPx pins. The CMPx and ROSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): TPS65257
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS65257RHAR
TPS65257RHAT
ACTIVE
ACTIVE
VQFN
VQFN
RHA
RHA
40
40
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65257RHAR
TPS65257RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65257RHAR
TPS65257RHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
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