TPS65182RGZR [TI]
PMIC FOR E Ink Vizplex ENABLED ELECTRONIC PAPER DISPLAY; PMIC，用于E Ink公司的Vizplex启用电子纸显示屏
| 型号： | TPS65182RGZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PMIC FOR E Ink Vizplex ENABLED ELECTRONIC PAPER DISPLAY |
| 文件： | 总24页 (文件大小：844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65182, TPS65182B
www.ti.com
SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
PMIC FOR E Ink® Vizplex™ ENABLED ELECTRONIC PAPER DISPLAY
Check for Samples: TPS65182, TPS65182B
1
FEATURES
•
•
Thermistor Monitoring
2345
•
Single Chip Power Management Solution for
–
–10°C to 85°C Temperature Range
E Ink® Vizplex™ Electronic Paper Displays
–
±1°C Accuracy from 0°C to 50°C
I2C Serial Interface
Slave Address 0x48h (1001000)
•
Generates Positive and Negative Gate and
Source Driver Voltages and Back-Plane Bias
from a Single, Low-Voltage Input Supply
–
•
•
•
Flexible Power-Up Sequencing
Sleep Mode Support
•
•
•
3-V to 6-V Input Voltage Range
Boost Converter for Positive Rail Base
Thermally Enhanced Package for Efficient
Heat Management
(48-Pin 7 mm x 7 mm x 0.9 mm QFN)
Inverting Buck-Boost Converter for Negative
Rail Base
•
Two Adjustable LDOs for Source Driver
Supply
APPLICATIONS
•
Power Supply for Active Matrix E Ink®
Vizplex™ Panels
–
–
LDO1: 15 V, 120 mA (VPOS)
LDO2: –15 V, 120 mA (VNEG)
•
•
•
E-Book Readers
•
•
Accurate Output Voltage Tracking
VPOS - VNEG = ±50 mV
Two Charge Pumps for Gate Driver Supply
EPSON® S1D13522 (ISIS) Timing Controller
–
EPSON® S1D13521 (Broadsheet) Timing
Controller
Application Processors With Integrated or
Software Timing Controller ( OMAP™)
–
–
CP1: 22 V, 10 mA (VDDH)
CP2: –20 V, 12 mA, (VEE)
•
•
Adjustable VCOM Driver for Accurate
Panel-Backplane Biasing
–
–
–
–0.3 V to –2.5 V
Adjustable Through External Potentiometer
15-mA Max Integrated Switch
DESCRIPTION
The TPS65182/TPS65182B device is a single-chip power supplies designed to for E Ink® Vizplex™ displays
used in portable e-reader applications and support panel sizes up to 9.7 inches. Two high efficiency DC/DC
boost converters generate ±17-V rails which are boosted to 22 V and –20 V by two change pumps to provide the
gate driver supply for the Vizplex™ panel. Two tracking LDOs create the ±15-V source driver supplies which
support up to 120-mA of output current. All rails are adjustable through the I2C interface to accommodate specific
panel requirements.
Accurate back-plane biasing is provided by a linear amplifier and can be adjusted either by an external resistor or
the I2C interface. The VCOM driver can source or sink current depending on panel condition.
The TPS65182/TPS65182B provides precise temperature measurement function to monitor the panel
temperature during operation. The temperature reading is updated every 60 s and can be accessed through the
I2C interface.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
5
OMAP is a trademark of Texas Instruments.
Vizplex is a trademark of E Ink Corporation.
E Ink is a registered trademark of E Ink Corporation.
EPSON is a registered trademark of Seiko Epson Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS65182, TPS65182B
SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
10uF
10uF
2.2uH
VIN_P
From Input Supply
(3.0V-6.0V)
VB_SW
From Input Supply
(3.0V-6.0V)
4.7uH
VN_SW
4.7uF
DCDC1
DCDC2
PGND3
VB
VN
10uF
PBKG
4.7uF
4.7uF
VDDH_IN
VDDH_D
VEE_IN
VEE_D
Gate driver Supply
(22V, 10mA)
Gate driver Supply
(-20V, 12mA)
POSITIVE
CHARGE
PUMP
NEGATIVE
CHARGE
PUMP
VDDH_DRV
VDDH_FB
VEE_DRV
VEE_FB
1M
1M
4.7uF
10nF
10nF
4.7uF
47.5k
53.6k
PGND2
VPOS_IN
VPOS
4.7uF
VNEG_IN
4.7uF
VNEG
4.7uF
Source Driver Supply
(15V, 120mA)
Source Driver Supply
(-15V, 120mA)
4.7uF
LDO1
LDO2
INT_LDO1
INT_LDO2
VREF
10k NTC
43k
TS
INT_LDO1
INT_LDO2
VREF
TEMP
SENSOR
4.7uF
ADC
4.7uF
4.7uF
10uF
VIN
From Input Supply
(3.0V-6.0V)
VCOM
VCOM_XADJ
VCOM_PWR
4.7uF
AGND1
AGND2
DGND
VNEG
4.7uF
4.7uF
GATE DRIVER
VCOM_PANEL
VCOM_CTRL
To panel back -plane
(-0.3 to -2.5V, 15mA)
From uC or DSP
10k
VIO
PWR[3]
PWR[2]
PWR[1]
PWR[0]
WAKEUP
PWR_GOOD
From uC or DSP
From uC or DSP
From uC or DSP
From uC or DSP
From uC or DSP
To uC or DSP
DIGITAL
CORE
10k
VIO
SDA
SCL
From uC or DSP
I2C
From/to uC or DSP
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS65182
TPS65182RGZR
-10°C to 85°C
RGZ
TPS65182BRGZR
TPS65182B
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
SELECTION GUIDE
DEVICE
TPS6518
TPS6518B
PART NUMBER
TPS65182RGZR
TPS65182BRGZR
STATUS
Not recommended for new designs
Active
2
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
DEVICE INFORMATION
RGZ PACKAGE
(TOP VIEW)
24 - PWR_GOOD
23 - PBKG
VDDH_IN - 37
N/C - 38
22 - PWR0
N/C - 39
21 - PWR1
VB_SW - 40
PGND3 - 41
VB - 42
20 - PWR2
19 - PWR3
18 - SDA
VPOS_IN - 43
VPOS - 44
17 - SCL
16 - VCOM_PWR
15 - VCOM
14 - VCOM_PANEL
13 - N/C
- 45
- 46
N/C
N/C
TS - 47
AGND2 - 48
TERMINAL FUNCTIONS(1)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
1
VREF
N/C
O
Filter pin for 2.25-V internal reference to ADC
Not connected
2
VNEG
3
O
I
Negative supply output pin for panel source drivers
Input pin for LDO2 (VNEG)
VNEG_IN
WAKEUP
DGND
4
5
I
Wake up pin (active high). Pull this pin high to wake up from sleep mode.
Digital ground
6
INT_LDO2
AGND1
INT_LDO1
VIN
7
O
Internal supply (digital circuitry) filter pin
Analog ground for general analog circuitry
Internal supply (analog circuitry) filter pin
Input power supply to general circuitry
8
9
O
I
10
Analog input for conventional VCOM setup method. Tie this pin to ground if VCOM is set
through I2C interface.
VCOM_XADJ
11
I
I
VCOM_CTRL
N/C
12
13
VCOM_PANEL gate driver enable (active high)
Not connected
(1) There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively.
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Product Folder Link(s): TPS65182 TPS65182B
TPS65182, TPS65182B
SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
www.ti.com
TERMINAL
I/O
DESCRIPTION
NAME
VCOM_PANEL
VCOM
NO.
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
O
O
I
Panel common-voltage output pin
Filter pin for panel common-voltage driver
Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.
Serial interface (I2C) clock input
VCOM_PWR
SCL
I
SDA
I/O
I
Serial interface (I2C) data input/output
Enable pin for CP1 (VDDH) (active high)
Enable pin for LDO1 (VPOS) (active high)
Enable pin for CP2 (VEE) (active high)
Enable pin for LDO2 (VNEG) and VCOM (active high)
Open drain power good output pin (active low)
Inverting buck-boost converter switch out (DCDC2)
Not connected
PWR3
PWR2
I
PWR1
I
PWR0
I
PWR_GOOD
VN_SW
N/C
O
O
VIN_P
I
I
Input power supply to inverting buck-boost converter (DCDC2)
Feedback pin for inverting buck-boost converter (DCDC2)
Input supply pin for CP1 (VEE)
VN
VEE_IN
VEE_DRV
VEE_D
VEE_FB
PGND2
VDDH_FB
VDDH_D
VDDH_DRV
VDDH_IN
N/C
I
O
O
I
Driver output pin for negative charge pump (CP2)
Base voltage output pin for negative charge pump (CP2)
Feedback pin for negative charge pump (CP2)
Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps
Feedback pin for positive charge pump (CP1)
Base voltage output pin for positive charge pump (CP1)
Driver output pin for positive charge pump (CP1)
Input supply pin for positive charge pump (CP1)
Not connected
I
O
O
I
N/C
Not connected
VB_SW
PGND3
VB
O
Boost converter switch out (DCDC1)
Power ground for DCDC1
I
I
Feedback pin for boost converter (DCDC1)
Input pin for LDO1 (VPOS)
VPOS_IN
VPOS
O
Positive supply output pin for panel source drivers
Not connected
N/C
N/C
Not connected
Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor
between this pin and AGND2.
TS
47
48
23
I
AGND2
Reference point to external thermistor and linearization resistor
Die substrate/thermal pad. Connect to VN with short, wide trace. Wide copper trace will
improve heat dissipation. PowerPad must not be connected to ground.
PowerPad (PBKG)
4
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Product Folder Link(s): TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)(2)
VALUE
–0.3 to 7
–0.3 to 0.3
UNIT
V
Input voltage range at VIN, VINP
Ground pins to system ground
V
Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0, VCOM_CTRL,
VDDH_FB, VEE_FB, PWR_GOOD
–0.3 to 3.6
V
VCOM_XADJ
–3.6 to 0.3
–0.3 to 20
–20 to 0.3
–0.3 to 30
Internally limited
2
V
V
Voltage on VB, VB_SW, VPOS_IN, VDDH_IN
Voltage on VN, VNEG_IN, VEE_IN, VCOM_PWR
Voltage from VINP to VN_SW
Peak output current
V
V
mA
W
Continuous total power dissipation
Junction-to-ambient thermal resistance(3)
Operating junction temperature
Operating ambient temperature(4)
Storage temperature
qJA
TJ
23
°C/W
°C
°C
°C
-10 to 125
-10 to 85
-65 to 150
±2000
TA
Tstg
(HBM) Human body model
ESD rating
V
(CDM) Charged device model
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and
2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.
(4) It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad
is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the
buck-boost output will help heat dissipated efficiently.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage range at VIN, VINP
3
3.7
6
V
Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0,
VCOM_CTRL, VDDH_FB, VEE_FB, VCOM_XADJ, PWR_GOOD
0
3.6
V
TA
TJ
Operating ambient temperature range
Operating junction temperature range
–10
–10
85
°C
°C
125
RECOMMENDED EXTERNAL COMPONENTS
PART NUMBER
INDUCTORS
VALUE
SIZE
MANUFACTURER
LQH44PN4R7MP0
VLS252012T-2R2M1R3
CAPACITORS
4.7 µH
2.2 µH
4 mm x 4 mm x 1.65 mm
2 mm x 2.5 mm x 1.2 mm
Murata
TDK
GRM21BC81E475KA12L
GRM32ER71H475KA88L
All other caps
4.7 µF, 25 V, X6S
4.7 µF, 50 V, X7R
X5R or better
805
Murata
Murata
1210
DIODES
BAS3010
SOD-323
SOD-123
Infineon
MBR130T1
ON-Semi
THERMISTOR
NCP18XH103F03RB
10 KΩ
603
Murata
Copyright © 2010, Texas Instruments Incorporated
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TPS65182, TPS65182B
SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
www.ti.com
MAX UNIT
ELECTRICAL CHARACTERISTICS
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
INPUT VOLTAGE
VIN
Input voltage range
3
3.7
2.9
6
10
6
V
V
VUVLO
VHYS
Undervoltage lockout threshold
Undervoltage lockout hysteresis
VIN falling
VIN rising
400
mV
INPUT CURRENT
IQ
Operating quiescent current into VIN
Device switching, no load
Device in standby mode
Device in sleep mode
5.5
130
2.8
mA
µA
µA
ISTD
ISLEEP
Operating quiescent current into VIN
Shutdown current
INTERNAL SUPPLIES
VINT_LDO1 Internal supply
VINT_LDO2 Internal supply
2.7
2.7
V
V
V
VREF
Internal supply
2.25
DCDC1 (POSITIVE BOOST REGULATOR)
VIN
Input voltage range
Output voltage range
DC set tolerance
Output current
3
3.7
17
V
V
VOUT
-5
5
%
IOUT
160
mA
mΩ
A
RDS(ON)
MOSFET on resistance
Switch current limit
Switch current accuracy
Switching frequency
Inductor
VIN = 3.7 V
350
1.5
ILIMIT
-30
30
%
fSW
L
1
2.2
MHz
µH
µF
mΩ
C
Capacitor
2x4.7
20
ESR
Capacitor ESR
DCDC2 (INVERTING BUCK-BOOST REGULATOR)
VIN
Input voltage range
Output voltage range
DC set tolerance
Output current
3
3.7
-17
6
V
V
VOUT
-5
5
%
IOUT
160
mA
mΩ
A
RDS(ON)
MOSFET on resistance
Switch current limit
Switch current accuracy
Inductor
VIN = 3.7 V
350
1.5
ILIMIT
-30
30
%
L
4.7
2x4.7
20
µH
µF
mΩ
C
Capacitor
ESR
Capacitor ESR
LDO1 (VPOS)
VPOS_IN Input voltage range
VSET Output voltage set value
16.15
14.25
17
15
17.85
15.75
V
V
VIN = 17 V
VIN = 17 V
VINTERVAL Output voltage set resolution
VPOS_OUT Output voltage range
250
15
mV
V
VSET = 15 V, ILOAD = 20 mA
VSET = 15 V, ILOAD = 20 mA
ILOAD = 120 mA
14.85
-1
15.15
1
VOUTTOL
Output tolerance
%
VDROPOUT Dropout voltage
250
1
mV
%
VLOADREG Load regulation – DC
ILOAD = 10% to 90%
ILOAD
ILIMIT
TSS
Load current range
Output current limit
Soft start time
120
1
mA
mA
ms
200
6
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Product Folder Link(s): TPS65182 TPS65182B
TPS65182, TPS65182B
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SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
C
Recommended output capacitor
4.7
µF
LDO2 (VNEG)
VNEG_IN Input voltage range
VSET Output voltage set value
-17.85
-15.75
-17
-15
250
-15
-16.15
-14.25
V
V
VIN = –17 V
VIN = –17 V
VINTERVAL Output voltage set resolution
VNEG_OUT Output voltage range
mV
V
VSET = –15 V, ILOAD = –20 mA
VSET = –15 V, ILOAD = –20 mA
ILOAD = 120 mA
-15.15
-1
-14.85
VOUTTOL
Output tolerance
1
250
1
%
VDROPOUT Dropout voltage
mV
%
VLOADREG Load regulation – DC
ILOAD = 10% to 90%
ILOAD
ILIMIT
TSS
C
Load current range
120
mA
mA
ms
µF
Output current limit
200
Soft start time
1
Recommended output capacitor
4.7
LD01 (POS) AND LDO2 (VNEG) TRACKING
VDIFF Difference between VPOS and VNEG
VCOM DRIVER
VSET = ±15 V,
ILOAD = ±20 mA, 0°C to 60°C
-50
50
mV
VCOM
G
Output voltage range
VCOM gain (VCOM_XADJ/VCOM
-2.5
-0.3
V
)
VCOM_ADJ = 0 V
1
V/V
VCOM SWITCH
VCOM = –1.25 V, VCOM_PANEL = 0 V
CVCOM = 4.7 µF, CVCOM_PANEL = 4.7 µF
TON
Switch ON time
1
ms
RDS(ON)
ILIMIT
MOSFET ON resistance
MOSFET current limit
VCOM = –1.25 V, ICOM = 30 mA
Not tested in production
20
35
Ω
200
mA
VCOM = 0 V,
VCOM_PANEL = –2.5 V
ISWLEAK
Switch leakage current
8.3
nA
CP1 (VDDH) CHARGE PUMP
VDDH_IN
Input voltage range
Feedback voltage
Accuracy
16.15
17
1
17.85
V
V
VFB
-3
3
23
10
%
VDDH_OUT Output voltage range
VSET = 22 V, ILOAD = 2 mA
21
22
V
ILOAD
fSW
CD
Load current range
Switching frequency
mA
KHz
nF
µF
560
10
Recommended driver capacitor
Recommended output capacitor
CO
4.7
CP2 (VEE) NEGATIVE CHARGE PUMP
VEE_IN
Input voltage range
Feedback voltage
-17.75
-17
-1
-16.15
V
V
VFB
Accuracy
-3
3
-19
12
%
VEE_OUT
ILOAD
fSW
Output voltage range
Load current range
VSET = –20 V, ILOAD = 3 mA
-21
-20
V
mA
KHz
nF
µF
Switching frequency
Recommended driver capacitor
Recommended output capacitor
560
10
CD
CO
4.7
Copyright © 2010, Texas Instruments Incorporated
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TPS65182, TPS65182B
SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
www.ti.com
MAX UNIT
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
THERMISTOR MONITOR(1)
ATMS Temperature to voltage ratio
TEST CONDITIONS
MIN
TYP
Not tested in production
Temperature = 0°C
-0.0158
1.575
0.768
0.845
2.25
V/°C
V
OffsetTMS Offset
VTMS_HOT Temp hot trip voltage (T = 50°C)
VTMS_COOL Temp hot escape voltage (T = 45°C)
VTMS_MAX Maximum input level
TEMP_HOT_SET = 0x8C
TEMP_COOL_SET = 0x82
V
V
V
RNTC_PU
RLINEAR
ADCRES
ADCDEL
Internal pull up resistor
External linearization resistor
ADC resolution
7.307
43
KΩ
KΩ
mV
µs
Not tested in production, 1 bit
Not tested in production
Not tested in production
16.1
ADC conversion time
19
TMSTTOL Accuracy
-1
1
LSB
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, PWR_GOOD, PWRx, WAKEUP)
IO = 3 mA, sink current
(SDA, PWR_GOOD)
VOL
Output low threshold level
0.4
0.4
V
VIL
Input low threshold level
Input high threshold level
Input bias current
V
V
VIH
1.2
I(bias)
VIO = 1.8 V
1
µA
ms
tlow,WAKEUP WAKEUP low time
fSCL SCL clock frequency
OSCILLATOR
fOSC Oscillator frequency
Frequency accuracy
THERMAL SHUTDOWN
TSHTDWN Thermal trip point
Thermal hysteresis
minimum low time for WAKEUP pin
150
400 KHz
9
MHz
TA = –40°C to 85°C
-10
10
%
150
20
°C
°C
(1) 10-KΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 KΩ, 1%) are used at TS pin for panel
temperature measurement.
8
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SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
MODES OF OPERATION
The TPS65182/TPS65182B has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the
lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the
device is ready to accept commands through PWR[3:0] pins and/or I2C interface. In ACTIVE mode one or more
power rails are enabled.
SLEEP
This is the lowest power mode of operation. All internal circuitry is turned off and the device
does not respond to I2C communications. TPS65182/TPS65182B enters SLEEP mode
whenever WAKEUP pin is pulled low.
STANDBY
In STANDBY all internal support circuitry is powered up and the device is ready to accept
commands either through GPIO or I2C control but none of the power rails are enabled. To
enter STANDBY mode the WAKEUP pin must be pulled high and all PWRx pins must be
pulled low. The device also enters STANDBY mode if input under voltage lock out (UVLO),
positive boost under voltage (VB_UV), or inverting buck-boost under voltage (VN_UV) is
detected, or thermal shutdown occurs.
ACTIVE
The device is in ACTIVE mode when any of the output rails are enabled and no fault
condition is present. This is the normal mode of operation while the device is powered up. In
ACTIVE mode, a falling edge on any PWRx pin shuts down and a rising edge powers up the
corresponding rail.
MODE TRANSISITONS
SLEEP → ACTIVE
WAKEUP pin is pulled high (rising edge) with any PWRx pin high. Rails come up in a
pre-defined power-up sequence.
SLEEP → STANDBY
WAKEUP pin is pulled high (rising edge) with all PWRx pins low. Rails will remain down until
one or more PWRx pin is pulled high.
ACTIVE → SLEEP
WAKEUP pin is pulled low (falling edge). Rails are shut down following the pre-defined
power-down sequence.
ACTIVE → STANDBY
WAKEUP pin is high. All PWRx pins are pulled low (falling edge). Rails shut down in the
order in which PWRx pins are pulled low. In the event of thermal shut down (TSD), under
voltage lock out (UVLO), positive boost or inverting buck-boost under voltage (UV), the
device shuts down all rails in a pre-defined power-down sequence.
STANDBY → ACTIVE
WAKEUP pin is high and any PWRx pin is pulled high (rising edge). Rails come up in the
same order as PWRx pins are pulled high.
STANDBY → SLEEP
WAKEUP pin is pulled low (falling edge) while none of the output rails are enabled.
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POWER DOWN
Battery removed
All rails
I2 C
= OFF
= NO
SLEEP
WAKEUP
All PWRx pins
( ) &
WAKEUP
(¯ )
=
low
All rails
I2 C
= OFF
= YES
STANDBY
WAKEUP
all PWRx pins
= high
= ( ¯ )
FAULT
&
||
(**)
WAKEUP
any PWRx pin
= high
&
(**)
( )(**)
)
)
Rails
I2 C
= ON
= YES
ACTIVE
NOTES
||, &
( ), ( ¯ )
:
= logic OR , logic AND .
= rising edge , falling edge
.
FAULT
(*)
= UVLO || TSD ( thermal shutdown
= Device follows default power
= Power sequencing is GPIO controlled
)|| BOOST UV
-up /down sequence
.
.
.
(**)
Figure 1. Global State Diagram
WAKE-UP AND POWER UP SEQUENCING
The TPS65182/TPS65182B supports a default power-up sequence supporting E Ink® Vizplex™ displays. It also
offers full user control of the power-up sequence through GPIO control using the PWR3, 2, 1, 0 pins. Using GPIO
control, the output rails are enabled/disabled in the order in which the PWRx pins are asserted/de-asserted,
respectively, and the power-up timing is controlled by the host only. Rails are in regulation 2 ms after their
respective PWRx pin has been asserted with the exception of the first rail, which takes 6 ms to power up. The
additional time is needed to power up the positive and inverting buck-boost regulator which need to be turned on
before any other rail can be enabled. Once all rails are enabled and in regulation the PWR_GOOD pin is
released (pin status = HiZ and power good line is pulled high by external pull-up resistor). The PWRx pins are
assigned to the rails as follows:
•
•
•
•
PWR0: LDO2 (VNEG) and VCOM
PWR1: CP2 (VEE)
PWR3: LDO2 (VPOS)
PWR4: CP1 (VDDH)
Rails are powered down whenever the host de-asserts the respective PWRx pin, and once all rails are disabled
the device enters STANDBY mode. The next step is then to de-assert the WAKEUP pin to enter SLEEP mode
which is the lowest-power mode of operation.
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It is possible for the host to force the TPS65182/TPS65182B directly into SLEEP mode from ACTIVE mode by
de-asserting the WAKEUP pin in which case the device follows the pre-defined power-down sequence before
entering SLEEP mode.
DEPENDENCIES BETWEEN RAILS
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and
several dependencies exist that affect the power-up sequencing. These dependencies are listed below.
1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.
Internally, DCDC1 enable is gated by DCDC2 power good.
2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable
is gated DCDC1 power-good.
3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is
gated by DCDC1 power good.
4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally
CP2 enable is gated by DCDC1 power good.
5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally
CP1 enable is gated by DCDC1 power good.
6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power
good.
7. The minimum delay time between any two PWRx pins must be > 62.5 µs in order to follow the power up
sequence defined by GPIO control. If any two PWRx pins are pulled up together (< 62.5 µs apart) rails will
be staggered in a manner that a subsequent rail’s enable is gated by PG of a preceding rail. In this case, the
default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and CP1(VDDH). If any two PWRx
pins are pulled low then all rails will go down at the same time.
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VIN
D0
PWR0
1.8ms(1)
D1
PWR1
D2
PWR2
PWR3
D3
SLEEP
WAKEUP
STANDBY
ACTIVE
ACTIVE
VN
VB
VNEG
DLY1
VCOM
6ms(2,5)
DLY0 + 4ms(2)
DLY2
VEE
1ms(5)
DLY1
DLY3
VPOS
VDDH
2ms(5)
DLY2
DLY0
1ms(5)
DLY3
PWR_GOOD
300us (max)
11.8ms (min)
(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .
(2) It takes 2ms minimum for each internal boost regulator to start up before VNEG can be enabled
.
(5) It takes up to 2ms for LDOs (VPOS,VNEG) and 1ms for charge pumps (VDDH,VEE), to reach their steady state after being enabled.
DLY0-DLY3 are power up/down delays are factory-set to 2ms.
Figure 2. Power-Up and Power-Down Timing Diagram
SOFTSTART
Softstart for DCDC1, DCDC2, LDO1, and LDO2 is accomplished by lowering the current limits during start-up. If
DCDC1 or DCDC2 are unable to reach power-good status within 10 ms, the device enters STANDBY mode.
VCOM ADJUSTMENT
VCOM can be adjusted by an external potentiometer by connecting a potentiometer to the VCOM_XADJ pin. The
potentiometer must be connected between ground and a negative supply. The gain from VCOM_XADJ to VCOM
is 1 and therefore the voltage applied to VCOM_XADJ pin should range from -0.3 to -2.5V.
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VPOS / VNEG SUPPLY TRACKING
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV.
FAULT HANDLING AND RECOVERY
The TPS65182/TPS65182B monitors input and output voltages and die temperature and will take action if
operating conditions are outside normal limits. Whenever the TPS65182/TPS65182B encounters:
•
•
•
•
Thermal Shutdown (TSD)
Positive Boost Under Voltage (VB_UV)
Inverting Buck-Boost Under Voltage (VN_UV)
Input Under Voltage Lock Out (UVLO)
it will shut down all power rails and enter STANDBY mode. Shut down follows the pre-defined power-down
sequence and once a fault is detected, the PWR_GOOD pin is pulled low.
Whenver the TPS65182/TPS65182B encounters under voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE
(VEE_UV) or VDDH (VDDH_UV) it will shut down the corresponding rail (plus any dependent rail) only and
remain in ACTIVE mode, allowing the DCDC converters to remain up. Again, the PWR_GOOD pin will be pulled
low.
As the PWRx inputs are edge sensitive, the host must toggle the PWRx pins to re-enable the rails through GPIO
control, i.e. it must bring the PWRx pins low before asserting them again.
POWER GOOD PIN
The power good pin (PWR_GOOD) is an open drain output that is pulled high when all four power rails (CP1,
CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains
low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released
to HiZ state (pulled up by external resistor).
PANEL TEMPERATURE MONITORING
The TPS65182/TPS65182B provides circuitry to bias and measure an external negative temperature coefficient
resistor (NTC) to monitor device temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C
to 50°C. Temperature reading is automatically updated every 60 s.
NTC BIAS CIRCUIT
Figure 3 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-KΩ bias resistor. A 43-KΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-KΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.
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Table 1. ADC Output Value vs Termperature
TEMPERATURE
TMST_VALUE[7:0]
1111 0110
1111 0110
1111 0111
...
< -10°C
-10°C
-9°C
...
-2°C
-1°C
0°C
1111 1110
1111 1111
0000 0000
0000 0001
0000 0010
...
1°C
2°C
...
25°C
...
0001 1001
85°C
> 85°C
0101 0101
0101 0101
2.25V
7.307kW
10
Digital
10 bit ADC
43kW
10 kW NTC
TPS6518x
Figure 3. NTC Bias and Measurement Circuit
I2C BUS OPERATION
The TPS65182/TPS65182B supports a special I2C mode making it compatible with the EPSON® Broadsheet
S1D13521 timing controller. Standard I2C protocol requires the following steps to read data from a register:
1. Send device slave address, R/nW bit set low (write command)
2. Send register address
3. Send device slave address, R/nW set high (read command)
4. The slave will respond with data from the specified register address.end device slave address, R/nW set high
(read command).
The EPSON® Broadsheet S1D13521 controller does not support I2C writes nor I2C reads from addressed
registers, therefore the TPS65182/TPS65182B I2C interface has been modified and the reading the temperature
data is reduced to two steps:
1. Send device address, R/nW set high (read command)
2. Read the data from the slave. The slave will respond with data from TMST_VALUE register address.
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S
SLAVE ADDRESS
R
A
DATA 0
A P
From master to slave
From slave to master
R
A
Read
Acknowlege
S Start
P Stop
Figure 4. Subaddress in I2C Transmission
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open Drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 5. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Map section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. Reference Figure 5.
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
START
ADDRESS R/W ACK
DATA
ACK
DATA
STOP
ACK/
nACK
Figure 5. I2C Start/Stop/Acknowledge Protocol
SDA
SCL
tSU;DAT
tf
tLOW
tr
tHD;STA
tSP
tr
tBUF
tHD;STA
tSU;STA
tSU;STO
tf
tHD;DAT tHIGH
S
Sr
P
S
Figure 6. I2C Data Transmission Timing
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DATA TRANSMISSION TIMING
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
100
TYP
MAX
UNIT
400 KHz
µs
f(SCL)
Serial clock frequency
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
4
600
4.7
1.3
4
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD;STA
ns
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
LOW period of the SCL clock
µs
µs
ns
µs
ns
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
600
4.7
600
0
3.45
900
µs
ns
0
250
100
Data set-up time
ns
ns
ns
1000
300
300
300
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus Free Time Between Stop and Start Condition
tf
4
600
4.7
1.3
n/a
0
µs
ns
tSU;STO
tBUF
tSP
µs
ns
pF
n/a
50
Pulse width of spikes which mst be suppressed
by the input filter
400
400
Cb
Capacitive load for each bus line
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SLVSAA2C –MARCH 2010–REVISED OCTOBER 2010
REGISTER ADDRESS MAP
DEFAULT
VALUE
REGISTER
ADDRESS (HEX)
NAME
DESCRIPTION
0
0x00
TMST_VALUE
N/A
Thermistor value read by ADC
THERMISTOR READOUT (TMST_VALUE)
Address – 0x00h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
TMST_VALUE[7:0]
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Temperature read-out
1111 0110 – < -10°C
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1 °C
0000 0000 – 0 °C
0000 0001 – 1°C
0000 0010 – 2°C
...
TMST_VALUE[7:0]
0001 1001 – 25°C
...
0101 0101 – 85°C
0101 0101 – > 85°C
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PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS65182BRGZR
TPS65182BRGZT
TPS65182RGZR
TPS65182RGZT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
48
48
48
48
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
2500
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65182BRGZR
TPS65182BRGZT
TPS65182RGZR
TPS65182RGZT
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
48
48
48
48
2500
250
330.0
180.0
330.0
180.0
16.4
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65182BRGZR
TPS65182BRGZT
TPS65182RGZR
TPS65182RGZT
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
48
48
48
48
2500
250
346.0
190.5
346.0
190.5
346.0
212.7
346.0
212.7
33.0
31.8
33.0
31.8
2500
250
Pack Materials-Page 2
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