TPS65186RGZR_技术文档

TPS65186

www.ti.com

SLVSB04 –JULY 2011

PMIC FOR E Ink^®Vizplex™ ENABLED ELECTRONIC PAPER DISPLAY

Check for Samples: TPS65186

•

Flexible Power-Up and Power Down

Sequencing

Integrated 10-Ω, 3.3-V Power Switch for

Disabling System Power Rail to E-Ink Panel

1

FEATURES

2345

•

Single Chip Power Management Solution for

E Ink^®Vizplex™ Electronic Paper Displays

•

Generates Positive and Negative Gate and

Source Driver Voltages and Back-Plane Bias

from a Single, Low-Voltage Input Supply

Supports 9.7 Inch and Larger Panel Size

3-V to 6-V Input Voltage Range

Boost Converter for Positive Rail Base

Inverting Buck-Boost Converter for Negative

Rail Base

Thermistor Monitoring

–

–10°C to 85°C Temperature Range

±1°C Accuracy from 0°C to 50°C

–

•

I²C Serial Interface

Slave Address 0x48h

Package Options:

–

48-Pin, 0.5 mm Pitch,

7 mm x 7 mm x 0.9 mm (QFN) RGZ

•

Two Adjustable LDOs for Source Driver

Supply

APPLICATIONS

•

–

LDO1: 15 V, 120 mA (VPOS)

LDO2: –15 V, 120 mA (VNEG)

Power Supply for Active Matrix E Ink^®

Vizplex™ Panels

EPD Power Supply

•

Accurate Output Voltage Tracking

VPOS - VNEG = ±50 mV

Two Charge Pumps for Gate Driver Supply

•

–

E-Book Readers

EPSON^®S1D13522 (ISIS) Timing Controller

–

CP1: 22 V, 10 mA (VDDH)

CP2: –20 V, 12 mA, (VEE)

EPSON^®S1D13521 (Broadsheet) Timing

Controller

•

Adjustable VCOM Driver for Accurate

Panel-Backplane Biasing

•

Application Processors With Integrated or

Software Timing Controller ( OMAP™)

–

User Programmable Default

0 V to -5.11 V

± 1.5% accuracy (±10 mV)

9-Bit Control (10-mV Nominal Step Size)

DESCRIPTION

The TPS65186 is a single-chip power supply designed to for E Ink^®Vizplex™ displays used in portable e-reader

applications and supports panel sizes up to 9.7 inches and greater. Two high efficiency DC/DC boost converters

generate ±16-V rails which are boosted to 22 V and –20 V by two change pumps to provide the gate driver

supply for the Vizplex™ panel. Two tracking LDOs create the ±15-V source driver supplies which support up to

120-mA of output current. All rails are adjustable through the I²C interface to accommodate specific panel

requirements.

Accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 V to -5.11 V with 9-bit

control through the serial interface and can source or sink current depending on panel condition. The TPS65186

supports automatic panel kickback voltage measurement which eliminates the need of manual VCOM calibration

in the production line. The measurement result can be stored in non-volatile memory to become the new VCOM

power-up default value.

TPS65186 is available in a 48-pin 7x7 mm²QFN with 0.5-mm pitch.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

5

OMAP is a trademark of Texas Instruments.

Vizplex is a trademark of E Ink Corporation.

E Ink is a registered trademark of E Ink Corporation.

EPSON is a registered trademark of Seiko Epson Corporation.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

TPS65186

SLVSB04 –JULY 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

10uF

2.2uH

VIN_P

From Battery

(3.0V-6.0V)

VB_SW

From Battery

(3.0V-6.0V)

4.7uH

VN_SW

VN

4.7uF

DCDC1

DCDC2

PGND1

VB

4.7uF

VDDH_IN

VDDH_D

VEE_IN

VEE_D

100n

VDDH (22V)

VEE (-20V)

VDDH

CHARGE

PUMP

VEE

CHARGE

PUMP

VDDH_DRV

VDDH_FB

VEE_DRV

VEE_FB

1M

2.2uF

10nF

2.2uF

47.5k

52.3k

PGND2

4.7uF

VDDH_EN

VEE_EN

4.7uF

VPOS_IN

VPOS

VNEG_IN

VNEG

VPOS (15V)

LDO1

LDO2

VNEG (-15V)

4.7uF

VPOS_EN

VNEG_EN

10k NTC

43k

PBKG

TS

PowerPad®

TEMP

SENSOR

TMST_VALUE[7:0]

AGND2

ADC

VIN

INT_LDO

From Input Supply

(3.0V-6.0V)

INT_LDO

VREF

4.7uF

10uF

VREF

4.7uF

AGND1

VCOM

To panel back -plane

(0 to -5.11V)

VCOM[8:0]

VCOM_CTRL

DAC

4.7uF

From uC

VCOM_PWR

VIN3P3

3.3V supply from system

To EPD panel

V3P3_EN

GATE DRIVER

V3P3

1k

10k

VIO

SDA

SCL

From uC

From/to uC or DSP

From uC

10k

VIO

INT

PWRUP

WAKEUP

DGND

To uC

DIGITAL

CORE

PWR_GOOD

From uC

2

TPS65186

www.ti.com

SLVSB04 –JULY 2011

ORDERING INFORMATION⁽¹⁾

ORDERABLE PART NUMBER

TPS65186RGZR

T_A

-10°C to 85°C

PACKAGE⁽²⁾

TOP-SIDE MARKING

TPS65186

RGZ

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

DEVICE INFORMATION

RGZ PACKAGE

(TOP VIEW)

VDDH_IN – 37

N/C – 38

24 – PWR_GOOD

23 – PBKG

22 – PWRUP

21 – N/C

N/C – 39

VB_SW – 40

PGND1 – 41

VB – 42

20 – N/C

19 – N/C

VPOS_IN – 43

VPOS – 44

VIN3P3 – 45

V3P3 – 46

TS – 47

18 – SDA

17 – SCL

16 – VCOM_PWR

15 – N/C

14 – VCOM

13 – N/C

AGND2 – 48

TERMINAL FUNCTIONS⁽³⁾

TERMINAL

I/O

DESCRIPTION

NAME

VREF

nINT

NO.

1

O

I

Filter pin for 2.25-V internal reference to ADC

Open drain interrupt pin (active low)

2

VNEG

3

Negative supply output pin for panel source drivers

Input pin for LDO2 (VNEG)

VNEG_IN

4

Wake up pin (active high). Pull this pin high to wake up from sleep mode. IC accepts I²C

commands after WAKEUP pin is pulled high but power rails remain disabled until

PWRUP pin is pulled high.

WAKEUP

5

I

DGND

INT_LDO

AGND1

6

7

8

Digital ground. Connect to ground plane.

Filter pin for 2.7-V internal supply

O

Analog ground for general analog circuitry

(3) There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively.

3

TPS65186

SLVSB04 –JULY 2011

www.ti.com

TERMINAL

I/O

DESCRIPTION

NAME

N/C

NO.

9

Not internally connected

VIN

10

11

I

Input power supply to general circuitry

Not internally connected

N/C

VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low

and VN is enabled, VCOM discharge is enabled.

VCOM_CTRL

12

N/C

VCOM

N/C

13

14

15

16

17

18

19

20

21

22

Not internally connected

Filter pin for panel common-voltage driver

Not internally connected

VCOM_PWR

SCL

I

Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.

Serial interface (I²C) clock input

Serial interface (I²C) data input/output

SDA

I/O

N/C

Not internally connected

N/C

Not internally connected

N/C

Not internally connected

PWRUP

I

Power-up pin. Pull this pin high to power-up all output rails.

Die substrate. Connect to VN (-16 V) with short, wide trace. Wide copper trace will

improve heat dissipation.

PBKG

23

24

Open drain power good output pin. Pin is pulled low when one or more rails are disabled

or not in regulation. DCDC1, DCDC2, and VCOM have no effect on this pin.

PWR_GOOD

O

VN_SW

N/C

25

26

27

Inverting buck-boost converter switch out (DCDC2)

Not internally connected

VIN_P

I

Input power supply to inverting buck-boost converter (DCDC2)

Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and

VEE charge pump

VN

28

VEE_IN

VEE_DRV

VEE_D

29

30

31

32

33

34

35

36

37

38

39

40

41

I

O

I

Input supply pin for negative charge pump (CP2) (VEE)

Driver output pin for negative charge pump (CP2)

Base voltage output pin for negative charge pump (CP2)

Feedback pin for negative charge pump (CP2)

Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps

Feedback pin for positive charge pump (CP1)

Base voltage output pin for positive charge pump (CP1)

Driver output pin for positive charge pump (CP1)

Input supply pin for positive charge pump (CP1)

Not internally connected

VEE_FB

PGND2

VDDH_FB

VDDH_D

VDDH_DRV

VDDH_IN

N/C

I

O

I

N/C

Not internally connected

VB_SW

PGND1

O

I

Boost converter switch out (DCDC1)

Power ground for DCDC1

Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge

pump

VB

42

VPOS_IN

VPOS

43

44

45

46

I

Input pin for LDO1 (VPOS)

O

I

Positive supply output pin for panel source drivers

Input pin to 3.3-V power switch

VIN3P3

V3P3

O

Output pin of 3.3-V power switch

Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor

between this pin and AGND.

TS

47

48

I

AGND2

PowerPad

Reference point to external thermistor and linearization resistor

Power Pad, internally connected to PBKG. Connect to VN with short, wide trace. Wide

copper trace will improve heat dissipation. PowerPad must not be connected to ground.

N/A

4

TPS65186

www.ti.com

SLVSB04 –JULY 2011

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)(2)

VALUE

–0.3 to 7

–0.3 to 0.3

UNIT

V

Input voltage range at VIN⁽²⁾, VIN_P, VIN3P3

Ground pins to system ground

V

Voltage range at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB,

PWR_GOOD, nINT

–0.3 to 3.6

V

Voltage on VB, VB_SW, VPOS_IN, VDDH_IN

Voltage on VN, VEE_IN, VCOM_PWR, VNEG_IN

Voltage from VIN_P to VN_SW

Peak output current

–0.3 to 20

–20 to 0.3

–0.3 to 30

Internally limited

2

V

mA

W

Continuous total power dissipation

Junction-to-ambient thermal resistance⁽³⁾

Operating junction temperature

Operating ambient temperature⁽⁴⁾

Storage temperature

θ_JA

T_J

23

°C/W

°C

-10 to 125

-10 to 85

-65 to 150

±2000

T_A

T_stg

(HBM) Human body model

ESD rating

V

(CDM) Charged device model

±500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and

2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.

(4) It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad

is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the

buck-boost output will help heat dissipated efficiently.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage range at VIN, VIN_P, VIN3P3

3

3.7

6

V

Voltage range at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL,

VDDH_FB, VEE_FB, PWR_GOOD, nINT

0

3.6

V

T_A

T_J

Operating ambient temperature range

Operating junction temperature range

–10

85

°C

125

5

TPS65186

SLVSB04 –JULY 2011

www.ti.com

RECOMMENDED EXTERNAL COMPONENTS

PART NUMBER

INDUCTORS

VALUE

SIZE

MANUFACTURER

LQH44PN4R7MP0

NR4018T4R7M

VLS252015ET-2R2M

NR4012T2R2M

CAPACITORS

GRM21BC81E475KA12L

GRM32ER71H475KA88L

All other caps

4.7 µH

2.2 µH

4 mm x 4 mm x 1.65 mm

4 mm x 4 mm x 1.8 mm

2 mm x 2.5 mm x 1.5 mm

4 mm x 4 mm x 1.2 mm

Murata

Taiyo Yuden

TDK

Taiyo Yuden

4.7 µF, 25 V, X6S

4.7 µF, 50 V, X7R

X5R or better

0805

1210

Murata

DIODES

BAS3010

SOD-323

SOD-123

SOT-23

Infineon

ON-Semi

Fairchild

MBR130T1

BAV99

THERMISTOR

NCP18XH103F03RB

10 KΩ

0603

Murata

ELECTRICAL CHARACTERISTICS

V_IN= 3.7 V, T_A= –10°C to 85ºC, Typical values are at T_A= 25ºC (unless otherwise noted)

PARAMETER

INPUT VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN

Input voltage range

3

3.7

2.9

6

V

V_UVLO

V_HYS

Undervoltage lockout threshold

Undervoltage lockout hysteresis

V_INfalling

V_INrising

400

mV

INPUT CURRENT

I_Q

Operating quiescent current into V_IN

Device switching, no load

Device in standby mode

Device in sleep mode

5.5

130

3.5

mA

µA

I_STD

I_SLEEP

Operating quiescent current into V_IN

Shutdown current

10

INTERNAL SUPPLIES

VI_{NT_LDO}

C_{INT_LDO}

V_REF

Internal supply

2.7

4.7

V

µF

V

Nominal output capacitor

Internal supply

Capacitor tolerance ±10%

1

3.3

3

2.25

4.7

C_REF

Nominal output capacitor

µF

DCDC1 (POSITIVE BOOST REGULATOR)

V_IN

Input voltage range

Power good threshold

Power good time-out

Output voltage range

DC set tolerance

3.7

90

50

16

6

V

%

Fraction of nominal output voltage

Not tested in production

PG

ms

V

V_OUT

-4.5

4.5

%

I_OUT

Output current

250

mA

mΩ

A

R_DS(ON)

MOSFET on resistance

Switch current limit

Switch current accuracy

Switching frequency

Inductor

V_IN= 3.7 V

350

1.5⁽¹⁾

I_LIMIT

-30

1

30

%

f_SW

1

2.2

MHz

µH

µF

mΩ

L_DCDC1

C_DCDC1

ESR

Nominal output capacitor

Output capacitor ESR

Capacitor tolerance ±10%

2x4.7

20

(1) Contact factory for 1-A, 2-A, or 2.5-A option.

6

TPS65186

www.ti.com

SLVSB04 –JULY 2011

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.7 V, T_A= –10°C to 85ºC, Typical values are at T_A= 25ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DCDC2 (INVERTING BUCK-BOOST REGULATOR)

V_IN

Input voltage range

Power good threshold

Power good time-out

Output voltage range

DC set tolerance

3

3.7

90

6

V

%

Fraction of nominal output voltage

Not tested in production

PG

50

ms

V

-16

V_OUT

-4.5

4.5

%

I_OUT

Output current

250

mA

mΩ

A

R_DS(ON)

MOSFET on resistance

Switch current limit

Switch current accuracy

Inductor

V_IN= 3.7 V

350

1.5⁽²⁾

I_LIMIT

-30

1

30

%

L_DCDC1

C_DCDC1

ESR

4.7

3x4.7

20

µH

µF

mΩ

Nominal output capacitor

Capacitor ESR

Capacitor tolerance ±10%

LDO1 (VPOS)

V_{POS_IN}Input voltage range

15.2

16

90

50

16.8

15

V

%

Power good threshold

Power good time-out

Fraction of nominal output voltage

Not tested in production

PG

ms

V_IN= 16 V,

VSET[2:0] = 0x3h to 0x6h

V_SET

Output voltage set value

14.25

-1

15

V

V_INTERVALOutput voltage set resolution

V_OUTTOLOutput tolerance

V_IN= 16 V

V_SET= 15 V, I_LOAD= 20 mA

I_LOAD= 120 mA

250

mV

%

1

250

1

V_DROPOUTDropout voltage

mV

%

V_LOADREGLoad regulation – DC

I_LOAD= 10% to 90%

I_LOAD

I_LIMIT

C_LDO1

Load current range

120

mA

µF

Output current limit

120

1

Nominal output capacitor

Capacitor tolerance ±10%

4.7

LDO2 (VNEG)

V_{NEG_IN}Input voltage range

16.8

16

90

50

-15.2

V

%

Power good threshold

Power good time-out

Fraction of nominal output voltage

Not tested in production

PG

ms

V_IN= –16 V

VSET[2:0] = 0x3h to 0x6h

V_SET

Output voltage set value

-15

-1

-15

-14.25

V

V_INTERVALOutput voltage set resolution

V_OUTTOLOutput tolerance

V_IN= –16 V

250

mV

%

V_SET= –15 V, I_LOAD= –20 mA

I_LOAD= 120 mA

1

250

1

V_DROPOUTDropout voltage

mV

%

V_LOADREGLoad regulation – DC

I_LOAD= 10% to 90% of I_LOAD,MAX

I_LOAD

I_LIMIT

C_LDO2

Load current range

120

mA

µF

Output current limit

120

1

Nominal output capacitor

Capacitor tolerance ±10%

4.7

(2) Contact factory for 1-A, 2-A, or 2.5-A option.

7

TPS65186

SLVSB04 –JULY 2011

www.ti.com

MAX UNIT

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.7 V, T_A= –10°C to 85ºC, Typical values are at T_A= 25ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

LD01 (POS) AND LDO2 (VNEG) TRACKING

V_SET= ±15 V,

I_LOAD= ±20 mA, 0°C to 60°C

V_DIFF

Difference between VPOS and VNEG

-50

50

mV

VCOM DRIVER

I_VCOMDrive current

15

mA

V

Outside this range VCOM is shut down

and VCOMF interrupt is set

Allowed operating range

-5.5

-0.8

1

VCOM[8:0] = 0x07Dh

(-1.25 V), V_IN= 3.4 V to 4.2 V, no load

0.8

Accuracy

%

VCOM[8:0] = 0x07Dh

(-1.25 V), V_IN= 3.0 V to 6.0 V, no load

V_COM

-1.5

1.5

0

Output voltage range

Resolution

-5.11

V

1LSB

10

TBD

4.7

mV

Max number of EEPROM writes

Output impedance

V_COMcalibration

100

R_OUT

R_IN

VCOM_CTRL = high, HiZ = 0

HiZ = 1

Ω

Input impedance, HiZ state

Nominal output capacitor

150

3.3

MΩ

µF

C_VCOM

Capacitor tolerance ±10%

CP1 (VDDH) CHARGE PUMP

V_{DDH_IN}

Input voltage range

Power good threshold

Power good time-out

Feedback voltage

Accuracy

15.2

16

90

16.8

V

%

Fraction of nominal output voltage

Not tested in production

PG

50

ms

V

0.998

V_FB

I_LOAD= 2 mA

-2

2

23

10

%

V_{DDH_OUT}Output voltage range

V_SET= 22 V, I_LOAD= 2 mA

21

22

V

I_LOAD

f_SW

C_D

Load current range

Switching frequency

Driver capacitor

mA

KHz

nF

µF

560

10

C_O

Output capacitor

1

2.2

CP2 (VEE) NEGATIVE CHARGE PUMP

V_{EE_IN}

Input voltage range

Power good threshold

Power good time-out

Feedback voltage

Accuracy

16.8

-16

90

-15.2

V

%

Fraction of nominal output voltage

Not tested in production

PG

50

ms

V

-0.994

V_FB

I_LOAD= 2 mA

-2

2

-19

12

%

V_{EE_OUT}

I_LOAD

f_SW

Output voltage range

Load current range

Switching frequency

Driver capacitor

V_SET= –20 V, I_LOAD= 3 mA

-21

-20

V

mA

KHz

nF

µF

560

10

C_D

C_O

Nominal output capacitor

Capacitor tolerance ±10%

1

2.2

8

TPS65186

www.ti.com

SLVSB04 –JULY 2011

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 3.7 V, T_A= –10°C to 85ºC, Typical values are at T_A= 25ºC (unless otherwise noted)

PARAMETER

VIN3P3 TO V3P3 SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

VIN3P3 = 3.3 V, I_D= 10 mA

Over full temperature range

10.5

TBD

Ω

R_DS(ON)

MOSFET ON resistance

VIN3P3 = 2.7 V, I_D= 10 mA

Over full temperature range

12.3

TBD

R_DIS

Discharge impedance to ground

V3P3EN = 0

800

1000

1200

Ω

THERMISTOR MONITOR⁽³⁾

A_TMS

Temperature to voltage ratio

Not tested in production

Temperature = 0°C

-0.0161

1.575

0.768

0.845

2.25

V/°C

V

Offset_TMSOffset

V_{TMS_HOT}Temp hot trip voltage (T = 50°C)

V_{TMS_COOL}Temp hot escape voltage (T = 45°C)

V_{TMS_MAX}Maximum input level

TEMP_HOT_SET = 0x8C

TEMP_COOL_SET = 0x82

V

R_{NTC_PU}

R_LINEAR

ADC_RES

ADC_DEL

Internal pull up resistor

External linearization resistor

ADC resolution

7.307

43

KΩ

mV

µs

Not tested in production, 1 bit

Not tested in production

16.1

ADC conversion time

19

TMST_TOLAccuracy

-1

1

LSB

LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, nINT, PWR_GOOD, PWRUP)

I_O= 3 mA, sink current

(SDA, nINT, PWR_GOOD)

V_OL

Output low threshold level

0.4

V

V_IL

Input low threshold level

Input high threshold level

Input bias current

V

V_IH

1.2

I_(bias)

V_IO= 1.8 V

1

µA

Deglitch time, WAKEUP pin

Deglitch time, PWRUP pin

SCL clock frequency

Not tested in production

500

400

t_deglitch

f_SCL

µs

400 KHz

I²C slave address

7-bit address

0x48h⁽⁴⁾

OSCILLATOR

f_OSCOscillator frequency

Frequency accuracy

THERMAL SHUTDOWN

T_SHTDWNThermal trip point

Thermal hysteresis

9

MHz

T_A= –40°C to 85°C

-10

10

%

150

20

°C

(3) 10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 kΩ, 1%) are used at TS pin for panel

temperature measurement.

(4) Contact factory for alternate address of 0x68h.

9

TPS65186

SLVSB04 –JULY 2011

www.ti.com

TYPICAL CHARACTERISTICS

DEFAULT POWER-DOWN SEQUENCE

DEFAULT POWER-UP SEQUENCE

(1-kΩ External Discharge Resistor on Each Rail)

Figure 1.

Figure 2.

INRUSH CURRENT @ V_IN= 3.7 V, C_IN= 100 µF

INRUSH CURRENT @ V_IN= 5 V, C_IN= 100 µF

Figure 3.

Figure 4.

SWITCHING WAVE FORMS, VN

V_IN= 3 V, R_{LOAD, VPOS}= 330 Ω, R_{LOAD, VNEG}= 330 Ω,

No Load on VDDH, VEE

SWITCHING WAVE FORMS, VB

V_IN= 3 V, R_{LOAD, VPOS}= 330 Ω, R_{LOAD, VNEG}= 330 Ω,

No Load on VDDH, VEE

Figure 5.

Figure 6.

10

TPS65186

www.ti.com

SLVSB04 –JULY 2011

TYPICAL CHARACTERISTICS (continued)

SWITCHING WAVE FORMS, VN

SWITCHING WAVE FORMS, VB

V_IN= 3.7 V, R_{LOAD, VPOS}= 330 Ω, R_{LOAD, VNEG}= 330 Ω,

No Load on VDDH, VEE

Figure 7.

Figure 8.

SWITCHING WAVE FORMS, VN

V_IN= 5 V, R_{LOAD, VPOS}= 330 Ω, R_{LOAD, VNEG}= 330 Ω,

No Load on VDDH, VEE

SWITCHING WAVE FORMS, VB

V_IN= 5 V, R_{LOAD, VPOS}= 330 Ω, R_{LOAD, VNEG}= 330 Ω,

No Load on VDDH, VEE

Figure 9.

Figure 10.

VN DCDC EFFICIENCY, T = 25°C

VB DCDC EFFICIENCY, T = 25°C

100

90

100

90

80

70

VIN= 3.5

60

50

40

30

20

10

0

VIN= 3.5

VIN= 5V

50

40

30

20

10

0

25

50

75

100

125

150

175

0

25

50

75

100

125

150

175

Output Current [mA]

Figure 11.

Figure 12.

11

TPS65186

SLVSB04 –JULY 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

VEE CHARGE PUMP EFFICIENCY, T = 25°C

VDDH CHARGE PUMP EFFICIENCY, T = 25°C

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

VIN=5V

VIN=3.5

VIN=3.5V

0

2

4

6

8

10

12

0

2

4

6

8

10

12

Output Current [mA]

Figure 13.

Figure 14.

3p3V SWITCH IMPEDANCE

V_IN= 3.7 V, I_{LOAD, V3p3}= 10 mA

SOURCE DRIVER SUPPLY TRACKING

V_IN= 3.7 V

5 0

4 0

25

20

15

10

5

IPO S =INE G

IPO S swe ep, INE G=15m A

IPO S =15mA , INEG sweep

3 0

2 0

1 0

0

-1 0

-2 0

-3 0

-4 0

-5 0

0

25

50

75

100

125

1 50

1 75

1

1.5

2

2.5

3

3.5

4

Curre nt [m A]

VIN3P3[V]

Figure 15.

Figure 16.

VCOM INTEGRATED NON-LINEARITY

VCOM DIFFERENTIAL NON-LINEARITY

V_IN= 3.7 V, R_{LOAD, VCOM}= 1 kΩ

5

4

0.2

0 .15

0.1

3

2

0 .05

0

1

0

-1

-2

-3

-4

-5

-0 .05

-0.1

-0 .15

-0.2

0

6 4

12 8 1 92 2 56 3 20 384 448 512

0

64

128

192 25 6 320

384 44 8 512

VCO M CODE

V CO M CODE

Figure 17.

Figure 18.

12

TPS65186

www.ti.com

SLVSB04 –JULY 2011

TYPICAL CHARACTERISTICS (continued)

KICKBACK VOLTAGE MEASUREMENT TIMING

KICKBACK VOLTAGE MEASUREMENT ERROR

V_IN= 3.7 V; AVG[1:0] = 00 (Single Measurement)

Time from ACQ Bit Set to ACQC Interrupt Received

V_IN= 3.7 V

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0

640 12 80 192 0 2560 3200 3840 44 80 512 0

Force d Kick ba c k Volta ge [m V]

Figure 19.

Figure 20.

KICKBACK VOLTAGE MEASUREMENT TIMING

V_IN= 3.7 V; AVG[1:0] = 11 (Eight Measurements)

Time from ACQ Bit Set to ACQC Interrupt Received

Figure 21.

13

TPS65186

SLVSB04 –JULY 2011

www.ti.com

MODES OF OPERATION

The TPS65186 has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the

lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the

device is ready to accept commands through the I²C interface. In ACTIVE mode one or more power rails are

enabled.

SLEEP

This is the lowest power mode of operation. All internal circuitry is turned off, registers are

reset to default values and the device does not respond to I²C communications. TPS65186

enters SLEEP mode whenever WAKEUP pin is pulled low.

STANDBY

In STANDBY all internal support circuitry is powered up and the device is ready to accept

commands through the I²C interface but none of the power rails are enabled. The device

enters STANDBY mode when the WAKEUP pin is pulled high and either the PWRUP pin is

pulled low or the STANDBY bit is set. The device also enters STANDBY mode if input Under

Voltage Lock Out (UVLO), positive boost Under Voltage (VB_UV), or inverting buck-boost

Under Voltage (VN_UV) is detected, thermal shutdown occurs, or the PROG bit is set (see

VCOM calibration).

ACTIVE

The device is in ACTIVE mode when any of the output rails are enabled and no fault

condition is present. This is the normal mode of operation while the device is powered up.

MODE TRANSISITONS

SLEEP → ACTIVE

WAKEUP pin is pulled high with PWRUP pin high. Rails come up in the order defined by the

UPSEQx registers (OK to tie WAKEUP and PWRUP pin together).

SLEEP → STANDBY

WAKEUP pin is pulled high with PWRUP pin low. Rails will remain powered down.

STANDBY → ACTIVE

WAKEUP pin is high and PWRRUP pin is pulled high (rising edge) or the ACTIVE bit is set.

Output rails will power up in the order defined by the UPSEQx registers.

ACTIVE → STANDBY

WAKEUP pin is high and STANDBY bit is set or PWRUP pin is pulled low (falling edge).

Rails are shut down in the order defined by DWNSEQx registers. Device also enters

STANDBY in the event of Thermal Shut Down (TSD), Under Voltage Lock Out (UVLO),

positive boost or inverting buck-boost Under Voltage (UV), VCOM fault (VCOMF), or when

the PROG bit is set (see VCOM calibration).

STANDBY → SLEEP

WAKEUP pin is pulled low while none of the output rails are enabled.

ACTIVE → SLEEP

WAKEUP pin is pulled low while at least one output rail is enabled. Rails are shut down in

the order defined by DWNSEQx registers.

14

TPS65186

www.ti.com

SLVSB04 –JULY 2011

POWER DOWN

Battery removed

All rails = OFF

V3P3 switch= OFF

I2C = NO

Registersà default

SLEEP

WAKEUP= high &

PWRUP= low

WAKEUP= low

All rails = OFF

= YES

STANDBY

I2C

WAKEUP= high &

(STANDBY bit = 1||

PWRUP(?) || FAULT )

WAKEUP= high &

(ACTIVE bit= 1 || PWRUP( ) )

?

Rails

I2C

= ON

= YES

ACTIVE

NOTES:

||, &

= logic OR, logic AND.

( ), (?) = rising edge, falling edge.

?

UVLO

TSD

UV

= Under Voltage Lock Out

= Thermal Shut Down

= Under Voltage

FAULT = UVLO || TSD || BOOST UV|| VCOM fault.

Figure 22. Global State Diagram

15

TPS65186

SLVSB04 –JULY 2011

www.ti.com

WAKE-UP AND POWER UP SEQUENCING

The power-up/down order and timing is defined by user register settings. The default settings support the E Ink^®

Vizplex™ panel and typically do not need to be changed.

In SLEEP mode the TPS65186 is completely turned off, the I²C registers are reset, and the device does not

accept any I²C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY

mode which enables the I²C interface. Write to the UPSEQ0 register to define the order in which the output rails

are enabled at power-up and to the UPSEQ1 registers to define the power-up delays between rails. Finally, set

the ACTIVE bit in the ENABLE register to ‘1’ to execute the power-up sequence and bring up all power rails.

Alternatively pull the PWRUP pin high (rising edge).

After the ACTIVE bit has been set, the negative boost converter (VN) is powered up first, followed by the positive

boost (VB). The positive boost enable is gated by the internal power-good signal of the negative boost. Once VB

is in regulation, it issues an internal power-good signal and after delay time UDLY1 has expired, STROBE1 is

issued. The rail assigned to STROBE1 will power up next and after its power-good signal has been asserted and

delay time UDLY2 has expired, STROBE2 is issued. The sequence continues until STROBE4 has occurred and

the last rail has been enabled.

To power-down the device, set the STANDBY bit of the ENABLE register to ‘1’ or pull the PWRUP pin low (falling

edge) and the TPS65186 will power down in the order defined by DWNSEQx registers. The delay times DDLY2,

DDLY3, and DDLY4 are weighted by a factor of DFCTR which allows the user to space out the power-down of

the rails to avoid crossing during discharge. DFCTR is located in register DWNSEQ1. The positive boost (VB) is

shut down together with the last rail at STROBE4. However, the negative boost (VN) remains up and running for

another 50 ms. Then VN is powered down and the device enters STANDBY or SLEEP mode, depending on the

WAKEUP pin.

If either the ACTIVE bit is set or the PWRUP pin is pulled high while the device is powering down, the

power-down sequence (STROBE1-4) is completed first, followed by a power-up sequence. VB and VN may or

may not be powered down and depending on the relative timing of STROBE4 to the new power-up event.

During power-up, if the STANDBY bit is set or the PWRUP pin is pulled low, the power-up sequence is aborted

and the power-down sequence starts immediately.

DEPENDENCIES BETWEEN RAILS

Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and

several dependencies exist that affect the power-up sequencing. These dependencies are listed below.

1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.

Internally, DCDC1 enable is gated by DCDC2 power good.

2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable

is gated DCDC1 power-good.

3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is

gated by DCDC1 power good.

4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally

CP2 enable is gated by DCDC1 power good.

5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally

CP1 enable is gated by DCDC1 power good.

6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power

good.

16

TPS65186

www.ti.com

SLVSB04 –JULY 2011

VN PG

VB PG

VN

powers up

VB

powers up

STROBE 1

STROBE 2

STROBE 3

STROBE 4

PG4

UDLY1

UDLY2

UDLY3

UDLY4

1^strail

powers up

2^ndrail

powers up

3^ndrail

powers up

4^thrail

powers up

ACTIVE bit

or

WAKEUP high

STROBE 1

STROBE 2

STROBE 3

STROBE 4

DDLY1

DDLY2

DDLY3

DDLY4

1^strail

powers down

2^ndrail

powers down

3^ndrail

powers down

4^thrail

powers down

50ms

VB

powers down

VN

powers down

STANDBY bit

or

WAKEUP low

TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after

ACTIVE bit is set and STROBE4 is the last event in the sequence. Strobes are assigned to rails in UPSEQ0 register

and delays between STROBES are defined in UPSEQ1 register.

BOTTOM: Power-down sequence is independent of power-up sequence. Strobes and delay times for power down

sequence are set in DWNSEQ0 and DWNSEQ1 register.

Figure 23. Power-Up and Power-Down Sequence

17

TPS65186

SLVSB04 –JULY 2011

www.ti.com

VIN

I2C

1.8ms⁽¹⁾

PWRUP

WAKEUP

VN

SLEEP

STANDBY

ACTIVE

50ms

VB

UDLY 1

DDLY 4

UDLY 1

VNEG

UDLY 2

VEE

UDLY 3

DDLY 3

UDLY3

VPOS

UDLY 4

DDLY 2

UDLY 4

VDDH

DDLY 1

PWR_GOOD

300us (max)

(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .

In this example the first power-up sequence is started by pulling the PWRUP pin high (rising edge). Power-down is

initiated by pulling the WAKEUP pin low (device enters SLEEP mode). The 2nd power-up sequence is initiated by

pulling the WAKEUP pin high while the PWRUP pin is also high (power up from SLEEP to ACTIVE).

Figure 24. Power-Up and Power-Down Timing Diagram

SOFTSTART

TPS65186 supports soft-start for all rails, i.e. inrush current is limited during startup of DCDC1, DCDC2, LDO1,

LDO2, CP1 and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the

corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters

STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out

limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set

and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.

VPOS/VNEG SUPPLY TRACKING

LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.

The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV.

18

TPS65186

www.ti.com

SLVSB04 –JULY 2011

V3P3 POWER SWITCH

The integrated power switch is used to cut the 3.3-V supply to the EPD panel and is controlled through the

V3P3_EN pin of the ENABLE register. In SLEEP mode the switch is automatically turned off and its output is

discharged to ground. The default power-up state is OFF. To turn the switch ON, set the V3P3_ENbit to 1.

VCOM ADJUSTMENT

VCOM is the output of a power-amplifier with an output voltage range of 0 V to -5.11 V, adjustable in 10-mV

steps. In a typical application VCOM is connected to the VCOM terminal of the EPD panel and the amplifier is

controlled through the VCOM_CTRL pin. With VCOM_CTRL high, the amplifier drives the VCOM pin to the

voltage specified by the VCOM1 and VCOM2 register.

For ease of design, the VCOM_CTRL pin may also be tied to the battery or IO supply. In this case, VCOM is

enabled with STROBE4 during the power-up sequence and disabled on STROBE1 of the power-down sequence.

Therefore VCOM is the last rail to be enabled and the first to be disabled.

KICK-BACK VOLTAGE MEASUREMENT

TPS65186 can perform a voltage measurement on the VCOM pin to determine the kick-back voltage of the

panel. This allows in-system calibration of VCOM. To perform a kick-back voltage measurement, follow these

steps:

•

Pull the WAKEUP pin and the PWRUP pin high to enable all output rails.

Set the HiZ bit in the VCOM2 register. This puts the VCOM pin in a high-impedance state.

Drive the panel with the Null waveform. Refer to E-Ink specification for detail.

Set the ACQ bit in the VCOM2 register to 1. This starts the measurement routine.

When the measurement is complete, the ACQC (Acquisition Complete) bit in the INT1 register is set and the

nINT pin is pulled low.

•

The measurement result is stored in the VCOM[8:0] bits of the VCOM1 and VCOM2 register.

Please note that the measurement result is not automatically programmed into non-volatile memory. Changing

the power-up default is described in the following paragraph.

STORING THE VCOM POWER-UP DEFAULT VALUE IN MEMORY

The power-up default value of VCOM can be user-set and programmed into non-volatile memory. To do so, write

the default value to the VCOM[8:0] bits of the VCOM1 and VCOM2 register, then set the PROG bit in VCOM2

register to 1. First, all power rails are shut-down, then the VCOM[8:0] value is committed to non-volatile memory

such that it becomes the new power-up default. Once programming is complete, the PRGC bit in the INT1

register is set and the nINT pin is pulled low. To verify that the new value has been saved properly, first write the

VCOM[8:0] bits to 0x000h, then pull the WAKEUP pin low. After the WAKEUP pin is pulled back high, read the

VCOM[8:0] bits to verify that the new default value is correct.

VIN

INT_LDO

From Input Supply

(3.0V-6.0V)

INT_LDO

VREF

4.7uF

10uF

VREF

4.7uF

AGND1

VCOM

To panel back -plane

(-0.5 to -5.0V, 15mA)

VCOM[8:0]

VCOM_CTRL

DAC

4.7uF

From uC

VCOM_PWR

From VN (-17V)

Figure 25. Block Diagram of VCOM Circuit

19

TPS65186

SLVSB04 –JULY 2011

www.ti.com

Pull WAKEUP= HIGH

Pull PWRUP= HIGH

Write HiZ = 1

Device enters ACTIVE mode

All power rails are up except VCOM

VCOM pin is in HiZ state

Processor drives panel with NULL waveform

Write ACQ = 1

Starts A/D conversion

Indicates A/D conversion is complete

If AVG[1:0] is <> 00, interrupt is issed

after all conversions are complete and

average has been calcutated.

Wait for ACQC interrupt

Read result from VCOM1/2

registers

Check result and decide to keep the

value or repeat measurmen.t

Pull PWRUP= LOW

Write HiZ = 0

Device enters STANDBY mode

Starts the EEPROM programming cycle.

Power must not be interrupted.

Write PROG= 1

Wait for PRGC interrupt

Pull WAKEUP= LOW

Pull WAKEUP= HIGH

Read VCOM[8:0]

Indicates programming is complete

Device enters SLEEP mode

Device enters STANDBY mode

Compare against written value to

confirm new default has been

programmed correctly.

Figure 26. VCOM Calibration Flow

20

TPS65186

www.ti.com

SLVSB04 –JULY 2011

FAULT HANDLING AND RECOVERY

The TPS65186 monitors input and output voltages and die temperature and will take action if operating

conditions are outside normal limits. Whenever the TPS65186 encounters:

•

Thermal Shutdown (TSD)

Positive Boost Under Voltage (VB_UV)

Inverting Buck-Boost Under Voltage (VN_UV)

Input Under Voltage Lock Out (UVLO)

it shuts down all power rails and enters STANDBY mode. Shut-down follows the order defined by DWNSEQx

registers. The exception is VCOM fault witch leads to immediate shutdown of all rails. Once a fault is detected,

the PWR_GOOD and nINT pins are pulled low and the corresponding interrupt bit is set in the interrupt register.

Power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the INT1 and INT2

register. Alternatively, toggling the WAKEUP pin also resets the interrupt bits. As the PWRUP input is edge

sensitive, the host must toggle the PWRUP pin to re-enable the rails through GPIO control, i.e. it must bring the

PWRUP pin low before asserting it again. Alternatively rails can be re-enbled through the I²C interface.

Whenever the TPS65186 encounters under-voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV)

or VDDH (VDDH_UV), rails are not shut down but the PWR_GOOD and nINT is pulled low with the

corresponding interrupt bit set. The device remains in ACTIVE mode and recovers automatically once the fault

has been removed.

POWER GOOD PIN

The power good pin (PWR_GOOD) is an open drain output that is pulled high (by an external pull-up resistor)

when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails

encounters a fault or is disabled. PWR_GOOD remains low if one of the rails is not enabled by the host and only

after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor).

INTERRUPT PIN

The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT1 or INT2 bits

are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the register with the set bit

has been read by the host. If the fault persists, the nINT pin will be pulled low again after a maximum of 32 µs.

Interrupt events can be masked by re-setting the corresponding enable bit in the INT_EN1 and INT_EN2 register,

i.e. the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits

affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT1/INT2 bits

themselves.

Note that persisting faults such as thermal shutdown can cause the nINT pin to be pulled low for an extended

period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set

the corresponding mask bit after receiving the interrupt and keep polling the INT1/INT2 register to see when the

fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.

PANEL TEMPERATURE MONITORING

The TPS65186 provides circuitry to bias and measure an external Negative Temperature Coefficient Resistor

(NTC) to monitor the display panel temperature in a range from -10°C to 85°C with and accuracy of ±1°C from

0°C to 50°C. Temperature measurement must be triggered by the controlling host and the last temperature

reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the

programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed

by more than a user-defined threshold from the baseline value. Details are explained under “HOT, COLD, and

temperature-change interrupts”.

21

TPS65186

SLVSB04 –JULY 2011

www.ti.com

NTC BIAS CIRCUIT

Figure 27 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an

internally generated 2.25-V reference voltage through an integrated 7.307-KΩ bias resistor. A 43-kΩ resistor is

connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a

nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is

digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.

Table 1. ADC Output Value vs Termperature

TEMPERATURE

TMST_VALUE[7:0]

1111 0110

1111 0111

...

< -10°C

-10°C

-9°C

...

-2°C

-1°C

0°C

1111 1110

1111 1111

0000 0000

0000 0001

0000 0010

...

1°C

2°C

...

25°C

...

0001 1001

85°C

> 85°C

0101 0101

2.25V

7.307k

10

TS

Digital

ADC

43k

10k NTC

AGND2

Figure 27. NTC Bias and Measurement Circuit

A temperature measurement is triggered by setting the READ_THERM bit of the TMST1 register to 1.During the

A/D conversion the CONV_END bit of the TMST1 register reads ‘0’, otherwise it reads ‘1’. At the end of the A/D

conversion the EOC bit in the INT2 register is set and the temperature value is available in the TMST_VALUE

register.

HOT, COLD, AND TEMPERATURE-CHANGE INTERRUPTS

Each temperature acquisition is compared against the programmable TMST_HOT and TMST_COLD thresholds

and to the baseline temperature, to determine if the display is within allowed operating temperature range and if

the temperature has changed by more than a user-defined threshold since the last update. The first temperature

reading after the WAKEUP pin has been pulled high automatically becomes the baseline temperature. Any

subsequent reading is compared against the baseline temperature. If the difference is equal or greater than the

threshold value, an interrupt is issued (DTX bit in register INT1 is set to ‘1’) and the latest value becomes the

new baseline. If the difference is less than the threshold value, no action is taken. The threshold value is defined

by DT[1:0] bits in the TMST1 register and has a default value of ±2°C. In summary:

•

When the temperature is equal or less than the TMST_COLD[3:0] threshold, the TMST_COLD interrupt bit of

the INT1 register is set, and the nINT pin is pulled low.

•

When the temperature is greater than TMST_COLD but lower then TMST_HOT, no action is taken.

22

TPS65186

www.ti.com

SLVSB04 –JULY 2011

•

When the temperature is equal or greater than the TMST_HOT[3:0] threshold, the TMST_HOT interrupt bit of

the INT1 register is set, and the nINT pin is pulled low.

If the last temperature is different from the baseline temperature by ±2°C (default) or more, the DTX interrupt

bit of the INT1 register is set. The latest temperature becomes the new baseline temperature. Please note

that by default the DTX interrupt is disabled, i.e. the nINT pin is not pulled low unless the DTX_EN bit was

previously set high.

•

If the last temperature change is less than ±2°C (default), no action is taken.

TYPICAL APPLICATION OF THE TEMPERATURE MONITOR

In a typical application the temperature monitor and interrupts are used in the following manner:

•

After the WAKEUP pin has been pulled high, the Application Processor (AP) writes 0x80h to the TMST1

register (address 0x0Dh). This starts the temperature measurement.

•

The AP waits for the EOC interrupt. Alternatively the AP can poll the CONV_END bit in register TMST1. This

will notify the AP that the A/D conversion is complete and the new temperature reading is available in the

TMST_VALUE register (address (0x00h).

•

The AP reads the temperature value from the TMST_VALUE register (address (0x00h).

If the temperature changes by ±2°C (default) or more from the first reading, the processor is notified by the

DTX interrupt. The A/P may or may not decide to select a different set of wave forms to drive the panel.

•

If the temperature is outside the allowed operating range of the panel, the processor is notified by the THOT

and TCOLD interrupts, respectively. It may or may not decide to continue with the page update.

Once an over/under temperature has been detected, the AP should reset the TMST_HOT_EN or

TMST_COLD_EN bits, respectively, to avoid the nINT pin to be continuously pulled low. The TMST_HOT and

TMST_COLD interrupt bits then should be polled continuously, to determine when the panel temperature

recovers to the normal operating range. Once the temperature has recovered, the TMST_HOT_EN or

TMST_COLD_EN bits should be set to ‘1’ again and normal operation can resume.

I²C BUS OPERATION

The TPS65186 hosts a slave I²C interface that supports data rates up to 400 kbit/s and auto-increment

addressing and is compliant to I²C standard 3.0.

Slave Address + R/nW

Reg Address

Data

R/nW

S

A6 A5 A4 A3 A2 A1 A0

A

S7 S6 S5 S4 S3 S2 S1 S0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

P

S

Start Condition

Read / not Write

A

P

Acknowledge

A6 ... A0 Device Address

S7 ... S0 Sub-Address

D7 ... D0 Data

R/nW

Stop Condition

Figure 28. Subaddress in I²C Transmission

The I²C Bus is a communications link between a controller and a series of slave terminals. The link is established

using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is

sourced from the controller in all cases where the serial data line is bi-directional for data communication

between the controller and the slave terminals. Each device has an open drain output to transmit data on the

serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high

during data transmission.

Data transmission is initiated with a start bit from the controller as shown in Figure 30. The start condition is

recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon

reception of a start bit, the device will receive serial data on the SDA input and check for valid address and

control information. If the appropriate slave address bits are set for the device, then the device will issue an

acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte

received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data

from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the

23

TPS65186

SLVSB04 –JULY 2011

www.ti.com

reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the

SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the

low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and

data words. The I²C interfaces will auto-sequence through register addresses, so that multiple data words can be

sent for a given I²C transmission. Reference Figure 29 and Figure 30 for deail.

S

SLAVE ADDRESS

W A

REG ADDRESS

A

DATA_REGADDR

A

DATA _{SUBADDR +n}

n bytes + ACK

A

DATA _{SUBADDR +n+1}

Ā

P

S

SLAVE ADDRESS

W A

REG ADDRESS

A

S

SLAVE ADDRESS

R

A

DATA_REGADDR

A

Ā

DATA_{REGADDR +n}

n bytes + ACK

DATA_{REGADDR +n+1}

P

From master to slave

From slave to master

R Read (high)

W Write (low)

S Start

P Stop

Ā

Not Acknowlege

A Acknowlege

TOP: Master writes data to slave.

BOTTOM: Master reads data from slave.

Figure 29. I²C Data Protocol

SDA

SCL

1-7

8

9

1-7

8

9

1-7

8

9

S

P

START

ADDRESS R/W ACK

DATA

ACK

DATA

STOP

ACK/

nACK

Figure 30. I²C Start/Stop/Acknowledge Protocol

SDA

SCL

t_SU;DAT

t_f

t_LOW

t_r

t_HD;STA

t_SP

t_r

t_BUF

t_HD;STA

t_SU;STA

t_SU;STO

t_f

t_HD;DATt_HIGH

S

S_r

P

S

Figure 31. I²C Data Transmission Timing

24

TPS65186

www.ti.com

SLVSB04 –JULY 2011

DATA TRANSMISSION TIMING

V_BAT= 3.6 V ±5%, T_A= 25ºC, C_L= 100 pF (unless otherwise noted)

PARAMETER

Serial clock frequency

TEST CONDITIONS

MIN

100

TYP

MAX

UNIT

f_(SCL)

400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

4

600

4.7

1.3

4

µs

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

t_HD;STA

ns

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

LOW period of the SCL clock

µs

ns

µs

ns

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

600

4.7

600

0

3.45

900

µs

0

ns

250

100

Data set-up time

ns

1000

300

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Bus Free Time Between Stop and Start Condition

t_f

4

600

4.7

1.3

n/a

0

µs

t_SU;STO

t_BUF

t_SP

ns

µs

ns

pF

n/a

50

Pulse width of spikes which mst be suppressed

by the input filter

400

C_b

Capacitive load for each bus line

25

TPS65186

SLVSB04 –JULY 2011

www.ti.com

REGISTER ADDRESS MAP

REGISTER

ADDRESS (HEX)

NAME

TMST_VALUE

ENABLE

VADJ

DESCRIPTION

0

1

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

Thermistor value read by ADC

Enable/disable bits for regulators

VPOS/VNEG voltage adjustment

Voltage settings for VCOM

Voltage settings for VCOM + control

Interrupt enable group1

2

3

VCOM1

VCOM2

INT_EN1

INT_EN2

INT1

4

5

6

Interrupt enable group2

7

Interrupt group1

8

INT2

Interrupt group2

9

UPSEQ0

UPSEQ1

DWNSEQ0

DWNSEQ1

TMST1

Power-up strobe assignment

Power-up sequence delay times

Power-down strobe assignment

Power-down sequence delay times

Thermistor configuration

10

11

12

13

14

15

16

TMST2

Thermistor hot temp set

PG

Power good status each rails

Device revision ID information

REVID

THERMISTOR READOUT (TMST_VALUE)

Address – 0x00h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

TMST_VALUE[7:0]

R

N/A

FIELD NAME

BIT DEFINITION

Temperature read-out

1111 0110 – < -10°C

1111 0110 – -10°C

1111 0111 – -9°C

...

1111 1110 – -2°C

1111 1111 – -1 °C

0000 0000 – 0 °C

0000 0001 – 1°C

0000 0010 – 2°C

...

TMST_VALUE[7:0]

0001 1001 – 25°C

...

0101 0101 – 85°C

0101 0101 – > 85°C

26

TPS65186

www.ti.com

SLVSB04 –JULY 2011

ENABLE (ENABLE)

Address – 0x01h

DATA BIT

D7

ACTIVE

R/W

D6

D5

D4

D3

D2

D1

D0

VNEG_EN

R/W

FIELD NAME

READ/WRITE

RESET VALUE

STANDBY V3P3_EN VCOM_EN VDDH_EN VPOS_EN

VEE_EN

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

FIELD NAME

BIT DEFINITION⁽¹⁾

STANDBY to ACTIVE transition bit

1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by UPSEQx registers

ACTIVE

0 – no effect

NOTE: After transition bit is cleared automatically

STANDBY to ACTIVE transition bit

1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by DWNSEQx registers

STANDBY

0 – no effect

NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE.

VIN3P3 to V3P3 switch enable

V3P3_EN

VCOM_EN

VDDH_EN

1 – switch is ON

0 – switch is OFF

VCOM buffer enable

1 – enabled

0 – disabled

VDDH charge pump enable

1 – enabled

0 – disabled

VPOS LDO regulator enable

1 – enabled

VPOS_EN

VEE_EN

0 – disabled

NOTE: VPOS cannot be enabled before VNEG is enabled.

VEE charge pump enable

1 – enabled

0 – disabled

VNEG LDO regulator enable

1 – enabled

VNEG_EN

0 – disabled

NOTE: When VNEG is disabled VPOS will also be disabled.

(1) Enable bits always reflect actual status of the corresponding rail.

27

TPS65186

SLVSB04 –JULY 2011

www.ti.com

VOLTAGE ADJUSTMENT REGISTER (VADJ)

Address – 0x02h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

not used

R/W

D6

not used

R/W

D5

not used

R/W

D4

not used

R/W

D3

D2

D1

VSET[2:0]

R/W

D0

not used

R

0

R/W

0^E2

R/W

1^E2

0

1

0

1^E2

FIELD NAME

not used

BIT DEFINITION

N/A

VPOS and VNEG voltage setting

000 - not valid

001 - not valid

010 - not valid

VSET[2:0]

011 - ±15.000 V

100 - ±14.750 V

101 - ±14.500 V

110 - ±14.250 V

111 - reserved

VCOM 1 (VCOM1)

Address – 0x03h

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

FIELD NAME

READ/WRITE

RESET VALUE

VCOM [7:0]

R/W

0^E2

R/W

1^E2

R/W

1^E2

R/W

1^E2

R/W

1

R/W

1

R/W

0

R/W

1

FIELD NAME

BIT DEFINITION

VCOM voltage, least significant byte. See VCOM2 register for details.

VCOM[7:0]

28

TPS65186

www.ti.com

SLVSB04 –JULY 2011

VCOM 2 (VCOM2)

Address – 0x04h

DATA BIT

D7

ACQ

R/W

0

D6

PROG

R/W

0

D5

HiZ

R/W

0

D4

D3

D2

not used

R/W

D1

D0

VCOM[8]

R/W

FIELD NAME

READ/WRITE

RESET VALUE

AVG[1:0]

not used

R/W

0

R/W

0

R/W

0

1

0^E2

FIELD NAME

BIT DEFINITION

Kick-back voltage acquisition bit

1 – starts kick-back voltage measurement routine

0 – no effect

ACQ

NOTE: After measurement is complete bit is cleared automatically and measurement result is

reflected in VCOM[8:0] bits.

VCOM programming bit

1 – VCOM[8:0] value is committed to non-volatile memory and becomes new power-up default

PROG

HiZ

0 – no effect

NOTE: After programming bit is cleared automatically and TPS65186 will enter STANDBY mode.

VCOM HiZ bit

1 – VCOM pin is placed into hi-impedance state to allow VCOM measurement

0 – VCOM amplifier is connected to VCOM pin

Number of acquisitions that is averaged to a single kick-back voltage measurement

00 – 1x

01 – 2x

10 – 4x

11 – 8x

AVG[1:0]

NOTE: When the ACQ bit is set, the state machine repeat the A/D conversion of the kick-back

voltage AVD[1:0] times and returns a single, averaged, value to VCOM[8:0]

not used

N/A

VCOM voltage adjustment

VCOM = VCOM[8:0] x -10 mV in the range from 0 mV to -5.110 V

0x000h – 0 0000 0000 – -0 mV

0x001h – 0 0000 0001 – -10 mV

0x002h – 0 0000 0010 – -20 mV

...

VCOM[8:0]

0x07Dh - 0 0111 1101 - -1250 mV

...

0x1FEh – 1 1111 1110 – -5100 mV

0x1FFh – 1 1111 1111 – -5110 mV

29

TPS65186

SLVSB04 –JULY 2011

www.ti.com

INTERRUPT ENABLE 1 (INT_EN1)

Address – 0x05h

DATA BIT

D7

D6

D5

D4

D3

D2

D1

D0

TMST_HOT TMST_COLD

FIELD NAME

DTX_EN

TSD_EN

HOT_EN

UVLO_EN

ACQC_EN

PRGC_EN

_EN

R/W

1

_EN

R/W

1

READ/WRITE

R

0

R/W

1

R/W

1

R/W

1

R

1

R

1

RESET VALUE

FIELD NAME

BIT DEFINITION⁽¹⁾

Panel temperature-change interrupt enable

1 – enabled

DTX_EN

0 – disabled

Thermal shutdown interrupt enable

1 – enabled

TSD_EN

HOT_EN

0 – disabled

Thermal shutdown early warning enable

1 – enabled

0 – disabled

Thermistor hot interrupt enable

1 – enabled

TMST_HOT_EN

TMST_COLD_EN

UVLO_EN

0 – disabled

Thermistor cold interrupt enable

1 – enabled

0 – disabled

VIN under voltage detect interrupt enable

1 – enabled

0 – disabled

VCOM acquisition complete interrupt enable

1 – enabled

ACQC_EN

0 – disabled

VCOM programming complete interrupt enable

1 – enabled

PRGC_EN

0 – disabled

(1) Enabled means nINT pin is pulled low when interrupt occurs.

Disabled means nINT pin is not pulled low when interrupt occurs.

30

TPS65186

www.ti.com

SLVSB04 –JULY 2011

INTERRUPT ENABLE 2 (INT_EN2)

Address – 0x06h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

VBUVEN

R/W

D6

VDDHUVEN

R/W

D5

VNUV_EN

R/W

D4

VPOSUVEN

R/W

D3

VEEUVEN

R/W

D2

D1

D0

EOCEN

R/W

1

VCOMFEN VNEGUVEN

R/W

1

R/W

1

FIELD NAME

BIT DEFINITION⁽¹⁾

Positive boost converter under voltage detect interrupt enable

VBUVEN

1 – enabled

0 – disabled

VDDH under voltage detect interrupt enable

VDDHUVEN

VNUVEN

1 – enabled

0 – disabled

Inverting buck-boost converter under voltage detect interrupt enable

1 – enabled

0 – disabled

VPOS under voltage detect interrupt enable

VPOSUVEN

VEEUVEN

VCOMFEN

VNEGUVEN

EOCEN

1 – enabled

0 – disabled

VEE under Voltage detect interrupt enable

1 – enabled

0 – disabled

VCOM FAULT interrupt enable

1 – enabled

0 – disabled

VNEG under Voltage detect interrupt enable

1 – enabled

0 – disabled

Temperature ADC end of conversion interrupt enable

1 – enabled

0 – disabled

(1) Enabled means nINT pin is pulled low when interrupt occurs.

Disabled means nINT pin is not pulled low when interrupt occurs.

31

TPS65186

SLVSB04 –JULY 2011

www.ti.com

INTERRUPT 1 (INT1)

Address – 0x07h

DATA BIT

D7

DTX

R

D6

TSD

R

D5

HOT

R

D4

D3

D2

UVLO

R

D1

ACQC

R

D0

PRGC

R

FIELD NAME

TMST_HOT TMST_COLD

READ/WRITE

RESET VALUE

R

0

N/A

0

FIELD NAME

BIT DEFINITION

Panel temperature-change interrupt

DTX

1 – temperature has changed by 3 deg or more over previous reading

0 – no significance

Thermal shutdown interrupt

TSD

HOT

1 – chip is in over-temperature shutdown

0 – no fault

Thermal shutdown early warning

1 – chip is approaching over-temperature shutdown

0 – no fault

Thermistor hot interrupt

TMST_HOT

TMST_COLD

UVLO

1 – thermistor temperature is equal or greater than TMST_HOT threshold

0 – no fault

Thermistor cold interrupt

1 – thermistor temperature is equal or less than TMST_COLD threshold

0 – no fault

VIN under voltage detect interrupt

1 – input voltage is below UVLO threshold

0 – no fault

VCOM acquisition complete

ACQC

1 – VCOM measurement is compete

0 – no significance

VCOM programming complete

1 – VCOM programming is complete

0 – no significance

PRGC

32

TPS65186

www.ti.com

SLVSB04 –JULY 2011

INTERRUPT 2 (INT2)

Address – 0x08h

DATA BIT

D7

VB_UV

R

D6

VDDH_UV

R

D5

VN_UV

R

D4

VPOS_UV

R

D3

VEE_UV

R

D2

VCOMF

R

D1

D0

EOC

R

FIELD NAME

READ/WRITE

RESET VALUE

VNEG_UV

R

N/A

FIELD NAME

BIT DEFINITION

Positive boost converter under voltage detect interrupt

1 – under-voltage on DCDC1 detected

0 – no fault

VB_UV

VDDH under voltage detect interrupt

1 – under-voltage on VDDH charge pump detected

0 – no fault

VDDH_UV

VN_UV

Inverting buck-boost converter under voltage detect interrupt

1 – under-voltage on DCDC2 detected

0 – no fault

VPOS under voltage detect interrupt

1 – under-voltage on LDO1(VPOS) detected

0 – no fault

VPOS_UV

VEE_UV

VCOMF

VNEG_UV

EOC

VEE under Voltage detect interrupt

1 – under-voltage on VEE charge pump detected

0 – no fault

VCOM fault detection

1 – fault on VCOM detected (VCOM is outside normal operating range)

0 – no fault

VNEG under Voltage detect interrupt

1 – under-voltage on LDO2(VNEG) detected

0 – no fault

ADC end of conversion interrupt

1 – ADC conversion is complete (temperature acquisition is complete)

0 – no significance

33

TPS65186

SLVSB04 –JULY 2011

www.ti.com

POWER UP SEQUENCE REGISTER 0 (UPSEQ0)

Address – 0x09h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

VDDH_UP[1:0]

R/W R/W

1^E21^E2

D6

D5

VPOS_UP[1:0]

R/W R/W

1^E20^E2

D4

D3

D2

D1

VNEG_UP[1:0]

R/W R/W

0^E20^E2

D0

VEE_UP[1:0]

R/W

0^E2

R/W

1^E2

FIELD NAME

BIT DEFINITION

VDDH power-up order

00 – power up on STROBE1

01 – power up on STROBE2

10 – power up on STROBE3

11 – power up on STROBE4

VPOS power-up order

VDDH_UP[1:0]

00 – power up on STROBE1

01 – power up on STROBE2

10 – power up on STROBE3

11 – power up on STROBE4

VEE power-up order

VPOS_UP[1:0]

VEE_UP[1:0]

00 – power up on STROBE1

01 – power up on STROBE2

10 – power up on STROBE3

11 – power up on STROBE4

VNEG power-up order

00 – power up on STROBE1

01 – power up on STROBE2

10 – power up on STROBE3

11 – power up on STROBE4

VNEG_UP[1:0]

6ms

48ms

VDDH

VPOS

VNEG

VEE

Figure 32. Default Power-Up/Down Sequence

34

TPS65186

www.ti.com

SLVSB04 –JULY 2011

POWER UP SEQUENCE REGISTER 1 (UPSEQ1)

Address – 0x0Ah

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

UDLY4[1:0]

UDLY3[1:0]

UDLY2[1:0]

UDLY1[1:0]

R/W

0^E2

R/W

1^E2

R/W

0^E2

R/W

1^E2

R/W

0^E2

R/W

1^E2

R/W

0^E2

R/W

1^E2

FIELD NAME

BIT DEFINITION

DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up.

00 – 3 ms

UDLY4[1:0]

01 – 6 ms

10 – 9 ms

11 – 12 ms

DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up.

00 – 3 ms

UDLY3[1:0]

UDLY2[1:0]

UDLY1[1:0]

01 – 6 ms

10 – 9 ms

11 – 12 ms

DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up.

00 – 3 ms

01 – 6 ms

10 – 9 ms

11 – 12 ms

DLY1 delay time set; defines the delay time from VN_PG high to STROBE1 during power-up.

00 – 3 ms

01 – 6 ms

10 – 9 ms

11 – 12 ms

35

TPS65186

SLVSB04 –JULY 2011

www.ti.com

POWER DOWN SEQUENCE REGISTER 0 (DWNSEQ0)

Address – 0x0Bh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

VDDH_DWN[1:0]

VPOS_DWN[1:0]

VEE_DWN[1:0]

VNEG_DWN[1:0]

R/W

0^E2

R/W

0^E2

R/W

0^E2

R/W

1^E2

R/W

1^E2

R/W

1^E2

R/W

1^E2

R/W

0^E2

FIELD NAME

BIT DEFINITION

VDDH power-down order

00 – power down on STROBE1

01 – power down on STROBE2

10 – power down on STROBE3

11 – power down on STROBE4

VPOS power-down order

VDDH_DWN[1:0]

00 – power down on STROBE1

01 – power down on STROBE2

10 – power down on STROBE3

11 – power down on STROBE4

VEE power-down order

VPOS_DWN[1:0]

VEE_DWN[1:0]

VNEG_DWN[1:0]

00 – power down on STROBE1

01 – power down on STROBE2

10 – power down on STROBE3

11 – power down on STROBE4

VNEG power-down order

00 – power down on STROBE1

01 – power down on STROBE2

10 – power down on STROBE3

11 – power down on STROBE4

36

TPS65186

www.ti.com

SLVSB04 –JULY 2011

POWER DOWN SEQUENCE REGISTER 1 (DWNSEQ1)

Address – 0x0Ch

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

DFCTR

R/W

DDLY4[1:0]

DDLY3[1:0]

DDLY2[1:0]

DDLY1

R/W

0^E2

R/W

1^E2

R/W

1^E2

R/W

1^E2

R/W

0^E2

R/W

0^E2

R/W

0^E2

FIELD NAME

BIT DEFINITION

DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-down.

00 – 6 ms

DDLY4[1:0]

01 – 12 ms

10 – 24 ms

11 – 48 ms

DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-down.

00 – 6 ms

DDLY3[1:0]

DDLY2[1:0]

01 – 12 ms

10 – 24 ms

11 – 4 8ms

DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-down.

00 – 6 ms

01 – 12 ms

10 – 24 ms

11 – 48 ms

DLY2 delay time set; defines the delay time from WAKEUP low to STROBE1 during power-down.

DDLY1

DFCTR

0 – 3 ms

1 – 6 ms

At power-down delay time DLY2[1:0], DLY3[1:0], DLY4[1:0] are multiplied with DFCTR[1:0]

0 – 1x

1 – 16x

37

TPS65186

SLVSB04 –JULY 2011

www.ti.com

THERMISTOR REGISTER 1 (TMST1)

Address – 0x0Dh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

not used

R/W

D5

D4

not used

R/W

D3

not used

R/W

D2

not used

R/W

D1

D0

READ_THERM

CONV_END

DT[1:0]

R/W

0

R

1

R/W

0

R/W

0

FIELD NAME

BIT DEFINITION

Read thermistor value

1 – initiates temperature acquisition

0 – no effect

READ_THERM

NOTE: Bit is self-cleared after acquisition is completed

not used

N/A

ADC conversion done flag

CONV_END

1 – conversion is finished

0 – conversion is not finished

not used

N/A

Panel temperature-change interrupt threshold

00 – 2°C

01 – 3°C

10 – 4°C

11 – 5°C

DT[1:0]

DTX interrupt is issued when difference between most recent temperature reading and baseline

temperature is equal to or greater than threshold value. See “HOT, COLD, and temperature-change

interrupts” section for details.

38

TPS65186

www.ti.com

SLVSB04 –JULY 2011

THERMISTOR REGISTER 2 (TMST2)

Address – 0x0Eh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

TMST_COLD[3:0]

TMST_HOT[3:0]

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

0

R/W

0

R/W

0

FIELD NAME

BIT DEFINITION

Thermistor COLD threshold

0000 – -7°C

0001 – -6°C

0010 – -5°C

0011 – -4°C

0100 – -3°C

0101 – -2°C

0110 – -1°C

0111 – 0°C

TMST_COLD [3:0]

1000 – 1°C

1001 – 2°C

1010 – 3°C

1011 – 4°C

1100 – 5°C

1101 – 6°C

1110 – 7°C

1111 – 8°C

NOTE: An interrupt is issued when thermistor temperature is equal or less than COLD threshold

Thermistor HOT threshold

0000 – 42°C

0001 – 43°C

0010 – 44°C

0011 – 45°C

0100 – 46°C

0101 – 47°C

0110 – 48°C

0111 – 49°C

TMST_HOT [3:0]

1000 – 50°C

1001 – 51°C

1010 – 52°C

1011 – 53°C

1100 – 54°C

1101 – 55°C

1110 – 56°C

1111 – 57°C

NOTE: An interrupt is issued when thermistor temperature is equal or greater than HOT threshold

39

TPS65186

SLVSB04 –JULY 2011

www.ti.com

POWER GOOD STATUS (PG)

Address – 0x0Fh

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

VB_PG

VDDH_PG

VN_PG

VPOS_PG

VEE_PG

not used

VNEG_PG

not used

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

FIELD NAME

BIT DEFINITION⁽¹⁾

Positive boost converter power good

VB_PG

1 – DCDC1 is in regulation

0 – DCDC1 is not in regulation or turned off

VDDH power good

VDDH_PG

VN_PG

1 – VDDH charge pump is in regulation

0 – VDDH charge pump is not in regulation or turned off

Inverting buck-boost power good

1 – DCDC2 is in regulation

0 – DCDC2 is not in regulation or turned off

VPOS power good

VPOS_PG

1 – LDO1(VPOS) is in regulation

0 – LDO1(VPOS) is not in regulation or turned off

VEE power good

VEE_PG

not used

VNEG_PG

not used

1 – VEE charge pump is in regulation

0 – VEE charge pump is not in regulation or turned off

N/A

VNEG power good

1 – LDO2(VNEG) is in regulation

0 – LDO2(VNEG) is not in regulation or turned off

N/A

(1) PG pin is pulled hi (HiZ state) when VDDH_PG = VPOS_PG = VEE_PG = VNEG_PG = 1

REVISION AND VERSION CONTROL (REVID)

Address – 0x10h

DATA BIT

FIELD NAME

READ/WRITE

RESET VALUE

D7

D6

D5

D4

D3

D2

D1

D0

REVID[7:0]

R

0

R

1

R

0

R

0

R

0^E2

R

1^E2

R

0^E2

R

1^E2

FIELD NAME

REVID[7:6]

REVID[5:4]

REVID[3:0]

BIT DEFINITION

MJREV

MNREV

VERSION

0100 0101 - TPS65186 1p0

REVID [7:0]

0101 0101 – TPS65186 1p1

0110 0101 – TPS65186 1p2

40

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65186RGZR

TPS65186RGZT

VQFN

RGZ

48

2500

250

330.0

180.0

16.4

7.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS65186RGZR

TPS65186RGZT

VQFN

RGZ

48

2500

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65186RGZR
厂家：	TEXAS INSTRUMENTS
描述：	PMIC，用于启用 E-Ink® Vizplex™ 技术的电子纸显示器 \| RGZ \| 48 \| -10 to 85 电子集成电源管理电路电源电路显示器
文件：	总47页 (文件大小：2587K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65186RGZR [TI]

相关型号：

TPS65186RGZT

TPS65190

TPS65190RHDR

TPS65191

TPS65191RHBR

TPS65192

TPS65192RHDR

TPS65192RHDT

TPS65193

TPS65193RGE

TPS65193RGER

TPS65194