TPS65185RSLR [TI]
PMIC FOR E Ink Vizplex ENABLED ELECTRONIC PAPER; PMIC，用于E Ink公司的Vizplex启用电子纸
| 型号： | TPS65185RSLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PMIC FOR E Ink Vizplex ENABLED ELECTRONIC PAPER |
| 文件： | 总48页 (文件大小：2428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
PMIC FOR E Ink® Vizplex™ ENABLED ELECTRONIC PAPER
DISPLAY
Check for Samples: TPS65185
1
FEATURES
•
•
Active Discharge on All Rails
Flexible Power-Up and Power Down
Sequencing
2345
•
Single Chip Power Management Solution for
E Ink® Vizplex™ Electronic Paper Displays
•
•
Integrated 10-Ω, 3.3-V Power Switch for
Disabling System Power Rail to E-Ink Panel
•
Generates Positive and Negative Gate and
Source Driver Voltages and Back-Plane Bias
from a Single, Low-Voltage Input Supply
Thermistor Monitoring
•
•
•
•
Supports 9.7 Inch and Larger Panel Size
3-V to 6-V Input Voltage Range
–
–10°C to 85°C Temperature Range
–
±1°C Accuracy from 0°C to 50°C
Boost Converter for Positive Rail Base
•
•
I2C Serial Interface
Slave Address 0x68h
Package Options:
Inverting Buck-Boost Converter for Negative
Rail Base
–
•
Two Adjustable LDOs for Source Driver
Supply
–
48-Pin, 0.5 mm Pitch,
7 mm x 7 mm x 0.9 mm (QFN) RGZ
–
–
LDO1: 15 V, 120 mA (VPOS)
–
48-Pin, 0.4 mm Pitch,
6 mm x 6 mm x 0.9 mm (QFN) RSL
LDO2: –15 V, 120 mA (VNEG)
•
•
Accurate Output Voltage Tracking
VPOS - VNEG = ±50 mV
Two Charge Pumps for Gate Driver Supply
APPLICATIONS
–
•
Power Supply for Active Matrix E Ink®
Vizplex™ Panels
–
–
CP1: 22 V, 10 mA (VDDH)
•
•
•
•
EPD Power Supply
CP2: –20 V, 12 mA, (VEE)
E-Book Readers
EPSON® S1D13522 (ISIS) Timing Controller
EPSON® S1D13521 (Broadsheet) Timing
Controller
•
Adjustable VCOM Driver for Accurate
Panel-Backplane Biasing
–
–
–
–
User Programmable Default
0 V to -5.11 V
•
Application Processors With Integrated or
± 1.5% accuracy (±10 mV)
9-Bit Control (10-mV Nominal Step Size)
Software Timing Controller ( OMAP™)
DESCRIPTION
The TPS65185 is a single-chip power supply designed to for E Ink® Vizplex™ displays used in portable e-reader
applications and supports panel sizes up to 9.7 inches and greater. Two high efficiency DC/DC boost converters
generate ±16-V rails which are boosted to 22 V and –20 V by two change pumps to provide the gate driver
supply for the Vizplex™ panel. Two tracking LDOs create the ±15-V source driver supplies which support up to
120-mA of output current. All rails are adjustable through the I2C interface to accommodate specific panel
requirements.
Accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 V to -5.11 V with 9-bit
control through the serial interface and can source or sink current depending on panel condition. The TPS65185
supports automatic panel kickback voltage measurement which eliminates the need of manual VCOM calibration
in the production line. The measurement result can be stored in non-volatile memory to become the new VCOM
power-up default value.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
5
OMAP is a trademark of Texas Instruments.
Vizplex is a trademark of E Ink Corporation.
E Ink is a registered trademark of E Ink Corporation.
EPSON is a registered trademark of Seiko Epson Corporation.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2011, Texas Instruments Incorporated
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
TPS65185 is available in two packages, a 48-pin 7x7 mm2 QFN with 0.5-mm pitch and a 48-pin 6x6 mm2 QFN
with 0.4-mm pitch.
FUNCTIONAL BLOCK DIAGRAM
10uF
10uF
2.2uH
VIN_P
From Battery
(3.0V-6.0V)
VB_SW
From Battery
(3.0V-6.0V)
4.7uH
VN_SW
VN
4.7uF
DCDC1
DCDC2
PGND1
VB
4.7uF
VDDH_IN
VEE_IN
100n
100n
VDDH_D
VDDH_DRV
VDDH_FB
VEE_D
VEE
(-20V)
VDDH (22V)
VDDH
CHARGE
PUMP
VEE
CHARGE
PUMP
VEE_DRV
VEE_FB
1M
1M
2.2uF
10nF
10nF
2.2uF
1k
1k
47.5k
VDDH_DIS
VEE_DIS
52.3k
PGND2
PGND2
VDDH_EN
VEE_EN
PGND2
4.7uF
4.7uF
PGND2
PGND2
VPOS_IN
VNEG_IN
VPOS
VNEG
VNEG
(-15V)
VPOS (15V)
LDO1
LDO2
1k
1k
VPOS_DIS
VNEG_DIS
4.7uF
4.7uF
VPOS_EN
VNEG_EN
PGND2
PGND2
10k NTC
43k
PBKG
TS
PowerPad®
TEMP
SENSOR
TMST_VALUE[7:0]
INT_LDO
AGND2
ADC
VIN
INT_LDO
From Input Supply
(3.0V-6.0V)
4.7uF
4.7uF
10uF
4.7uF
VREF
VREF
AGND1
VCOM
To panel back-plane
(0 to-5.11V)
VCOM[8:0]
VCOM_CTRL
DAC
4.7uF
From uC
VCOM_PWR
VIN3P3
1k
VCOM_DIS
3.3V supply from system
To EPD panel
V3P3_EN
GATE DRIVER
V3P3
1k
10k
10k
VIO
VIO
SDA
SCL
From uC
10k
10k
VIO
VIO
From/to uC or DSP
From uC
INT
PWRUP
WAKEUP
DGND
To uC
To uC
DIGITAL
CORE
PWR_GOOD
From uC
2
Copyright © 2011, Texas Instruments Incorporated
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
ORDERING INFORMATION(1)
TA
-10°C to 85°C
PACKAGE(2)
RGZ
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS65185RGZR
TBD
TBD
RSL
TPS65185RSLR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVICE INFORMATION
RGZ OR RSL PACKAGE
(TOP VIEW)
VDDH_IN – 37
N/C – 38
24 – VIN_P
23 – PWR_GOOD
22 – PBKG
N/C – 39
VB_SW – 40
PGND1 – 41
VB – 42
21 – PWRUP
20 – N/C
19 – VPOS_DIS
18 – SDA
VPOS_IN – 43
VPOS – 44
VIN3P3 – 45
V3P3 – 46
TS – 47
17 – SCL
16 – VCOM_PWR
15 – VCOM
14 – VCOM_DIS
13 – N/C
AGND2 – 48
TERMINAL FUNCTIONS(3)
TERMINAL
I/O
DESCRIPTION
NAME
VREF
INT
NO.
1
O
O
O
I
Filter pin for 2.25-V internal reference to ADC
Open drain interrupt pin (active low)
2
VNEG
3
Negative supply output pin for panel source drivers
VNEG_IN
4
Input pin for LDO2 (VNEG)
Wake up pin (active high). Pull this pin high to wake up from sleep mode. IC accepts I2C
commands after WAKEUP pin is pulled high but power rails remain disabled until
PWRUP pin is pulled high.
WAKEUP
5
I
DGND
6
7
Digital ground. Connect to ground plane.
Filter pin for 2.7-V internal supply
INT_LDO
O
(3) There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively.
Copyright © 2011, Texas Instruments Incorporated
3
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
TERMINAL
I/O
DESCRIPTION
Analog ground for general analog circuitry
NAME
NO.
AGND1
8
Discharge pin for VNEG. Connect to VNEG to discharge VNEG to ground whenever the
rail is disabled. Leave floating if discharge function is not desired.
VNEG_DIS
9
O
I
VIN
N/C
10
11
Input power supply to general circuitry
Not internally connected
VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low
and VN is enabled, VCOM discharge is enabled.
VCOM_CTRL
N/C
12
13
14
I
Not internally connected
Discharge pin for VCOM. Connect to ground to discharge VCOM to ground whenever
VCOM is disabled. Leave floating if discharge function is not desired.
VCOM_DIS
I
VCOM
VCOM_PWR
SCL
15
16
17
18
O
I
Filter pin for panel common-voltage driver
Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.
Serial interface (I2C) clock input
Serial interface (I2C) data input/output
I
SDA
I/O
Discharge pin for VPOS. Connect a resistor from VPOS_DIS to VPOS to discharge
VPOS to ground whenever the rail is disabled. Leave floating if discharge function is not
desired.
VPOS_DIS
19
I
I
N/C
20
21
Not internally connected
PWRUP
Power-up pin. Pull this pin high to power-up all output rails.
Die substrate. Connect to VN (-16 V) with short, wide trace. Wide copper trace will
improve heat dissipation.
PBKG
22
23
Open drain power good output pin. Pin is pulled low when one or more rails are disabled
or not in regulation. DCDC1, DCDC2, and VCOM have no effect on this pin.
PWR_GOOD
O
VIN_P
24
25
I
Input power supply to inverting buck-boost converter (DCDC2)
Inverting buck-boost converter switch out (DCDC2)
VN_SW
O
Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and
VEE charge pump
VN
26
I
VEE_IN
27
28
I
Input supply pin for negative charge pump (CP2) (VEE)
Driver output pin for negative charge pump (CP2)
VEE_DRV
O
Discharge pin for VEE. Connect a resistor from VEE _DIS to VEE to discharge VEE to
ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VEE_DIS
29
I
VEE_D
VEE_FB
PGND2
30
31
32
33
34
O
I
Base voltage output pin for negative charge pump (CP2)
Feedback pin for negative charge pump (CP2)
Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps
Feedback pin for positive charge pump (CP1)
VDDH_FB
VDDH_D
I
O
Base voltage output pin for positive charge pump (CP1)
Discharge pin for VDDH. Connect to VDDH to discharge VDDH to ground whenever the
rail is disabled. Leave floating if discharge function is not desired.
VDDH_DIS
35
I
VDDH_DRV
VDDH_IN
N/C
36
37
38
39
40
41
O
I
Driver output pin for positive charge pump (CP1)
Input supply pin for positive charge pump (CP1)
Not internally connected
N/C
Not internally connected
VB_SW
PGND1
O
I
Boost converter switch out (DCDC1)
Power ground for DCDC1
Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge
pump
VB
42
VPOS_IN
VPOS
43
44
45
46
I
Input pin for LDO1 (VPOS)
O
I
Positive supply output pin for panel source drivers
Input pin to 3.3-V power switch
VIN3P3
V3P3
O
Output pin of 3.3-V power switch
4
Copyright © 2011, Texas Instruments Incorporated
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
TERMINAL
NAME
I/O
DESCRIPTION
NO.
47
Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor
between this pin and AGND.
TS
I
AGND2
48
Reference point to external thermistor and linearization resistor
Power Pad, internally connected to PBKG. Connect to VN with short, wide trace. Wide
copper trace will improve heat dissipation. PowerPad must not be connected to ground.
PowerPad
N/A
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)(2)
VALUE
–0.3 to 7
–0.3 to 0.3
UNIT
V
Input voltage range at VIN(2), VIN_P, VIN3P3
Ground pins to system ground
V
Voltage range at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB,
PWR_GOOD, nINT
–0.3 to 3.6
V
Voltage on VB, VB_SW, VPOS_IN, VPOS_DIS, VDDH_IN
VDDH_DIS
–0.3 to 20
–0.3 to 30
–20 to 0.3
–0.3 to 30
–5 to 0.3
–30 to 0.3
Internally limited
2
V
V
Voltage on VN, VEE_IN, VCOM_PWR, VNEG_DIS, VNEG_IN
Voltage from VIN_P to VN_SW
Voltage on VCOM_DIS
V
V
V
VEE_DIS
V
Peak output current
mA
W
Continuous total power dissipation
θJA
TJ
Junction-to-ambient thermal resistance(3)
Operating junction temperature
Operating ambient temperature(4)
Storage temperature
23
°C/W
°C
°C
°C
-10 to 125
-10 to 85
-65 to 150
±2000
TA
Tstg
(HBM) Human body model
ESD rating
V
(CDM) Charged device model
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and
2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.
(4) It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad
is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the
buck-boost output will help heat dissipated efficiently.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage range at VIN, VIN_P, VIN3P3
3
3.7
6
V
Voltage range at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL,
VDDH_FB, VEE_FB, PWR_GOOD, nINT
0
3.6
V
TA
TJ
Operating ambient temperature range
Operating junction temperature range
–10
–10
85
°C
°C
125
Copyright © 2011, Texas Instruments Incorporated
5
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
RECOMMENDED EXTERNAL COMPONENTS
PART NUMBER
INDUCTORS
VALUE
SIZE
MANUFACTURER
LQH44PN4R7MP0
NR4018T4R7M
VLS252015ET-2R2M
NR4012T2R2M
CAPACITORS
GRM21BC81E475KA12L
GRM32ER71H475KA88L
All other caps
4.7 µH
4.7 µH
2.2 µH
2.2 µH
4 mm x 4 mm x 1.65 mm
4 mm x 4 mm x 1.8 mm
2 mm x 2.5 mm x 1.5 mm
4 mm x 4 mm x 1.2 mm
Murata
Taiyo Yuden
TDK
Taiyo Yuden
4.7 µF, 25 V, X6S
4.7 µF, 50 V, X7R
X5R or better
805
Murata
Murata
1210
DIODES
BAS3010
SOD-323
SOD-123
SOT-23
Infineon
ON-Semi
Fairchild
MBR130T1
BAV99
THERMISTOR
NCP18XH103F03RB
10 KΩ
603
Murata
ELECTRICAL CHARACTERISTICS
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
INPUT VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Input voltage range
3
3.7
2.9
6
V
V
VUVLO
VHYS
Undervoltage lockout threshold
Undervoltage lockout hysteresis
VIN falling
VIN rising
400
mV
INPUT CURRENT
IQ
Operating quiescent current into VIN
Device switching, no load
Device in standby mode
Device in sleep mode
5.5
130
3.5
mA
µA
µA
ISTD
ISLEEP
Operating quiescent current into VIN
Shutdown current
10
INTERNAL SUPPLIES
VINT_LDO
CINT_LDO
VREF
Internal supply
2.7
4.7
V
µF
V
Nominal output capacitor
Internal supply
Capacitor tolerance ±10%
Capacitor tolerance ±10%
1
3.3
3
2.25
4.7
CREF
Nominal output capacitor
µF
DCDC1 (POSITIVE BOOST REGULATOR)
VIN
Input voltage range
Power good threshold
Power good time-out
Output voltage range
DC set tolerance
3.7
90
50
16
6
V
%
Fraction of nominal output voltage
Not tested in production
PG
ms
V
VOUT
-4.5
4.5
%
IOUT
Output current
250
mA
mΩ
A
RDS(ON)
MOSFET on resistance
Switch current limit
Switch current accuracy
Switching frequency
Inductor
VIN = 3.7 V
350
1.5(1)
ILIMIT
-30
1
30
%
fSW
1
2.2
MHz
µH
µF
mΩ
LDCDC1
CDCDC1
ESR
Nominal output capacitor
Output capacitor ESR
Capacitor tolerance ±10%
2x4.7
20
(1) Contact factory for 1-A, 2-A, or 2.5-A option.
6
Copyright © 2011, Texas Instruments Incorporated
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DCDC2 (INVERTING BUCK-BOOST REGULATOR)
VIN
Input voltage range
Power good threshold
Power good time-out
Output voltage range
DC set tolerance
3
3.7
90
6
V
%
Fraction of nominal output voltage
Not tested in production
PG
50
ms
V
-16
VOUT
-4.5
4.5
%
IOUT
Output current
250
mA
mΩ
A
RDS(ON)
MOSFET on resistance
Switch current limit
Switch current accuracy
Inductor
VIN = 3.7 V
350
1.5(2)
ILIMIT
-30
1
30
%
LDCDC1
CDCDC1
ESR
4.7
3x4.7
20
µH
µF
mΩ
Nominal output capacitor
Capacitor ESR
Capacitor tolerance ±10%
LDO1 (VPOS)
VPOS_IN Input voltage range
15.2
16
90
50
16.8
15
V
%
Power good threshold
Power good time-out
Fraction of nominal output voltage
Not tested in production
PG
ms
VIN = 16 V,
VSET[2:0] = 0x3h to 0x6h
VSET
Output voltage set value
14.25
-1
V
VINTERVAL Output voltage set resolution
VOUTTOL Output tolerance
VIN = 16 V
VSET = 15 V, ILOAD = 20 mA
ILOAD = 120 mA
250
mV
%
1
250
1
VDROPOUT Dropout voltage
mV
%
VLOADREG Load regulation – DC
ILOAD = 10% to 90%
ILOAD
ILIMIT
Load current range
120
mA
mA
Ω
Output current limit
120
800
-2
Discharge impedance to ground
Mismatch to any other RDIS
Nominal output capacitor
Enabled when rail is disabled
1000
4.7
1200
2
RDIS
%
CLDO1
Capacitor tolerance ±10%
1
µF
LDO2 (VNEG)
VNEG_IN Input voltage range
15.2
16
90
50
16.8
V
%
Power good threshold
Power good time-out
Fraction of nominal output voltage
Not tested in production
PG
ms
VIN = –16 V
VSET[2:0] = 0x3h to 0x6h
VSET
Output voltage set value
-15
-1
-14.25
V
VINTERVAL Output voltage set resolution
VOUTTOL Output tolerance
VIN = –16 V
VSET = –15 V, ILOAD = –20 mA
ILOAD = 120 mA
250
mV
%
1
250
1
VDROPOUT Dropout voltage
mV
%
VLOADREG Load regulation – DC
ILOAD = 10% to 90%
ILOAD
ILIMIT
Load current range
120
mA
mA
Ω
Output current limit
180
800
-2
Discharge impedance to ground
Mismatch to any other RDIS
Soft start time
Enabled when rail is disabled
1000
1200
2
RDIS
%
TSS
Not tested in production
1
ms
µF
CLDO2
Nominal output capacitor
Capacitor tolerance ±10%
1
4.7
(2) Contact factory for 1-A, 2-A, or 2.5-A option.
Copyright © 2011, Texas Instruments Incorporated
7
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
MAX UNIT
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
LD01 (POS) AND LDO2 (VNEG) TRACKING
VSET = ±15 V,
ILOAD = ±20 mA, 0°C to 60°C
VDIFF
Difference between VPOS and VNEG
-50
50
mV
VCOM DRIVER
IVCOM Drive current
15
mA
V
Outside this range VCOM is shut down
and VCOMF interrupt is set
Allowed operating range
-5.5
-0.8
1
VCOM[8:0] = 0x07Dh
(-1.25 V), VIN = 3.4 V to 4.2 V, no load
0.8
Accuracy
%
VCOM[8:0] = 0x07Dh
(-1.25 V), VIN = 3.0 V to 6.0 V, no load
VCOM
-1.5
1.5
0
Output voltage range
-5.11
V
Resolution
1LSB
VCOM calibration
HiZ = 1
10
mV
Max number of EEPROM writes
Input impedance, HiZ state
Discharge impedance to ground
Mismatch to any other RDIS
Nominal output capacitor
100
RIN
150
800
-2
MΩ
Ω
VCOM_CTRL = low, HiZ = 0
1000
4.7
1200
2
RDIS
%
CVCOM
Capacitor tolerance ±10%
3.3
µF
CP1 (VDDH) CHARGE PUMP
VDDH_IN
Input voltage range
Power good threshold
Power good time-out
Feedback voltage
Accuracy
15.2
16
90
16.8
V
%
Fraction of nominal output voltage
Not tested in production
PG
50
ms
V
0.998
VFB
ILOAD = 2 mA
-2
2
23
10
%
VDDH_OUT Output voltage range
VSET = 22 V, ILOAD = 2 mA
21
22
V
ILOAD
fSW
Load current range
mA
KHz
Ω
Switching frequency
Discharge impedance to ground
Mismatch to any other RDIS
Driver capacitor
560
Enabled when rail is disabled
800
-2
1000
1200
2
RDIS
%
CD
CO
10
nF
µF
Output capacitor
1
2.2
CP2 (VEE) NEGATIVE CHARGE PUMP
VEE_IN
Input voltage range
Power good threshold
Power good time-out
Feedback voltage
15.2
16
90
16.8
V
%
Fraction of nominal output voltage
Not tested in production
PG
50
ms
V
-0.994
VFB
Accuracy
ILOAD = 2 mA
-2
2
-19
12
%
VEE_OUT
ILOAD
fSW
Output voltage range
Load current range
Switching frequency
Discharge impedance to ground
Mismatch to any other RDIS
Driver capacitor
VSET = –20 V, ILOAD = 3 mA
-21
-20
V
mA
KHz
Ω
560
Enabled when rail is disabled
800
-2
1000
1200
2
RDIS
%
CD
CO
10
nF
µF
Nominal output capacitor
Capacitor tolerance ±10%
1
2.2
8
Copyright © 2011, Texas Instruments Incorporated
TPS65185
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
THERMISTOR MONITOR(3)
ATMS Temperature to voltage ratio
TEST CONDITIONS
MIN
TYP
MAX UNIT
Not tested in production
Temperature = 0°C
-0.0161
1.575
0.768
0.845
2.25
V/°C
V
OffsetTMS Offset
VTMS_HOT Temp hot trip voltage (T = 50°C)
VTMS_COOL Temp hot escape voltage (T = 45°C)
VTMS_MAX Maximum input level
TEMP_HOT_SET = 0x8C
TEMP_COOL_SET = 0x82
V
V
V
RNTC_PU
RLINEAR
ADCRES
ADCDEL
Internal pull up resistor
External linearization resistor
ADC resolution
7.307
43
KΩ
KΩ
mV
µs
Not tested in production, 1 bit
Not tested in production
Not tested in production
16.1
ADC conversion time
19
TMSTTOL Accuracy
-1
1
LSB
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, PWR_GOOD, PWRx, WAKEUP)
IO = 3 mA, sink current
(SDA, nINT, PWR_GOOD)
VOL
Output low threshold level
0.4
0.4
V
VIL
Input low threshold level
Input high threshold level
Input bias current
V
V
VIH
1.2
I(bias)
VIO = 1.8 V
1
µA
Deglitch time, WAKEUP pin
Deglitch time, PWRUP pin
Discharge delay
Not tested in production
Not tested in production
Not tested in production
500
400
100(4)
tdeglitch
µs
tdischarge
fSCL
ms
SCL clock frequency
I2C slave address
400 KHz
7-bit address
0x68h(5)
OSCILLATOR
fOSC Oscillator frequency
Frequency accuracy
THERMAL SHUTDOWN
TSHTDWN Thermal trip point
Thermal hysteresis
9
MHz
TA = –40°C to 85°C
-10
10
%
150
20
°C
°C
(3) 10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 kΩ, 1%) are used at TS pin for panel
temperature measurement.
(4) Contact factory for 50-ms, 200-ms or 400-ms option.
(5) Contact factory for alternate address of 0x48h.
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TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
DEFAULT POWER-UP SEQUENCE
DEFAULT POWER-DOWN SEQUENCE
Figure 1.
Figure 2.
INRUSH CURRENT @ VIN = 3.7 V, CIN = 100 µF
INRUSH CURRENT @ VIN = 5 V, CIN = 100 µF
Figure 3.
Figure 4.
SWITCHING WAVE FORMS, VN
VIN = 3 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
SWITCHING WAVE FORMS, VB
VIN = 3 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
Figure 5.
Figure 6.
10
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TPS65185
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
SWITCHING WAVE FORMS, VN
VIN = 3.7 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
SWITCHING WAVE FORMS, VB
VIN = 3.7 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
No Load on VDDH, VEE
Figure 7.
Figure 8.
SWITCHING WAVE FORMS, VN
VIN = 5 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
SWITCHING WAVE FORMS, VB
VIN = 5 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
Figure 9.
Figure 10.
VN DCDC EFFICIENCY, T = 25°C
VB DCDC EFFICIENCY, T = 25°C
100
90
100
90
80
80
70
70
VIN= 3.5
60
60
50
40
30
20
10
0
VIN= 3.5
VIN= 5V
VIN= 5V
50
40
30
20
10
0
0
25
50
75
100
125
150
175
0
25
50
75
100
125
150
175
Output Current [mA]
Output Current [mA]
Figure 11.
Figure 12.
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11
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VEE CHARGE PUMP EFFICIENCY, T = 25°C
VDDH CHARGE PUMP EFFICIENCY, T = 25°C
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN=5V
VIN=5V
VIN=3.5
VIN=3.5V
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Current [mA]
Output Current [mA]
Figure 13.
Figure 14.
3p3V SWITCH IMPEDANCE
VIN = 3.7 V, ILOAD, V3p3 = 10 mA
SOURCE DRIVER SUPPLY TRACKING
VIN = 3.7 V
5 0
4 0
25
20
15
10
5
IPO S =INE G
IPO S swe ep, INE G=15m A
IPO S =15mA , INEG sweep
3 0
2 0
1 0
0
-1 0
-2 0
-3 0
-4 0
-5 0
0
0
25
50
75
100
125
1 50
1 75
1
1.5
2
2.5
3
3.5
4
Curre nt [m A]
VIN3P3[V]
Figure 15.
Figure 16.
VCOM INTEGRATED NON-LINEARITY
VCOM DIFFERENTIAL NON-LINEARITY
VIN = 3.7 V, RLOAD, VCOM = 1 kΩ
VIN = 3.7 V, RLOAD, VCOM = 1 kΩ
5
4
0.2
0 .15
0.1
3
2
0 .05
0
1
0
-1
-2
-3
-4
-5
-0 .05
-0.1
-0 .15
-0.2
0
6 4
12 8 1 92 2 56 3 20 384 448 512
0
64
128
192 25 6 320
384 44 8 512
VCO M CODE
V CO M CODE
Figure 17.
Figure 18.
12
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TPS65185
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
KICKBACK VOLTAGE MEASUREMENT TIMING
VIN = 3.7 V; AVG[1:0] = 00 (Single Measurement)
Time from ACQ Bit Set to ACQC Interrupt Received
KICKBACK VOLTAGE MEASUREMENT ERROR
VIN = 3.7 V
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
640 12 80 192 0 2560 3200 3840 44 80 512 0
Force d Kick ba c k Volta ge [m V]
Figure 19.
Figure 20.
KICKBACK VOLTAGE MEASUREMENT TIMING
VIN = 3.7 V; AVG[1:0] = 11 (Eight Measurements)
Time from ACQ Bit Set to ACQC Interrupt Received
Figure 21.
Copyright © 2011, Texas Instruments Incorporated
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TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
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MODES OF OPERATION
The TPS65185 has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the
lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the
device is ready to accept commands through the I2C interface. In ACTIVE mode one or more power rails are
enabled.
SLEEP
This is the lowest power mode of operation. All internal circuitry is turned off, registers are
reset to default values and the device does not respond to I2C communications. TPS65185
enters SLEEP mode whenever WAKEUP pin is pulled low.
STANDBY
In STANDBY all internal support circuitry is powered up and the device is ready to accept
commands through the I2C interface but none of the power rails are enabled. The device
enters STANDBY mode when the WAKEUP pin is pulled high and either the PWRUP pin is
pulled low or the STANDBY bit is set. The device also enters STANDBY mode if input Under
Voltage Lock Out (UVLO), positive boost Under Voltage (VB_UV), or inverting buck-boost
Under Voltage (VN_UV) is detected, thermal shutdown occurs, or the PROG bit is set (see
VCOM calibration).
ACTIVE
The device is in ACTIVE mode when any of the output rails are enabled and no fault
condition is present. This is the normal mode of operation while the device is powered up.
MODE TRANSISITONS
SLEEP → ACTIVE
WAKEUP pin is pulled high with PWRUP pin high. Rails come up in the order defined by the
UPSEQx registers (OK to tie WAKEUP and PWRUP pin together).
SLEEP → STANDBY
WAKEUP pin is pulled high with PWRUP pin low. Rails will remain powered down.
STANDBY → ACTIVE
WAKEUP pin is high and PWRRUP pin is pulled high (rising edge) or the ACTIVE bit is set.
Output rails will power up in the order defined by the UPSEQx registers.
ACTIVE → STANDBY
WAKEUP pin is high and STANDBY bit is set or PWRUP pin is pulled low (falling edge).
Rails are shut down in the order defined by DWNSEQx registers. Device also enters
STANDBY in the event of Thermal Shut Down (TSD), Under Voltage Lock Out (UVLO),
positive boost or inverting buck-boost Under Voltage (UV), VCOM fault (VCOMF), or when
the PROG bit is set (see VCOM calibration).
STANDBY → SLEEP
WAKEUP pin is pulled low while none of the output rails are enabled.
ACTIVE → SLEEP
WAKEUP pin is pulled low while at least one output rail is enabled. Rails are shut down in
the order defined by DWNSEQx registers.
14
Copyright © 2011, Texas Instruments Incorporated
TPS65185
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
POWER DOWN
Battery removed
All rails
V3P3 switch= OFF
I2C = NO
Registersà default
= OFF
SLEEP
WAKEUP= high &
PWRUP= low
WAKEUP= low
All rails = OFF
= YES
STANDBY
I2C
WAKEUP= high &
(STANDBY bit = 1||
PWRUP(?) || FAULT )
WAKEUP= high &
(ACTIVE bit= 1 || PWRUP( ) )
?
Rails
I2C
= ON
= YES
ACTIVE
NOTES:
||, &
= logic OR, logic AND.
( ), (?) = rising edge, falling edge.
?
UVLO
TSD
UV
= Under Voltage Lock Out
= Thermal Shut Down
= Under Voltage
FAULT = UVLO || TSD || BOOST UV|| VCOM fault.
Figure 22. Global State Diagram
Copyright © 2011, Texas Instruments Incorporated
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TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
WAKE-UP AND POWER UP SEQUENCING
The power-up/down order and timing is defined by user register settings. The default settings support the E Ink®
Vizplex™ panel and typically do not need to be changed.
In SLEEP mode the TPS65185 is completely turned off, the I2C registers are reset, and the device does not
accept any I2C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY
mode which enables the I2C interface. Write to the UPSEQ0 register to define the order in which the output rails
are enabled at power-up and to the UPSEQ1 registers to define the power-up delays between rails. Finally, set
the ACTIVE bit in the ENABLE register to ‘1’ to execute the power-up sequence and bring up all power rails.
Alternatively pull the PWRUP pin high (rising edge).
After the ACTIVE bit has been set, the negative boost converter (VN) is powered up first, followed by the positive
boost (VB). The positive boost enable is gated by the internal power-good signal of the negative boost. Once VB
is in regulation, it issues an internal power-good signal and after delay time UDLY1 has expired, STROBE1 is
issued. The rail assigned to STROBE1 will power up next and after its power-good signal has been asserted and
delay time UDLY2 has expired, STROBE2 is issued. The sequence continues until STROBE4 has occurred and
the last rail has been enabled.
To power-down the device, set the STANDBY bit of the ENABLE register to ‘1’ or pull the PWRUP pin low (falling
edge) and the TPS65185 will power down in the order defined by DWNSEQx registers. The delay times DDLY2,
DDLY3, and DDLY4 are weighted by a factor of DFCTR which allows the user to space out the power-down of
the rails to avoid crossing during discharge. DFCTR is located in register DWNSEQ1. The positive boost (VB) is
shut down together with the last rail at STROBE4. However, the negative boost (VN) remains up and running for
another 100 ms (discharge delay) to allow complete discharge of all rails. After the discharge delay, VN is
powered down and the device enters STANDBY or SLEEP mode, depending on the WAKEUP pin.
If either the ACTIVE bit is set or the PWRUP pin is pulled high while the device is powering down, the
power-down sequence (STROBE1-4) is completed first, followed by a power-up sequence. VB and VN may or
may not be powered down and the discharge delay may be cut short depending on the relative timing of
STROBE4 to the new power-up event.
During power-up, if the STANDBY bit is set or the PWRUP pin is pulled low, the power-up sequence is aborted
and the power-down sequence starts immediately.
DEPENDENCIES BETWEEN RAILS
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and
several dependencies exist that affect the power-up sequencing. These dependencies are listed below.
1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.
Internally, DCDC1 enable is gated by DCDC2 power good.
2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable
is gated DCDC1 power-good.
3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is
gated by DCDC1 power good.
4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally
CP2 enable is gated by DCDC1 power good.
5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally
CP1 enable is gated by DCDC1 power good.
6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power
good.
16
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TPS65185
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
VN PG
VB PG
VN
powers up
VB
powers up
STROBE 1
STROBE 2
STROBE 3
STROBE 4
PG1
PG2
PG3
PG4
UDLY1
UDLY2
UDLY3
UDLY4
1st rail
powers up
2nd rail
powers up
3nd rail
powers up
4th rail
powers up
ACTIVE bit
or
WAKEUP high
STROBE 1
STROBE 2
STROBE 3
STROBE 4
DDLY1
DDLY2
DDLY3
DDLY4
1st rail
powers down
2nd rail
powers down
3nd rail
powers down
4th rail
powers down
Discharge DELAY
VB
powers down
VN
powers down
STANDBY bit
or
WAKEUP low
TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after
ACTIVE bit is set and STROBE4 is the last event in the sequence. Strobes are assigned to rails in UPSEQ0 register
and delays between STROBES are defined in UPSEQ1 register.
BOTTOM: Power-down sequence is independent of power-up sequence. Strobes and delay times for power down
sequence are set in DWNSEQ0 and DWNSEQ1 register.
Figure 23. Power-Up and Power-Down Sequence
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TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
VIN
1.8ms(1)
I2C
PWRUP
SLEEP
WAKEUP
STANDBY
ACTIVE
ACTIVE
Discharge Delay
VN
VB
UDLY 1
DDLY 4
UDLY 1
VNEG
UDLY 2
UDLY 2
VEE
UDLY 3
DDLY 3
UDLY3
VPOS
UDLY 4
DDLY 2
UDLY 4
VDDH
DDLY 1
PWR_GOOD
300us (max)
300us (max)
(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .
In this example the first power-up sequence is started by pulling the PWRUP pin high (rising edge). Power-down is
initiated by pulling the WAKEUP pin low (device enters SLEEP mode). The 2nd power-up sequence is initiated by
pulling the WAKEUP pin high while the PWRUP pin is also high (power up from SLEEP to ACTIVE).
Figure 24. Power-Up and Power-Down Timing Diagram
SOFTSTART
TPS65185 supports soft-start for all rails, i.e. inrush current is limited during startup of DCDC1, DCDC2, LDO1,
LDO2, CP1 and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the
corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters
STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out
limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set
and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.
ACTIVE DISCHARGE
TPS65185 provides low-impedance discharge paths for the display power rails (VEE, VNEG, VPOS, VDDH, and
VCOM) which are enabled whenever the corresponding rail is disabled. The discharge paths are connected to
the rails on the PCB which allows adding external resistors to customize the discharge time. However, external
resistors are not required.
Active discharge remains enabled for 100 ms after the last rail has been disabled (STROBE4 has been
executed). During this time the negative boost converter (VN) remains up. After the discharge delay, VN is shut
down and the device enters STANDBY or SLEEP mode, depending on the state of the WAKEUP pin.
18
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TPS65185
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
VPOS/VNEG SUPPLY TRACKING
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV.
V3P3 POWER SWITCH
The integrated power switch is used to cut the 3.3-V supply to the EPD panel and is controlled through the
V3P3_EN pin of the ENABLE register. In SLEEP mode the switch is automatically turned off and its output is
discharged to ground. The default power-up state is OFF. To turn the switch ON, set the V3P3_ENbit to 1.
VCOM ADJUSTMENT
VCOM is the output of a power-amplifier with an output voltage range of 0 V to -5.11 V, adjustable in 10-mV
steps. In a typical application VCOM is connected to the VCOM terminal of the EPD panel and the amplifier is
controlled through the VCOM_CTRL pin. With VCOM_CTRL high, the amplifier drives the VCOM pin to the
voltage specified by the VCOM1 and VCOM2 register. When pulled low, the amplifier turns off and VCOM is
actively discharged to ground through VCOM_DIS pin. If active discharge is not desired, simply leave the
VCOM_DIS pin open.
For ease of design, the VCOM_CTRL pin may also be tied to the battery or IO supply. In this case, VCOM is
enabled with STROBE4 during the power-up sequence and disabled on STROBE1 of the power-down sequence.
Therefore VCOM is the last rail to be enabled and the first to be disabled.
KICK-BACK VOLTAGE MEASUREMENT
TPS65185 can perform a voltage measurement on the VCOM pin to determine the kick-back voltage of the
panel. This allows in-system calibration of VCOM. To perform a kick-back voltage measurement, follow these
steps:
•
•
•
•
•
Pull the WAKEUP pin and the PWRUP pin high to enable all output rails.
Set the HiZ bit in the VCOM2 register. This puts the VCOM pin in a high-impedance state.
Drive the panel with the Null waveform. Refer to E-Ink specification for detail.
Set the ACQ bit in the VCOM2 register to 1. This starts the measurement routine.
When the measurement is complete, the ACQC (Acquisition Complete) bit in the INT1 register is set and the
nINT pin is pulled low.
•
The measurement result is stored in the VCOM[8:0] bits of the VCOM1 and VCOM2 register.
Please note that the measurement result is not automatically programmed into non-volatile memory. Changing
the power-up default is described in the following paragraph.
STORING THE VCOM POWER-UP DEFAULT VALUE IN MEMORY
The power-up default value of VCOM can be user-set and programmed into non-volatile memory. To do so, write
the default value to the VCOM[8:0] bits of the VCOM1 and VCOM2 register, then set the PROG bit in VCOM2
register to 1. First, all power rails are shut-down, then the VCOM[8:0] value is committed to non-volatile memory
such that it becomes the new power-up default. Once programming is complete, the PRGC bit in the INT1
register is set and the nINT pin is pulled low. To verify that the new value has been saved properly, first write the
VCOM[8:0] bits to 0x000h, then pull the WAKEUP pin low. After the WAKEUP pin is pulled back high, read the
VCOM[8:0] bits to verify that the new default value is correct.
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TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
10uF
VIN
INT_LDO
From Input Supply
(3.0V-6.0V)
INT_LDO
VREF
4.7uF
4.7uF
VREF
500
VCOM_DIS
4.7uF
AGND1
VCOM
To panel back -plane
(-0.5 to -5.0V, 15mA)
VCOM[8:0]
VCOM_CTRL
DAC
4.7uF
From uC
VCOM_PWR
From VN (-17V)
Figure 25. Block Diagram of VCOM Circuit
20
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TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
Pull WAKEUP= HIGH
Pull PWRUP= HIGH
Write HiZ = 1
Device enters ACTIVE mode
All power rails are up except VCOM
VCOM pin is in HiZ state
Processor drives panel with NULL waveform
Write ACQ = 1
Starts A/D conversion
Indicates A/D conversion is complete
If AVG[1:0] is <> 00, interrupt is issed
after all conversions are complete and
average has been calcutated.
Wait for ACQC interrupt
Read result from VCOM1/2
registers
Check result and decide to keep the
value or repeat measurmen.t
Pull PWRUP= LOW
Write HiZ = 0
Device enters STANDBY mode
Starts the EEPROM programming cycle.
Power must not be interrupted.
Write PROG= 1
Wait for PRGC interrupt
Pull WAKEUP= LOW
Pull WAKEUP= HIGH
Read VCOM[8:0]
Indicates programming is complete
Device enters SLEEP mode
Device enters STANDBY mode
Compare against written value to
confirm new default has been
programmed correctly.
Figure 26. VCOM Calibration Flow
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TPS65185
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FAULT HANDLING AND RECOVERY
The TPS65185 monitors input and output voltages and die temperature and will take action if operating
conditions are outside normal limits. Whenever the TPS65185 encounters:
•
•
•
•
Thermal Shutdown (TSD)
Positive Boost Under Voltage (VB_UV)
Inverting Buck-Boost Under Voltage (VN_UV)
Input Under Voltage Lock Out (UVLO)
it shuts down all power rails and enters STANDBY mode. Shut-down follows the order defined by DWNSEQx
registers. The exception is VCOM fault witch leads to immediate shutdown of all rails. Once a fault is detected,
the PWR_GOOD and nINT pins are pulled low and the corresponding interrupt bit is set in the interrupt register.
Power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the INT1 and INT2
register. Alternatively, toggling the WAKEUP pin also resets the interrupt bits. As the PWRUP input is edge
sensitive, the host must toggle the PWRUP pin to re-enable the rails through GPIO control, i.e. it must bring the
PWRUP pin low before asserting it again. Alternatively rails can be re-enbled through the I2C interface.
Whenever the TPS65185 encounters under-voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV)
or VDDH (VDDH_UV), rails are not shut down but the PWR_GOOD and nINT is pulled low with the
corresponding interrupt bit set. The device remains in ACTIVE mode and recovers automatically once the fault
has been removed.
POWER GOOD PIN
The power good pin (PWR_GOOD) is an open drain output that is pulled high (by an external pull-up resistor)
when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails
encounters a fault or is disabled. PWR_GOOD remains low if one of the rails is not enabled by the host and only
after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor).
INTERRUPT PIN
The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT1 or INT2 bits
are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the register with the set bit
has been read by the host. If the fault persists, the nINT pin will be pulled low again after a maximum of 32 µs.
Interrupt events can be masked by re-setting the corresponding enable bit in the INT_EN1 and INT_EN2 register,
i.e. the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits
affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT1/INT2 bits
themselves.
Note that persisting faults such as thermal shutdown can cause the nINT pin to be pulled low for an extended
period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set
the corresponding mask bit after receiving the interrupt and keep polling the INT1/INT2 register to see when the
fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
PANEL TEMPERATURE MONITORING
The TPS65185 provides circuitry to bias and measure an external Negative Temperature Coefficient Resistor
(NTC) to monitor the display panel temperature in a range from -10°C to 85°C with and accuracy of ±1°C from
0°C to 50°C. Temperature measurement must be triggered by the controlling host and the last temperature
reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the
programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed
by more than a user-defined threshold from the baseline value. Details are explained under “HOT, COLD, and
temperature-change interrupts”.
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Copyright © 2011, Texas Instruments Incorporated
TPS65185
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
NTC BIAS CIRCUIT
Figure 27 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-KΩ bias resistor. A 43-kΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.
Table 1. ADC Output Value vs Termperature
TEMPERATURE
TMST_VALUE[7:0]
1111 0110
1111 0110
1111 0111
...
< -10°C
-10°C
-9°C
...
-2°C
-1°C
0°C
1111 1110
1111 1111
0000 0000
0000 0001
0000 0010
...
1°C
2°C
...
25°C
...
0001 1001
85°C
> 85°C
0101 0101
0101 0101
2.25V
7.307k
10
TS
Digital
ADC
43k
10k NTC
AGND2
Figure 27. NTC Bias and Measurement Circuit
A temperature measurement is triggered by setting the READ_THERM bit of the TMST1 register to 1.During the
A/D conversion the CONV_END bit of the TMST1 register reads ‘0’, otherwise it reads ‘1’. At the end of the A/D
conversion the EOC bit in the INT2 register is set and the temperature value is available in the TMST_VALUE
register.
HOT, COLD, AND TEMPERATURE-CHANGE INTERRUPTS
Each temperature acquisition is compared against the programmable TMST_HOT and TMST_COLD thresholds
and to the baseline temperature, to determine if the display is within allowed operating temperature range and if
the temperature has changed by more than a user-defined threshold since the last update. The first temperature
reading after the WAKEUP pin has been pulled high automatically becomes the baseline temperature. Any
subsequent reading is compared against the baseline temperature. If the difference is equal or greater than the
threshold value, an interrupt is issued (DTX bit in register INT1 is set to ‘1’) and the latest value becomes the
new baseline. If the difference is less than the threshold value, no action is taken. The threshold value is defined
by DT[1:0] bits in the TMST1 register and has a default value of ±2°C. In summary:
•
When the temperature is equal or less than the TMST_COLD[3:0] threshold, the TMST_COLD interrupt bit of
the INT1 register is set, and the nINT pin is pulled low.
•
When the temperature is greater than TMST_COLD but lower then TMST_HOT, no action is taken.
Copyright © 2011, Texas Instruments Incorporated
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TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
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•
•
When the temperature is equal or greater than the TMST_HOT[3:0] threshold, the TMST_HOT interrupt bit of
the INT1 register is set, and the nINT pin is pulled low.
If the last temperature is different from the baseline temperature by ±2°C (default) or more, the DTX interrupt
bit of the INT1 register is set. The latest temperature becomes the new baseline temperature. Please note
that by default the DTX interrupt is disabled, i.e. the nINT pin is not pulled low unless the DTX_EN bit was
previously set high.
•
If the last temperature change is less than ±2°C (default), no action is taken.
TYPICAL APPLICATION OF THE TEMPERATURE MONITOR
In a typical application the temperature monitor and interrupts are used in the following manner:
•
After the WAKEUP pin has been pulled high, the Application Processor (AP) writes 0x80h to the TMST1
register (address 0x0Dh). This starts the temperature measurement.
•
The AP waits for the EOC interrupt. Alternatively the AP can poll the CONV_END bit in register TMST1. This
will notify the AP that the A/D conversion is complete and the new temperature reading is available in the
TMST_VALUE register (address (0x00h).
•
•
The AP reads the temperature value from the TMST_VALUE register (address (0x00h).
If the temperature changes by ±2°C (default) or more from the first reading, the processor is notified by the
DTX interrupt. The A/P may or may not decide to select a different set of wave forms to drive the panel.
•
•
If the temperature is outside the allowed operating range of the panel, the processor is notified by the THOT
and TCOLD interrupts, respectively. It may or may not decide to continue with the page update.
Once an over/under temperature has been detected, the AP should reset the TMST_HOT_EN or
TMST_COLD_EN bits, respectively, to avoid the nINT pin to be continuously pulled low. The TMST_HOT and
TMST_COLD interrupt bits then should be polled continuously, to determine when the panel temperature
recovers to the normal operating range. Once the temperature has recovered, the TMST_HOT_EN or
TMST_COLD_EN bits should be set to ‘1’ again and normal operation can resume.
I2C BUS OPERATION
The TPS65185 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
Slave Address + R/nW
Reg Address
Data
R/nW
S
A6 A5 A4 A3 A2 A1 A0
A
S7 S6 S5 S4 S3 S2 S1 S0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
S
Start Condition
Read / not Write
A
P
Acknowledge
A6 ... A0 Device Address
S7 ... S0 Sub-Address
D7 ... D0 Data
R/nW
Stop Condition
Figure 28. Subaddress in I2C Transmission
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 30. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate slave address bits are set for the device, then the device will issue an
acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte
received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data
from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the
24
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the
SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the
low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and
data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be
sent for a given I2C transmission. Reference Figure 29 and Figure 30 for deail.
S
SLAVE ADDRESS
W A
REG ADDRESS
A
DATAREGADDR
A
DATA SUBADDR +n
n bytes + ACK
A
DATA SUBADDR +n+1
Ā
P
S
SLAVE ADDRESS
W A
REG ADDRESS
A
S
SLAVE ADDRESS
R
A
A
DATAREGADDR
A
Ā
DATAREGADDR +n
n bytes + ACK
DATAREGADDR +n+1
P
From master to slave
From slave to master
R Read (high)
W Write (low)
S Start
P Stop
Ā
Not Acknowlege
A Acknowlege
TOP: Master writes data to slave.
BOTTOM: Master reads data from slave.
Figure 29. I2C Data Protocol
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
START
ADDRESS R/W ACK
DATA
ACK
DATA
STOP
ACK/
nACK
Figure 30. I2C Start/Stop/Acknowledge Protocol
SDA
SCL
tSU;DAT
tf
tLOW
tr
tHD;STA
tSP
tr
tBUF
tHD;STA
tSU;STA
tSU;STO
tf
tHD;DAT tHIGH
S
Sr
P
S
Figure 31. I2C Data Transmission Timing
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DATA TRANSMISSION TIMING
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
PARAMETER
Serial clock frequency
TEST CONDITIONS
MIN
100
TYP
MAX
UNIT
400 KHz
µs
f(SCL)
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
4
600
4.7
1.3
4
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD;STA
ns
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
LOW period of the SCL clock
µs
µs
ns
µs
ns
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
600
4.7
600
0
3.45
900
µs
0
ns
250
100
Data set-up time
ns
ns
ns
1000
300
300
300
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus Free Time Between Stop and Start Condition
tf
4
600
4.7
1.3
n/a
0
µs
tSU;STO
tBUF
tSP
ns
µs
ns
pF
n/a
50
Pulse width of spikes which mst be suppressed
by the input filter
400
400
Cb
Capacitive load for each bus line
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
REGISTER ADDRESS MAP
DEFAULT
VALUE
REGISTER
ADDRESS (HEX)
NAME
DESCRIPTION
0
1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
TMST_VALUE
ENABLE
VADJ
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Thermistor value read by ADC
Enable/disable bits for regulators
VPOS/VNEG voltage adjustment
Voltage settings for VCOM
Voltage settings for VCOM + control
Interrupt enable group1
2
3
VCOM1
VCOM2
INT_EN1
INT_EN2
INT1
4
5
6
Interrupt enable group2
7
Interrupt group1
8
INT2
Interrupt group2
9
UPSEQ0
UPSEQ1
DWNSEQ0
DWNSEQ1
TMST1
Power-up strobe assignment
Power-up sequence delay times
Power-down strobe assignment
Power-down sequence delay times
Thermistor configuration
10
11
12
13
14
15
16
TMST2
Thermistor hot temp set
PG
Power good status each rails
Device revision ID information
REVID
THERMISTOR READOUT (TMST_VALUE)
Address – 0x00h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
TMST_VALUE[7:0]
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Temperature read-out
1111 0110 – < -10°C
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1 °C
0000 0000 – 0 °C
0000 0001 – 1°C
0000 0010 – 2°C
...
TMST_VALUE[7:0]
0001 1001 – 25°C
...
0101 0101 – 85°C
0101 0101 – > 85°C
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ENABLE (ENABLE)
Address – 0x01h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
ACTIVE
R/W
D6
D5
D4
D3
D2
D1
VEE_EN
R/W
D0
VNEG_EN
R/W
STANDBY V3P3_EN VCOM_EN VDDH_EN VPOS_EN
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
FIELD NAME
BIT DEFINITION(1)
STANDBY to ACTIVE transition bit
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by UPSEQx registers
ACTIVE
0 – no effect
NOTE: After transition bit is cleared automatically
STANDBY to ACTIVE transition bit
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by DWNSEQx registers
STANDBY
0 – no effect
NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE.
VIN3P3 to V3P3 switch enable
V3P3_EN
VCOM_EN
VDDH_EN
1 – switch is ON
0 – switch is OFF
VCOM buffer enable
1 – enabled
0 – disabled
VDDH charge pump enable
1 – enabled
0 – disabled
VPOS LDO regulator enable
1 – enabled
VPOS_EN
VEE_EN
0 – disabled
NOTE: VPOS cannot be enabled before VNEG is enabled.
VEE charge pump enable
1 – enabled
0 – disabled
VNEG LDO regulator enable
1 – enabled
VNEG_EN
0 – disabled
NOTE: When VNEG is disabled VPOS will also be disabled.
(1) Enable bits always reflect actual status of the corresponding rail.
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
VOLTAGE ADJUSTMENT REGISTER (VADJ)
Address – 0x02h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
not used
R/W
D6
not used
R/W
D5
not used
R/W
D4
not used
R/W
D3
D2
D1
VSET[2:0]
R/W
D0
not used
R
0
R/W
0E2
R/W
1E2
0
0
1
0
1E2
FIELD NAME
not used
not used
not used
not used
not used
BIT DEFINITION
N/A
N/A
N/A
N/A
N/A
VPOS and VNEG voltage setting
000 - not valid
001 - not valid
010 - not valid
VSET[2:0]
011 - ±15.000 V
100 - ±14.750 V
101 - ±14.500 V
110 - ±14.250 V
111 - reserved
VCOM 1 (VCOM1)
Address – 0x03h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
READ/WRITE
RESET VALUE
VCOM [7:0]
R/W
0E2
R/W
1E2
R/W
1E2
R/W
1E2
R/W
1
R/W
1
R/W
0
R/W
1
FIELD NAME
BIT DEFINITION
VCOM voltage, least significant byte. See VCOM2 register for details.
VCOM[7:0]
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VCOM 2 (VCOM2)
Address – 0x04h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
ACQ
R/W
0
D6
PROG
R/W
0
D5
HiZ
R/W
0
D4
D3
D2
not used
R/W
D1
not used
R/W
D0
VCOM[8]
R/W
AVG[1:0]
R/W
0
R/W
0
1
0
0E2
FIELD NAME
BIT DEFINITION
Kick-back voltage acquisition bit
1 – starts kick-back voltage measurement routine
0 – no effect
ACQ
NOTE: After measurement is complete bit is cleared automatically and measurement result is
reflected in VCOM[8:0] bits.
VCOM programming bit
1 – VCOM[8:0] value is committed to non-volatile memory and becomes new power-up default
PROG
HiZ
0 – no effect
NOTE: After programming bit is cleared automatically and TPS65185 will enter STANDBY mode.
VCOM HiZ bit
1 – VCOM pin is placed into hi-impedance state to allow VCOM measurement
0 – VCOM amplifier is connected to VCOM pin
Number of acquisitions that is averaged to a single kick-back voltage measurement
00 – 1x
01 – 2x
10 – 4x
11 – 8x
AVG[1:0]
NOTE: When the ACQ bit is set, the state machine repeat the A/D conversion of the kick-back
voltage AVD[1:0] times and returns a single, averaged, value to VCOM[8:0]
not used
not used
N/A
N/A
VCOM voltage adjustment
VCOM = VCOM[8:0] x -10 mV in the range from 0 mV to -5.110 V
0x000h – 0 0000 0000 – -0 mV
0x001h – 0 0000 0001 – -10 mV
0x002h – 0 0000 0010 – -20 mV
...
VCOM[8:0]
0x07Dh - 0 0111 1101 - -1250 mV
...
0x1FEh – 1 1111 1110 – -5100 mV
0x1FFh – 1 1111 1111 – -5110 mV
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INTERRUPT ENABLE 1 (INT_EN1)
Address – 0x05h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
TMST_HOT TMST_COLD
FIELD NAME
DTX_EN
TSD_EN
HOT_EN
UVLO_EN
ACQC_EN
PRGC_EN
_EN
R/W
1
_EN
R/W
1
READ/WRITE
R
0
R/W
1
R/W
1
R/W
1
R
1
R
1
RESET VALUE
FIELD NAME
BIT DEFINITION(1)
Panel temperature-change interrupt enable
1 – enabled
DTX_EN
0 – disabled
Thermal shutdown interrupt enable
1 – enabled
TSD_EN
HOT_EN
0 – disabled
Thermal shutdown early warning enable
1 – enabled
0 – disabled
Thermistor hot interrupt enable
1 – enabled
TMST_HOT_EN
TMST_COLD_EN
UVLO_EN
0 – disabled
Thermistor cold interrupt enable
1 – enabled
0 – disabled
VIN under voltage detect interrupt enable
1 – enabled
0 – disabled
VCOM acquisition complete interrupt enable
1 – enabled
ACQC_EN
0 – disabled
VCOM programming complete interrupt enable
1 – enabled
PRGC_EN
0 – disabled
(1) Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
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INTERRUPT ENABLE 2 (INT_EN2)
Address – 0x06h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
VBUVEN
R/W
D6
VDDHUVEN
R/W
D5
VNUV_EN
R/W
D4
VPOSUVEN
R/W
D3
VEEUVEN
R/W
D2
D1
D0
EOCEN
R/W
1
VCOMFEN VNEGUVEN
R/W
1
R/W
1
1
1
1
1
1
FIELD NAME
BIT DEFINITION(1)
Positive boost converter under voltage detect interrupt enable
VBUVEN
1 – enabled
0 – disabled
VDDH under voltage detect interrupt enable
VDDHUVEN
VNUVEN
1 – enabled
0 – disabled
Inverting buck-boost converter under voltage detect interrupt enable
1 – enabled
0 – disabled
VPOS under voltage detect interrupt enable
VPOSUVEN
VEEUVEN
VCOMFEN
VNEGUVEN
EOCEN
1 – enabled
0 – disabled
VEE under Voltage detect interrupt enable
1 – enabled
0 – disabled
VCOM FAULT interrupt enable
1 – enabled
0 – disabled
VNEG under Voltage detect interrupt enable
1 – enabled
0 – disabled
Temperature ADC end of conversion interrupt enable
1 – enabled
0 – disabled
(1) Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
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SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
INTERRUPT 1 (INT1)
Address – 0x07h
DATA BIT
D7
DTX
R
D6
TSD
R
D5
HOT
R
D4
D3
D2
UVLO
R
D1
ACQC
R
D0
PRGC
R
FIELD NAME
TMST_HOT TMST_COLD
READ/WRITE
RESET VALUE
R
R
0
N/A
N/A
N/A
N/A
N/A
0
0
FIELD NAME
BIT DEFINITION
Panel temperature-change interrupt
DTX
1 – temperature has changed by 3 deg or more over previous reading
0 – no significance
Thermal shutdown interrupt
TSD
HOT
1 – chip is in over-temperature shutdown
0 – no fault
Thermal shutdown early warning
1 – chip is approaching over-temperature shutdown
0 – no fault
Thermistor hot interrupt
TMST_HOT
TMST_COLD
UVLO
1 – thermistor temperature is equal or greater than TMST_HOT threshold
0 – no fault
Thermistor cold interrupt
1 – thermistor temperature is equal or less than TMST_COLD threshold
0 – no fault
VIN under voltage detect interrupt
1 – input voltage is below UVLO threshold
0 – no fault
VCOM acquisition complete
ACQC
1 – VCOM measurement is compete
0 – no significance
VCOM programming complete
1 – VCOM programming is complete
0 – no significance
PRGC
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INTERRUPT 2 (INT2)
Address – 0x08h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
VB_UV
R
D6
VDDH_UV
R
D5
VN_UV
R
D4
VPOS_UV
R
D3
VEE_UV
R
D2
VCOMF
R
D1
VNEG_UV
R
D0
EOC
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Positive boost converter under voltage detect interrupt
1 – under-voltage on DCDC1 detected
0 – no fault
VB_UV
VDDH under voltage detect interrupt
1 – under-voltage on VDDH charge pump detected
0 – no fault
VDDH_UV
VN_UV
Inverting buck-boost converter under voltage detect interrupt
1 – under-voltage on DCDC2 detected
0 – no fault
VPOS under voltage detect interrupt
1 – under-voltage on LDO1(VPOS) detected
0 – no fault
VPOS_UV
VEE_UV
VCOMF
VNEG_UV
EOC
VEE under Voltage detect interrupt
1 – under-voltage on VEE charge pump detected
0 – no fault
VCOM fault detection
1 – fault on VCOM detected (VCOM is outside normal operating range)
0 – no fault
VNEG under Voltage detect interrupt
1 – under-voltage on LDO2(VNEG) detected
0 – no fault
ADC end of conversion interrupt
1 – ADC conversion is complete (temperature acquisition is complete)
0 – no significance
34
Copyright © 2011, Texas Instruments Incorporated
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
POWER UP SEQUENCE REGISTER 0 (UPSEQ0)
Address – 0x09h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
VDDH_UP[1:0]
R/W R/W
1E2 1E2
D6
D5
VPOS_UP[1:0]
R/W R/W
1E2 0E2
D4
D3
D2
D1
VNEG_UP[1:0]
R/W R/W
0E2 0E2
D0
VEE_UP[1:0]
R/W
0E2
R/W
1E2
FIELD NAME
BIT DEFINITION
VDDH power-up order
00 – power up on STROBE1
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VPOS power-up order
VDDH_UP[1:0]
00 – power up on STROBE1
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VEE power-up order
VPOS_UP[1:0]
VEE_UP[1:0]
00 – power up on STROBE1
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VNEG power-up order
00 – power up on STROBE1
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VNEG_UP[1:0]
6ms
6ms
6ms
6ms
6ms
48ms
VDDH
VPOS
VNEG
VEE
Figure 32. Default Power-Up/Down Sequence
Copyright © 2011, Texas Instruments Incorporated
35
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
POWER UP SEQUENCE REGISTER 1 (UPSEQ1)
Address – 0x0Ah
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
UDLY4[1:0]
UDLY3[1:0]
UDLY2[1:0]
UDLY1[1:0]
R/W
0E2
R/W
1E2
R/W
0E2
R/W
1E2
R/W
0E2
R/W
1E2
R/W
0E2
R/W
1E2
FIELD NAME
BIT DEFINITION
DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up.
00 – 3 ms
UDLY4[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up.
00 – 3 ms
UDLY3[1:0]
UDLY2[1:0]
UDLY1[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up.
00 – 3 ms
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY1 delay time set; defines the delay time from VN_PG high to STROBE1 during power-up.
00 – 3 ms
01 – 6 ms
10 – 9 ms
11 – 12 ms
36
Copyright © 2011, Texas Instruments Incorporated
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
POWER DOWN SEQUENCE REGISTER 0 (DWNSEQ0)
Address – 0x0Bh
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
VDDH_DWN[1:0]
VPOS_DWN[1:0]
VEE_DWN[1:0]
VNEG_DWN[1:0]
R/W
0E2
R/W
0E2
R/W
0E2
R/W
1E2
R/W
1E2
R/W
1E2
R/W
1E2
R/W
0E2
FIELD NAME
BIT DEFINITION
VDDH power-down order
00 – power down on STROBE1
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VPOS power-down order
VDDH_DWN[1:0]
00 – power down on STROBE1
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VEE power-down order
VPOS_DWN[1:0]
VEE_DWN[1:0]
VNEG_DWN[1:0]
00 – power down on STROBE1
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VNEG power-down order
00 – power down on STROBE1
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
Copyright © 2011, Texas Instruments Incorporated
37
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
POWER DOWN SEQUENCE REGISTER 1 (DWNSEQ1)
Address – 0x0Ch
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
DDLY1
R/W
D0
DFCTR
R/W
DDLY4[1:0]
DDLY3[1:0]
DDLY2[1:0]
R/W
1E2
R/W
1E2
R/W
1E2
R/W
0E2
R/W
0E2
R/W
0E2
0E2
0E2
FIELD NAME
BIT DEFINITION
DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-down.
00 – 6 ms
DDLY4[1:0]
01 – 12 ms
10 – 24 ms
11 – 48 ms
DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-down.
00 – 6 ms
DDLY3[1:0]
DDLY2[1:0]
01 – 12 ms
10 – 24 ms
11 – 4 8ms
DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-down.
00 – 6 ms
01 – 12 ms
10 – 24 ms
11 – 48 ms
DLY2 delay time set; defines the delay time from WAKEUP low to STROBE1 during power-down.
DDLY1
DFCTR
0 – 3 ms
1 – 6 ms
At power-down delay time DLY2[1:0], DLY3[1:0], DLY4[1:0] are multiplied with DFCTR[1:0]
0 – 1x
1 – 16x
38
Copyright © 2011, Texas Instruments Incorporated
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
THERMISTOR REGISTER 1 (TMST1)
Address – 0x0Dh
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
not used
R/W
D5
D4
not used
R/W
D3
not used
R/W
D2
not used
R/W
D1
D0
READ_THERM
CONV_END
DT[1:0]
R/W
0
R
1
R/W
0
R/W
0
0
0
0
0
FIELD NAME
BIT DEFINITION
Read thermistor value
1 – initiates temperature acquisition
0 – no effect
READ_THERM
NOTE: Bit is self-cleared after acquisition is completed
not used
N/A
ADC conversion done flag
CONV_END
1 – conversion is finished
0 – conversion is not finished
not used
not used
N/A
N/A
Panel temperature-change interrupt threshold
00 – 2°C
01 – 3°C
10 – 4°C
11 – 5°C
DT[1:0]
DTX interrupt is issued when difference between most recent temperature reading and baseline
temperature is equal to or greater than threshold value. See “HOT, COLD, and temperature-change
interrupts” section for details.
Copyright © 2011, Texas Instruments Incorporated
39
TPS65185
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
THERMISTOR REGISTER 2 (TMST2)
Address – 0x0Eh
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
TMST_COLD[3:0]
TMST_HOT[3:0]
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
FIELD NAME
BIT DEFINITION
Thermistor COLD threshold
0000 – -7°C
0001 – -6°C
0010 – -5°C
0011 – -4°C
0100 – -3°C
0101 – -2°C
0110 – -1°C
0111 – 0°C
TMST_COLD [3:0]
1000 – 1°C
1001 – 2°C
1010 – 3°C
1011 – 4°C
1100 – 5°C
1101 – 6°C
1110 – 7°C
1111 – 8°C
NOTE: An interrupt is issued when thermistor temperature is equal or less than COLD threshold
Thermistor HOT threshold
0000 – 42°C
0001 – 43°C
0010 – 44°C
0011 – 45°C
0100 – 46°C
0101 – 47°C
0110 – 48°C
0111 – 49°C
TMST_HOT [3:0]
1000 – 50°C
1001 – 51°C
1010 – 52°C
1011 – 53°C
1100 – 54°C
1101 – 55°C
1110 – 56°C
1111 – 57°C
NOTE: An interrupt is issued when thermistor temperature is equal or greater than HOT threshold
40
Copyright © 2011, Texas Instruments Incorporated
TPS65185
www.ti.com
SLVSAQ8A –FEBRUARY 2011–REVISED MAY 2011
POWER GOOD STATUS (PG)
Address – 0x0Fh
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
VB_PG
VDDH_PG
VN_PG
VPOS_PG
VEE_PG
not used
VNEG_PG
not used
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
FIELD NAME
BIT DEFINITION(1)
Positive boost converter power good
VB_PG
1 – DCDC1 is in regulation
0 – DCDC1 is not in regulation or turned off
VDDH power good
VDDH_PG
VN_PG
1 – VDDH charge pump is in regulation
0 – VDDH charge pump is not in regulation or turned off
Inverting buck-boost power good
1 – DCDC2 is in regulation
0 – DCDC2 is not in regulation or turned off
VPOS power good
VPOS_PG
1 – LDO1(VPOS) is in regulation
0 – LDO1(VPOS) is not in regulation or turned off
VEE power good
VEE_PG
not used
VNEG_PG
not used
1 – VEE charge pump is in regulation
0 – VEE charge pump is not in regulation or turned off
N/A
VNEG power good
1 – LDO2(VNEG) is in regulation
0 – LDO2(VNEG) is not in regulation or turned off
N/A
(1) PG pin is pulled hi (HiZ state) when VDDH_PG = VPOS_PG = VEE_PG = VNEG_PG = 1
REVISION AND VERSION CONTROL (REVID)
Address – 0x10h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
D6
D5
D4
D3
D2
D1
D0
REVID[7:0]
R
0
R
1
R
0
R
0
R
0E2
R
1E2
R
0E2
R
1E2
FIELD NAME
REVID[7:6]
REVID[5:4]
REVID[3:0]
BIT DEFINITION
MJREV
MNREV
VERSION
0100 0101 - TPS65185 1p0
REVID [7:0]
0101 0101 – TPS65185 1p1
0110 0101 – TPS65185 1p2
Copyright © 2011, Texas Instruments Incorporated
41
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS65185RGZR
TPS65185RGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65185RGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGZ 48
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPS65185RGZR
2500
Pack Materials-Page 2
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