TPS40056PWP [TI]
WIDE-INPUT SYNCHRONOUS, TRACKING BUCK CONTROLLER; 宽输入同步，跟踪降压控制器
| 型号： | TPS40056PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | WIDE-INPUT SYNCHRONOUS, TRACKING BUCK CONTROLLER |
| 文件： | 总31页 (文件大小：769K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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8
SLVS612 − APRIL 2006
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FEATURES
CONTENTS
D
D
D
D
Operating Input Voltage 10 V to 40 V
Device Ratings
2
3
5
7
22
29
Output Voltage Tracks External Reference
Electrical Characteristics
Terminal Information
Application Information
Design Example
Programmable Fixed-Frequency Up to
100 kHz to 1 MHz Voltage Mode Controller
Internal Gate Drive Outputs for High-Side
and Synchronous N-Channel MOSFETs
Additional References
D
D
D
D
D
Externally Synchronizable
Programmable Short-Circuit Protection
Thermal Shutdown
DESCRIPTION
The TPS40056 is part of a family of high-voltage,
wide input, synchronous, step-down converters.
The TPS40056 offers design flexibility with a
variety of user programmable functions, including
soft-start, operating frequency, high-side current
limit, and loop compensation. The TPS40056 is
also synchronizable to an external supply. It
incorporates MOSFET gate drivers for external
N-channel high-side and synchronous rectifier
(SR) MOSFETs. Gate drive logic incorporates
anti-cross conduction circuitry to prevent
simultaneous high-side and synchronous rectifier
conduction. The externally programmable short
circuit protection provides pulse-by-pulse current
limit, as well as hiccup mode operation utilizing an
internal fault counter for longer duration
overloads.
16-Pin PowerPADt Package (θ = 2°C/W)
JC
Programmable Closed-Loop Soft-Start
APPLICATIONS
D
D
D
D
DDR Tracking Regulators
Power Modules
Networking Equipment
Industrial Servers
SIMPLIFIED APPLICATION DIAGRAM
+
TPS40056PWP
V
−
IN
1
2
3
4
5
6
7
8
SYNC
16
15
ILIM
VIN
RT
BP5
BOOST 14
EA_REF HDRV 13
V
TRKIN
12
SGND
SS
SW
+
BP10 11
LDRV 10
VFB
V
−
TT
COMP PGND
PAD
9
UDG−03080
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Copyright 2006, Texas Instruments Incorporated
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SLVS612 − APRIL 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
PACKAGE
PART NUMBER
(1)
−40°C to 85°C
Plastic HTSSOP(PWP)
TPS40056PWP
(1)
The PWP package is also available taped and reeled. Add an R suffix to the device type
(i.e., TPS40056PWPR). See the application section of the data sheet for PowerPAD
drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(2)
TPS40056
45
UNIT
VIN
VFB, SS, SYNC, EA_REF
−0.3 to 6
−0.3 to 45
−2.5
Input voltage range, V
IN
SW
V
SW, transient < 50 ns
COMP, RT, SS
RT
Output voltage range, V
−0.3 to 6
200
O
Output current, I
OUT
µA
°C
Operating junction temperature range, T
−40 to 125
−55 to 150
260
J
Storage temperature, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage, V
10
40
85
V
I
Operating free-air temperature, T
−40
°C
A
(3)(4)
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
RT
BP5
EA_REF
SGND
SS/SD
VFB
ILIM
VIN
BOOST
HDRV
SW
BP10
LDRV
PGND
THERMAL
PAD
COMP
(3)
(4)
For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.
PowerPADt heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
2
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ELECTRICAL CHARACTERISTICS
T
= −40°C to 85°C, V = 12 V , R = 90.9 kΩ, f
= 500 kHz, V = 1.25 V, all parameters at zero power dissipation (unless
EA_REF
A
IN
dc
T
SW
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
V
IN
Input voltage range, VIN
10
40
V
OPERATING CURRENT
Output drivers not switching,
= 1.3 V
I
Quiescent current
Ouput voltage
1.5
5.0
3.0
mA
V
DD
V
FB
BP5
V
I
= 1 mA
4.5
520
2
5.5
BP5
LOAD
OSCILLATOR/RAMP GENERATOR
f
Accuracy
9 V ≤ V ≤ 40 V
IN
580
2.0
640
kHz
V
OSC
(1)
V
V
V
PWM ramp voltage
V
−V
RAMP
PEAK VAL
High-level input voltage, SYNC
Low-level input voltage, SYNC
Input current, SYNC
5
0.8
10
IH
V
µA
ns
V
IL
I
5
SYNC
Pulse width, SYNC
50
2.38
90%
85%
V
RT voltage
2.50
2.58
RT
V
FB
V
FB
V
FB
= 0 V,
f
≤ 600 kHz
SW
= 0 V, 600 kHz ≤ f
Maximum duty cycle
Minumum duty cycle
≤ 1 MHz
SW
≥ EA_REF + 0.05 V
0%
SOFT START
I
Soft-start source current
Soft-start clamp voltage
Discharge time
1.65
2.35
3.7
3.05
µA
SS
V
V
SS
t
t
C
C
= 220 pF
1.6
2.2
2.8
DSCH
SS
SS
µs
Soft-start time
= 220 pF, 0 V ≤ V
SS
≤ 1.6 V
100
155
205
SS
BP10
V
BP10
Ouput voltage
9.0
9.6
10.3
V
ERROR AMPLIFIER
(1)(2)
V
Error amplifier reference input voltage
Input offset voltage
10 V ≤ V ≤ 40 V
IN
0.2
−6
2.5
6
V
EA_REF
0.5 V ≤ V
0.2 V ≤ V
0.2 V ≤ V
0.5 V ≤ V
≤ 2.25 V
≤ 0.5 V
≤ 0.5 V
≤ 2.25 V
mV
MV
MHz
MHz
dB
FB
FB
FB
FB
Input offset voltage
−10
1.5
2.5
60
0
3.5
5.0
80
10
G
G
Gain bandwidth
BW
BW
Gain bandwidth
A
VOL
Open loop gain
I
I
High-level output source current
Low-level output sink current
High-level output voltage
Low-level output voltage
Input bias current
1.5
2.0
3.2
4.0
4.0
3.5
0.20
100
OH
mA
OL
V
I
I
= 500 µA
OH
OL
SOURCE
= 500 µA
V
V
0.35
200
SINK
= 1.2 V
I
V
nA
BIAS
FB
(1)
(2)
Ensured by design. Not production tested.
Common mode range extends to ground, but not tested below 200 mV.
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SLVS612 − APRIL 2006
ELECTRICAL CHARACTERISTICS
T
= −40°C to 85°C, V = 12 V , R = 90.9 kΩ, f
= 500 kHz, V = 1.25 V all parameters at zero power dissipation (unless
EA_REF
A
IN
dc
T
SW
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
I
Current limit sink current
8
10
300
250
12
µA
SINK
V
V
= 11.7 V,
= 11.7 V,
V
V
= (V
= (V
− 0.5 V)
− 2 V)
ILIM
SW
ILIM
Propagation delay to output
ns
ILIM
SW
ILIM
(1)
t
t
Switch leading-edge blanking pulse time
100
ON
Off time during a fault
7
cycles
OFF
V
V
V
= 11.6 V,
= 11.6 V,
= 11.6 V,
T
= 25°C
−100
−125
−125
−70
−40
−30
−15
ILIM
ILIM
ILIM
A
0°C ≤ T ≤ 85°C
V
Offset voltage SW vs. ILIM
mV
ns
A
OS
−40°C ≤ T ≤ 85°C
A
OUTPUT DRIVER
t
t
t
t
Low-side driver rise time
Low-side driver fall time
High-side driver rise time
High-side driver fall time
48
24
48
36
96
48
96
72
LRISE
LFALL
HRISE
HFALL
C
C
= 2200 pF
LOAD
LOAD
= 2200 pF, (HDRV − SW)
BOOST BOOST
−1.5 V −1.0 V
V
OH
V
OL
V
OH
V
OL
High-level ouput voltage, HDRV
Low-level ouput voltage, HDRV
High-level ouput voltage, LDRV
I
I
I
I
−0.1 A (HDRV − SW)
0.1 A (HDRV − SW)
−0.1 A
HDRV =
HDRV =
LDRV =
LDRV =
0.75
V
BP10 BP10
−1.4 V − 1.0 V
Low-level ouput voltage, LDRV
Minimum controllable pulse width
0.1 A
0.5
(1)
100
150
ns
SS/SD SHUTDOWN
V
V
Shutdown threshold voltage
Outputs off
90
125
210
165
260
SD
mV
Device active threshold voltage
165
EN
BOOST REGULATOR
Output voltage
V
V
IN
= 12.0 V
19
20
21
25
V
BOOST
SW NODE
Leakage current
THERMAL SHUTDOWN
Shutdown temperature
(1)
(1)
I
µA
LEAK
(1)
165
20
T
SD
°C
Hysteresis
UVLO
Input voltage UVLO threshold
Input voltage UVLO hysteresis
8.20
8.75
1.0
9.25
V
(1)
Ensured by design. Not production tested.
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SLVS612 − APRIL 2006
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input
voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the SW pin.
BOOST
14
O
5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used
BP5
3
O
O
with an external dc load of 1 mA or less.
10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF
BP10
11
ceramic capacitor. This pin may be used with an external dc load of 1 mA or less.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to
improve large signal transient response.
COMP
HDRV
ILIM
8
O
O
I
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).
13
16
Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a
voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared
to the voltage drop (VIN −SW) across the high side MOSFET during conduction.
EA_REF
LDRV
4
I
Non-inverting input to the error amplifier and used as the reference for the feedback loop.
Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground
(MOSFET off).
10
O
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s)
of the lower MOSFET(s).
PGND
9
−
RT
2
5
I
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
Signal ground reference for the device.
SGND
−
Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used
as a second non-inverting input to the error amplifier. Output voltage regulation is controlled by the SS voltage
ramp until the voltage on the SS pin reaches the internal reference voltage , EA_REF V. Pulling this pin low
disables the controller.
SS/SD
6
I
SW
12
1
I
I
This pin is connected to the switched node of the converter and used for overcurrent sensing.
Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master
frequency. If synchronization is not used, connect this pin to SGND.
SYNC
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the EA_REF reference
voltage.
VFB
VIN
7
I
I
15
Supply voltage for the device.
5
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SLVS612 − APRIL 2006
FUNCTIONAL BLOCK DIAGRAM
ILIM
16
BP10
VIN 15
11
14
BP10
RAMP
RT
2
1
+
BOOST
Clock
Oscillator
10 V Regulator
SYNC
CLK
7
1.5 VREF
7
CL
7
BP5
0.7 VREF
BP5
3
8
4
7
7
7
7
7
3−Bit Up/Down
Fault Counter
1.5 VREF
N−channel
Driver
13
HDRV
Reference
Voltages
COMP
3.5 VREF
BP5
EA_REF
Restart Fault
12 SW
+
+
VFB
7
BP10
7
Fault
7
7
0.7 V
+
S
R
Q
Q
CL
6
SS/SD
10
+
N−channel
Driver
LDRV
0.7 VREF
7
7
CLK
9
PGND
Restart
5
SGND
UDG−03081
6
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SLVS612 − APRIL 2006
APPLICATION INFORMATION
The TPS40056 allows the user to optimize the PWM controller to the specific application.
The TPS40056 is the controller of choice for synchronous buck designs, the output of which is required to track
another voltage. It has two quadrant operation and can source or sink output current, providing the best transient
response.
SW NODE RESISTOR AND DIODE
The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs
are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output
current which flows during this dead time. This negative voltage could affect the operation of the controller,
especially at low input voltages.
Therefore, a resistor ( 3.3 Ω to 4.7 Ω) and Schottky diode must be placed between the lower MOSFET drain
and pin 12, SW, of the controller as shown in Figure 10. The Schottky diode must have a voltage rating to
accommodate the input voltage and ringing on the SW node of the converter. A 30-V Schottky such as a BAT54
or a 40-V Schottky such as a Zetex ZHCS400 or Vishay SD103AWS are adequate. These components are
shown in Figure 10 as R
and D2.
SW
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS40056 has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the
master clock to the ramp generator circuit. The switching frequency, f
in kHz, of the clock oscillator is set by
SW
a single resistor (R ) to ground. The clock frequency is related to R , in kΩ by Equation (1).
T
T
1
R +
ǒ
* 23
Ǔ
kW
T
*6
f
17.82 10
SW
(1)
UVLO OPERATION
The TPS40056 uses fixed UVLO protection. The fixed UVLO monitors the input voltage. The UVLO circuit holds
the soft-start low until the input voltage has exceeded the undervoltage threshold.
TRACKING CONFIGURATION (V
TRACKING V )
IN
OUT
Setting the output, V
to track another voltage, V
, is simply a matter of selecting the proper voltage
TRKIN
OUT
divider(s) R4,R5,R1 and R6 as shown in Figure 1. The voltage on the EA_REF input should be in the range of
0.2 V to 2.5 V. If the output voltage is less than 2.5 V, resistor R6 can be omitted. For example in the DDR case,
if the voltage V
and omit R6. In general, the output voltage, V
in Equation (2).
ramps up to 2.5 V and it is desired to have V
to track it and come up to 1.25 V, set R4=R5
TRKIN
OUT
, in terms of VTRKIN and the two voltage dividers is shown
OUT
R5
R4 ) R5
R6 ) R1
ǒ
Ǔ ǒ
Ǔ V
V
+ V
TRKIN
OUT
R6
(2)
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SLVS612 − APRIL 2006
TPS40056PWP
R4
4
5
6
7
EA_REF HDRV 13
+
V
TRKIN
R5
V
OUT
SGND
SS
SW 12
BP10 11
LDRV 10
R3
R1
VFB
−
R6
8
COMP
PGND 9
UDG−06020
Figure 1. Tracking Configuration, V
Tracks V
TRKIN
OUT
BP10 AND BP5
vs
INPUT VOLTAGE
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
600
10
9
8
BP10
500
400
300
200
7
6
BP5
5
4
3
2
100
0
1
0
2
4
6
8
10
12
14
0
200
400
600
800
1000
V
IN
− Input Voltage − V
f
− Switching Frequency − kHz
SW
Figure 2
Figure 3
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SLVS612 − APRIL 2006
APPLICATION INFORMATION
BP5 AND BP10 INTERNAL VOLTAGE REGULATORS
Start-up characteristics of the BP5 and BP10 regulators are shown in Figure 2. Slight variations in the BP5
occurs dependent upon the switching frequency. Variation in the BP10 regulation characteristics is also based
on the load presented by switching the external MOSFETs.
SELECTING THE INDUCTOR VALUE
The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but
is physically larger for the same load current. Too small an inductance results in larger ripple currents and a
greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good
compromise is to select the inductance value such that the converter doesn’t enter discontinuous mode until
the load approximated somewhere between 10% and 30% of the rated output. The inductance value is
described in equation (3).
ǒV
V
Ǔ
* V V
IN
IN
O
O
L +
(Henries)
DI f
SW
(3)
where:.
D
D
V is the output voltage
O
∆I is the peak-to-peak inductor current
CALCULATING THE OUTPUT CAPACITANCE
The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.
The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output
ripple is described in equation (4).
1
ESR ) ǒ
Ǔ
DV + DI
ƪ
ƫ
V
P*P
8 C f
O
SW
(4)
The output ripple voltage is typically between 90% and 95% due to the ESR component.
The output capacitance requirement typically increases in the presence of a load transient requirement. During
a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess
inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the
inductor.
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SLVS612 − APRIL 2006
APPLICATION INFORMATION
Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in
equation (5).
1
2
2
E + L I (Joules)
L
(5)
where:
OHǓ2 ǒ Ǔ2
2
2
ǒ
ǒ(
) Ǔ
I + ƪI
ƫ
* I
Amperes
OL
(6)
where:
D
D
I
I
is the output current under heavy load conditions
is the output current under light load conditions
OH
OL
Energy in the capacitor is described in equation (7).
1
2
2
E
+
C V (Joules)
C
(7)
(8)
where:
ǒ Ǔ2 ǒ Ǔ2 ǒVolts
2
2
Ǔ
V + ƪV
ƫ
* V
f
i
where:
D
D
V is the final peak capacitor voltage
f
V is the initial capacitor voltage
i
Substituting equation (6) into equation (5), then substituting equation (8) into equation (7), then setting equation
(7) equal to equation (5), and then solving for C yields the capacitance described in equation (9).
O
ǒ
OHǓ2 ǒ Ǔ2
ƪI
ƫ
(Farads)
L
* I
OL
C
+
O
ǒ Ǔ2 ǒ Ǔ2
ƪV
ƫ
* V
f
i
(9)
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APPLICATION INFORMATION
PROGRAMMING SOFT START
TPS40056 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start
is programmed by charging an external capacitor (C ) via an internally generated current source. The voltage
SS
on C is fed into a separate non-inverting input to the error amplifier (in addition to FB and EA_REF). The loop
SS
is closed on the lower of the C voltage or the the external reference voltage EA_REF. Once the C voltage
SS
SS
rises above the external reference voltage, regulation is based on the external reference. To ensure a controlled
ramp-up of the output voltage the soft-start time should be greater than the L-C time constant as described
O
in equation (10).
w 2p ǸL C
t
(seconds)
START
O
(10)
There is a direct correlation between t
the higher the input current required during start-up. This relationship is describe in more detail in the section
and the input current required during start-up. The faster t
,
START
START
titled, Programming the Current Limit which follows. The soft-start capacitance, C , is described in
SS
equation (11).
For applications in which the V supply ramps up slowly, (typically between 50 ms and 100 ms) it may be
IN
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time should be longer than the time that the V supply transitions between 8 V and 9 V.
IN
2.3 mA
0.7 V
C
+
t
(Farads)
START
SS
(11)
PROGRAMMING CURRENT LIMIT
The TPS40056 uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is
issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this
period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the
PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the
counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 3 for typical
overcurrent protection waveforms.
The minimum current limit setpoint (I ) depends on t
, C , V , and the load current at turn-on (I ).
LIM
START
O
O
L
ǒC
t
OǓ
V
O
I
+
) I (Amperes)
L
ƪ ƫ
LIM
START
(12)
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SLVS612 − APRIL 2006
APPLICATION INFORMATION
The current limit programming resistor (R
) is calculated using equation (13). Care must be taken in choosing
ILIM
the values used for V
the minimum value of I
and I
in the equation. In order to ensure the output current at the overcurrent level,
OS
SINK
and the maximum value of V
must be used.
OS
SINK
I
R
V
OC
DS(on)[max]
OS
R
+
)
(W)
ILIM
I
I
SINK
SINK
(13)
where:
D
D
D
I
is the current into the ILIM pin and is 8.6 µA, minimum
SINK
I
is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current
is the overcurrent comparator offset and is 30 mV, maximum
OC
V
OS
HDRV
CLOCK
t
BLANKING
V
V
ILIM
−V
VIN SW
SS
7 CURRENT LIMIT TRIPS
(HDRV CYCLE TERMINATED BY CURRENT LIMIT
TRIP)
UDG−02136
7 SOFT-START CYCLES
Figure 4. Typical Current Limit Protection Waveforms
SYNCHRONIZING TO AN EXTERNAL SUPPLY
The TPS40056 can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the
falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher
than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock
generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS40056 to freely run at the
frequency programmed by R .
T
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SLVS612 − APRIL 2006
APPLICATION INFORMATION
LOOP COMPENSATION
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40056
includes no voltage feedforward control, the gain of the PWM modulator must be included. The modulator gain
is described in Figure 5.
V
V
IN
V
S
IN
+ 20 log ǒ Ǔ
A
+
or
A
MOD(dB)
MOD
V
S
(14)
Duty dycle, D, varies from 0 to 1 as the control voltage, V , varies from the minimum ramp voltage to the
C
maximum ramp voltage, V . Also, for a synchronous buck converter, D = V / V . To get the control voltage
S
O
IN
to output voltage modulator gain in terms of the input voltage and ramp voltage,
V
V
V
V
V
V
V
O
C
S
O
C
IN
D +
+
or
+
V
IN
S
(15)
Calculate the Poles and Zeros
For a buck converter using voltage mode control there is a double pole due to the output L-C . The double pole
O
is located at the frequency calculated in equation (16).
1
f
+
(Hertz)
LC
2p ǸL C
O
(16)
There is also a zero created by the output capacitance, C , and its associated ESR. The ESR zero is located
O
at the frequency calculated in equation (17).
1
f +
(Hertz)
Z
2p ESR C
O
(17)
Calculate the value of R
V
to set the output voltage, V
.
BIAS
OUT
R1
EA_REF
R
+
W
BIAS
V
* V
OUT
EA_REF
(18)
(19)
The maximum crossover frequency (0 dB loop gain) is calculated in equation (19).
f
SW
f
+
(Hertz)
C
4
Typically, f is selected to be close to the midpoint between the L-C double pole and the ESR zero. At this
C
O
frequency, the control to output gain has a –2 slope (−40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (−20 dB/decade).
Figure 5 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be
compensated.
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APPLICATION INFORMATION
MODULATOR GAIN
vs
SWITCHING FREQUENCY
PWM MODULATOR RELATIONSHIPS
ESR Zero, + 1
A
MOD
= V / V
IN
S
V
S
Resultant, − 1
V
C
D = V / V
LC Filter, − 2
C
S
100
1 k
10 k
100 k
f
− Switching Frequency − Hz
SW
Figure 5
Figure 6
A Type III topology, shown in Figure 7, has two zero-pole pairs in addition to a pole at the origin. The gain and
phase boost of a Type III topology is shown in Figure 8. The two zeros are used to compensate the L-C double
O
pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled
gain roll-off. In many cases the second pole can be eliminated and the amplifier’s gain roll-off used to roll-off
the overall gain at higher frequencies.
C2
(optional)
C1
− 1
R2
R3
+ 1
0 dB
C3
VFB
7
R1
− 1
GAIN
−90°
8
COMP
VOUT
+
R
BIAS
180°
PHASE
−270°
EA_REF
UDG−03099
Figure 8. Type III Compensation Gain and Phase
Figure 7. Type III Compensation Configuration
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APPLICATION INFORMATION
The poles and zeros for a type III network are described in equations (20).
1
1
f
f
+
+
(Hertz)
(Hertz)
f
+
+
(Hertz)
(Hertz)
Z1
P1
Z2
P2
(20)
2p R2 C1
2p R1 C3
1
1
f
2p R2 C2
2p R3 C3
The value of R1 is somewhat arbitraty, but influences other component values. A value between 50 kΩ and
100 kΩ usually yields reasonable values.
The unity gain frequency is described in equation (21)
1
f
+
(Hertz)
C
(21)
2p R1 C2 G
where G is the reciprocal of the modulator gain at f .
C
The modulator gain as a function of frequency at f , is described in equation (22).
C
2
f
LC
1
ǒ Ǔ
AMOD(f) + AMOD
and G +
f
AMOD(f)
C
(22)
Minimum Load Resistance
Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too
small. The error amplifier has a finite output source and sink current which must be considered when sizing R2.
Too small a value does not allow the output to swing over its full range.
V
C (max)
3.45 V
2 mA
R2
+
+
+ 1725 W
(MIN)
I
SOURCE (min)
(23)
CALCULATING THE BOOST AN BP10 BYPASS CAPACITOR
The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor
should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate
charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance
is described in equation (24).
Q
g
C
+
(Farads)
BOOST
DV
(24)
The 10-V reference pin, BP10V needs to provide energy for both the synchronous MOSFET and the high-side
MOSFET via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in
equation (25).
ǒQ
gSRǓ
) Q
DV
gHS
C
+
(Farads)
BP10
(25)
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SLVS612 − APRIL 2006
APPLICATION INFORMATION
dv/dt Induced Turn−On
MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (V ) applications. The turn-on is caused
DS
by the capacitor divider that is formed by C
the MOSFET causes current flow through C
and C . High dv/dt conditions and drain-to-source voltage, on
GD
GS
and causes the gate-to-source voltage to rise. If the
GD
gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large
shoot-through currents. Therefore, the SR MOSFET should be chosen so that the C capacitance is smaller
GD
than the C
capacitance.
GS
High Side MOSFET Power Dissipation
The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The
conduction losses are a function of the I
high-side MOSFET conduction losses are defined by equation (26).
current through the MOSFET and the R
of the MOSFET. The
RMS
DS(on)
+ ǒIRMSǓ2
1 ) TC ƪT * 25ƫ
R J
ǒ
Ǔ
P
R
(Watts)
COND
DS(on)
(26)
where:
D
TC is the temperature coefficient of the MOSFET R
R DS(on)
The TC varies depending on MOSFET technology and manufacturer but is typically ranges between
R
.0035 ppm/_C and .010 ppm/_C.
The I
current for the high side MOSFET is described in equation (27).
RMS
Ǹ
ǒAmperesRMSǓ
I
+ I d
RMS
O
(27)
(28)
The switching losses for the high-side MOSFET are descibed in equation (28).
+ ǒV
Ǔ
f
P
I
t
(Watts)
SW
SW(fsw)
IN
OUT
SW
where:
D
D
D
I
t
f
is the DC output current
O
is the switching rise time, typically < 20 ns
is the switching frequency
SW
SW
Typical switching waveforms are shown in Figure 8.
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APPLICATION INFORMATION
I
D2
I
O
∆I
}
I
D1
d
1−d
BODY DIODE
CONDUCTION
BODY DIODE
CONDUCTION
SW
0
ANTI−CROSS
CONDUCTION
SYNCHRONOUS
RECTIFIER ON
HIGH SIDE ON
UDG−02139
Figure 9. Inductor Current and SW Node Waveforms
The maximum allowable power dissipation in the MOSFET is determined by equation (29).
ǒT * TAǓ
J
P +
(Watts)
T
q
JA
(29)
(30)
where:
P + P
) P
(Watts)
T
COND
SW(fsw)
and θ is the package thermal impedance.
JA
Synchronous Rectifier MOSFET Power Dissipation
The power dissipated in the synchronous rectifier MOSFET is comprised of three components: R
DS(on)
conduction losses, body diode conduction losses, and reverse recovery losses. R
) conduction losses can
DS(on
be found using equation (32) and the RMS current through the synchronous rectifier MOSFET is described in
equation (31).
Ǹ
ǒAmperesRMSǓ
I
+ I 1 * d
RMS
O
(31)
The body-diode conduction losses are due to forward conduction of the body diode during the anti−cross
conduction delay time. The body diode conduction losses are described by equation (32).
P
+ 2 I V t
f
(Watts)
SW
DC
O
F
DELAY
(32)
where:
D
V is the body diode forward voltage
F
D
t
is the total delay time just before the SW node rises.
DELAY
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SLVS612 − APRIL 2006
APPLICATION INFORMATION
The 2-multiplier is used because the body-diode conducts twice each cycle (once on the rising edge and once
on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recovery from
a forward bias to a reverse blocking state. The reverse recovery losses are described in equation (33).
P
+ 0.5 Q V f
(Watts)
SW
RR
RR
IN
(33)
where:
D
Q
is the reverse recovery charge of the body diode
RR
The total synchronous rectifier MOSFET power dissipation is described in equation (34).
P
+ P ) P ) P
(Watts)
COND
SR
DC
RR
(34)
TPS40056 POWER DISSIPATION
The power dissipation in the TPS40056 is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance, refer to [2] can be calculated from equation (35).
P
+ Q V f
(Watts)
SW
g
D
DR
(35)
And the total power dissipation in the TPS40056, assuming the same MOSFET is selected for both the high-side
and synchronous rectifier is described in equation (36).
2 P
D
P + ǒ Ǔ
) I
V
(Watts)
IN
T
Q
V
DR
(36)
(37)
or
P + ǒ2 Q f
Ǔ
) I V (Watts)
g
T
SW
Q
IN
where:
D
I is the quiescent operating current (neglecting drivers)
Q
The maximum power capability of the device’s PowerPad package is dependent on the layout as well as air flow.
The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no
air flow.
θ
= 36.51°C/W
JA
The maximum allowable package power dissipation is related to ambient temperature by equation (29).
Substituting equation (29) into equation (37) and solving for f
the TPS4005x. The result is described in equation (38).
yields the maximum operating frequency for
SW
ǒ
AǓ
DDǓ
V
T *T
J
ƪ ƫ* I
ǒ Ǔ
Q
ǒ
q
JA
f
+
(Hz)
SW
ǒ2 QgǓ
(38)
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SLVS612 − APRIL 2006
LAYOUT CONSIDERATIONS
The PowerPADt package
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For
maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the
package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP
(PWP) package the area is 5 mm x 3.4 mm [3].
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper
is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with
a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally
[3]
Enhanced Package and the mechanical illustration at the end of this document for more information on the
PowerPAD package.
X: Minimum PowerPAD = 1.8 mm
Y: Minimum PowerPAD = 1.4 mm
Thermal Pad
4,50 mm 6,60 mm
4,30 mm 6,20 mm
X
1
10
Y
Figure 10. PowerPAD Dimensions
MOSFET Packaging
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions.
In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance
(θ ) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends
JA
on proper layout and thermal management. The θ specified in the MOSFET data sheet refers to a given
JA
copper area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch
of 2-ounce copper on a G−10/FR−4 board. Lower thermal impedances can be achieved at the expense of board
area. Please refer to the selected MOSFET’s data sheet for more information regarding proper mounting.
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LAYOUT CONSIDERATIONS
Grounding and Circuit Layout Considerations
The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that
circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, R , and ILIM should be connected to the SGND plane. The
T
SGND plane should only make a single point connection to the PGND plane.
Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible
to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located
near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).
The SW pin Schottky diode, D2 in Figure 10, should be placed close to the TPS40056 with short, wide traces
to pins 9 and 12.
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DESIGN EXAMPLE
D
D
D
D
D
D
D
Input Voltage: 10 Vdc to 14.4 Vdc
Output voltage: 1.25 V 1% (1.2375 ≤ V ≤1.2625)
O
Output current: 8 A (maximum, steady state), 10 A (surge, 10ms duration, 10% duty cycle maximum)
Output ripple: 33 mV at 8 A
P-P
Output load response: 0.1 V => 10% to 90% step load change, from 1 A to 7 A
Operating temperature: −40°C to 85°C
f
=170 kHz
SW
1. Calculate maximum and minimum duty cycles
V
V
V
O(min)
O(max)
IN(min)
1.2375
14.4
1.2625
10
d
+
+
+ 0.086
d
+
MAX
+
+ 0.126
MIN
V
IN(max)
(39)
2. Select switching frequency
The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET, t , must be greater
ON
than 400 ns (see Electrical Characteristics table). Therefore
V
t
O(min)
ON
+
or
V
T
SW
IN(max)
(40)
V
ȡǒ Ǔȣ
O(min)
V
IN(max)
+ȧ
ȧ
ȧ
ȧ
1
+ f
ȧ
SW
T
T
SW
ON
ȧ
Ȣ
Ȥ
(41)
(42)
Using 450 ns to provide margin,
0.086
f
+
+ 191 kHz
SW
450 ns
Since the oscillator can vary by 10%, decrease f , by 10%
SW
f
+ 0.9 191 kHz + 172 kHz
SW
and therefore choose a frequency of 170 kHz.
3. Select ∆I
In this case ∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load.
DI + I 2 0.2 + 8 2 0.2 + 3.2 A
O
(43)
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DESIGN EXAMPLE
4. Calculate the power losses
Power losses in the high-side MOSFET (Si7860DP) at 14.4-V where switching losses dominate can be
IN
calculated from equation (27).
Ǹ
Ǹ
I
+ I d + 8 0.086 + 2.35 A
O
RMS
(44)
(45)
substituting (27) into (26) yields
2
(
(
))
P
+ 2.35 0.008 1 ) 0.007 150 * 25 + 0.083 W
COND
and from equation (28), the switching losses can be determined.
+ ǒV
Ǔ
f
P
I t
+ 14.4 V 8 A 20 ns 170 kHz + 0.39 W
SW
SW(fsw)
IN
O
SW
(46)
(47)
The MOSFET junction temperature can be found by substituting equation (30) into equation (29)
O
T + ǒP
Ǔ
(
)
) P
q ) T + 0.083 ) 0.39 40 ) 85 + 90 C
J
COND
SW
JA
A
5. Calculate synchronous rectifier losses
The synchronous rectifier MOSFET has two loss components, conduction, and diode reverse recovery losses.
The conduction losses are due to I losses as well as body diode conduction losses during the dead time
RMS
associated with the anti-cross conduction delay.
The I
current through the synchronous rectifier from (31)
RMS
Ǹ
Ǹ
I
+ I 1 * d + 8 1 * 0.126 + 7.48 A
O RMS
RMS
(48)
The synchronous MOSFET conduction loss from (26) is:
2
(
(
))
P
+ 7.48 0.008 1 ) 0.007 150 * 25 + 0.83 W
COND
(49)
(50)
(51)
(52)
(53)
The body diode conduction loss from (32) is:
+ 2 I V t f
P
+ 2 8.0 A 0.8 V 100 ns 170 kHz + 0.218
SW
DC
O
FD
DELAY
The body diode reverse recovery loss from (33) is:
+ 0.5 Q V f + 0.5 30 nC 14.4 V 170 kHz + 0.037 W
P
RR
RR
IN
SW
The total power dissipated in the synchronous rectifier MOSFET from (34) is:
+ P ) P ) P + 0.037 ) 0.83 ) 0.218 + 1.085 W
P
SR
RR
COND
DC
The junction temperature of the synchronous rectifier at 85°C is:
o
(
)
T + P q ) T + 1.085 40 ) 85 + 128 C
J
SR
JA
A
In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the
overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode
conduction and reverse recovery periods.
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SLVS612 − APRIL 2006
DESIGN EXAMPLE
6. Calculate the inductor value
The inductor value is calculated from equation (3).
(
)
14.4 * 1.25 V 1.25 V
L +
+ 2.1 mH
14.4 V 3.2 A 170 kHz
(54)
A 2.9-µH Coev DXM1306−2R9 or 2.6-µH Panasonic ETQ−P6F2R9LFA can be used.
7. Setting the switching frequency
The clock frequency is set with a resistor (R ) from the RT pin to ground. The value of R can be found from
T
T
equation (1), with f
in kHz.
SW
1
R +
ǒ
* 23
Ǔ
kW + 307 kW N use 309 kW
T
*6
f
17.82 10
SW
(55)
8. Calculating the output capacitance (C )
O
In this example the output capacitance is determined by the load response requirement of ∆V = 0.1 V for a 1 A
to 7 A step load. C can be calculated using (9)
O
2
2
2.9 m ǒ(8 A * 1 A) Ǔ
)
(
C
+
+ 761 mF
O
2
2
ǒ(
) Ǔ
)
(
1.25 * 1.15
(56)
Using (4) we can calculate the ESR required to meet the output ripple requirements.
1
33 mV + 3.2 AǒESR )
Ǔ
8 761 mF 170 kHz
(57)
(58)
ESR + 10.3 mW * 1.0 mW + 9.3 mW
For this design example two (2) Panasonic SP EEFUEOD471R capacitors, (2.0 V, 470 µF, 12 mΩ) are used.
9. Calculate the soft-start capacitor (C
)
SS
This design requires a soft−start time (t
) of 1 ms. C can be calculated on (11)
SS
START
2.3 mA
0.7 V
C
+
1 ms + 3.29 nF + 3300 pF
SS
(59)
23
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SLVS612 − APRIL 2006
DESIGN EXAMPLE
10. Calculate the current limit resistor (R
)
ILIM
The current limit set point depends on t
design,
, V ,C and I
LOAD
at start-up as shown in equation (12). For this
(60)
START
O
O
940 mF 1.25 V
I
u
) 8.0 A + 9.2 A
LIM
1 ms
For this design, set I for 11.0 A
plus one-half the ripple current of 3.2 A and R
minimum. From equation (13), with I equal to the DC output surge current
OC
LIM
DC
is increased 30% (1.3 * 0.008) to allow for MOSFET heating.
DS(on)
(0.03)
8.6 mA
12.6 A 0.0104W
8.6 mA
R
+
)
+ 15.24 kW * 3.5 kW + 11.74 kW ^ 11.8 W
ILIM
(61)
(62)
11. Calculate loop compensation values
Calculate the DC modulator gain (A
12
) from equation (14)
MOD
( )
+ 20 log 6 + 15.6 dB
A
+
+ 6.0
A
MOD(dB)
MOD
2
Calculate the output filter L-C poles and C ESR zeros from (16) and (17)
O
O
1
1
f
+
+
+ 3.05 kHz
LC
Ǹ
2p ǸL C
2p 2.9 mH 940 mF
O
(63)
(64)
and
1
1
f +
+
+ 28.2 kHz
Z
2p ESR C
2p 0.006 940 mF
O
Select the close-loop 0 dB crossover frequency, f . For this example f = 20 kHz.
C
C
Select the double zero location for the Type III compensation network at the output filter double pole at 3.05 kHz.
Select the double pole location for the Type III compensation network at the output capacitor ESR zero at
28.2 kHz.
The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from equation (22).
2
2
f
LC
3.05 kHz
20 kHz
ǒ
Ǔ
ǒ Ǔ
A
+ A
MOD
+ 6
+ 0.14
MOD(f)
f
C
(65)
(66)
And also from equation (22).
1
1
0.14
G +
+
+ 7.14
A
MOD(f)
Choose R1 = 100 kΩ
24
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SLVS612 − APRIL 2006
DESIGN EXAMPLE
The poles and zeros for a type III network are described in equations (20) and (21).
1
1
f
+
+
N C3 +
N R3 +
+ 522 pF, choose 560 pF
+ 10.08 kW, choose 10 kW
Z2
2p 100 kW 3.05 kHz
(67)
(68)
2p R1 C3
1
1
f
f
P2
2p R3 C3
2p 560 pF 28.2 kHz
1
1
f
+
N C2 +
+ 11.1 pF, choose 10 pF
C
2p 100 kW 7.14 20 kHz
(69)
2p R1 C2 G
1
1
+
+
N R2 +
+ 564 kW, choose 562 kW
P1
2p R2 C2
2p 10 pF 28.2 kHz
(70)
(71)
1
1
f
N C1 +
+ 92.9 pF, choose 100 pF
Z1
2p R2 C1
2p 562 kW 3.05 kHz
Calculate the value of R
EA_REF input specification of 0.5 V to 1.5 V, an R
from equation (17) with R1 = 100 kΩ. Since the output of 1.25-V is within the
BIAS
resistor is not required.
BIAS
CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage droop
on the BOOST pin from equation (24) is:
Q
g
18 nC
0.5 V
C
+
+
+ 36 nF
BOOST
DV
(72)
(73)
and the BP10V capacitance from (25) is
Q
) Q
DV
2 Q
DV
gHS
gSR
g
36 nC
0.5 V
C
+
+
+
+ 72 nF
BP(10 V)
For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1.0-µF capacitor is used
for the BP10V bypass.
Figure 10 shows component selection for the 10-V to 14.4-V to 1.25-V at 8 A dc-to-dc converter specified in the
design example.
REFERENCES
1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM−1400 Topic 2.
2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI
Literature No. SLMA002
25
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SLVS612 − APRIL 2006
UDG−03100
Figure 11. 12-V to 1.25-V at 8-A DC-to-DC Converter (DDR) Design Example
26
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SLVS612 − APRIL 2006
Center Power Pad Solder Stencil Opening
Stencil Thickness
0.1mm
X
Y
2.5
2.65
2.46
2.3
0.127mm
0.152mm
0.178mm
2.31
2.15
2.05
2.15
27
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