TPS40057QPWPRQ1_技术文档

TPS40054

TPS40055

8

TPS40057

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SLUS593H –DECEMBER 2003–REVISED JULY 2012

WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER

Check for Samples: TPS40054, TPS40055, TPS40057

1

FEATURES

CONTENTS

2

•

Operating Input Voltage 8 V to 40 V

Device Ratings

2

3

Input Voltage Feed-Forward Compensation

< 1 % Internal 0.7-V Reference

Electrical Characteristics

Pin Descriptions

5

Programmable Fixed-Frequency Up to 1-MHz

Voltage Mode Controller

Application Information

Design Examples

7

•

Internal Gate Drive Outputs for High-Side and

Synchronous N-Channel MOSFETs

22

27

Additional References

•

16-Pin PowerPAD™ Package (θ_JC= 2°C/W)

Thermal Shutdown

DESCRIPTION

The TPS4005x is a family of high-voltage, wide input

(8 V to 40 V), synchronous, step-down controllers.

The TPS4005x family offers design flexibility with a

variety of user-programmable functions, including

soft-start, UVLO, operating frequency, voltage feed-

Externally Synchronizable

Programmable High-Side Sense Short-Circuit

Protection

•

Programmable Closed-Loop Soft-Start

TPS40054 Source Only

forward,

high-side

current

limit,

and

loop

compensation.

TPS40055 Source/Sink

The TPS4005x uses voltage feed-forward control

techniques to provide good line regulation over the

wide (4:1) input voltage range, and fast response to

input line transients. Near-constant modulator gain

with input variation eases loop compensation. The

externally programmable current limit provides pulse-

by-pulse current limit, as well as hiccup mode

operation utilizing an internal fault counter for longer

duration overloads.

TPS40057 Source/Sink With V_OPrebias

APPLICATIONS

•

Power Modules

Networking/Telecom

Industrial/Servers

TPS4005xPWP

+

1

2

3

4

5

6

7

8

16

15

KFF

ILIM

VIN

RT

V_IN

BOOST 14

HDRV 13

BP5

SYNC

–

12

SW

SGND

SS/SD

VFB

+

V_O

–

BP10 11

LDRV 10

PGND

9

COMP

UDG-03179

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS40054

TPS40055

TPS40057

SLUS593H –DECEMBER 2003–REVISED JULY 2012

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T_A

PACKAGE

APPLICATION

OUTPUT SUPPLY

MINIMUM QUANTITY

DEVICE NUMBER

TPS40054PWP

TPS40054PWPR

TPS40055PWP

TPS40055PWPR

TPS40057PWP

TPS40057PWPR

Tube

90

2000

90

Source

Tape and Reel

Tube

Plastic HTSSOP

(PWP)

–40°C to 85°C

Source/Sink

Tape and Reel

Tube

2000

90

Source/Sink with

prebias

Tape and Reel

2000

DEVICE RATINGS

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

TPS40054

TPS40055

UNIT

TPS40057

–0.3 to 6

–0.3 to 45

–2.5

VFB, SS/SD, SYNC

VIN, SW

V_IN

Input voltage range SW, transient < 50 ns

SW, transient < 50 ns, V_VIN< 14 V

–5.0

KFF, with I_IN(max)= – 5 mA

COMP, RT, SS/SD

KFF

–0.3 to 11

–0.3 to 6

5

Output voltage

range

V_O

mA

µA

I_O

Output current

RT

200

(2)

T_J

Maximum junction temperature

Operating junction temperature range

Storage temperature

150

T_J

–40 to 125

–55 to 150

°C

T_stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Device may shut down at junction temperatures below 150°C

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX UNIT

V_IN

T_A

Input voltage

8

40

85

V

Operating free-air temperature

–40

°C

THERMAL INFORMATION

THERMAL METRIC⁽¹⁾

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

PWP (20 PINS)

UNITS

θ_JA

38.3

28.0

9.0

θ_JCtop

θ_JB

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

8.9

θ_JCbot

2.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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SLUS593H –DECEMBER 2003–REVISED JULY 2012

ELECTRICAL CHARACTERISTICS

T_A= –40°C to 85°C, V_IN= 24 V_dc, R_T= 90.9 kΩ, I_KFF= 150 µA, f_SW= 500 kHz, all parameters at zero power dissipation

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT SUPPLY

V_INInput voltage range, VIN

OPERATING CURRENT

8

40

3.0

5.2

570

V

mA

V

I_DD

Quiescent current

Output drivers not switching, V_FB≥ 0.75 V

1.5

5.0

BP5

V_BP5

Output voltage

I_O≤ 1 mA

4.7

470

2

OSCILLATOR/RAMP GENERATOR

f_OSC

V_RAMP

V_IH

Accuracy

8 V ≤ V_IN≤ 40 V

520

2.0

kHz

V

PWM ramp voltage⁽¹⁾

High-level input voltage, SYNC

Low-level input voltage, SYNC

Input current, SYNC

Pulse width, SYNC

RT voltage

V_PEAK– V_VAL

V_IL

0.8

10

V

µA

ns

V

I_SYNC

5

50

2.38

85%

80%

V_RT

2.50

2.58

94%

V_FB= 0 V, f_SW≤ 500 kHz

V_FB= 0 V, 500 kHz ≤ f_SW≤ 1 MHz⁽¹⁾

D_MAX

Maximum duty cycle

Minumum duty cycle

V_FB≥ 0.75 V

0%

3.65

1100

V_KFF

I_KFF

Feed-forward voltage

Feed-forward current operating range^{(1) (2)}

3.35

20

3.48

V

µA

SOFT START

I_SS/SD

Soft-start source current

1.65

2.35

3.7

2.95

µA

V

V_SS/SDSoft-start clamp voltage

t_DSCH

t_SS/SD

BP10

V_BP10

Discharge time

Soft-start time

C_SS/SD= 220 pF

1.6

2.2

2.8

µs

C_SS/SD= 220 pF, 0 V ≤ V_SS/SD≤ 1.6 V

115

150

215

Output voltage

I_O≤ 1 mA

9.0

9.6

10.3

V

ERROR AMPLIFIER

8 V ≤ V_IN≤ 40 V, T_A= 25°C

0.698

0.693

3.0

0.700

5.0

0.704

0.707

0.715

V_FB

Feedback input voltage

8 V ≤ V_IN≤ 40 V, 0°C ≤ T_A≤ 85°C

8 V ≤ V_IN≤ 40 V, -40°C≤ T_A≤ 85°C

V

G_BW

A_VOL

I_OH

Gain bandwidth⁽¹⁾

MHz

dB

Open loop gain

60

80

High-level output source current

Low-level output sink current

High-level output voltage

Low-level output voltage

Input bias current

2.0

4.0

mA

I_OL

2.0

4.0

V_OH

V_OL

I_BIAS

I_SOURCE= 500 µA

I_SINK= 500 µA

V_FB= 0.7 V

3.2

3.5

V

0.20

100

0.35

200

nA

(1) Ensured by design. Not production tested.

(2) I_KFFincreases with SYNC frequency, maximum duty cycle decreases with I_KFF

.

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ELECTRICAL CHARACTERISTICS (continued)

T_A= –40°C to 85°C, V_IN= 24 V_dc, R_T= 90.9 kΩ, I_KFF= 150 µA, f_SW= 500 kHz, all parameters at zero power dissipation

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CURRENT LIMIT

I_SINK

Current limit sink current

8.5

10.0

300

200

11.5

µA

ns

V_ILIM= 23.7 V, V_SW= (V_ILIM– 0.5 V)

V_ILIM= 23.7 V, V_SW= (V_ILIM– 2 V)

Propagation delay to output

t_ON

Switch leading-edge blanking pulse time⁽³⁾

Off time during a fault (soft-start cycle time)

100

t_OFF

7

cycles

mV

T_A= 25°C

–90

–120

–70

–50

–38

–20

V_OS

Offset voltage SW vs. ILIM

V_ILIM= 23.6 V, 0°C ≤ T_A≤ 85°C

V_ILIM= 23.6 V, -40°C ≤ T_A≤ 85°C

OUTPUT DRIVER

t_LRISE

t_LFALL

t_HRISE

t_HFALL

Low-side driver rise time

48

24

48

36

96

48

96

72

C_LOAD= 2200 pF

Low-side driver fall time

High-side driver rise time

High-side driver fall time

ns

V

C_LOAD= 2200 pF (HDRV – SW)

V_BOOST

–1.5 V

V_BOOST

–1.0 V

V_OH

V_OL

V_OH

V_OL

High-level ouput voltage, HDRV

Low-level ouput voltage, HDRV

High-level ouput voltage, LDRV

I_HDRV= –0.1 A (HDRV – SW)

I_HDRV= 0.1 A (HDRV – SW)

I_LDRV= –0.1 A

0.75

V_BP10

–1.4 V

V_BP10

– 1.0 V

Low-level ouput voltage, LDRV

Minimum controllable pulse width

I_LDRV= 0.1 A

0.5

100

150

ns

SS/SD SHUTDOWN

V_SD

V_EN

Shutdown threshold voltage

Device active threshold voltage

Outputs off

V_IN= 24.0 V

90

125

210

160

245

mV

190

BOOST REGULATOR

V_BOOSTOutput voltage

31.2

–10

32.2

–5

33.5

0

V

RECTIFIER ZERO CURRENT COMPARATOR (TPS40054 ONLY)

V_SW

Switch voltage

LDRV output OFF

mV

µA

SW NODE

I_LEAK

Leakage current⁽³⁾(out of pin)

25

THERMAL SHUTDOWN

Shutdown temperature⁽³⁾

Hysteresis⁽³⁾

165

20

T_SD

°C

V

UVLO

V_UVLO

V_DD

KFF programmable threshold voltage

UVLO, fixed

R_KFF= 28.7 kΩ

6.95

7.2

7.50

7.5

7.95

7.9

V_DD

UVLO, hysteresis

0.46

(3) Ensured by design. Not production tested.

4

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SLUS593H –DECEMBER 2003–REVISED JULY 2012

Table 1. PIN DESCRIPTIONS

TERMINAL

I/O

DESCRIPTION

NAME NO.

Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the SW voltage. A

0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.

BOOST 14

O

5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with an

external DC load of 1 mA or less.

BP5

3

10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF

ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.

BP10

11

Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the VFB

pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large

signal transient response.

COMP

HDRV

ILIM

8

O

I

Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW

(MOSFET off).

13

16

Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage

drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage

drop (VIN – SW) across the high-side MOSFET during conduction.

A resistor is connected from this pin to VIN to program the amount of voltage feed-forward and UVLO level. The

current fed into this pin is internally divided and used to control the slope of the PWM ramp.

KFF

1

10

9

I

Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET

off).

LDRV

PGND

O

Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the

lower MOSFET(s).

RT

2

5

I

A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.

Signal ground reference for the device.

SGND

Soft-start programming and shutdown pin. A capacitor connected from this pin to ground programs the soft-start time.

The capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS/SD pin is

used as a second non-inverting input to the error amplifier. The output voltage begins to rise when V_SS/SDis

approximately 0.85 V. The output continues to rise and reaches regulation when V_SS/SDis approximately 1.55 V. The

controller is considered shut down when V_SS/SDis 125 mV or less. The internal circuitry is enabled when V_SS/SDis 210

mV or greater. When V_SS/SDis less than approximately 0.85 V, the outputs cease switching and the output voltage

(V_O) decays while the internal circuitry remains active.

SS/SD

6

This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40054 also

uses this pin for zero current sensing.

SW

12

4

I

Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency.

If synchronization is not used, connect this pin to SGND.

SYNC

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference

voltage, 0.7 V.

VFB

VIN

7

I

15

Supply voltage for the device.

PWP PACKAGE (TOP VIEW)

KFF

RT

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ILIM

VIN

BP5

BOOST

HDRV

SW

SYNC

SGND

SS/SD

VFB

Thermal Pad

BP10

LDRV

PGND

COMP

A. For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.

B. PowerPAD™ heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.

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SIMPLIFIED BLOCK DIAGRAM

ILIM

16

BP10

15

11

14

VIN

CLK

2

4

RT

CLK

Oscillator

+

SYNC

BOOST

10V Regulator

CLK

7

1V5REF

CL

7

Ramp Generator

07VREF

7

3-bit up/down

Fault Counter

1

KFF

N-channel

Driver

1V5REF

3V5REF

BP5

7

13

12

HDRV

SW

Reference

Voltages

Restart

Fault

BP5

3

7

BP5

VFB

07VREF

7

BP10

+

7

Fault

7

Soft Start

S

R

Q

CL

7

SS/SD

6

N-channel

Driver

10

LDRV

PGND

t

START

Overtemperature

SW

Restart

7

S

R

Q

CLK

7

9

COMP

8

Q

Zero Current Detector

(TPS40054 Only)

5

UDG-08118

SGND

6

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SLUS593H –DECEMBER 2003–REVISED JULY 2012

APPLICATION INFORMATION

The TPS40054/55/57 family of devices allows the user to optimize the PWM controller to the specific application.

The TPS40057 is safe for pre-biased outputs, not turning on the synchronous rectifier until the high-side FET has

already started switching.

The TPS40054 operates in one quadrant and sources output current only, allowing for paralleling of converters

and ensures that one converter does not sink current from another converter. This controller also emulates a

non-synchronous buck converter at light loads where the inductor current goes discontinuous. At continuous

output inductor currents the controller operates as a synchronous buck converter to optimize efficiency.

The TPS40055 operates in two quadrants, sourcing and sinking output current.

SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)

The TPS4005x has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the

master clock to the ramp generator circuit. The switching frequency, f_SWin kHz, of the clock oscillator is set by a

single resistor (R_T) to ground. The clock frequency is related to R_T, in kΩ by Equation 1 and the relationship is

charted in Figure 2.

1

_{R +}ǒ

_* 17Ǔ_kW

T

*6

f

17.82 10

SW

(1)

PROGRAMMING THE RAMP GENERATOR CIRCUIT

The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides

voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp

magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since

the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).

V_IN

SW

V_PEAK

COMP

RAMP

V_VALLEY

t₁

t_ON1

t_ON2

t₂

t_ON

D =

t_ON1> t_ON2and D₁> D₂

UDG-08119

t

Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle

The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The

PWM ramp time is programmed via a single resistor (R_KFF) pulled up to VIN. R_KFFis related to R_T, and the

minimum input voltage, V_IN(min)through the following:

R_KFF= V

- V_KFF´ 58.14´R +1340 W

T

(

)

(

)

IN(min)

where

•

V_IN(min)is the ensured minimum start-up voltage (the actual start-up voltage is nominally about 10% lower at

25°C)

•

R_Tis the timing resistance in kΩ

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•

V_KFFis the voltage at the KFF pin (typical value is 3.48 V)

(2)

The curve showing the R_KFFrequired for a given switching frequency, f_SW, and V_UVLOis shown in Figure 3.

For low-input voltage and high duty-cycle applications, the voltage feed-forward may limit the duty cycle

prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and

regulates the output voltage. For more information on large duty cycle operation, refer to Application Note

(SLUA310), Effect of Programmable UVLO on Maximum Duty Cycle.

SWITCHING FREQUENCY

vs

TIMING RESISTANCE

FEED-FORWARD IMPEDANCE

vs

SWITCHING FREQUENCY

600

500

700

600

500

400

300

V

IN

= 9 V

300

200

V

= 15 V

IN

V

IN

= 25 V

200

100

0

100

0

100 200 300 400 500 600 700 800 900 1000

f

SW

- Switching Frequency - kHz

f

SW

- Switching Frequency - kHz

Figure 2.

Figure 3.

UVLO OPERATION

The TPS4005x uses variable (user-programmable) UVLO protection. See the Programming the Ramp Generator

section for more information on setting the UVLO voltage. The UVLO circuit holds the soft-start low until the input

voltage has exceeded the user-programmable undervoltage threshold.

The TPS4005x uses the feed-forward pin, KFF, as a user-programmable low-line UVLO detection. This variable

low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage

condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude.

The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The

KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor

can be referenced to the oscillator frequency as descibed in Equation 2.

The programmable UVLO function uses a three-bit counter to prevent spurious shut-downs or turn-ons due to

spikes or fast line transients. When the counter reaches a total of seven counts in which the ramp duration is

shorter than the clock cycle, a powergood signal is asserted and a soft-start initiated, and the upper and lower

MOSFETS are turned off.

Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp

duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4).

8

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UVLO Threshold

VIN

Clock

PWM RAMP

1

2

3

4

5

6

7

1

2

1 2 3 4 5 6 7

PowerGood

UDG-02132

Figure 4. Undervoltage Lockout Operation

The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the

device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the

nominal start-up voltage.

The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter

starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents

nuisance shutdowns at the UVLO point. With R_Tchosen to select the operating frequency and R_KFFchosen to

select the start-up voltage, the approximate amount of hysteresis voltage is shown in Figure 5.

UNDERVOLTAGE LOCKOUT THRESHOLD

vs

HSYTERESIS

1.2

1.0

0.8

0.6

0.4

0.2

0

10

15

20

25

30

35

40

V

– Undervoltage Lockout Threshold – V

UVLO

Figure 5.

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Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This

applies to applications which have high impedance on the input voltage line or which have excessive ringing on

the V_INline. The input voltage impedance can cause the input voltage to sag enough at start up to cause a

UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and

cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to

prevent the nuisance UVLO shutdown.

Assuming a hysteresis current of 10% I_KFF, and the peak detector charges to 8 V and V_IN(min)= 10 V, the value of

R_Ais calculated by Equation 3 using a R_KFF= 71.5 kΩ.

R_KFF´ 8 - 3.48

(

)

R_A

=

= 495kW = 499kW

0.1´ V

(

- 3.48

)

IN min

(

)

(3)

C_Ais chosen to maintain the peak voltage between switching cycles in order to keep the capacitor charge from

drooping 0.1 V (from 8 V to 7.9 V).

8 - 3.48

(

)

C

=

A

R

(

´ 7.9´ f

SW

)

A

(4)

The value of C_Amay calculate to less than 10 pF, but some standard value up to 47 pF works adequately. The

diode can be a small-signal switching diode or Schottky rated for more then 20 V. Figure 6 illustrates a typical

implementation using a small switching diode.

The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the

device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the

nominal start up voltage.

TPS4005xPWP

R

KFF

71.5 kW

R

A

499 kW

1

2

3

4

5

6

7

8

KFF

ILIM 16

VIN 15

C

RT

A

47 pF

BP5

BOOST 14

HDRV 13

SW 12

SYNC

SGND

SS

BP10 11

LDRV 10

VFB

D

COMP

PGND

9

A

1N914, 1N4150

Type Signal Diode

PGND

UDG-08102

Figure 6. Hysteresis for Programmable UVLO

10

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BP5 AND BP10 INTERNAL VOLTAGE REGULATORS

Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in Figure 7

and Figure 8. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BP10

regulation characteristics is also based on the load presented by switching the external MOSFETs.

INPUT VOLTAGE

vs

INPUT VOLTAGE

vs

BP5 VOLTAGE

BP10 VOLTAGE

6

10

9

110°C

5

4

8

7

6

110°C

25°C

– 55°C

5

4

25°C

3

2

3

2

– 55°C

1

0

1

2

4

6

8

10

12

2

4

6

8

10

12

V

– Input Voltage – V

V

IN

– Input Voltage – V

IN

Figure 7.

Figure 8.

SELECTING THE INDUCTOR VALUE

The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current

at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is

physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater

number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good

compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the

load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in

Equation 5.

ǒ_V

V

Ǔ

* V V

IN

O

L +

(Henries)

DI f

SW

where

•

V_Ois the output voltage

ΔI is the peak-to-peak inductor current

(5)

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CALCULATING THE OUTPUT CAPACITANCE

The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any

output voltage deviation requirement during a load transient.

The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst-case output

ripple is described in Equation 6.

æ

ö

÷

ø

æ

ç

è

ö

÷

ø

1

D V = DI´ ESR +

ç

è

8´ C_O´ f_SW

where

•

C_Ois the output capacitance

ESR is the equivalent series resistance of the output capacitance

(6)

The output ripple voltage is typically between 90% and 95% due to the ESR component.

The output capacitance requirement typically increases in the presence of a load transient requirement. During a

step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess

inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The

amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the

inductor.

Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the

inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in

Equation 7.

1

2

E + L I (Joules)

L

(7)

where

_OHǓ²ǒ Ǔ²

2

ǒ

ǒ₍

₎Ǔ

_{I +}ƪ_I

ƫ

* I

Amperes

OL

•

I_OHis the output current under heavy load conditions

•

I_OLis the output current under light load conditions

(8)

(9)

Energy in the capacitor is described in Equation 9.

1

2

E

+

C V (Joules)

C

where

ǒ Ǔ²ǒ Ǔ²ǒ_Volts

2

Ǔ

_{V +}ƪ_V

ƫ

* V

f

i

where

•

V_fis the final peak capacitor voltage

V_iis the initial capacitor voltage

(10)

Substituting Equation 8 into Equation 7, then substituting Equation 10 into Equation 9, then setting Equation 9

equal to Equation 7, and then solving for C_Oyields the capacitance described in Equation 11.

ǒ

_OHǓ²ǒ Ǔ²

ƪ_I

ƫ

(Farads)

L

* I

OL

C

+

O

ǒ Ǔ²ǒ Ǔ²

ƪ_V

ƫ

* V

f

i

(11)

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PROGRAMMING SOFT START

The TPS4005x uses a closed-loop soft-start system to ensure a controlled ramp of the output during startup. The

reference voltage used for the startup is derived in the following manner. A capacitor (C_SS/SD) is connected to the

SS/SD pin. There is a ramped voltage generated at this pin by charging C_SS/SDwith a current source. A value of

0.85 V is subtracted from the voltage at the SS/SSD pin and is applied to a non-inverting input of the error

amplifier. This is the effective soft-start ramp voltage, V_SSRMP. The error amplifier also has the 0.7-V reference

(V_FB) voltage applied to a non-inverting input. The structure of the error amplifier input stage is such that the

lower of V_FBor V_SSRMPbecomes the dominant voltage that the error amplifier uses to regulate the FB pin. This

provides a clean, closed-loop startup while V_SSRMPis lower than V_FBand a precision reference regulated supply

as V_SSRMPclimbs above V_FB. To ensure a controlled ramp-up of the output voltage, the soft-start time should be

greater than the L-C_Otime constant as described in Equation 12.

Ǹ_{L C}

t

w 2p

(seconds)

START

O

where

•

t_STARTis the startup ramp time in s

(12)

There is a direct correlation between t_STARTand the input current required during start-up. The faster t_START, the

higher the input current required during start-up. This relationship is described in more detail in the section titled,

Programming the Current Limit which follows. The soft-start capacitance, C_SS/SD, is described in Equation 13.

For applications in which the V_INsupply ramps up slowly (typically between 50 ms and 100 ms), it may be

necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO

tripping. The soft-start time should be longer than the time that the V_INsupply transitions between 6 V and 7 V.

æ

ç

è

ö

÷

ø

I_{SS / SD}

C_{SS / SD}

=

´ t

F

_START( )

V_FB

where

•

I_SS/SDis the soft-start charge current (typical value is 2.35 μA)

V_FBis the feedback reference voltage (typical value is 0.7 V)

(13)

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PROGRAMMING CURRENT LIMIT

The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection

scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the

MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a

resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across

the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.

The MOSFET remains off until the next switching cycle is initiated.

The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and

decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is

issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this

period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM

is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter

counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 9 for typical overcurrent

protection waveforms.

The minimum current limit setpoint (I_ILIM) is calculated in Equation 14.

æ

ç

è

ö

÷

ø

C

t

´ V

O

I

=

+ I

A

_LOAD( )

ILIM

START

where

•

I_LOADis the load current at start-up

(14)

HDRV

CLOCK

t

BLANKING

V

ILIM

V -V

VIN SW

SS

7 CURRENT LIMIT TRIPS

(HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP)

UDG-02136

7 SOFT-START CYCLES

Figure 9. Typical Current Limit Protection Waveforms

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The current limit programming resistor (R_ILIM) is calculated using Equation 15. Care must be taken in choosing

the values used for V_OSand I_SINKin the equation. In order to ensure the output current at the overcurrent level,

the minimum value of I_SINKand the maximum value of V_OSmust be used. The main purpose is hard fault

protection of the power switches.

( )_ë

42.86´10^-3

I_SINK

I_OC´R_{DS on max}+ V_OS

é

ù

û

R_ILIM

=

+

W

( )

1.12´I_SINK

where

•

I_SINKis the current into the ILIM pin and is 8.5 μA, minimum

I_OCis the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current

V_OSis the overcurrent comparator offset and is –20 mV, maximum

(15)

SYNCHRONIZING TO AN EXTERNAL SUPPLY

The TPS4005x can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the

falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher

than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock

generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the

frequency programmed by R_T.

The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM

ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically

this is of concern under low-line conditions only. In any case, R_KFFneeds to be adjusted for the higher switching

frequency. In order to specify the correct value for R_KFFat the synchronizing frequency, calculate a dummy value

for R_Tthat would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the

design.

æ

ç

è

ö

1

÷

R

=

-17 kW

_÷( )

T dummy

(

)

-6

f

´17.82´10

SYNC

ø

where

•

f_SYNCis the synchronizing frequency in kHz

(16)

(17)

Use the value of R_T(dummy)to calculate the value for R_KFF

.

R_KFF= V

- V_KFF´ 58.14´R

+1340 W

T dummy

)

(

IN min

(

)

(

)

where

•

R_T(dummy)is in kΩ

This value of R_KFFensures that UVLO is not engaged when operating at the synchronization frequency.

LOOP COMPENSATION

Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x

uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be

included. The generic modulator gain is described in Figure 10. Duty cycle, D, varies from 0 to 1 as the control

voltage, V_C, varies from the minimum ramp voltage to the maximum ramp voltage, V_S. Also, for a synchronous

buck converter, D = V_O/ V_IN. To get the control voltage to output voltage modulator gain in terms of the input

voltage and ramp voltage,

V

O

C

S

O

C

IN

D +

+

or

+

V

IN

S

(18)

With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore the

moderator DC gain is independent to the change of input voltage.

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For the TPS4005x, with V_IN(min)being the minimum input voltage required to cause the ramp excursion to reach

the maximum ramp amplitude of V_RAMP, the modulator dc gain is shown in Equation 19.

V

IN min

æ

ç

ö

÷

æ

ç

ö

÷

IN min

(

)

(

)

A

=

or

A

= 20´log

MOD dB

MOD

( )

ç

è

÷

ø

ç

è

÷

ø

V

RAMP

(19)

Calculate the Poles and Zeros

For a buck converter using voltage mode control there is a double pole due to the output L-C_O. The double pole

is located at the frequency calculated in Equation 20.

1

f

+

(Hertz)

LC

Ǹ_{L C}

2p

O

(20)

There is also a zero created by the output capacitance, C_O, and its associated ESR. The ESR zero is located at

the frequency calculated in Equation 21.

1

f +

(Hertz)

Z

2p ESR C

O

(21)

Calculate the value of R_BIASto set the output voltage, V_O.

0.7´R1

R

=

W

BIAS

V - 0.7

O

(22)

(23)

The maximum crossover frequency (0 dB loop gain) is set by Equation 23.

f

SW

f

+

(Hertz)

C

4

Typically, f_Cis selected to be close to the midpoint between the L-C_Odouble pole and the ESR zero. At this

frequency, the control to output gain has a –2 slope (–40 dB/decade), while the Type III topology has a +1 slope

(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 11 shows the modulator

gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.

ESR Zero, +1

V

S

A_MOD= V_IN(min)/V_RAMP

V_C

Resultant, –1

D= V_C/V_S

L-C Filter, –2

100

1 k

10 k

100 k

Switching Frequency (Hz)

Figure 10. PWM Modulator Relationships

Figure 11. Modulator Gain vs Switching Frequency

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A Type III topology, shown in Figure 12, has two zero-pole pairs in addition to a pole at the origin. The gain and

phase boost of a Type III topology is shown in Figure 13. The two zeros are used to compensate the L-C_O

double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide

controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to

roll-off the overall gain at higher frequencies.

C2

(optional)

- 1

+ 1

C1

0 dB

-90

R2

R3

- 1

GAIN

C3

°

VFB

R1

7

V

O

8

COMP

°

180

+

PHASE

R

°

BIAS

-270

VREF

UDG-08103

Figure 12. Type III Compensation Configuration

Figure 13. Type III Compensation Gain and Phase

The poles and zeros for a Type III network are described in Equation 24 through Equation 27.

1

f

=

Hz

( )

Z1

2p´R2´ C1

(24)

(25)

(26)

(27)

1

2p´R1´ C3

1

=

Hz

( )

Z2

=

Hz

( )

P1

2p´R2´ C2

1

f

=

Hz

( )

P2

2p´R3´ C3

The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 kΩ and

100 kΩ usually yields reasonable values.

The unity gain frequency is described in Equation 28.

1

f

+

(Hertz)

C

2p R1 C2 G

where

•

G is the reciprocal of the modulator gain at f_C

(28)

(29)

The modulator gain as a function of frequency at f_C, is described in Equation 29.

2

æ

ç

è

ö

÷

ø

f

1

LC

A

= A

´

and G =

MOD

MOD f

( )

f

A

MOD f

C

( )

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Minimum Load Resistance

Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too

small. The error amplifier has a finite output source and sink current which must be considered when sizing R2.

Too small a value does not allow the output to swing over its full range.

V

C (max)

3.5 V

2 mA

R2

+

+ 1750 W

(MIN)

I

SOURCE (min)

(30)

CALCULATING THE BOOST AND BP10 BYPASS CAPACITOR

The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor

should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate

charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance is

described in Equation 31.

Q

g

C

+

(Farads)

BOOST

D

V

(31)

The 10-V reference pin, BP10V provides energy for both the synchronous MOSFET and the high-side MOSFET

via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 32.

ǒ_Q

_gSRǓ

) Q

D

V

gHS

C

+

(Farads)

BP10

(32)

dv/dt INDUCED TURN-ON

MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (V_DS) applications. The turn-on is caused

by the capacitor divider that is formed by C_GDand C_GS. High dv/dt conditions and drain-to-source voltage, on the

MOSFET causes current flow through C_GDand causes the gate-to-source voltage to rise. If the gate-to-source

voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through

currents. Therefore, the SR MOSFET should be chosen so that the Q_GDcharge is smaller than the Q_GScharge.

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HIGH-SIDE MOSFET POWER DISSIPATION

The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The

conduction losses are a function of the I_RMScurrent through the MOSFET and the R_DS(on)of the MOSFET. The

high-side MOSFET conduction losses are defined by Equation 33.

₊ǒ_I_RMSǓ²

O

_{1 ) TC}ƪ_{T * 25 C}

ƫ

ǒ

Ǔ

P

R

(Watts)

COND

DS(on)

R

J

where

•

TC_Ris the temperature coefficient of the MOSFET R_DS(on)

(33)

The TC_Rvaries depending on MOSFET technology and manufacturer, but typically ranges between 3500

ppm/°C and 7000 ppm/°C.

The I_RMScurrent for the high-side MOSFET is described in Equation 34.

Ǹ

ǒ_A_RMSǓ

I

+ I

d

RMS

OUT

(34)

The switching losses for the high-side MOSFET are descibed in Equation 35.

₊ǒ_V

Ǔ

f

P

I

t

(Watts)

SW

SW(fsw)

IN

OUT

SW

where

•

I_Ois the DC output current

t_SWis the switching rise time, typically < 20 ns

f_SWis the switching frequency

(35)

Typical switching waveforms are shown in Figure 14.

I

D2

I

O

∆I

}

I

D1

d

1-d

BODY DIODE

CONDUCTION

BODY DIODE

CONDUCTION

SW

0

ANTI-CROSS

CONDUCTION

SYNCHRONOUS

RECTIFIER ON

HIGH SIDE ON

UDG-02139

Figure 14. Inductor Current and SW Node Waveforms

The maximum allowable power dissipation in the MOSFET is determined by Equation 36.

ǒ_{T * T}_AǓ

J

P +

(Watts)

T

q

JA

where

•

P_T= P_COND+ P_{SW(fsw) (W)}

θ_JAis the package thermal impedance

(36)

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SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION

The power dissipated in the synchronous rectifier MOSFET is comprised of three components: R_DS(on)conduction

losses, body diode conduction losses, and reverse recovery losses. R_DS(on)conduction losses can be defined

using Equation 31 and the RMS current through the synchronous rectifier MOSFET is described in Equation 37.

Ǹ

ǒ_Amperes_RMSǓ

I

+ I 1 * d

RMS

O

(37)

The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross

conduction delay time. The body diode conduction losses are described by Equation 38.

P

+ 2 I V t

f

(Watts)

SW

DC

O

F

DELAY

where

•

V_Fis the body diode forward voltage

t_DELAYis the delay time just before the SW node rises

(38)

The 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and

once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recover

from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 39.

P

+ 0.5 Q V f

(Watts)

SW

RR

IN

where

•

Q_RRis the reverse recovery charge of the body diode

(39)

The Q_RRis not always described in a MOSFET data sheet, but may be obtained from the MOSFET vendor. The

total synchronous rectifier MOSFET power dissipation is described in Equation 40.

P

+ P ) P ) P

(Watts)

COND

SR

DC

RR

(40)

TPS4005x POWER DISSIPATION

The power dissipation in the TPS4005x is largely dependent on the MOSFET driver currents and the input

voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power

[2]

(neglecting external gate resistance, ( refer to PowerPAD Thermally Enhanced Package

) can be calculated

from Equation 41.

P

+ Q V f

(Wattsńdriver)

SW

g

D

DR

(41)

And the total power dissipation in the TPS4005x, assuming the same MOSFET is selected for both the high-side

and synchronous rectifier, is described in Equation 42.

2 P

D

_{P +}ǒ Ǔ

) I

V

(Watts)

IN

T

Q

V

DR

(42)

or

_{P +}ǒ_{2 Q f}

Ǔ

) I V (Watts)

g

T

SW

Q

IN

where

•

I_Qis the quiescent operating current (neglecting drivers)

(43)

The maximum power capability of the PowerPad package is dependent on the layout as well as air flow. The

thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow,

O

q

+ 36.515 CńW

JA

(44)

The maximum allowable package power dissipation is related to ambient temperature by Equation 45.

T * T

J

A

P +

(Watts)

T

q

JA

(45)

Substituting Equation 38 into Equation 43 and solving for f_SWyields the maximum operating frequency for the

TPS4005x. The result is described in Equation 46.

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æ

ç

è

ö

÷

ø

æ

ç

è

ö

T - T

(

)

IN

J

A

-I

÷

ø

Q

q

´ V

JA

f

=

Hz

( )

SW

2´ Qg

(46)

LAYOUT CONSIDERATIONS

MOSFET PACKAGING

MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In

general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θ_JA)

and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on

proper layout and thermal management. The θ_JAspecified in the MOSFET data sheet refers to a given copper

area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of 2-ounce

copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please

refer to the selected MOSFET's data sheet for more information regarding proper mounting.

GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS

The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that

circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if

possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling

capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.

Sensitive nodes such as the FB resistor divider, R_T, and ILIM should be connected to the SGND plane. The

SGND plane should only make a single point connection to the PGND plane.

Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to

their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located

near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).

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DESIGN EXAMPLE

•

Input voltage: 10 Vdc to 24 Vdc

Output voltage: 3.3 V ±2% (3.234 ≤ V_O≤ 3.366)

Output current: 8 A (maximum, steady state), 10 A (surge, 10 ms duration, 10% duty cycle maximum)

Output ripple: 33 mV_PPat 8 A

Output load response: 0.3 V ≥ 10% to 90% step load change, from 1 A to 7 A

Operating temperature: -40°C to 85°C

f_SW= 300 kHz

1. Calculate maximum and minimum duty cycles

V_{O min}

V_{O max}

(

)

3.234

24

(

)

3.366

10

D_MIN

=

= 0.135

D_MAX

=

= 0.337

V

IN min

IN max

(

)

(

(47)

2. Select switching frequency

The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit

comparator. In order to maintain current limit capability, the on time of the upper MOSFET, t_ON, must be greater

than 300 ns (see Electrical Characteristics Table ). Therefore:

æ

ç

è

ö

÷

ø

æ

ö

÷

V

O min

(

)

ç

ç V

÷

æ

ç

ö

÷

V

IN max

(

æ

ç

è

ö

÷

ø

)

O min

(

t

ON

)

1

è

ø

=

or

= f

=

SW

ç

÷

V

t

SW

ON

IN max

(

)

è

ø

(48)

(49)

Using 400 ns to provide margin,

0.135

400 ns

f

+

+ 337 kHz

SW

Since the oscillator can vary by 10%, decrease f_SW, by 10%

f_SW= 0.9 × 337 kHz = 303 kHz

and therefore choose a frequency of 300 kHz.

3. Select ΔI

In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load.

DI + I 2 0.2 + 8 2 0.2 + 3.2 A

O

(50)

4. Calculate the high-side MOSFET power losses

Power losses in the high-side MOSFET (Si7860DP) at 24-V_INwhere switching losses dominate can be calculated

from Equation 51.

Ǹ

I

+ I d + 8 0.135 + 2.93 A

O

RMS

(51)

Substituting Equation 34 into Equation 33 yields

2

(

))

P

+ 2.93 0.008 1 ) 0.007 150 * 25 + 0.129 W

COND

(52)

and from Equation 35, the switching losses can be determined.

₊ǒ_V

Ǔ

f

P

I t

+ 24 V 8 A 20 ns 300 kHz + 1.152 W

SW

SW(fsw)

IN

O

SW

(53)

The MOSFET junction temperature can be found by substituting Equation 52 and Equation 53 into Equation 36:

O

_{T +}ǒ_P

Ǔ

(

)

) P

q ) T + 0.129 ) 1.152 40 ) 85 + 136 C

J

COND

SW

JA

A

(54)

22

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5. Calculate synchronous rectifier losses

The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery

losses. The conduction losses are due to I_RMSlosses as well as body diode conduction losses during the dead

time associated with the anti-cross conduction delay.

The I_RMScurrent through the synchronous rectifier from Equation 37:

Ǹ

I

+ I 1 * d + 8 1 * 0.135 + 7.44 A

O RMS

RMS

(55)

The synchronous MOSFET conduction loss from Equation 33 is:

2

P

= 7.44 ´0.008 ´ 1+ 0.007 ´ 150 - 25 = 0.83W

(

)

(

COND

(56)

(57)

(58)

(59)

(60)

The body diode conduction loss from Equation 38 is:

+ 2 I V t f + 2 8.0 A 0.8 V 100 ns 300 kHz + 0.384

P

DC

O

FD

DELAY

SW

The body diode reverse recovery loss from Equation 39 is:

+ 0.5 Q V f + 0.5 30 nC 24 V 300 kHz + 0.108 W

P

RR

IN

SW

The total power dissipated in the synchronous rectifier MOSFET from Equation 40 is:

+ P ) P ) P + 0.108 ) 0.83 ) 0.384 + 1.322 W

P

SR

RR

COND

DC

The junction temperature of the synchronous rectifier at 85°C is:

o

(

)

T + P q ) T + 1.322 40 ) 85 + 139 C

J

SR

JA

A

In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the

overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode

conduction and reverse recovery periods.

6. Calculate the inductor value

The inductor value is calculated from Equation 5.

(

)

24 * 3.3 V 3.3 V

L +

+ 2.96 mH

24 V 3.2 A 300 kHz

(61)

A 2.9-µH Coev DXM1306-2R9 or 2.6-µH Panasonic ETQ-P6F2R9LFA can be used.

7. Setting the switching frequency

The clock frequency is set with a resistor (R_T) from the RT pin to ground. The value of R_Tcan be found from

^Equa_R^tion₊^1,ǒ^{with f}^SW^{in kHz.}_* 17Ǔ_{kW + 170 kW N use 169 kW}

1

T

*6

f

17.82 10

SW

(62)

8. Programming the ramp generator circuit

The PWM ramp is programmed through a resistor (R_KFF) from the KFF pin to V_IN. The ramp generator also

controls the input UVLO voltage. For an undervoltage level of 10 V, R_KFFcan be calculated from Equation 2:

R_KFF= V

- 3.48 ´ 58.14´R +1340 = 72.8kW \use71.5kW

T

(

)

(

)

IN(min)

(63)

9. Calculating the output capacitance (C_O)

In this example the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1-A

to 8-A step load. C_Ocan be calculated using Equation 11:

2

ǒ₍

₎Ǔ

)

(

2.9 m 8 A * 1 A

C

+

+ 97 mF

O

2

ǒ₍

₎Ǔ

)

(

3.3 * 3.0

(64)

23

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Using Equation 6 calculate the ESR required to meet the output ripple requirements.

æ

ç

è

ö

æ

ç

è

ö

÷

ø

1

33mV = 3.2A ESR +

ç

÷

8´ 97mF´300kHz

ø

(65)

(66)

ESR = 10.3mW - 4.3mW = 6.0mW

For this design example two (2) Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.

10. Calculate the soft-start capacitor (C_SS/SD

)

This design requires a soft-start time (t_START) of 1 ms. C_SS/SDcan be calculated using Equation 13:

2.35mA

C

=

´1ms = 3.36nF @ 3300pF

SS/SD

0.7V

(67)

11. Calculate the current limit resistor (R_ILIM

)

The current limit set point depends on t_START, V_O,C_Oand I_LOADat start-up as shown in Equation 14. For this

design,

360mF´ 3.3V

I

>

+ 8.0A = 9.2A

ILIM

1ms

(68)

For this design, add I_ILIM(9.2 A) to one-half the ripple current (1.6 A) and increase this value by 30% to allow for

tolerances. This yields a overcurrent setpoint (I_OC) of 14 A. R_DS(on)is increased 30% (1.3 × 0.008) to allow for

MOSFET heating. Using Equation 15 to calculate R_ILIM

.

-3

14´ 0.0104 - 0.020 42.86 ´10

+

R

=

= 18.24kW @ 18.7kW

ILIM

-6

1.12´8.5´10

8.5 ´10

(69)

(70)

12. Calculate loop compensation values

Calculate the DC modulator gain (A_MOD) from Equation 19:

10

2

( )

+ 20 log 5 + 14 dB

A

+

+ 5.0

A

MOD(dB)

MOD

Calculate the output filter L-C_Opoles and C_OESR zeros from Equation 20 and Equation 21:

1

f

+

+ 4.93 kHz

LC

Ǹ

_2pǸ_{L C}

2p 2.9 mH 360 mF

O

(71)

(72)

and

1

f +

+

+ 73.7 kHz

Z

2p ESR C

2p 0.006 360 mF

O

Select the close-loop 0 dB crossover frequency, f_C. For this example f_C= 20 kHz.

Select the double zero location for the Type III compensation network at the output filter double pole at 4.93 kHz.

Select the double pole location for the Type III compensation network at the output capacitor ESR zero at

73.7 kHz.

The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain

AMOD at the crossover frequency from Equation 29:

2

f

LC

4.93 kHz

20 kHz

ǒ

Ǔ

ǒ Ǔ

A

+ A

MOD

+ 5

+ 0.304

MOD(f)

f

C

(73)

And also from Equation 29:

1

G +

+

+ 3.29

0.304

A

MOD(f)

(74)

24

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Choose R1 = 100 kΩ

The poles and zeros for a type III network are described in Equation 24 through Equation 28.

1

f

+

N C3 +

+ 323 pF, choose 330 pF

Z2

2p R1 C3

2p 100 kW 4.93 kHz

(75)

1

f

+

N R3 +

+ 6.55 kW, choose 6.49 kW

P2

2p R3 C3

2p 330 pF 73.3 kHz

(76)

(77)

1

f

+

N C2 +

+ 24.2 pF, choose 22 pF

C

2p R1 C2 G

2p 100 kW 3.29 20 kHz

1

f

+

N R2 +

+ 98.2 kW, choose 97.6 kW

P1

2p R2 C2

2p 22 pF 73.3 kHz

(78)

(79)

1

f

+

N C1 +

+ 331 pF, choose 330 pF

Z1

2p R2 C1

2p 97.6 kW 4.93 kHz

Calculate the value of R_BIASfrom Equation 22 with R1 = 100 kΩ.

0.7 V R1

0.7 V 100kW

3.3 V * 0.7 V

R

+

+ 26.9 kW, choose 26.7 kW

BIAS

V

* 0.7 V

O

(80)

CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE

The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount

of droop allowed on the bypass capacitor. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage

droop on the BOOST pin from Equation 31 is:

Q

g

18 nC

0.5 V

C

+

+ 36 nF

BOOST

DV

(81)

and the BP10V capacitance from Equation 32 is

Q

) Q

2 Q

DV

gHS

gSR

g

36 nC

0.5 V

C

+

+ 72 nF

BP(10 V)

DV

(82)

For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1.0-µF capacitor is used

for the BP10V bypass.

DESIGN EXAMPLE SUMMARY

Figure 15 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the

design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST

to get sufficient gate drive for the upper MOSFET. As seen in Figure 7, the BP10 output is about 6 V with the

input at 8 V so the upper MOSFET gate drive may be less than 5 V.

A schottky diode is shown connected across the synchronous rectifier MOSFET as an optional device that may

be required if the layout causes excessive negative SW node voltage, greater than or equal to 2 V.

TPS40054-Q1, TPS40055-Q1 and TPS40057-Q1 automotive qualified versions TPS40055-EP Enhanced product

4.5 to 18V controller with power good TPS40195 4.5 to 18V controller with synchronization power good

TPS40200 Wide input non-synchronous DC-DC controller

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+

R_KFF

330 mF 330 mF

71.5 kW

V_IN

TPS4005xPWP

100 pF

–

18.7 kW

1

2

3

4

5

6

7

8

KFF

ILIM 16

VIN 15

RT

R_T

1.0 mF

0.1 mF

169 kW

22 mF

50 V

22 mF

50 V

BP5

BOOST 14

HDRV 13

SW 12

1.0 mF

1.0 kW

SYNC

SGND

SS/SD

VFB

2.9 mH

Si7860

+

C_SS/SD

R3

6.49 kW

3300 pF

180 mF 180 mF

BP10 11

LDRV 10

R1

100 kW

*optional

Si7860

V_O

C1

330 pF

R2

97.6 kW

C3

330 pF

COMP

PGND

9

1.0 mF

–

C2

22 pF

PWP

R_BIAS

26.7 kW

UDG-08117

Figure 15. 24-V to 3.3-V at 8-A DC-to-DC Converter Design Example

26

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ADDITIONAL REFERENCES

RELATED DEVICES

The following devices have characteristics similar to the TPS40054/5/7 and may be of interest.

Table 2. RELATED DEVICES

DEVICE

TPS40055-EP

TPS40054-Q1

TPS40057-Q1

TPS40055-Q1

TPS40192

DESCRIPTION

Enhanced performance TPS40055.

Automotive qualified versions of the TPS5005x series.

4.5-V to 18-V Controller with Synchronization Power Good

Wide-Input Non-Synchronous DC-DC Controller

TPS40193

TPS40200

REFERENCES

1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas

Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2.

2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief

(SLMA002)

REVISION HISTORY

Changes from Revision F (SEPTEMBER 2008) to Revision G

Page

•

Deleted errors in schematic. ................................................................................................................................................. 1

Changed I_LIMto I_ILIM(corrected typographical error) ........................................................................................................... 14

Added clarity to Loop Compensation section ..................................................................................................................... 15

Changed V_IN(UVLO)to V_IN(min)in two places (corrected typographic errors) ......................................................................... 16

Changed corrected Equation 46 ......................................................................................................................................... 21

Changed corrected Equation 56 ......................................................................................................................................... 23

Changed corrected Equation 67 ......................................................................................................................................... 24

Changed corrected Equation 69 ......................................................................................................................................... 24

Changed corrected reference designator values in Figure 15 ............................................................................................ 26

Changes from Revision G (SEPTEMBER 2011) to Revision H

Page

•

Added the Thermal Information table ................................................................................................................................... 2

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PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS40054PWPR

TPS40055PWPR

TPS40057PWPR

HTSSOP PWP

16

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS40054PWPR

TPS40055PWPR

TPS40057PWPR

HTSSOP

PWP

16

2000

367.0

35.0

Pack Materials-Page 2

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型号：	TPS40057QPWPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO16, PLASTIC, HTSSOP-16 开关光电二极管
文件：	总36页 (文件大小：1210K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS40057QPWPRQ1 [TI]

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