TPS2359RHHR [TI]
TPS2359 Full Featured Dual-Slot AdvancedMC⑩ Controller; TPS2359全功能双插槽的AdvancedMC ™控制器
| 型号： | TPS2359RHHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS2359 Full Featured Dual-Slot AdvancedMC⑩ Controller |
| 文件： | 总51页 (文件大小：1239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2359
www.ti.com ................................................................................................................................................... SLUS792D–FEBRUARY 2008–REVISED JUNE 2008
TPS2359 Full Featured Dual-Slot AdvancedMC™ Controller
1
FEATURES
DESCRIPTION
2
•
•
•
•
•
•
•
ATCA AdvancedMC™ Compliant
Full Control for Two AdvancedMC™ Modules
Independent 12-V Current Limit and Fast Trip
3.3-V and 12-V FET ORing for MicroTCA™
Internal 3.3-V Current Limit and ORing
Power Good and Fault Reporting Through I2C
The TPS2359 dual-slot hot-plug controllers perform
all necessary power interface functions for two
AdvancedMC™
modules.
(Advanced
Mezzanine
Card)
Two fully integrated 3.3-V channels provide inrush
control, over-current protection, and FET ORing. Two
12-V channels provide the same functions using
external FETs and sense resistors. The 3.3-V current
limits are factory set to AdvancedMC™ compliant
levels and the 12-V current limits are programmed
using external sense resistors. The accurate current
sense comparators of the TPS2359 satisfy the narrow
ATCA™ AdvancedMC™ current limit requirements.
I2C Programmable Fault Times and Current
Limits
•
•
FET Status Bits for all Channels
36-Pin PQFN Package
APPLICATIONS
•
•
•
•
•
ATCA Carrier Boards
MicroTCA™ Power Modules
AdvancedMC™ Slots
Systems Using 12 V and 3.3 V
Base Stations
TPS2359 Application Diagram
HAT2165
HAT2165
12 V in
12 V
AdvancedMC™
.005
698
Slot A
SENPA
SETA
SENMA
PASSA
BLKA OUT12A
IN12A
EN3A
IN3A
OUT3A
3.3 V
6810
3320
SUM12A
SUM3A
3v3 in
VDD3A
SDA
SCL
IRPT\
A0
VINT
AGND
GNDA
GNDB
COMMON
CIRCUITRY
TPS2359
36 QFN
A1
A2
EN3B
IN3B
6810
3320
SUM12B
SUM3B
3v3 in
VDD3B
IN12B
OUT3B
3.3 V
AdvancedMC™
SENPB
SETB
SENMB
PASSB
BLKB
OUT12B
Slot B
698
.005
12 V in
12 V
Optional ORing FETs for Redundant Systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
AdvancedMC, MicroTCA are trademarks of PICMG.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS2359
SLUS792D–FEBRUARY 2008–REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
(1)
ORDERING INFORMATION
DEVICE
TEMPERATURE
PACKAGE(2)
ORDERING INFORMATION
TPS2359
-40°C to 85°C
QFN36
TPS2359RHH
(1) Add an R suffix to the device type for tape and reel.
(2) For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VALUE
0 to 30
UNIT
PASSx, BLKx
IN12x; OUT12x; SENPx; SENMx; SETx; IRPT
0 to 17
IN3x; OUT3x; EN3x; VDDx; SUMx; SDA, SCL
0 to 5
V
AGND, GNDx
A0, A1, A2
SUMx
-0.3 to 0.3
0 to VINT
5
VINT
-1 to 1
mA
OUT3x
Internally limited
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is
neither implied nor guaranteed. Exposure to absolute maximum rated conditions for extended periods of time may affect device
reliability.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
TEST METHOD
MIN
2
UNITS
Human Body Model (HBM)
Charged Device model (CDM)
kV
0.5
DISSIPATION RATINGS
PACKAGE
θJA - High-k (°C/W)
36 QFN
35
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VIN12x
VIN3x
Payload power input voltage
Management power input voltage
Management power supply voltage
Management power output current
Summing pin current
8.5
3
12
3.3
3.3
15
4
V
VVDD3x,3
IOUT3x
ISUMx
3
4
165
mA
100
10
1000
1
µA
PASSx pin board leakage current
VINT bypass capacitance
-1
1
250
125
nF
°C
TJ
Operating junction temperature range
-40
2
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www.ti.com ................................................................................................................................................... SLUS792D–FEBRUARY 2008–REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS(1)
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12
V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to
ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages
referenced to AGND, unless otherwise noted. over operating free-air temperature range (unless otherwise noted)
PARAMETER
ENABLE Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
Threshold voltage, falling edge
Hysteresis(2)
1.2
20
5
1.3
50
8
1.4
80
15
5
V
mV
Pullup current2
EN3x = 0 V
EN3x = 5 V
µA
Input bias current
3.3-V turn off time
1
EN3x deasserts to VOUT3x < 1.0 V, COUT = 0 µF
10
µs
EN3x deasserts to VOUT12x < 1.0 V, COUT = 0 µF,
QGATE = 35 nF
12-V turn off time
20
VINT
Output voltage
0 < IVINT < 50 µA
2
2.3
2.8
V
Power GOOD Comparators
12xPG, falling OUT12x
3xPG, falling OUT3x
10.2
2.7
10.5
2.8
130
50
10.8
2.9
Threshold voltage
Hysteresis
V
12xPG, measured at OUT12x
3xPG, measured at OUT3x
mV
Fault Timer
Minimum fault time
Fault time bit weight
Timer duty cycle
12-V Summing node
3xFT[4:0] = 12xFT[4:0] = 00001B
= (fault time) / (retry period)
1
0.5
ms
1.4%
1.5%
1.6%
2
VSENMx = 10.8 – 13.2 V, VSENPx = VSENMx + 50
mV, measure VSETx – VSENMx
Input referred offset
–2
mV
Summing threshold
Leakage current
12xCL[3:0] = 1111B, VPASSx = 15 V
VSETx = VSENMx – 10 mV
0.66
0.675
50
0.69
1
V
µA
12-V Current limit
RSUMx = 6.8 kΩ, RSETx = 422 Ω, increase ILOADx
and measure VSENPx – VSENMx when VPASSx = 15
V
Current limit threshold
47.5
52.5
mV
Sink current in current limit
Fast trip threshold
Fast turn-off delay(2)
Bleed down resistance
Bleed down threshold
Timer start threshold
VSUMx = 1 V, VPASSx = 12 V, measure IPASSx
Measure VSENPx – VSENMx
20
80
40
120
300
2.1
130
7
µA
mV
ns
100
200
1.6
100
6
20-mV overdrive, CPASSx = 0 pF, tp50-50
VOUT = 6 V
1.1
75
5
kΩ
mV
V
VPASSx – VINx when fault timer starts
(1) When setting an address bit to a logic 1 the pin should be connected to VINT.
(2) Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12
V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to
ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages
referenced to AGND, unless otherwise noted. over operating free-air temperature range (unless otherwise noted)
PARAMETER
12-V UVLO
CONDITIONS
MIN
TYP
MAX
UNITS
UVLO rising
IN12x rising
IN12x falling
8.1
8.5
0.5
8.9
V
UVLO hysteresis
12-V BLOCKING
Turn-on threshold
Turn-off threshold
Turn-off delay(3)
0.44
0.59
Measure VSENPx – VOUTx
5
10
–3
15
0
mV
ns
Measure VSENPx – VOUTx
–5
20-mV overdrive, CBLKx = 0 pF, tp50-50
200
300
12-V Gate drivers (PASSx, BLKx)
Output voltage
VINx = VOUTx = 10 V
21.5
20
0.5
6
23
30
1
24.5
40
V
µA
A
Sourcing current
VIN12x = VOUT12x = 10 V, VPASSx = VBLKx = 17 V
Fast turnoff, VPASSx = VBLKx = 14 V
Sustained, VPASSx = VBLKx = 4 – 25 V
In OTSD (at 150 °C)
Sinking current
14
20
10
25
26
mA
kΩ
ms
V
Pulldown resistance
Fast turnoff duration(3)
Safety gate pulldown(3)
Startup time(3)
14
5
15
IRF3710, slew S or D 15 V in 1 ms
1.25
0.25
IN12x rising to PASSx and BLKx sourcing
ms
3.3-V Summing node
Summing threshold
3.3-V Current limit
On resistance
655
675
695
mV
IOUT3x = 150 mA
290
195
300
750
400
100
500
225
mΩ
Current limit
RSUM3x = 3.3 kΩ , VOUT3x = 0 V
170
240
mA
Fast trip threshold
Fast turn-off delay(3)
Bleed down resistance
Bleed down threshold
3.3-V UVLO
400
IOUT3x = 400 mA, tp50-50
VOUT3x = 1.65 V
1300
500
ns
Ω
280
75
130
mV
UVLO rising
IN3x rising
IN3x falling
2.65
200
2.75
240
2.85
300
V
UVLO hysteresis
3.3-V Blocking
mV
Turn-on threshold
Turn-off threshold
Measure VIN3x – VOUT3x
Measure VIN3x – VOUT3x
5
10
–3
15
0
mV
–5
VIN3x = 3.3 V, VOUT3x = 3.5 V, OUT3x = 100 Ω to
GND, 3ORON = 1. Remove 3.5 V from OUT3x.
Measure time from VOUT3x thru 2.9 V to VOUT3x
3.2 V
ORing turn-on delay
300
250
350
350
µs
=
Fast turnoff delay(3)
20 mV overdrive, tp50-50
ns
(3) Not production tested.
4
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ELECTRICAL CHARACTERISTICS (continued)
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12
V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to
ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages
referenced to AGND, unless otherwise noted. over operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Currents (IINx + ISENPx + ISENMx + ISETx + IVDDx
)
All channels enabled
All channels disabled
Thermal Shutdown
IOUT3A = IOUT3B = 0
3.1
2.0
4
mA
2.8
Whole-chip shutdown temperature(4) TJ rising, IOUT3A = IOUT3B = 0
140
150
140
10
3.3-V channel shutdown
TJ rising, IOUT3A or IOUT3B in current limit
130
°C
temperature(4)
Hysteresis(4)
Whole chip or 3.3-V channel
Serial Interface (SDA, SCL, A0–2, IRPT
Lower logic threshold
Upper logic threshold
Input pullup resistance
Input pulldown resistance
Input open-circuit voltage
Threshold voltage, rising
Threshold voltage, falling
Hysteresis(4)
A0 – A2
0.33
1.32
400
200
0.5
0.35
1.35
700
350
0.8
0.37
1.38
1000
550
1.0
V
A0 – A2
A0 – A2, VAx = 0 V
A0 – A2, VAx = VINT
IAx = 0 V
kΩ
SDA, SCL
2.3
V
SDA, SCL
1.0
SDA, SCL
165
mV
mA
kHz
Leakage
SDA, IRPT
SCL
1
Input clock frequency
400
(4) Not production tested.
Signal and Pin Naming Convention
SIGNAL AND PIN NAMING
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DEVICE INFORMATION
TPS2359 BLOCK DIAGRAMS
RSENSE
12 V
R
SET
IN12
SENP
SET
SENM
PASS
BLK
OUT12
pgat
100 mv
12dis
Q
Pump
+
30 uA
30 uA
ogat
Vcp
~25 v
10 us
10 us
Fault
Timer
Vcp
EN
FLT
+
RSUM
SUM12
vthoc - 675 mv nominal
6810
10 mv
-3 mv
vpg
100
us
+
+
R
S
Q
Q
+
ogat
PG
OUT
OUT
pgat
oren
Figure 1. Payload Power Channel (two channels per device)
6
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Management Power Channel (two channels per device)
0.1 W
IN3x
OUT3x
2.8 V
245 W
gat
VDD3x
en
30 mv
30 us
Q
Pump
+
PG to I2C
30 mA
vcpx
~25 v
12dis
Fault
Timer
vcpx
30 us
FLT to I2C
Control
from I2C
SUM3x
RSUM
3300
+
vthoc - [ 675 mv nominal ]
en
EN3x
10 mv
-3 mv
+
gat
R
S
Q
Q
OUT3x
+
Common Circuitry
IN12A
IN12B
VINT
en
por
Selector
IN3A
IN3B
OUT12A
OUT12B
OUT3A
OUT3B
PREREG
POR
2.2V
Trim
NVM
SDA
SCL
A0-2
AGND
I2C
GNDA
GNDB
IRPT\
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Top View 36-Pin QFN
3A
12A
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
IN12A
SENPA
SETA
27 OUT3A
26
25
24
23
22
A2
SUM3A
IRPT
SENMA
VINT
36 Pin QFN
AGND
VDD3B
SUM12A
SDA
21 SUM3B
20 A1
I2C
3B
SCL
SUM12B
19 OUT3B
10
11
12
13
14
15
16
17
18
12B
8
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TPS2359 TERMINAL FUNCTIONS
PIN #
1
NAME
IN12A
SENPA
SETA
TYPE
VDD
I
DESCRIPTION
12A input
2
12A input sense
12A current limit set
12A current limit sense
3
I
4
SENMA
VINT
I
5
I/O
I/O
I/O
I
Bypass capacitor connection point for internal supply, pullup for A0 – A2
12A summing node
6
SUM12A
SDA
7
Serial data input/output
Serial data clock
8
SCL
9
SUM12B
BLKB
I/O
O
12B summing node
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
12B blocking transistor gate drive
12B output
OUT12B
GNDB
PASSB
SENMB
SETB
I/O
GND
O
12B power ground
12B pass transistor gate drive
12B current limit sense
12B current limit set
I
I
SENPB
IN12B
IN3B
I
12B input sense
VDD
VDD
I/O
I
12B input
3B input
OUT3B
A1
3B output
I2C address programming bit, LSB+1
SUM3B
VDD3B
AGND
IRPT
I/O
VDD
GND
O
3B summing node
3B charge pump input
Analog ground
Active low interrupt, asserts when a PG deasserts or when a FLT\ asserts
3A summing node
I2C address programming bit, LSB+2
SUM3A
A2
I/O
I
OUT3A
IN3A
I/O
VDD
VDD
I
3A output
3A input
VDD3A
EN3B
3A charge pump input
3B enable, active high
3A enable, active high
12A pass transistor gate drive
12A power ground
EN3A
I
PASSA
GNDA
OUT12A
BLKA
O
GND
I/O
O
12A output
12A blocking transistor gate drive
I2C address programming bit, LSB
A0
I
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DETAILED PIN DESCRIPTION
A0, A1, A2 These three pins select one of 27 unique I2C addresses for address of the TPS2359. Each pin may
be tied to ground, tied to the VINT pin, or left open. See TPS2359 I2C Interface section for details.
AGND Ground pin for analog circuitry inside the TPS2359.
BLKx Gate drive pin for the 12x channel BLK FET. This pin sources 30 µA to turn the FET on. An internal clamp
prevents this pin from rising more than 14.5 V above OUT12x. Setting the ORENx bit low holds the BLKx pin
low.
EN3x Active-high enable input. Pulling this pin low turns off channel 3x by pulling the gate of the internal pass
FET to GND. An internal 200-kΩ resistor pulls this pin up to VINTwhen disconnected.
GNDx Ground pin for power circuitry associated with the 12x channel. These pins should connect to a ground
plane shared with the AGND pin.
IN12x Supply pin for channel 12x internal circuitry.
IN3x Supply pin for channel 3x internal pass FET.
IRPT Open drain output that pulls low when internal circuitry sets any of the eight status bits in Register 7.
Reading Register 7 restores IRPT to its high-Z state.
OUT12x Senses the output voltage of the channel 12x path.
OUT3x Output of the channel 3x internal pass FET.
PASSx Gate drive pin for the 12x channel PASS FET. This pin sources 30 µA to turn the FET on. An internal
clamps prevents this pin from rising more than 14.5 V above IN12x.
SCL Serial clock input for the I2C interface. For details of the SCL line, see TPS2359 I2C Interface section.
SDA Bidirectional I2C data line. For details of the SDA line, see TPS2359 I2C Interface section for details.
SENMx Senses the voltage on the low side of the channel 12x current sense resistor.
SENPx Senses the voltage on the high side of the channel 12x current sense resistor.
SETx A resistor connected from this pin to SENPx sets the current limit level in conjunction with the current
sense resistor and the resistor connected to the SUM12x pin, as described in 12-V thresholds – setting current
limit and fast over current trip section.
SUMx A resistor connected from this pin to ground forms part of the channel x current limit. As the current
delivered to the load increases, so does the voltage on this pin. When the voltage on this pin reaches a threshold
(by default 675 mV), the current limit amplifier acts to prevent the current from further increasing.
VDD3x Supply pin for channel3x internal circuitry.
VINT This pin connects to the internal 2.35-V rail. A 0.1-µF capacitor must be connected from this pin to ground.
One can connect the A0–A2 pins to this supply to pull them high, but no other external circuitry should connect to
VINT.
10
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TYPICAL CHARACTERISTICS
IDD at 25°C
3-V CHANNEL ORING TURN-ON THRESHOLD
vs
12-V VDD
12
2.45
2.40
11
2.35
2.30
10
2.25
9
2.20
2.15
8
2.10
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
VDD - 25°C
Figure 2.
Figure 3.
3-V CHANNEL ORING TURN-OFF THRESHOLD
12-V CURRENT LIMIT THRESHOLD
51.0
50.8
0.0
-1.0
50.6
50.4
-2.0
-3.0
-4.0
-5.0
50.2
50.0
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 4.
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
3-V IDD
12-V CHANNEL ORING TURN-OFF THRESHOLD
vs
TEMPERATURE
0.0
0.26
-1.0
0.25
0.24
-2.0
0.23
-3.0
0.22
-4.0
0.21
-5.0
0.20
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 6.
Figure 7.
12-V CURRENT (mA)
vs
12-V CHANNEL ORING TURN-ON THRESHOLD
TEMPERATURE
12.0
11.5
2.4
2.3
11.0
10.5
10.0
9.5
2.2
2.1
2.0
6
9.0
8.5
8.0
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 8.
Figure 9.
12
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TYPICAL CHARACTERISTICS (continued)
Figure 10. OUT3A Startup Into 22-Ω (150 mA) 150-µF Load
Figure 11. OUT3A Load Stepped from 165 mA to 240 mA
Figure 12. OUT3A Short Circuit Under Full Load (165 mA)
Zoom View
Figure 13. OUT3A Short Circuit Under Full Load (165 mA)
Wide View
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TYPICAL CHARACTERISTICS (continued)
Figure 14. OUT3A Startup Into Short Circuit
Figure 15. OUT12A Startup Into 500-Ω, 830-µF Load
Figure 16. OUT12A Startup Into 80-Watt, 830-µF Load
Figure 17. OUT12A Short Circuit Under Full Load (6.7 A)
Wide View
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TYPICAL CHARACTERISTICS (continued)
Figure 18. OUT12A Short Circuit Under Full Load (6.7 A)
Zoom View
Figure 19. OUT12A Startup Into Short Circuit
Figure 20. OUT12A Overloaded While Supplying 6.7 A
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REFERENCE INFORMATION
The TPS2359 has been designed to simplify compliance with the PICMG-AMC.R2.0 and PICMG-MTCA.0
specifications. These specifications were developed by the PCI Industrial Computer Manufacturers Group
(PICMG). These two specifications are derivations of the PICMG-ATCA (Advanced Telecommunication
Computing Architecture) specification originally released in December, 2002.
PICMG-AMC Highlights
•
•
•
•
•
•
•
•
•
AMC - Advanced Mezzanine Cards
Designed to Plug into ATCA Carrier Boards
AdvancedMC™ Focuses on Low Cost
1 to 8 AdvancedMC™ per ATCA Carrier Board
3.3-V Management Power – Maximum Current Draw of 150 mA
12-V Payload Power – Converted to Required Voltages on AMC
Maximum 80-W Dissipation per AdvancedMC™
Hotswap and Current Limiting Must Be Present on Carrier Board
For Details, see www.picmg.org/v2internal/AdvancedMC.htm
PICMG-MTCA Highlights
•
•
•
•
•
•
MTCA – MicroTelecommunications Computing Architecture
Architecture for Using AMCs Without an ATCA Carrier Board
Up to 12 AMCs per System, Plus Two MCHs, Plus Two CUs
Focuses on Low Cost
All functions of ATCA Carrier Board Must Be Provided
MicroTCA is also known as MTCA, mTCA, or uTCA For Details, see www.picmg.org/v2internal/microTCA.htm
Control and Status Registers
Ten 8 bit registers are used to control and read the status of the TPS2359. Registers 0 and 1 control the 12A
channel and register 2 controls the 3A channel. Similarly, registers 3 and 4 control the 12B channel and register
5 controls the 3B channel. Register 6 contains eight general configuration bits. Read-only registers 7, 8, and 9
report back system status to the I2C controller. All ten registers use the I2C protocol and are organized as
follows:
Table 1. Top Level Register Functions
REG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
SLOT
A
VOLTAGE
12
FUNCTION
0
1
2
3
4
5
6
7
8
9
Set current limit, power good threshold, and OR functions of 12A.
Set fault time, enable, and bleed down functions of 12A.
Set fault time, enable, and bleed down functions of 3A.
Set current limit, power good threshold, and OR functions of 12B.
Set fault time, enable, and bleed down functions of 12B.
Set fault time, enable, and bleed down functions of 3B.
System configuration controls.
A
12
A
3.3
B
12
B
12
B
3.3
A, B
A, B
A, B
A, B
3.3, 12
3.3, 12
12
Fault and PG outputs for 3A, 12A, 3B, 12B – these bits set IRPT.
Over current and fast trip latches for 3A, 12A, 3B, 12B.
Channel status indicators for 3A, 12A, 3B, 12B.
R
R
3.3, 12
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Summary of Registers
Table 2. Summary of Registers
BIT
NAME
DEFAULT
DESCRIPTION
Register 0 Read/Write channel 12A configuration
0
1
2
3
4
5
6
7
12ACL0
12ACL1
12ACL2
12ACL3
12APG0
12APG1
12AHP
1
1
1
1
1
1
0
1
Clearing bit reduces 12A current limit & fast threshold by 5%.
Clearing bit reduces 12A current limit & fast threshold by 10%.
Clearing bit reduces 12A current limit & fast threshold by 20%.
Clearing bit reduces 12A current limit & fast threshold by 40%.
Clearing bit reduces 12A power good threshold by 600mV.
Clearing bit reduces 12A power good threshold by 1.2 V.
Setting bit shifts 12A OR VTURNOFF from –3 mV to +3 mV nominal.
Clearing bit turns off 12A ORing FET by pulling BLKA low.
12AOR
Register 1 Read/Write channel 12A configuration
0
1
2
3
4
5
6
7
12AFT0
12AFT1
12AFT2
12AFT3
12AFT4
12AEN
12AUV
12ADS
1
0
0
0
0
0
0
0
Setting bit increases 12A fault time by 0.5 ms.
Setting bit increases 12A fault time by 1 ms.
Setting bit increases 12A fault time by 2 ms.
Setting bit increases 12A fault time by 4 ms.
Setting bit increases 12A fault time by 8 ms.
Clearing bit disables 12A by pulling PASSA and BLKA to 0 V.
Setting bit prevents enabling unless OUT12A < bleed down threshold.
Clearing bit disconnects OUT12A bleed down resistor.
Register 2 Read/Write channel 3A configuration
0
1
2
3
4
5
6
7
3AFT0
3AFT1
3AFT2
3AFT3
3AFT4
3AEN
3AUV
3ADS
1
0
0
0
0
0
0
0
Setting bit increases 3A fault time by 0.5 ms.
Setting bit increases 3A fault time by 1 ms.
Setting bit increases 3A fault time by 2 ms.
Setting bit increases 3A fault time by 4 ms.
Setting bit increases 3A fault time by 8 ms.
Clearing bit disables 3A.
Setting bit prevents enabling unless OUT3A < bleed down threshold.
Clearing bit disconnects OUT3A bleed down resistor.
Register 3 Read/Write channel 12B configuration
0
1
2
3
4
5
6
7
12BCL0
12BCL1
12BCL2
12BCL3
12BPG0
12BPG1
12BHP
1
1
1
1
1
1
0
1
Clearing bit reduces 12B current limit & fast threshold by 5%.
Clearing bit reduces 12B current limit & fast threshold by 10%.
Clearing bit reduces 12B current limit & fast threshold by 20%.
Clearing bit reduces 12B current limit & fast threshold by 40%.
Clearing bit reduces 12B power good threshold by 600 mV.
Clearing bit reduces 12B power good threshold by 1.2 V.
Setting bit shifts 12B OR VTURNOFF from –3 mV to +3 mV nominal.
Clearing bit turns off 12B ORing FET by pulling BLKB low.
12BOR
Register 4 Read/Write channel 12B configuration
0
1
2
3
4
5
6
7
12BFT0
12BFT1
12BFT2
12BFT3
12BFT4
12BEN
12BUV
12BDS
1
0
0
0
0
0
0
0
Setting bit increases 12B fault time by 0.5 ms.
Setting bit increases 12B fault time by 1 ms.
Setting bit increases 12B fault time by 2 ms.
Setting bit increases 12B fault time by 4 ms.
Setting bit increases 12B fault time by 8 ms.
Clearing bit disables 12B by pulling PASSB and BLKB to 0 V.
Setting bit prevents enabling unless OUT12B < bleed down threshold.
Clearing bit disconnects OUT12B bleed down resistor.
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Table 2. Summary of Registers (continued)
BIT
NAME
DEFAULT
DESCRIPTION
Register 5 Read/Write channel 3B configuration
0
1
2
3
4
5
6
7
3BFT0
3BFT1
3BFT2
3BFT3
3BFT4
3BEN
3BUV
3BDS
1
0
0
0
0
0
0
0
Setting bit increases 3B fault time by 0.5 ms.
Setting bit increases 3B fault time by 1 ms.
Setting bit increases 3B fault time by 2 ms.
Setting bit increases 3B fault time by 4 ms.
Setting bit increases 3B fault time by 8 ms.
Clearing bit disables 3B.
Setting bit prevents enabling unless OUT3B < bleed down threshold.
Clearing bit disconnects OUT3B bleed down resistor.
Register 6 Read/Write system configuration
0
PPTEST
0
12-V pulldown test pin. Setting pin pulls the PASSx and BLKx pins to 0 V.
Clearing bit latchs off channels after over-current fault. Setting bit allows channels to
automatically attempt restart after fault.
1
FLTMODE
0
2
3
SPARE
3ORON
0
0
This bit must always be set to 0.
Setting bit enables 3A and 3B to prevent reverse current flow.
Non Redundant System in rush control bit. Setting bit allows increased inrush current
in 12A and 12B with proper setting of 12xCLx bits.
4
12VNRS
0
5
6
AIRM
BIRM
0
0
Setting this masking bit prevents REG7 bits 3:0 from setting IRPT.
Setting this masking bit prevents REG7 bits 7:4 from setting IRPT.
Setting bit allows the 12 V channels to operate despite loss of 3.3 V. This bit should
be low for uTCA and AMC applications
7
DCC
0
Register 7 Read only latched IRPT channel status indicators, cleared on read
0
1
2
3
4
5
6
7
12APG
12AFLT
3APG
0
0
0
0
0
0
0
0
Latches high when OUT12A goes from above VTH_PG to below VTH_PG
Latches high when 12A fault timer has run out.
.
Latches high when OUT3A goes from above VTH_PG to below VTH_PG
Latches high when 3A fault timer has run out.
.
3AFLT
12BPG
12BFLT
3BPG
Latches high when OUT12B goes from above VTH_PG to below VTH_PG
Latches high when 12B fault timer has run out.
.
Latches high when OUT3B goes from above VTH_PG to below VTH_PG
Latches high when 3B fault timer has run out.
.
3BFLT
Register 8 Read only latched overcurrent indicators, cleared on Read
0
1
2
3
4
5
6
7
12AOC
12AFTR
3AOC
0
0
0
0
0
0
0
0
Latches high when 12A enters over-current.
Latches high if 12A fast trip threshold exceeded.
Latches high when 3A enters over-current.
Latches high if 3A fast trip threshold exceeded.
Latches high when 12B enters over-current.
Latches high if 12B fast trip threshold exceeded.
Latches high when 3B enters over-current.
Latches high if 3B fast trip threshold exceeded.
3AFTR
12BOC
12BFTR
3BOC
3BFTR
Register 9 Read only unlatched FET status indicators
0
1
2
3
4
5
6
7
12ABS
12APS
3ABS
-
-
-
-
-
-
-
-
High indicates BLKA commanded high.
Low indicates VPASSA > VOUT12A + 61 V.
Low indicates IN3A > OUT3A.
12BBS
12BPS
3BBS
High indicates BLKB commanded high.
Low indicates VPASSB > VOUTB + 61 V.
Low indicates IN3B > OUT3B.
3AGS
3BGS
Low indicates channel 3A gate is driven on ( VGATE > ( VIN + 1.75 V ).
Low indicates channel 3B gate is driven on ( VGATE > ( VIN + 1.75 V ).
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Detailed Description of Registers
Register 0
Table 3. Register 0: Channel 12A Configuration (Read/write)
BIT
0
NAME
12ACL0
12ACL1
12ACL2
12ACL3
12APG0
12APG1
12AHP
DEFAULT
DESCRIPTION
1
1
1
1
1
1
0
1
Clearing bit reduces 12A current limit & fast threshold by 5%.
Clearing bit reduces 12A current limit & fast threshold by 10%.
Clearing bit reduces 12A current limit & fast threshold by 20%.
Clearing bit reduces 12A current limit & fast threshold by 40%.
Clearing bit reduces 12A power good threshold by 600 mV.
Clearing bit reduces 12A power good threshold by 1.2 V.
Setting bit shifts 12A OR VTURNOFF from –3 mV to +3 mV nominal.
Clearing bit turns off 12A ORing FET by pulling BLKA low.
1
2
3
4
5
6
7
12AOR
12ACL[3:0] These four bits adjusts the 12A current limit and fast trip threshold using the I2C interface. Setting
the bits to 1111B places the 12A current limit at its maximum level, corresponding to 675 mV at SUM12A. The
fast trip threshold then equals 100 mV. Clearing all bits reduces the current limit and fast trip threshold to 25% of
these maximums.
12APG[1:0] These two bits adjust the 12A power good threshold. Setting the bits to 11B places the power good
threshold at its maximum level of 10.5 V . Setting the bits to 00B places the threshold at its minimum level of 8.7
V. The lower thresholds may prove desirable in systems that routinely experience large voltage droops.
12AHP Setting this bit moves the 12A ORing turn off threshold from –3 mV to +3 mV. A positive threshold
prevents reverse current from flowing through the channel, but it may cause the ORing FET to repeatedly cycle
on-and-off if the load cannot maintain the required positive voltage drop across the combined resistance of the
external FETs and the sense resistor. For further information, see Adjusting Oring Turn Off threshold For High
Power Loads section
12AOR Clearing this bit forces the BLKA pin low, keeping the 12A ORing FET off. Clearing this bit does not
prevent current from flowing through the FET’s body diode.
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Register 1
Table 4. Register 1: Channel 12A Configuration (Read/write)
BIT
0
NAME
12AFT0
12AFT1
12AFT2
12AFT3
12AFT4
12AEN
12AUV
12ADS
DEFAULT
DESCRIPTION
Setting bit increases 12A fault time by 0.5 ms.
1
0
0
0
0
0
0
0
1
Setting bit increases 12A fault time by 1 ms.
2
Setting bit increases 12A fault time by 2 ms.
3
Setting bit increases 12A fault time by 4 ms.
4
Setting bit increases 12A fault time by 8 ms.
5
Clearing bit disables 12A by pulling PASSA and BLKA to 0 V.
Setting bit prevents enabling unless OUT12A < bleed down threshold.
Clearing bit disconnects OUT12A bleed down resistor.
6
7
12AFT[4:0] These five bits adjust the 12A channel fault time. The least-significant bit has a nominal weight of 0.5
ms, so fault times ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In
general the shortest fault time that fully charges downstream bulk capacitors without generating a fault should be
used. Once the load capacitors have fully charged, the fault time can be reduced to provide faster short circuit
protection. See Setting Fault Time section.
12AEN This bit serves as a master enable for channel 12A. Setting this bit allows the 12A channel to operate
normally. Clearing this bit disables the channel by pulling PASSA and BLKA low.
12AUV Setting this bit prevents channel 12A from turning on until OUT12A falls below the bleed down threshold
of 100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly
zero before the channel can enable them.
12ADS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT12A to ground.
Systems using redundant power supplies should clear 12ADS to prevent the bleed down resistor from
continuously sinking current.
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Register 2
Table 5. Register 2: Channel 3A Configuration (Read/write)
BIT
0
NAME
3AFT0
3AFT1
3AFT2
3AFT3
3AFT4
3AEN
3AUV
3ADS
DEFAULT
DESCRIPTION
Setting bit increases 3A fault time by 0.5 ms.
1
0
0
0
0
0
0
0
1
Setting bit increases 3A fault time by 1 ms.
Setting bit increases 3A fault time by 2 ms.
Setting bit increases 3A fault time by 4 ms.
Setting bit increases 3A fault time by 8 ms.
Clearing bit disables 3A.
2
3
4
5
6
Setting bit prevents enabling unless OUT3A < bleed down threshold.
Clearing bit disconnects OUT3A bleed down resistor.
7
3AFT[4:0] These five bits adjust the 3A channel fault time. The least-significant bit has a nominal weight of 0.5
ms, so fault times ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In
general the shortest fault time that fully charges downstream bulk capacitors without generating a fault should be
used. See Setting Fault Time section.
3AEN This bit serves as a master enable for channel 3A. Setting this bit allows the 3A channel to operate
normally, provided the EN3A pin is also asserted. Clearing this bit disables the channel by removing gate drive to
the internal pass FET, regardless of the state of the EN3A pin.
3AUV Setting this bit prevents channel 3A from turning on until OUT3A falls below the bleed down threshold of
100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly
zero before the channel can enable them.
3ADS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT3A to ground.
Systems using redundant power supplies should clear 3ADS to prevent the bleed down resistor from
continuously sinking current.
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Register 3
Table 6. Register 3: Channel 12B Configuration (Read/write)
BIT
0
NAME
12BCL0
12BCL1
12BCL2
12BCL3
12BPG0
12BPG1
12BHP
DEFAULT
DESCRIPTION
1
1
1
1
1
1
0
1
Clearing bit reduces 12B current limit & fast threshold by 5%.
Clearing bit reduces 12B current limit & fast threshold by 10%.
Clearing bit reduces 12B current limit & fast threshold by 20%.
Clearing bit reduces 12B current limit & fast threshold by 40%.
Clearing bit reduces 12B power good threshold by 600 mV.
Clearing bit reduces 12B power good threshold by 1.2 V.
Setting bit shifts 12B OR VTURNOFF from –3 mV to +3 mV nominal.
Clearing bit turns off 12B ORing FET by pulling BLKB low.
1
2
3
4
5
6
7
12BOR
12BCL[3:0] These four bits adjusts the 12B current limit and fast trip threshold using the I2C interface. Setting
the bits to 1111B places the 12B current limit at its maximum level, corresponding to 675 mV at SUM12B. The
fast trip threshold then equals 100 mV. Clearing all bits reduces the current limit and fast trip threshold to 25% of
these maximums.
12BPG[1:0] These two bits adjust the 12B power good threshold. Setting the bits to 11B places the power good
threshold at its maximum level of 10.5 V . Setting the bits to 00B places the threshold at its minimum level of 8.7
V. The lower thresholds may prove desirable in systems that routinely experience large voltage droops.
12BHP Setting this bit moves the 12B ORing turn off threshold from –3 mV to +3 mV. A positive threshold
prevents reverse current from flowing through the channel, but it may cause the ORing FET to repeatedly cycle
on-and-off if the load cannot maintain the required positive voltage drop across the combined resistance of the
external FETs and the sense resistor. For further information, see Adjusting ORing Turn Off threshold For High
Power Loads section.
12BOR Clearing this bit forces the BLKB pin low, keeping the 12B ORing FET off. Clearing this bit does not
prevent current from flowing through the FET’s body diode.
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Register 4
Table 7. Register 4: Channel 12B Configuration (Read/write)
BIT
0
NAME
12BFT0
12BFT1
12BFT2
12BFT3
12BFT4
12BEN
12BUV
12BDS
DEFAULT
DESCRIPTION
Setting bit increases 12B fault time by 0.5 ms.
1
0
0
0
0
0
0
0
1
Setting bit increases 12B fault time by 1 ms.
2
Setting bit increases 12B fault time by 2 ms.
3
Setting bit increases 12B fault time by 4 ms.
4
Setting bit increases 12B fault time by 8 ms.
5
Clearing bit disables 12B by pulling PASSB and BLKB to 0 V.
Setting bit prevents enabling unless OUT12B < bleed down threshold.
Clearing bit disconnects OUT12B bleed down resistor.
6
7
12BFT[4:0] These five bits adjust the 12B channel fault time. The least-significant bit has a nominal weight of 0.5
ms, so fault times ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In
general the shortest fault time that fully charges downstream bulk capacitors without generating a fault should be
used. Once the load capacitors have fully charged, the fault time can be reduced to provide faster short circuit
protection. See Setting Fault Time section.
12BEN This bit serves as a master enable for channel 12B. Setting this bit allows the 12B channel to operate
normally. Clearing this bit disables the channel by pulling PASSB and BLKB low.
12BUV Setting this bit prevents channel 12B from turning on until OUT12B falls below the bleed down threshold
of 100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly
zero before the channel can enable them.
12BDS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT12B to ground.
Systems using redundant power supplies should clear 12BDS to prevent the bleed down resistor from
continuously sinking current.
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Register 5
Table 8. Register 5: Channel 3B Configuration (Read/write)
BIT
0
NAME
3BFT0
3BFT1
3BFT2
3BFT3
3BFT4
3BEN
3BUV
3BDS
DEFAULT
DESCRIPTION
Setting bit increases 3B fault time by 0.5 ms.
1
0
0
0
0
0
0
0
1
Setting bit increases 3B fault time by 1 ms.
Setting bit increases 3B fault time by 2 ms.
Setting bit increases 3B fault time by 4 ms.
Setting bit increases 3B fault time by 8 ms.
Clearing bit disables 3B.
2
3
4
5
6
Setting bit prevents enabling unless OUT3B < bleed down threshold.
Clearing bit disconnects OUT3B bleed down resistor.
7
3BFT[4:0] These five bits adjust the 3B channel fault time. The least-significant bit has a nominal weight of 0.5
ms, so fault times ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In
general the shortest fault time that fully charges downstream bulk capacitors without generating a fault should be
used. See Setting Fault Time section.
3BEN This bit serves as a master enable for channel 3B. Setting this bit allows the 3B channel to operate
normally, provided the EN3B pin is also asserted. Clearing this bit disables the channel by removing gate drive to
the internal pass FET, regardless of the state of the EN3B pin.
3BUV Setting this bit prevents channel 3B from turning on until OUT3B falls below the bleed down threshold of
100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly
zero before the channel can enable them.
3BDS Clearing this bit disconnects the bleed down resistor that otherwise connects from OUT3B to ground.
Systems using redundant power supplies should clear 3BDS to prevent the bleed down resistor from
continuously sinking current.
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Register 6
Table 9. Register 6: System Configuration (Read/write)
BIT
NAME
DEFAULT
DESCRIPTION
0
PPTEST
0
12-V pulldown test pin. Asserting this pulls the PASSx and BLKx pins to 0 V.
Clearing bit forces channels to latch off after over-current fault. Setting bit allows
channels to automatically attempt restart after fault.
1
2
3
FLTMODE
SPARE
0
0
0
This bit must always be set to 0.
Setting bit enables 3A and 3B to prevent reverse current flow.Clearing bit disables 3A
and 3B ORing.
3ORON
Non Redundant System in rush control bit. Setting bit allows increased inrush current
in 12A and 12B.
4
12VNRS
0
5
6
AIRM
BIRM
0
0
Setting this masking bit prevents REG7 bits 3:0 from setting IRPT.
Setting this masking bit prevents REG7 bits 7:4 from setting IRPT.
Setting bit allows the 12 V channels to operate despite loss of 3.3 V. For uTCA and
AMC applications this bit should be low.
7
DCC
0
PPTEST This bit is used for testing the fast turnoff feature of the PASSx and BLKx pins. Setting this bit enables
the fast turnoff drivers for all four pins. Clearing this bit restores normal operation. PPTEST allows the fast turnoff
drivers to operate at full current indefinitely, whereas they would normally operate for only about 15 S. While
using PPTEST the energy dissipated in the fast turnoff drivers must be externally limited to 1 mJ per driver to
prevent damage to the TPS2359.
FLTMODE Setting this bit allows a channel to attempt an automatic restart after an overcurrent condition has
caused it to time out and shut off. The retry interval equals approximately 100 times the programmed fault time.
The FLTMODE bit affects all four channels. If cross-connection is enabled (DCC = 0), a fault on channel 3A turns
off channel 12A, and a fault on channel 3B turns off channel 12B. If a 3.3-V channel automatically restarts
because FLTMODE = 1, the associated 12-V channel remains disabled until its enable bit (12AEN or 12BEN) is
cycled on and off.
SPARE This bit must always be set to 0.
3ORON Setting this bit allows the 3.3-V ORing function to operate normally. Clearing this bit prevents the 3.3-V
channels from disabling if their output voltage exceeds their input voltage . This bit is typically cleared for
non-redundant systems.
12VNRS Setting this bit increases the current limit for either 12-V channel to its maximum value during the initial
inrush period that immediately follows the enabling of the channel. During inrush, the current limit behaves as if
12xCL[3:0] = 1111B. After the current drops below this limit, signifying the end of the inrush period, the current
limit returns to normal operation.
AIRM Setting this bit prevents the 12APG, 12AFLT, 3APG, and 3AFLT bits from setting the IRPT pin.
BIRM Setting this bit prevents the 12APG, 12BFLT, 3BPG, and 3BFLT bits from setting the IRPT pin.
DCC Setting this bit disables cross-connection. If DCC = 0, when a 3.3-V channel experiences a fault, both it and
its associated 12-V channel turn off. Specifically, a fault on channel 3A turns off channel 12A, and a fault on
channel 3B turns off channel 12B. If DCC = 1, then the 12-V channels continue to operate even if their
associated 3.3-V channels experience faults.
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Register 7
Table 10. Register 7: Latched IRPT Channel Status Indicators (Read-only, cleared on read)
BIT
0
NAME
12APG
12AFLT
3APG
DEFAULT
DESCRIPTION
0
0
0
0
0
0
0
0
Latches high when OUT12A goes from above VTH_PG to below VTH_PG
Latches high when 12A fault timer has run out.
.
.
1
2
Latches high when OUT3A goes from above VTH_PG to below VTH_PG
Latches high when 3A fault timer has run out.
.
3
3AFLT
12BPG
12BFLT
3BPG
4
Latches high when OUT12B goes from above VTH_PG to below VTH_PG
Latches high when 12B fault timer has run out.
5
6
Latches high when OUT3B goes from above VTH_PG to below VTH_PG
Latches high when 3B fault timer has run out.
.
7
3BFLT
12APG This bit is set if the voltage on OUT12A drops below the power-good threshold set by the 12APG[1:0]
bits, and it remains set until Register 7 is read. If AIRM = 0, setting this bit asserts the IRPT pin.
12AFLT This bit is set if the fault timer on channel 12A has run out, and it remains set until Register 7 is read. If
AIRM = 0, setting this bit asserts the IRPT pin.
3APG This bit is set if the voltage on OUT3A drops below the power-good threshold, and it remains set until
Register 7 is read. If AIRM = 0, setting this bit asserts the IRPT pin.
3AFLT This bit is set if the fault timer on channel 3A has run out, and it remains set until Register 7 is read. If
AIRM = 0, setting this bit asserts the IRPT pin.
12BPG This bit is set if the voltage on OUT12B drops below the power-good threshold set by the 12BPG[1:0]
bits, and it remains set until Register 7 is read. If BIRM = 0, setting this bit asserts the IRPT pin.
12BFLT This bit is set if the fault timer on channel 12B has run out, and it remains set until Register 7 is read. If
BIRM = 0, setting this bit asserts the IRPT pin.
3BPG This bit is set if the voltage on OUT3B drops below the power-good threshold, and it remains set until
Register 7 is read. if BIRM = 0, setting this bit asserts the IRPT pin.
3BFLT This bit is set if the fault timer on channel 3B has run out, and it remains set until Register 7 is read. If
BIRM = 0, setting this bit asserts the IRPT pin.
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Register 8
Table 11. Register 8: Latched Status Indicators (Read-only, cleared on read)
BIT
0
NAME
12AOC
12AFTR
3AOC
DEFAULT
DESCRIPTION
Latches high when 12A enters over-current.
0
0
0
0
0
0
0
0
1
Latches high if 12A fast trip threshold exceeded.
Latches high when 3A enters over-current.
Latches high if 3A fast trip threshold exceeded.
Latches high when 12B enters over-current.
Latches high if 12B fast trip threshold exceeded.
Latches high when 3B enters over-current.
Latches high if 3B fast trip threshold exceeded.
2
3
3AFTR
12BOC
12BFTR
3BOC
4
5
6
7
3BFTR
12AOC This bit is set if the voltage on the PASSA pin drops below the timer start threshold, signifying a current
limit condition. This bit remains set until Register 8 is read.
12AFTR This bit is set if the voltage across the sense resistor for channel 12A exceeds the fast trip threshold.
This bit remains set until Register 8 is read.
3AOC This bit is set if the gate-to-source voltage on the channel 3A pass FET drops low enough to start the fault
timer. This bit remains set until Register 8 is read.
3AFTR This bit is set if the current through channel 3A exceeds the fast trip threshold. This bit remains set until
Register 8 is read.
12BOC This bit is set if the voltage on the PASSB pin drops below the timer start threshold, signifying a current
limit condition. This bit remains set until Register 8 is read.
12BFTR This bit is set if the voltage across the sense resistor for channel 12B exceeds the fast trip threshold.
This bit remains set until Register 8 is read.
3BOC This bit is set if the gate-to-source voltage on the channel 3B pass FET drops low enough to start the fault
timer. This bit remains set until Register 8 is read.
3BFTR This bit is set if the current through channel 3B exceeds the fast trip threshold. This bit remains set until
Register 8 is read.
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Register 9
Table 12. Register 9: Unlatched Status Indicators (Read-only)
BIT
0
NAME
12ABS
12APS
3ABS
DEFAULT
DESCRIPTION
High indicates BLKA commanded high.
-
-
-
-
-
-
-
-
1
Low indicates VPASSA > VOUT12A + 61V.
Low indicates IN3A > OUT3A.
2
3
12BBS
12BPS
3BBS
High indicates BLKB commanded high.
4
Low indicates VPASSB > VOUTB + 61V.
5
Low indicates IN3B > OUT3B.
6
3AGS
3BGS
Low indicates channel 3A gate is driven on (VGATE > VIN + 1.75 V).
Low indicates channel 3B gate is driven on (VGATE > VIN + 1.75 V).
7
12ABS This bit goes high when the 12A ORing logic commands the BLKA pin high (25 V) and the BLKA FET
should be on.
12APS This bit goes low when the 12A PASS pin is above the timer start threshold (OUT12A + 7 V), indicating
that the 12A PASS FET should be on.
3ABS This bit goes low when the 3A ORing logic commands the pass 3A FET on, indicating that a reverse
blocking condition does not exist.
12BBS This bit goes high when the 12B ORing logic commands the BLKB pin high ( 25 V ) and the BLKB FET
should be on.
12BPS This bit goes low when the 12B PASS pin is above the timer start threshold (OUT12B + 7 V), indicating
that the 12B PASS FET should be on.
3BBS This bit goes low when the 3B ORing logic commands the 3B pass FET on, indicating that a reverse
blocking condition does not exist.
3AGS This bit goes low when the 3A FET gate-to-source voltage exceeds 1.75 V, indicating that the 3A FET
should be on.
3BGS This bit goes low when the 3B FET gate-to-source voltage exceeds 1.75 V, indicating that the 3B FET
should be on.
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APPLICATION INFORMATION
Introduction
The TPS2359 controls two 12-V power paths and two 3.3-V power paths. Each power path can draw from a
single common supply, or from two independent supplies. The TPS2359 occupies a 36-pin QFN package. An I2C
interface not only enables the implementation of two AdvancedMC™ slots using one small integrated circuit, but
it also provides many opportunities for design customization. The following sections describe the main functions
of the TPS2359 and provide guidance for designing systems around this device.
Control Logic and Power-On Reset
The TPS2359's circuitry, including the I2C interface, draws power from an internal bus fed by a preregulator. A
capacitor attached to the VINT pin provides decoupling and output filtering for this preregulator. It can draw
power from any of four inputs (IN12A, IN12B, IN3A, or IN3B) or from any of four outputs (OUT12A, OUT12B,
OUT3A, or OUT3B). This feature allows the internal circuitry to function regardless of which channels receive
power, or from what source. The four external FET drive pins (PASSA, PASSB, BLKA, and BLKB) are held low
during startup to ensure that the two 12-V channels remain off. The internal 3.3-V channels are also held off.
When the voltage on the internal VINT rail exceeds approximately 1 V, the power-on reset circuit loads the
internal registers with the default values listed in Detailed Description of Registers section.
Enable Functions
Table 13 lists the specific conditions required to enable each of the four channels of the TPS2359. The 3.3-V
channels each have an active-high enable pin with a 200-kΩ internal pullup resistor. The enable pin must be
pulled high, or allowed to float high, in order to enable the channel. The I2C interface includes an enable bit for
each of the four channels. The bit corresponding to a channel must be set in order to enable it. All four channels
also include bleed down threshold comparators. Setting the bleed down control bit ensures that a channel cannot
turn on until its output voltage drops below about 100 mV. This feature supports applications in which removal
and restoration of power re-initializes the state of downstream loads. The 12-V channels also include a
cross-connection feature to support PICMG.AMC™ and MicroTCA™ requirements. When enabled, this feature
ensures that when a 3.3-V output drops below 2.85 V the associated 12-V channel will automatically shut off.
This feature can be disabled by setting the DCC bit in Register 6.
Table 13. Enable Requirements
Channel
3A
Enable pins
EN3A > 1.4 V
EN3B > 1.4 V
Enable bits
3AEN = 1
3BEN = 1
12AEN = 1
12BEN = 1
Bleed down
Cross connection
OUT3A < 0.1 V or 3AUV = 0
OUT3B < 0.1 V or 3BUV = 0
OUT12A < 0.1 V or 12AUV = 0
OUT12B < 0.1 V or 12BUV = 0
3B
12A
3APG = 0 or DCC = 1
3BPG = 0 or DCC = 1
12B
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Fault, Power Good, Overcurrent, and FET Status Bits
The TPS2359 I2C interface includes six status bits for each channel, for a total of 24 bits. These status bits
occupy registers 7, 8, and 9. The following table summarizes the locations of these bits:
Table 14. TPS2359 Status Bit Locations(1)
12A
3A
12B
3B
FUNCTION
REGISTER [bit]
Power Good (PG)
R7[0]
R7[1]
R8[0]
R8[1]
R9[0]
R9[1]
R7[2]
R7[3]
R8[2]
R8[3]
R7[4]
R7[5]
R8[4]
R8[5]
R9[3]
R9[4]
R7[6]
R7[7]
R8[6]
R8[7]
Overcurrent Time out Fault (FLT)
Momentary Overcurrent (OC)
Overcurrent Fast Trip (FTR)
12-V Block FET Status (12xBS)
12-V Pass FET Status (12xPS)
3-V Block Status (3xBS)
R9[2]
R9[6]
R9[5]
R9[7]
3-V Gate Status (3xGS)
(1) For a description of each bit, refer to Detailed Description of Registers section.
Current Limit and Fast Trip Thresholds
All four channels monitor current by sensing the voltage across a resistor. The 3.3-V channels use internal sense
resistors with a nominal value of 290 mΩ. The 12-V channels use external sense resistors that typically lie in the
range of 4 - 10 mΩ. Each channel features two distinct thresholds: a current limit threshold and a fast trip
threshold.
The current limit threshold sets the regulation point of a feedback loop. If the current flowing through the channel
exceeds the current limit threshold, then this feedback loop reduces the gate-to-source voltage imposed on the
pass FET. This causes the current flowing through the channel to settle to the value determined by the current
limit threshold. For example, when a module first powers up, it draws an inrush current to charge its load
capacitance. The current limit feedback loop ensures that this inrush current does not exceed the current limit
threshold.
The current limit feedback loop has a finite response time. Serious faults such as shorted loads require a faster
response in order to prevent damage to the pass FETs or voltage sags on the supply rails. A comparator
monitors the current flowing through the sense resistor, and if it ever exceeds the fast trip threshold, then it
immediately shuts off the channel. The channel turns back on slowly, allowing the current limit feedback loop
time to respond. One normally sets the fast trip threshold some 2 – 5 times higher than the current limit.
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3.3V Current Limiting
The 3.3-V management power channels include internal pass FETs and current sense resistors. The
on-resistance of a management channel - including pass FET, sense resistor, metallization resistance, and bond
wires - typically equals 290 mΩ and never exceeds 500 mΩ. The AdvancedMC™ specification allows a total of 1
Ω between the power source and the load. The TPS2359 never consumes more than half of this budget.
The 3.3-V fast trip function protects the channel against short-circuit events. If the current through the channel
exceeds a nominal value of 300 mA, then the TPS2359 immediately disables the internal pass transistor and
then allows it to slowly turn back on into current limiting.
The 3.3-V current limit function internally limits the current to comply with the AdvancedMC™ and MicroTCA™
specifications. External resistor RSUM3x allows the user to adjust the current limit threshold. The nominal current
limit threshold ILIMIT equals
650V
ILIMIT
=
RSUM 3x
(1)
A 3320-Ω resistor gives a nominal current limit of ILIMIT = 195 mA which complies with AdvancedMC™ and
MicroTCA™ specifications. This resistance corresponds to an EIA 1% value. Alternatively, a 3.3-kΩ resistor will
also suffice. Whenever a 3.3-V channel enters current limit, its fault timer begins to operate (see Fault Timer
Programming section).
The 3.3-V over-temperature shutdown trips if a 3.3-V channel remains in current limit so long that the die
temperature exceeds approximately 140°C. When this occurs, any 3.3-V channel operating in current limit turns
off until the chip cools by approximately 10°C. This feature prevents a prolonged fault on one 3.3-V channel from
disabling the other 3.3-V channel, or disabling either of the 12-V channels.
3.3-V ORing
The 3.3-V channels limit reverse current flow by sensing the input-to-output voltage differential and turning off the
internal pass FET when this differential drops below -3 mV, which corresponds to a nominal reverse current flow
of 10 mA. The pass FET turns back on when the differential exceeds +10 mV. These thresholds provide a
nominal 13 mV of hysteresis to help prevent false triggering. This feature allows the implementation of redundant
power supplies (also known as supply ORing).
If the 3.3-V channels do not use redundant supplies, then one can clear the 3ORON bit to disable the ORing
circuitry. This precaution eliminates the chance that transients might trigger the ORing circuitry and upset system
operation.
12-V Fast Trip and Current Limiting
Figure 21 shows a simplified block diagram of the circuitry associated with the fast trip and current limit circuitry
within a 12-V channel. Each 12-V channel requires an external N-channel pass FET and three external resistors.
These resistors allow the user to independently set the fast trip threshold and the current limit threshold, as
described below.
The 12-V fast trip function protects the channel against short-circuit events. If the voltage across external resistor
RSENSE exceeds the 100-mV fast trip threshold, then the TPS2359 immediately disables the pass transistor. The
12xCL bits set the magnitude of the fast trip threshold. When 12xCL = 1111B, the fast trip threshold nominally
equals 100 mV. The fast trip current IFT corresponding to this threshold equals
100mV
IFT
=
RSENSE
(2)
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The recommended value of RSENSE = 5 mΩ sets the fast trip threshold at 20 A for 12xCL = 1111B. This choice of
sense resistor corresponds to the maximum 19.4-A inrush current allowed by the MicroTCA™ specification.
The 12-V current limit function regulates the PASSx pin voltage to prevent the current through the channel from
exceeding ILIMIT. The current limit circuitry includes two amplifiers, A1 and A2, as shown in Figure 21. Amplifier
A1 forces the voltage across external resistor RSET to equal the voltage across external resistor RSENSE. The
current that flows through RSET also flows through external resistor RSUM, generating a voltage on the 12SUMx
pin equal to:
æ
ç
è
ö
÷
ø
RSENSE RSUM
V
=
I
SENSE
12SUMx
RSET
(3)
Amplifier A2 senses the voltage on the 12SUMx pin. As long as this voltage is less than the reference voltage on
its positive input (nominally 0.675 V for 12xCL = 0000B), the amplifier sources current to PASSx. When the
voltage on the 12SUMx pin exceeds the reference voltage, amplifier A2 begins to sink current from PASSx. The
gate-to-source voltage of pass FET MPASS drops until the the voltages on the two inputs of amplifier A2
balance. The current flowing through the channel then nominally equals:
æ
ç
è
ö
÷
ø
RSET
ILIMIT
=
´0.675V
RSUM RSENSE
(4)
The recommended value of RSUM is 6810 Ω. This resistor should never equal less than 675 Ω to prevent
excessive currents from flowing through the internal circuitry. Using the recommended values of RSENSE = 5 mΩ
and RSUM = 6810 Ω gives:
( 0.0198A)
ILIMIT
=
´ RSET
W
(5)
A system capable of powering an 80-Watt AdvancedMC™ module should provide 8.25 A, +/- 10%, according to
MicroTCA™ specifications. The above equation suggests RSET = 417 Ω. The nearest 1% EIA value equals 422
Ω. The selection of RSET for MicroTCA™ power modules is described in the Redundant vs. Non-redundant Inrush
Current Limiting section.
RSENSE
IN12x
R
SET
Fast Trip
Comparator
SENPx
SENMx
PASSx
+
100 mV
30
A
A1
675 mV
+
A2
Current Limit
Amp
SUM12x
R
SUM
Figure 21. 12-V Channel Threshold Circuitry
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Redundant vs Non-Redundant Inrush Current Limiting
The TPS2359 can support either redundant or non-redundant systems. Redundant systems generally use a
single fixed current limit, as described above. Non-redundant systems can benefit from a higher current limit
during inrush to compensate for the lack of a redundant supply. The MicroTCA™ standard allows up to 19.4 A
for up to 200 ms in non-redundant systems, while limiting individual supplies in redundant systems to 9.1 A at all
times. One can optimize the performance of the system for either application by properly setting the 12VNRS bit
that controls inrush limiting. The ability to change the inrush profile using 12VNRS makes it possible to
reconfigure a controller for redundant or non-redundant operation with a single bit. This is particularly useful for
MicroTCA Power Modules which may be deployed in redundant or non-redundamnt systems.
The 12VNRS bit affects the value of the 12xCL bits during inrush. Setting 12VNRS causes the current limit
threshold and fast trip threshold to behave as if 12xCL = 1111B during inrush. Once the current flowing through
the channel falls below the current limit threshold, the current limit threshold and fast trip threshold correspond to
the actual values of the 12xCL bits.
Figure 22 helps illustrate the behavior of the 12VNRS bit. Figure 22A shows that setting the 12xCL bits to 1111B
results in a current limit equal to IMAX. Figure 22B shows how the 12xCL bits affect the current limit when the
12VNRS bit is cleared. Setting 12xCL = 0111B reduces the current limit to 60% of IMAX. Figure 22C shows how
the 12xCL bits affect the current limit when the 12VNRS bit is set. The current limit initially equals IMAX, but as
soon as the current drops below this level, the current limit resets to 60% of IMAX and remains there so long as
the channel remains enabled.
12VNRS = X
12VNRS = 0
12VNRS = 1
12xCL[3:0] = 1111B
12xCL[3:0] = 0111B
12xCL[3:0] = 0111B
IMAX
IMAX
IMAX
If 12xCL[3:0] = 1111B,
12VNRS has no effect
.6IMAX
.6IMAX
.6IMAX
A
B
C
T
0
0
T
0
T
0
TFAULT
0
TFAULT
0
TFAULT
Figure 22. Current Limits in Redundant and Non-Redundant Systems
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Example 1:
Set up 12A to start into an 80 W load and charge
a 1600 uF capacitor in less than 3 ms. Set an
operational ILIMIT of 8.25 A +/- 10%.
First, calculate how much current is needed for
capacitor charging and powering the load;
ISTARTUP = ICHARGE + ILOAD = 6.4A + 6.67 A = 13.7 A
Where;
ICHARGE = CV/T = 1600uF x 12V / .003 s = 6.4 A
ILOAD = PLOAD / VLOAD = 80 W / 12V = 6.67 A
Now calculate RSET for an ILIMIT of 13.7 A.
R
SET = ( ILIMIT x RSENSE x RSUM ) / 0.675
= 691 ( closest 1% value = 698
)
Where;
RSUM = 6810
RSENSE = 5 m
Now ILIMIT = 0.675RSET / ( RSUM RSENSE ) = 13.83 A
If R0 [3:0] are set to 0111 and R6 [4] = 1 the
current limit will drop to 60% of the programmed
maximum after dropping out of current limit
following inrush. The operational current limit is
now;
ILIMIT = 0.6 x IINRUSH = 0.6 x 13.83 = 8.3 A
The 8.3 A limit complies with 8.25 A +/ - 10 %.
Note - These calculations use all nominal values
and neglect di/dt rates at turn on.
Figure 23. Inrush Current Limiting Example 1
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Example 2:
Set up 12A to startup into an 80 W load and
charge a 1600 uF at not more than 17 A nominal.
Then drop to an operational ILIMIT of 8.25 A +/-
10%.
ISTARTUP = 17 A
First, the correct RSET must be found to set
maximum ILIMIT to less than 17 A.
RSET = ( ILIMIT x RSENSE x RSUM ) / 0.675
= 857 ( closest 1% value = 845
)
Where;
RSUM = 6810
RSENSE = 5 m
Now ILIMIT = 0.675RSET / ( RSUM RSENSE ) = 16.75 A
Neglecting current slew time, this will charge the
1600 uF capacitor in 1.9 ms.
If R0 [3:0] are set to 0101 and R6 [4] = 1 the
current limit will drop to 50% of the programmed
maximum after dropping out of current limit
following inrush. The operational current limit is
now;
ILIMIT = 0.5 x IINRUSH = 0.5 x 16.75 = 8.38 A
The new 8.38 A current limit is within the spec of
8.25 A +/- 10 %.
Note - These calculations use all nominal values.
Figure 24. Inrush Current Limiting Example 2
Table 15. Configuring 12-V Current Limits in Non-Redundant Systems
ILIMIT
OPERATIO
NAL
12VNRS =
1
CBULK CHARGE TIME
(ms)
ILIMIT - INRUSH 12VNRS
FAULT TIME (ms)
12xCLx
[3:0]
RSET
PLOAD (W)
R6[4]=0
R6[4]=1
800 µF
1600 µF
800 µF
1600 µF
412
698
845
1111
111
8.17
13.84
16.75
8.17
8.3
8.17
8.3
80
80
80
6.4
12.8
2.68
1.9
8.5
2
17
3.5
3
1.34
0.95
101
8.38
8.38
1.5
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Multiswap Operation in Redundant Systems
TheTPS2359 features an additional mode of operation called Multiswap redundancy. This technique does not
require a microcontroller, making it simpler and faster than the redundancy schemes described in the
MicroTCA™ standard. Multiswap is especially attractive for AdvancedMC™ applications requiring redundancy,
but need not comply with the MicroTCA™ power module standard.
In order to implement multiswap redundancy, connect the SUM pins of the redundant channels together and tie a
single RSUM resistor from this node to ground. The current limit thresholds now apply to the sum of the currents
delivered by the redundant supplies. When implementing multiswap redundancy on 12-V channels, all of the
channels must use the same values of resistors for RSENSE and RSET
.
Figure 25 compares the redundancy technique advocated by the MicroTCA™ specification with multiswap
redundancy. MicroTCA™ redundancy independently limits the current delivered by each power source. The
current drawn by the load cannot exceed the sum of the current limits of the individual power sources. Multiswap
redundancy limits the current drawn by the load to a fixed value regardless of the number of operational power
sources. Removing or inserting power sources within a multiswap system does not affect the current limit seen
by the load.
TM
MicroTCA Redundancy
Multiswap Redundancy
Power Source 1
Power Source 2
Power Source 1
Power Source 2
TPS2359
TPS2359
TPS2359
TPS2359
SUM12x
SUM3x
SUM12x
SUM3x
SUM12x
SUM3x
SUM12x
SUM3x
mC
mC
Backplane
Backplane
Figure 25. MicroTCA Redundancy vs. Multiswap Redundancy
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12-V Inrush Slew Rate Control
As normally configured, the turn-on slew rate of the 12-V channel output voltage VOUT12x equals:
dVout Isrc
@
dt
Cg
(6)
where ISRC equals the current sourced by the PASSx pin (nominally 30 µA) and Cg equals the effective gate
capacitance. For purposes of this computation, one can assume that the effective gate capacitance
approximately equals the reverse transfer capacitance, CRSS. To reduce the slew rate, increase Cg by connecting
additional capacitance from PASSx to ground. Place a resistor of at least 1000 Ω in series with the additional
capacitance to prevent it from interfering with the fast turn off of the FET.
R
SENSE
IN12x
C
R > 1k
PASSx
Figure 26. RC Slew Rate Control
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12-V ORing Operation for Redundant Systems
The 12-V channels use external pass FETs to provide reverse current blocking. The TPS2359 pulls the BLKx pin
high when the input-to-output differential voltage IN12x-OUT12x exceeds a nominal value of 10 mV, and it pulls
the pin low when this differential falls below a nominal value of -3 mV. These thresholds provide a nominal 13
mV of hysteresis to help prevent false triggering.
The source of the blocking FET connects to the source of the pass FET, and the drain of the blocking FET
connects to the load. This orients the body diode of the blocking FET such that it conducts forward current and
blocks reverse current. The body diode of the blocking FET does not normally conduct current because the FET
turns on when the voltage differential across it exceeds 10 mV.
Applications that do not use the blocking FET should clear the associated 12xOR bit to turn off the internal
circuitry that drives the BLKx pin.
12-V ORing for High-Power Loads
The 12AHP and 12BHP bits adjust the ORing turn-off thresholds of the 12A and 12B channels, respectively.
Clearing these bits sets the ORing turn-off thresholds to the default nominal value of -3 mV. Setting these bits
shifts the thresholds up by 6 mV to a nominal value of +3 mV (Figure 27). Shifting the turn-off threshold to a
postive value ensures that the blocking FET shuts off before any reverse current flows.
A light load may not draw sufficient current to keep the input-to-output differential VIN12x–OUT12x above 3 mV.
When this happens, the blocking FET shuts off and then the differential voltage increases until it turns back on.
This process endlessly repeats, wasting power and generating noise. Therefore 12AHP or 12BHP should only be
set for high-power loads that satisfy the relationship
10mV
ILOAD
>
RSENSE + RDSonPASS + RDSonBLK
(7)
where ILOAD equals the current drawn by the load, RSENSE equals the value of the sense resistor, RDS(on)PASS
equals the maximum on-resistance of the pass FET, and RDSo(n)BLK equals the maximum on-resistance of the
blocking FET.
Example: If RSENSE = RHSFET = RORFET = 5 mΩ then a high-power load must always draw at least 667 mA. Most,
although not all, AdvancedMC™ loads can benefit from using the high-power bits 12AHP and 12BHP.
12xHP = 0
12xHP = 1
25 V
25 V
Gnd
V
Gnd
V
OR
OR
Figure 27. 12-V ORing Thresholds - High Power vs. Low Power
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Internal Bleed-Down Resistors and Bleed-Down Thresholds
The TPS2359 includes two features intended to support downstream loads that require removal and
reapplication of power to properly reset their internal circuitry. Disabling and re-enabling a channel of the
TPS2359 will not necessarily reset such a load because the capacitance attached to the output bus may not fully
discharge.
The TPS2359 includes four bleed down comparators that monitor the output rails through pins OUT12A,
OUT12B, OUT3A, and OUT3B. The I2C interface includes four bits that enable these comparators — 3ADS,
3BDS, 12ADS, and 12BDS. Enabling a bleed down comparator prevents its corresponding channel from turning
on until the output voltage drops below about 100 mV. This precaution ensures that the output rail drops so low
that all downstream loads properly reset.
In case the downstream load cannot quickly bleed off charge from the output capacitance, the TPS2359 also
includes bleed down resistors connected to each output rail through pins OUT12A, OUT12B, OUT3A, and
OUT3B. Internal switches connect these resistors from their corresponding rails to ground when the channels are
disabled, providing that one sets the appropriate bits in the I2C interface. These bits are named 12AUV, 12BUV,
3AUV, and 3BUV. Clearing these bits ensures that the corresponding resistors never connect to their buses.
If redundant supplies connect to an output, then one should clear the corresponding bleed-down threshold and
bleed-down resistor bits. Failing to clear the bleed-down threshold bit will prevent the channel from enabling so
long as the redundant supply continues to hold up the output rail. Failing to clear the bleed-down resistor bit will
cause current to continually flow through the resistor when the TPS2359 is disabled and the redundant supply
holds up the output bus.
Fault Timer Programming
Each of the TPS2359's four channels includes a fault timer. This timer begins operating whenever the channel
enters current limit. If the channel remains in current limit so long that the fault timer runs out, then the channel
turns off the pass FET and reports a fault condition by means of the xFLT bit in the I2C interface.
The four fault timers are independently programmable from 0.5 to 16 ms in steps of 0.5 ms using the appropriate
xFT bits. A code of xFT = 00001B corresponds to the minimum programmable time of 0.5 ms. The code xFT =
00000B corresponds to an extremely short time interval of no practical use.
The locations of the fault timer programming bits are:
Table 16. Fault Time Control Bits
REGISTER [bit]
CHANNEL
8 ms
R1[4]
R4[4]
R2[4]
R5[4]
4 ms
R1[3]
R4[3]
R2[3]
R5[3]
2 ms
R1[2]
R4[2]
R2[2]
R5[2]
1 ms
R1[1]
R4[1]
R2[1]
R5[1]
0.5 ms
R1[0]
R4[0]
R2[0]
R5[0]
12A
12B
3A
3B
The user should select the shortest fault times sufficient to allow down-stream loads and bulk capacitors to
charge. Shorter fault times reduce the stresses imposed on the pass FETs under fault conditions. This
consideration may allow the use of smaller and less expensive pass FETs for the 12-V channels.
The TPS2359 supports two modes of fault timer operation. Clearing the FLTMODE bit causes a channel to latch
off whenever its fault timer runs out. The channel remains off until it has been disabled and re-enabled (see
Enable Functions section). The TPS2359 operates in this manner by default. Setting the FLTMODE bit causes a
faulted channel to automatically attempt to turn back on after a delay roughly one hundred times the fault time.
This process repeats until either the fault disappears or the user disables the channel. The pass FET for a 12-V
channel with a shorted output must therefore continuously dissipate
P
» 0.01×VIN12x ICL
fault
(8)
where VIN12x equals the voltage present at the input of the 12-V channel and ICL equals the current limit setting
for this channel (the inrush current if 12VNRS is set).
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TPS2359 I2C Interface
The TPS2359 digital interface meets the specifications for an I2C bus operating in the high-speed mode. One can
configure the interface to recognize any one of 27 separate I2C addresses using the A0, A1, and A2 pins
(Table 17 I2C Addressing). These pins accept any of three distinct voltage levels. Connecting a pin to ground
generates a low level (L). Connecting a pin to VINT generates a high level (H). Leaving a pin floating generates a
no-connect level (NC).
Table 17. I2C Addressing
EXTERNAL PINS
I2C (Device) ADDRESS
A2
L
A1
L
A0
L
Dec
8
Hex
8
Binary
1000
L
L
NC
H
9
9
1001
L
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
1010
L
NC
NC
NC
H
L
1011
L
NC
H
1100
L
1101
L
L
1110
L
H
NC
H
1111
L
H
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
100000
100001
100010
NC
NC
NC
NC
NC
NC
NC
NC
NC
H
L
L
L
NC
H
L
NC
NC
NC
H
L
NC
H
L
H
NC
H
H
L
L
H
L
NC
H
H
L
H
NC
NC
NC
H
L
H
NC
H
H
H
L
H
H
NC
H
H
H
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The I2C hardware interface consists of two wires known as serial data (SDA) and serial clock (SCL). The
interface is designed to operate from a nominal 3.3-V supply. SDA is a bidirectional wired-OR bus that requires
an external pullup resistor, typically a 2.2-kΩ resistor connected from SDA to the 3.3-V supply.
The I2C protocol assumes one device on the bus acts as a master and another device acts as a slave. The
TPS2359 supports only slave operation with two basic functions called register write and register read.
Register Write: Figure 28 Format of a Register Writeshows the format of a register write. First the master issues
a start condition, followed by a seven-bit I2C address. Next the master writes a zero to signify that it wishes to
conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register
number across the bus. Following a second acknowledge, the master writes the eight-bit data value for the
register across the bus. Upon receiving a third acknowledge, the master issues a stop condition. This action
concludes the register write.
0
Register Number
Data
A ddress
Figure 28. Format of a Register Write. Shaded Regions Denote Bus Control by TPS2358/9
Register Read: Figure 29 Format of a Register Read shows the format of a register read. First the master issues
a start condition followed by a seven-bit I2C address. Next, the master writes a zero to signify that it will conduct
a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number
across the bus. Following a second acknowledge, the master issues a repeat start condition. Then the master
issues a seven-bit I2C address followed by a one to signify that it will conduct a read operation. Upon receiving a
third acknowledge, the master releases the bus to the TPS2359. The TPS2359 then writes the eight-bit data
value from the register across the bus. The master acknowledges receiving this byte and issues a stop condition.
This action concludes the register read.
I2C Address
Register Number
I2C Address
Data
0
1
Figure 29. Format of a Register Read. Shaded Regions Denote Bus Control by TPS2358/9
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Using the TPS2359 to Control Two AdvancedMC™Slots
The TPS2359 has been designed for use in systems under I2C control. Figure 30 shows the TPS2359 in a
typical system implementing redundant power sources. A non-redundant application would omit the blocking
FETs and leave the BLKx pins unconnected.
12 V
R
SENSE
R
SET
SENPA
IN12A
SENMA
PASSA
SETA
BLKA
OUT12A
OUT3A
AMC A
HS FET
IN3A
3.3 V
VDD3A
SUM12A
SUM3A
EN3A\
SDA
SCL
A0
IRPT\
VINT
To IPMC
TPS2359
36 PIN QFN
COMMON
CIRCUITRY
AGND
GND0
GND1
From IPMC
3.3 V
6mm x 6mm
A1
12 V in
A2
SUM12B
SUM3B
EN3B\
IN3B
VDD3B
OUT3B
3.3 V
HS FET
IN12B
SENPB
SETB
SENMB
PASSB
BLKB
OUT12B
AMC B
R
SET
R
SENSE
12 V
Figure 30. Block Diagram of TPS2359 In a Redundant System
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Layout Consideration
TPS2359 applications require careful attention to layout in order to ensure proper performance and minimize
susceptibility to transients and noise. Important points to consider include:
1. Connect AGND, GNDA, and GNDB to a ground plane.
2. Place 0.01-µF or larger ceramic bypass capacitors on IN12A, IN12B, VDD3A, and VDD3B. Minimize the loop
area created by the leads running to these devices.
3. Minimize the loop area between the SENMx and SENPx leads by running them side-by-side. Use Kelvin
connections at the points of contact with RSENSE (Figure 31).
4. Minimize the loop area between the SETx and SENPx leads. Connect the SETx leads to the same Kelvin
points as the SENPx leads, or as close to these points as possible.
5. Size the following runs to carry at least 20 Amps:
–
–
Runs on both sides of RSENSE
Runs from the drains and sources of the external FETs
6. Minimize the loop area between the OUT12x and SENPx leads.
7. Size the runs to IN3x and OUT3x to carry at least 1 Amp.
8. Soldering the powerpad of the TPS2359 to the board will improve thermal performance.
LOAD CURRENT
PATH
LOAD CURRENT
PATH
SENSE
RESISTOR
RSET
RSET
4 3 2
4 3 2
TPS2359
TPS2359
(a)
(b)
Figure 31. SENMx and SENPx Runs Side-by-Side to Maximize Common Mode Rejection
NOTE:
Additional details omitted for clarity.
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Transient Protection
The need for transient protection in conjunction with hot-swap controllers should always be considered. When
the TPS2359 interrupts current flow, input inductance generates a positive voltage spike on the input and output
inductance generates a negative voltage spike on the output. The following equation estimates the magnitude of
these voltage spikes:
L
VSPIKE =VNOM + ILOAD
C
(9)
where VNOM equals the nominal supply voltage, ILOAD equals the load current, C equals the capacitance present
at the input or output of the TPS2359, and L equals the effective inductance seen looking into the source or the
load. The inductance due to a straight length of wire equals approximately
4L
æ
ö
LStraightWire » 0.2´ L´ln
- 0.75 nH
ç
÷
D
è
ø
(10)
where L equals the length of the wire and D equals its diameter.
If sufficient capacitance to prevent transients from exceeding the absolute ratings of the TPS2359 cannot be
included the application will require the addition of transient protectors.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2008
PACKAGING INFORMATION
Orderable Device
TPS2359RHHR
TPS2359RHHT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RHH
36
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
RHH
36
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2359RHHR
TPS2359RHHT
QFN
QFN
RHH
RHH
36
36
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2359RHHR
TPS2359RHHT
QFN
QFN
RHH
RHH
36
36
2500
250
346.0
190.5
346.0
212.7
33.0
31.8
Pack Materials-Page 2
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