TPS1H100-Q1 [TI]
具有可调节电流限制的 40V、100mΩ、汽车类单通道智能高侧开关;
| 型号： | TPS1H100-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节电流限制的 40V、100mΩ、汽车类单通道智能高侧开关 开关 |
| 文件： | 总51页 (文件大小：1854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
TPS1H100-Q1 40V、100mΩ 单通道智能高侧电源开关
1 特性
–
–
–
–
欠压锁定 (UVLO) 保护
具备自恢复功能的热关断/热振荡
接地失效保护和失电保护
对外部电路提供反向电池保护
1
•
•
符合汽车类 应用要求
具有符合 AEC-Q100 标准的下列特性：
–
器件温度等级 1：–40°C 至 125°C 的环境工作
温度范围
•
•
诊断
–
–
器件 HBM ESD 分类等级 H3A
器件 CDM ESD 分类等级 C4B
–
–
–
开启和关闭状态输出的开路和电池短路检测
过载和接地短路检测以及电流限制
•
•
提供功能安全
提供文档以帮助创建功能安全系统设计
具有全面诊断功能的单通道智能高侧电源开关
热关断/热振荡检测
–
14 引脚热增强型 PWP 封装
2 应用
–
–
版本 A：开漏状态输出
•
•
•
•
•
适用于子模块的高侧电源开关
版本 B：电流感应模拟输出
适用于低功率灯的电源开关
高侧继电器和电磁阀
•
•
•
•
•
宽工作电压范围：3.5V 至 40V
超低待机电流，低于 0.5µA
PLC 数字输出电源开关
一般阻性、感性和容性负载
工作结温范围，-40°C 至 150°C
输入控制，兼容 3.3V 和 5V 逻辑
高精度电流感应，电流为 1A 时为 ±30mA，
电流为 5mA 时为 ±4mA
3 说明
TPS1H100-Q1 是一款具有全方位保护的高侧电源开
关，它集成有 NMOS 功率 FET 和电荷泵，专用于对
各类阻性、感性和容性负载进行智能控制。精确的电流
检测和可编程电流限制 特性 使该器件从市场中脱颖而
出。
•
•
•
利用外部电阻器实现可编程电流限制（在 0.5A 时
为 ±20%）
用于对 MCU 模拟或数字接口进行多路复用的诊断
使能功能
测试符合 AECQ100-12 A 级标准，
经过 100 万次接地短路测试
器件信息(1)
•
•
通过 ISO7637-2 和 ISO16750-2 电瞬变抗扰度认证
器件型号
封装
封装尺寸（标称值）
保护
TPS1H100-Q1
HTSSOP (14)
4.40mm × 5.00mm
–
–
过载和短路保护
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
电感负载负电压钳位
典型应用原理图
VBAT
VS
Output
Clamp
IN
Gate Drive and
Clamp
5 V
ST
Version A
Logic and
Protection
DIAG_EN
OUT
MCU
CS
Version B
Current Sense/
Current Limit
Load
CL
GND
Dgnd
Rgnd
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCM2
TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
目录
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 31
Application and Implementation ........................ 32
8.1 Application Information............................................ 32
8.2 Typical Application ................................................. 32
Power Supply Recommendations...................... 37
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
8
9
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 37
10.3 Thermal Considerations........................................ 38
11 器件和文档支持 ..................................................... 39
11.1 接收文档更新通知 ................................................. 39
11.2 社区资源................................................................ 39
11.3 商标....................................................................... 39
11.4 静电放电警告......................................................... 39
11.5 Glossary................................................................ 39
12 机械、封装和可订购信息....................................... 39
6.6 Timing Requirements – Current Sense
Characteristics ........................................................... 8
6.7 Switching Characteristics.......................................... 9
6.8 Typical Characteristics............................................ 11
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 16
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (June 2018) to Revision D
Page
•
向特性 部分添加了提供功能安全的链接.................................................................................................................................. 1
Changes from Revision B (June 2015) to Revision C
Page
•
Changed the Pin Functions table to alphabetical order and created separate columns for the Version A and Version
B devices ................................................................................................................................................................................ 3
Added tablenotes to the Electrical Characteristics table ........................................................................................................ 7
添加了接收文档更新通知 部分.............................................................................................................................................. 39
•
•
Changes from Revision A (January 2015) to Revision B
Page
•
•
•
•
•
Updated Figure 6 and Figure 7 ............................................................................................................................................ 10
Updated Figure 38................................................................................................................................................................ 25
Updated Figure 39 ............................................................................................................................................................... 26
Updated Figure 40 ............................................................................................................................................................... 27
添加了社区资源..................................................................................................................................................................... 39
Changes from Original (October 2014) to Revision A
Page
•
将器件状态从预览更新为生产数据.......................................................................................................................................... 1
2
Copyright © 2014–2019, Texas Instruments Incorporated
TPS1H100-Q1
www.ti.com.cn
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
5 Pin Configuration and Functions
PWP Package Version A
14-Pin HTSSOP
Top View
NC
GND
IN
1
2
3
4
5
6
7
14
13
12
11
10
9
ST
CL
DIAG_EN
NC
Thermal
Pad
NC
OUT
OUT
OUT
VS
VS
8
VS
Not to scale
PWP Package Version B
14-Pin HTSSOP
Top View
NC
GND
IN
1
2
3
4
5
6
7
14
13
12
CS
CL
DIAG_EN
NC
Thermal
Pad
NC
11
10
9
OUT
OUT
OUT
VS
VS
8
VS
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VER. A
VER. B
Programmable current-limit pin. Connect to device GND if external
current limit is not used.
CL
CS
13
—
12
13
14
12
O
O
I
Current-sense output. Leave floating if not used.
Enable and disable pin for diagnostic functions. Connect to device GND
if not used.
DIAG_EN
GND
2
3
2
3
—
I
Ground pin
IN
Input control for channel activation
NC
1, 4, 11
5, 6, 7
14
1, 4, 11
5, 6, 7
—
—
O
O
I
No-connect pin; leave floating.
OUT
Output, connected to load (NMOS source)
Open-drain diagnostic status output. Leave floating if not used.
Power supply; battery voltage
ST
VS
8, 9, 10
—
8, 9, 10
—
Thermal pad
—
Thermal pad. Connect to device GND or leave floating.
Copyright © 2014–2019, Texas Instruments Incorporated
3
TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)(3)
MIN
MAX
UNIT
V
Supply voltage(4), t < 400 ms
Reverse polarity voltage(5)
Continuous drain current
Reverse current on GND
Reverse current on GND, t < 120 s
Voltage on IN/DIAG_EN pin
Current on IN /DIAG_EN pin
Voltage on ST pin
48
–18
V
Internally limited
A
–50
–250
–0.3
–30
20
20
7
mA
mA
V
2
mA
V
–0.3
–30
7
Current on ST pin
10
2
mA
KHz
V
IN pin PWM frequency
Voltage on CL pin
–0.3
–2
7
Current on CL pin
30
6.5
30
70
125
150
150
mA
V
Voltage on CS pin
–2.7
–2
Current on CS pin
mA
mJ
°C
°C
°C
Inductive load switch-off energy dissipation, single pulse(6)
Operating ambient temperature
Operating junction temperature
Storage temperature, Tstg
–40
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Absolute negative voltage on these terminals is not to go below –0.3 V.
(4) Absolute maximum voltage, withstand 48-V load dump voltage for 400 ms.
(5) Reverse polarity condition: t < 60 s, reverse current < Irev1, GND pin 1-kΩ resistor in parallel with diode.
(6) Test condition: VS = 13.5 V, L = 8 mH, R = 0 Ω, TJ = 150°C. FR4 2s2p board, 2- × 70-μm Cu, 2- × 35-μm Cu. 600-mm2 thermal pad
copper area.
6.2 ESD Ratings
VALUE
±5000
±4000
±750
UNIT
Human body model (HBM) AEC-Q100 Classification Level H3A(1) VS, OUT, GND
Electrostatic
discharge
V(ESD)
Human body model (HBM) AEC-Q100 Classification Level H2(1)
Charged device model (CDM), per AEC Q100-011(2)
Other pins
V
(1) The human-body model is a 107-pF capacitor discharged through a 1.5-kΩ resistor into each terminal.
(2) The charged-device model is tested according to AEC_Q100-011C.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5
MAX
40
5
UNIT
VS
Operating voltage
V
V
Voltage on IN/DIAG_EN pin
Voltage on ST pin
0
0
5
V
Io,nom
TJ
Nominal DC load current
Operating junction temperature range
0
4
A
–40
150
°C
4
Copyright © 2014–2019, Texas Instruments Incorporated
TPS1H100-Q1
www.ti.com.cn
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
6.4 Thermal Information
TPS1H100-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
14 PINS
41
(2)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.7
25.1
0.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
24.8
2.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The thermal data is based on JEDEC standard high-K profile – JESD 51-7. The copper pad is soldered to the thermal land pattern. Also,
correct attachment procedure must be incorporated.
80
4-layer PCB
2-layer PCB
70
60
50
40
30
20
0
100
200
300
400
500
600
700
800
Copper Area (mm2)
D025
(1) 4-layer board: FR4 2s2p board, 2.8-mil copper (top/bottom), 1.4-mil copper (internal layers). 76.4- × 114.3- × 1.5-mm
board size.
(2) 2-layer board: FR4 2s0p board, 2.8-mil copper (top/bottom). 76.4- × 114.3- × 1.5-mm board size.
Figure 1. RθJA Value vs Copper Area
Copyright © 2014–2019, Texas Instruments Incorporated
5
TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
MAX UNIT
6.5 Electrical Characteristics
5 V < VS < 40 V; –40°C < TJ < 150°C unless otherwise specified
PARAMETER
OPERATING VOLTAGE
TEST CONDITIONS
MIN
TYP
VS,nom
Nominal operating voltage
5
40
5
V
V
RDS(on) value increases maximum 20%,
compared to 5 V, see RDS(on) parameter
VS,op
Extended operating voltage
3.5
VS,UVR
VS,UVF
VUV,hys
Undervoltage restart
VS rises up, VS > VS,UVR, device turn on
VS falls down, VS < VS,UVF, device shuts off
3.5
3
3.7
3.2
0.5
4
V
V
V
Undervoltage shutdown
3.5
Undervoltage shutdown, hysteresis
OPERATING CURRENT
VIN = 5 V, VDIAG_EN = 0 V, no load
5
mA
Inom Nominal operating current
VIN = 5 V, VDIAG_EN = 0 V, 10-Ω load
10 mA
VS = 13.5 V, VIN = VDIAG_EN = VCS = VCL
VOUTPUT = 0 V, TJ = 25°C
=
=
0.5
5
µA
µA
Ioff
Standby current
VS = 13.5 V, VIN = VDIAG_EN = VCS = VCL
VOUTPUT = 0 V, TJ = 125°C
Ioff,diag
toff,deg
Standby current with diagnostic enabled VIN = 0 V, VDIAG_EN = 5 V
1.2 mA
ms
IN from high to low, if deglitch time > toff,deg
,
Standby mode deglitch time(1)
2
enters into standby mode.
VS = 13.5 V, VIN = VOUTPUT = 0, TJ = 25°C
0.5
3
µA
µA
Ileak,out
Off-state output leakage current
VS = 13.5 V, VIN = VOUTPUT = 0, TJ = 125°C
POWER STAGE
VS > 5 V, TJ = 25°C
VS > 5 V, TJ = 150°C
VS = 3.5 V, TJ = 25°C
80
100 mΩ
166 mΩ
120 mΩ
RDS-ON
On-state resistance
Ilim,nom
Internal current limit
7
13
A
A
Internal current limit, thermal cycling condition
5
External current limit, thermal cycling
condition; Percentage of current limit set
value
Ilim,tsd
Current limit during thermal shutdown
50%
Clamp drain-to-source voltage internally
clamped
VDS
50
70
V
OUTPUT DIODE CHARACTERISTICS
VF
Drain-to-source diode voltage
VIN = 0, IOUT = −0.2 A
0.7
4
V
A
t < 60 s, VS = 13.5 V, GND pin 1-kΩ resistor
in parallel with diode. TJ = 25°C. See Irev1 test
condition (Figure 6).
Continuous reverse current when
reverse polarity(2)
Irev1
Continuous reverse current when
VOUT > VS + Vdiode
t < 60 s, VS = 13.5 V. TJ = 25°C. See Irev2
test condition (Figure 7).
Irev2
2
A
(2)
LOGIC INPUT (IN AND DIAG_EN)
Vlogic,h Input or DIAG_EN high-level voltage
Vlogic,l
Vlogic,hys
Rpd,in
2
V
V
Input or DIAG_EN low-level voltage
Input or DIAG_EN hysteresis voltage
Input pulldown resistor
0.8
250
500
150
mV
kΩ
kΩ
Rpd,diag
Diag pulldown resistor
(1) Value is specified by design, not subject to production test.
(2) Value is based on the minimum value of the 10 pcs/3 lots samples.
6
Copyright © 2014–2019, Texas Instruments Incorporated
TPS1H100-Q1
www.ti.com.cn
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
Electrical Characteristics (continued)
5 V < VS < 40 V; –40°C < TJ < 150°C unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIAGNOSTICS
Iloss,gnd
Vol,off
Iol,off
tol,off
Loss-of-ground output leakage current
100
2.6
µA
V
Open-load detection threshold in off-
state
VIN = 0 V, When VS – VOUT < Vol,off, duration
longer than tol,off. Open load detected.
1.4
1.8
Off-state output sink current with open
load
VIN = 0 V, VS = VOUT = 13.5 V, TJ = 125°C.
–50
µA
µs
Open-load detection-threshold deglitch VIN = 0 V, When VS – VOUT < Vol,off, duration
time in off state
600
6
longer than tol,off. Open load detected.
VIN = 5 V, when IOUT < Iol,on, duration longer
than tol,on. Open load detected.
Version A only
Open-load detection threshold in on
state
Iol,on
2
10 mA
µs
VIN = 5 V, when IOUT < Iol,on, duration longer
than tol,on. Open load detected.
Version A only
Open-load detection-threshold deglitch
time in on-state
tol,on
700
IST = 2 mA
Version A only
VST
Status low output voltage
0.4
V
TSD
Thermal shutdown threshold
175
155
60
TSD,rst
Tsw
Thermal shutdown status reset
Thermal swing shutdown threshold
°C
Hysteresis for resetting the thermal
shutdown and swing
Thys
10
CURRENT SENSE (VERSION B) AND CURRENT LIMIT
K
Current sense current ratio
Current limit current ratio
500
KCL
2000
I
I
I
I
I
I
I
load ≥ 5 mA
load ≥ 25 mA
load ≥ 50 mA
load ≥ 0.1 A
load ≥ 1 A
–80
–10
–7
80
10
7
dK/K
Current-sense accuracy
%
%
–5
5
–3
3
limit ≥ 0.5 A
limit ≥ 1.6 A
–20
–14
0
20
14
4
dKCL/KCL
External current-limit accuracy(3)(4)
VCS,lin
IOUT,lin
Linear current sense voltage range(1)
Linear output current range(1)
V
V
V
S ≥ 5 V
V
A
S ≥ 5 V, VCS,lin ≤ 4 V
S ≥ 7 V
0
4
4.3
4.75
4.9
VCS,H
Current-sense fault high voltage
V
Min(VS
0.8, 4.3)
–
VS ≥ 5 V
4.9
ICS,H
Current sense fault condition current
Current limit internal threshold voltage(1)
VCS = 4.3 V, VS > 7 V
10
mA
V
VCL,th
1.233
VIN = 5 V, Rload = 10 Ω, VDIAG_EN = 0 V, TJ =
125°C
1
1
µA
µA
Current sense leakage current in
disabled mode
ICS,leak
VIN = 0 V, VDIAG_EN = 0 V, TJ = 125°C
(3) External current-limit accuracy is only applicable to overload conditions greater than 1.5× the current-limit setting.
(4) External current-limit setting is recommended to be higher than 500 mA.
Copyright © 2014–2019, Texas Instruments Incorporated
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TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
MAX UNIT
6.6 Timing Requirements – Current Sense Characteristics(1)
MIN NOM
CS settling time
from DIAG disabled value.
VIN = 5 V, Iload ≥ 5 mA. VDIAG_EN from 5 to 0 V. CS to 10% of sense
tCS,off1
tCS,on1
10
10
µs
µs
CS settling time
from DIAG enabled value.
VIN = 5 V, Iload ≥ 5 mA. VDIAG_EN from 0 to 5 V. CS to 90% of sense
VDIAG_EN = 5 V, Iload ≥ 5 mA. IN from 5 to 0 V. CS to 10% of sense
value.
10
180
150
µs
µs
µs
CS settling time
from IN falling edge
tCS,off2
VDIAG_EN = 5 V, Iload ≥ 5 mA. IN from 5 to 0 V. Current limit triggered.
CS settling time
from IN rising edge
VVS = 13.5 V, VDIAG_EN = 5 V, Iload ≥ 100 mA. VIN from 0 to 5 V. CS to
90% of sense value.
tCS,on2
(1) Value specified by design, not subject to production test.
In
Iout
Diag-En
CS
Tcs, on2
Tcs, off1
Tcs, on1 Tcs, off2
Figure 2. CS Delay Characteristics
Open
Load
Open Load
Vcs,H
In
CS
ST
Tol,off
Tol,on
Tol,off
Figure 3. Open-Load Blanking Time Characteristics
VS
IS
IN
IIN
ST
IST
DIAG_EN
OUT
IDIAG
IOUT
CL
ICL
GND
CS
ICS
Figure 4. Pin Current and Voltage Conventions
8
Copyright © 2014–2019, Texas Instruments Incorporated
TPS1H100-Q1
www.ti.com.cn
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
6.7 Switching Characteristics
VVS = 13.5 V, Rload = 10 Ω, over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
Turn-on delay time
Turn-off delay time
Slew rate on
TEST CONDITIONS
IN rising edge to VOUT = 10%, DIAG_EN high
IN falling edge to VOUT = 90%, DIAG_EN high
VOUT = 10% to 90%, DIAG_EN high
MIN
20
TYP
MAX
50
UNIT
µs
td,ON
td,OFF
dV/dtON
20
50
µs
0.1
0.5
V/µs
V/µs
V/µs
dV/dtOFF Slew rate off
Slew rate on and off matching
VOUT = 90% to 10%, DIAG_EN high
0.1
0.5
–0.15
0.15
(1) Value specified by design, not subject to production test.
In
90%
90%
Vout
10%
10%
Td,ON dV/dtON
Td,OFF dV/dtOFF
Figure 5. Switching Characteristics Diagram
Copyright © 2014–2019, Texas Instruments Incorporated
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TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
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DRAIN
Output
Clamp
SOURCE
Load
GND
VBAT
Rgnd
Dgnd
Figure 6. Irev1 Test Condition
DRAIN
Output
Clamp
VBAT
Load
SOURCE
GND
Rgnd
Dgnd
Figure 7. Irev2 Test Condition
10
Copyright © 2014–2019, Texas Instruments Incorporated
TPS1H100-Q1
www.ti.com.cn
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
6.8 Typical Characteristics
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
4
3.8
3.6
3.4
3.2
3
10
8
Vs,uvr
Vs,uvf
Inom(no load)
Inom(10-O load)
6
4
2
0
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
D001
D002
Figure 8. VVS,UVR and VVS,UVF
Figure 9. Inom With No Load and 10-Ω Load
0.3
0.25
0.2
1.2
1
Ioff
Ileak,out
0.8
0.6
0.4
0.2
0
0.15
0.1
0.05
0
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
D003
D004
Figure 10. Ioff and Ileak,out
Figure 11. Ioff,diag
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
Vlogic,h
Vlogic,l
0.8
0.6
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
D005
D006
Figure 12. Vlogic,h and Vlogic,l
Figure 13. VF
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Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
65
60
55
50
130
115
100
85
Rdson_VS_3P5V
Rdson_VS_5V
Rdson_VS_13P5
Rdson_VS_40V
70
55
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
-15
-15
-15
10
35 60
Temperature (°C)
85
110 125
D007
D008
Figure 14. VDS, clamp
Figure 15. RDSON
11
45
40
35
30
25
20
10.5
10
9.5
TD_On
TD_Off
9
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
10
35 60
Temperature (°C)
85
110 125
D009
D010
Figure 16. Ilim,nom
Figure 17. TDon and TDoff
0.4
0.38
0.36
0.34
0.32
0.3
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
dV/dtON
dV/dtOFF
-40
-15
10
35 60
Temperature (°C)
85
110 125
-40
10
35 60
Temperature (°C)
85
110 125
D011
D012
Figure 18. dV/dtON and dV/dtOFF
Figure 19. VCS,h
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Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
1.95
9
8
7
6
5
1.9
1.85
1.8
1.75
1.7
-40
-15
-10
-10
10
35 60
Temperature (°C)
85
110 125
-40
-15
10
35 60
Temperature (°C)
85
110 125
D013
D014
Figure 20. Vol,off
Figure 21. Iol,on
20%
10%
8%
15%
10%
5%
6%
4%
2%
0
0
-2%
-4%
-6%
-8%
-10%
-5%
-10%
-15%
-20%
-40
20
50
Temperature (°C)
80
110 125
-40
-10
20 50
Temperature (°C)
80
110 125
D015
D017
Figure 22. KCS = 5 mA, 13.5 V
Figure 23. KCS = 25 mA, 13.5 V
10%
8%
10%
8%
6%
6%
4%
4%
2%
2%
0
0
-2%
-4%
-6%
-8%
-10%
-2%
-4%
-6%
-8%
-10%
-40
20
50
Temperature (°C)
80
110 125
-40
-10
20 50
Temperature (°C)
80
110 125
D019
D016
Figure 24. KCS = 50 mA, 13.5 V
Figure 25. KCS = 100 mA, 13.5 V
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Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVS = 13.5 V if not specified.
10%
10%
8%
8%
6%
6%
4%
4%
2%
2%
0
0
-2%
-4%
-6%
-8%
-10%
-2%
-4%
-6%
-8%
-10%
-40
-10
20 50
Temperature (°C)
80
110 125
-40
-10
20 50
Temperature (°C)
80
110 125
D018
D020
Figure 26. KCS = 1 A, 13.5 V
Figure 27. KCL = 0.5 A, 13.5 V
10%
8%
6%
4%
2%
0
-2%
-4%
-6%
-8%
-10%
-40
-10
20 50
Temperature (°C)
80
110 125
D021
Figure 28. KCL = 1.6 A, 13.5 V
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7 Detailed Description
7.1 Overview
The TPS1H100-Q1 is a single-channel, fully-protected, high-side power switch with an integrated NMOS power
FET and charge pump. Full diagnostics and high-accuracy current-sense features enable intelligent control of the
load. A programmable current-limit function greatly improves the reliability of the whole system. The device
diagnostic reporting has two versions to support both digital status and analog current-sense output, both of
which can be set to the high-impedance state when diagnostics are disabled, for multiplexing the MCU analog or
digital interface among devices.
For version A, the digital status report is implemented with an open-drain structure. When a fault condition
occurs, it pulls down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply level.
For version B, high-accuracy current sensing allows a better real-time monitoring effect and more-accurate
diagnostics without further calibration. A current mirror is used to source 1 / K of the load current, which is
reflected as voltage on the CS pin. K is a constant value across the temperature and supply voltage. The current-
sensing function operates normally within a wide linear region from 0 to 4 V. The CS pin can also report a fault
by pulling up the voltage of VCS,h
.
The external high-accuracy current limit allows setting the current limit value by application. It highly improves the
reliability of the system by clamping the inrush current effectively under start-up or short-circuit conditions. Also, it
can save system costs by reducing PCB trace, connector size, and the preceding power-stage capacity. An
internal current limit is also implemented in this device. The lower value of the external or internal current-limit
value is applied.
An active drain and source voltage clamp is built in to address switching off the energy of inductive loads, such
as relays, solenoids, pumps, motors, and so forth. During the inductive switching-off cycle, both the energy of the
power supply (EBAT) and the load (ELOAD) are dissipated on the high-side power switch itself. With the benefits of
process technology and excellent IC layout, the TPS1H100-Q1 device can achieve excellent power dissipation
capacity, which can help save the external free-wheeling circuitry in most cases. See Inductive-Load Switching-
Off Clamp for more details.
Short-circuit reliability is critical for smart high-side power-switch devices. The standard of AEC-Q100-012 is to
determine the reliability of the devices when operating in a continuous short-circuit condition. Different grade
levels are specified according to the pass cycles. This device is qualified with the highest level, Grade A, 1
million times short-to-GND certification.
The TPS1H100-Q1 device can be used as a high-side power switch for a wide variety of resistive, inductive, and
capacitive loads, including the low-wattage bulbs, LEDs, relays, solenoids, and heaters.
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7.2 Functional Block Diagram
DRAIN (VS)
Internal LDO
Internal
Reference
IN
Charge Pump
Gate Driver
VDS Clamp
DIAG_EN
Open Load
Detection
ST
Diagnostics
and Protection
Current Limit
CL
SOURCE(OUT)
Thermal
Monitor
Current Sense
CS
GND
7.3 Feature Description
7.3.1 Accurate Current Sense
For version B, the high-accuracy current-sense function is internally implemented, which allows a better real-time
monitoring effect and more-accurate diagnostics without further calibration. A current mirror is used to source
1 / K of the load current, flowing out to the external resistor between the CS pin and GND, and reflected as
voltage on the CS pin.
K is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage. Each device was internally calibrated while in production, so post-calibration by users is not
required in most cases.
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Feature Description (continued)
4 A
1 A
dK/K = 3%
100 mA
dK/K = 5%
50 mA
dK/K = 7%
25 mA
dK/K = 10%
5 mA
dK/K = 80%
0 A
Figure 29. Current-Sense Accuracy
Ensure the CS voltage is in the linear region (0 to 4 V) during normal operation. Calculate RCS with Equation 1.
VCS VCS ì K
RCS
=
=
ICS
Iout
(1)
Also, when a fault condition occurs, CS works as a diagnostics report pin. When an open load or short to battery
occurs in the on-state, VCS almost equals 0. When current limit, thermal shutdown/swing, open load, or short to
battery in the off-state occurs, the voltage is pulled up to VCS,h. Figure 30 shows a typical current-sense voltage
according to the operating conditions, including fault conditions.
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Feature Description (continued)
Current Sense
Voltage
Vcs,H
ADC Full Scale
Range
Max Normal
Operating Current
Open Load Current
Operating
Range
On-state:
open load/short to battery
On-state: Current limit, thermal fault
Off-state: Open load/ short to battery
Over
current
Normal
Figure 30. Voltage Indication on the Current-Sense Pin
VBAT
VS
Iout/K
Iout/Kcl
CURRENT
CLAMP
t
Iout
Vcs,H
FAULT
+
CS
OUT
CL
Vcl,th
Rcs
RCL
Figure 31. Current-Sense and Current-Limit Block Diagram
7.3.2 Programmable Current Limit
A high-accuracy current limit allows higher reliability, which protects the power supply during short circuit or
power up. Also, it can save system costs by reducing PCB traces, connector size, and the capacity of the
preceding power stage.
Current limit offers protection from overstressing to the load and integrated power FET. Current limit holds the
current at the set value, and pulls up the CS pin to VCS,h as a diagnostic report. The two current-limit thresholds
are:
•
External programmable current limit -- An external resistor is used to convert a proportional load current into a
voltage, which is compared with an internal reference voltage, Vth,cl. When the voltage on the CL pin exceeds
Vth.cl, a closed loop steps in immediately. VGS voltage regulates accordingly, leading to the Vds voltage
regulation. When the closed loop is set up, the current is clamped at the set value. The external
programmable current limit provides the capability to set the current-limit value by application.
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Feature Description (continued)
•
Internal current limit -- The internal current limit is fixed and typically 10 A. To use the internal current limit for
large-current applications, tie the CL pin directly to the device GND.
Both the internal current limit (Ilim,nom) and external programmable current limit are always active when VVS is
powered and IN is high. The lower one (of Ilim,nom and the external programmable current limit) is applied as the
actual current limit.
Note that if a GND network is used (which leads to the level shift between the device GND and board GND), the
CL pin must be connected with device GND. Calculate RCL with Equation 2.
VCL,th
VCL,th ì KCL
Iout
ICL
=
=
ç RCL =
RCL
KCL
Iout
(2)
For better protection from a hard short-to-GND condition (when VS and input are high and a short to GND
happens suddenly), an open-loop fast-response behavior is set to turn off the channel, before the current-limit
closed loop is set up. The open-loop response time is around 1 µs. With this fast response, the device can
achieve better inrush-suppression performance.
7.3.3 Inductive-Load Switching-Off Clamp
When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance
characteristics. The power FET may break down if the voltage is not clamped during the current-decay period. To
protect the power FET in this situation, internally clamp the drain-to-source voltage, namely VDS,clamp, the clamp
diode between the drain and gate.
VDS,clamp = VBAT œ VOUT
(3)
During the current-decay period (TDECAY), the power FET is turned on for inductance-energy dissipation. Both the
energy of the power supply (EBAT) and the load (ELOAD) are dissipated on the high-side power switch itself, which
is called EHSD. If resistance is in series with inductance, some of the load energy is dissipated in the resistance.
EHSD = EBAT + ELOAD = EBAT +EL œ ER
(4)
From the high-side power switch’s view, EHSD equals the integration value during the current-decay period.
TDECAY
EHSD
=
VDS,clamp ì IOUT(t)dt
—
0
(5)
(6)
(7)
≈
’
R ì IOUT(MAX) + VOUT
L
∆
∆
«
÷
÷
◊
TDECAY
=
ì ln
R
VOUT
»
ÿ
Ÿ
VBAT + VOUT
≈ R ì IOUT(MAX) + VOUT
’
…
ì R ì IOUT(MAX) œ VOUT ln
EHSD = L ì
∆
÷
÷
◊
R2
∆
VOUT
…
Ÿ
⁄
«
When R approximately equals 0, EHSD can be given simply as:
VBAT + VOUT
1
EHSD
=
ì L ì I2
OUT(MAX)
R2
(8)
2
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Feature Description (continued)
VBAT
DRAIN
IN
L
-
-
SOURCE
+
GND
Figure 32. Driving Inductive Load
INPUT
VBAT
VOUT
IOUT
VDS, clamp
EHSD
tDECAY
Figure 33. Inductive-Load Switching-Off Diagram
As discussed previously, when switching off, battery energy and load energy are dissipated on the high-side
power switch, which leads to the large thermal variation. For each high-side power switch, the upper limit of the
maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board
dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test
condition: VVS = 13.5 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2- × 70-μm copper, 2- ×
35-μm copper, thermal pad copper area 600 mm2.
For one dedicated inductance, see Figure 34. If the maximum switching-off current is lower than the current
value shown on the curve, the internal clamp function can be used for the demagnetization energy dissipation. If
not, external free-wheeling circuitry is necessary for device protection.
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Feature Description (continued)
12
11
10
9
TA = 25°C
TA = 125°C
8
7
6
5
4
3
2
1
0
0.1 0.2
0.5
1
2 3 4 5 7 10 20 30 50 100 200 400
Inductance Range (mH)
D026
Figure 34. Maximum Current vs Inductance Range
7.3.4 Full Protections and Diagnostics
Table 1 is when DIAG_EN enabled. When DIAG_EN is low, current sense or ST is disabled accordingly. The
output is in high-impedance mode. Refer to Table 2 for details.
Table 1. Fault Table
ST
CS
(Version B)
CONDITIONS
IN
OUT
CRITERION
Diagnostics Recovery
(Version A)
L
H
H
L
H
L
H
H
L
0
Normal
In linear region
VCS,h
Short to GND
Current limit triggered.
AUTO
AUTO
AUTO
Open load(1)
Short to battery
Reverse polarity
Version A: Output current < Iol,on
Version B: Judged by users
H
L
H
H
L (deglitch)
Almost 0
VCS,h (deglitch)
VCS,h
VVS – VOUT < Vol,off
TSD triggered
Tsw triggered
L (deglitch)
Recovery when
temp < TSD,rst
Thermal shutdown
Thermal swing
H
H
L
L
VCS,h
AUTO
(1) Need external pullup resistor during off-state
Table 2. DIAG_EN Logic Table
DIAG_EN IN Condition
Protections and Diagnostics
See Table 1
See Table 1
ON
HIGH
OFF
Diagnostics disabled, protection normal
CS or ST is high Impedance
ON
LOW
Diagnostics disabled, no protections
CS or ST is high impedance
OFF
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7.3.4.1 Short-to-GND and Overload Detection
In the on state, the short-to-GND fault is reported as the low status output or VCS,h on CS, when a current limit is
triggered. The lower one of the internal and external set values is applied for the actual current limit. It is in auto-
recovery when the fault condition is cleared. If not cleared, thermal shutdown triggers to protect the power FET.
7.3.4.2 Open-Load Detection
In the on state for version A, if the current flowing through the output is less than Iol,on, the device recognizes an
open-load fault. For version B, faults are diagnosed by reading the voltage on the CS pin and judged by the user.
A benefit of high-accuracy current sense down to a verylow current range, this device can achieve a very low
open-load detection threshold, which correspondingly expands the normal operation region. TI suggests 10 mA
as the upper limit for the open-load detection threshold and 25 mA as the lower limit for the normal operation
current. In Figure 35, the recommended open-load detection region is shown as the dark-shaded region and the
light-shaded region is for normal operation. As a guideline, do not overlap these two regions.
Normal Operation
Region
27.5 mA
10% Tolerance
25 mA
22.5 mA
18 mA
80% Tolerance
On State, Open Load/
Short to Battery
10 mA
2 mA
Figure 35. On-State Open-Load Detection and Normal-Operation Diagram
In the off state, if a load is connected, the output voltage is pulled to 0 V. In the case of an open load, the output
voltage is close to the supply voltage, VS – VOUT < Vol,off. For version A, the ST pin goes low to indicate the fault
to the MCU. For version B, the CS pin is pulled up to VCS,h. There is always a leakage current Iol,off present on
the output, due to the internal logic control path or external humidity, corrosion, and so forth. Thus, TI
recommends an external pullup resistor to offset the leakage current. This pullup current should be less than the
output load current to avoid false detection in the normal operation mode. To reduce the standby current, TI
recommends always to use a switch in series with? the pullup resistor. TI recommends Rpu ≤ 15 kΩ.
VBAT
VS
OPEN LOAD
Vol,off
ST/CS
FAULT
Rpu
OUT
Figure 36. Open-Load Detection Circuit
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7.3.4.3 Short-to-Battery Detection
Short-to-battery detectioin has the same detection mechanism and behavior as open-load detection, both in the
on-state and off-state. See the fault truth table, Table 1, for more details. In the on-state, the reverse current
flows through the FET instead of the body diode, leading to less power dissipation. Thus, the worst case for off-
state is when reverse current occurs. In the off-state, if VOUT – VVS < VF, short to battery can be detected. (VF is
the body diode forward voltage and typically 0.7 V.) However, the reverse current does not occur. If VOUT – VVS
>
VF, short to battery can be detected, and the reverse current should be lower than Irev2 to ensure the survival of
the device. TI recommends switching on the input for lower power dissipation or the reverse block circuitry for the
supply. See Reverse Current Protection for more external protection circuitry information.
7.3.4.4 Reverse-Polarity Detection
Reverse-polarity detection has the same detection mechanism and behavior as open-load detection, both in the
on-state and off-state. See the fault truth table, Table 1, for more details. In the on-state, the reverse current
flows through the FET instead of the body diode, leading to less power dissipation. Thus, the worst case off-state
is when reverse current occurs. In off-state, the reverse current should be lower than Irev1 to ensure the survival
of the device. See Reverse Current Protection for more external protection circuitry information.
7.3.4.5 Thermal Protection Behavior
Both the absolute temperature thermal shutdown and the dynamic temperature thermal swing diagnostic and
protection are built into the device to increase the maximum reliability of the power FET. Thermal swing is active
when the temperature of the power FET is increasing sharply, that is ΔT = TDMOS – TLogic > Tsw, then the output is
shut down, and the ST pin goes low, or the CS pin is pulled up to VCS,h. It auto-recovers and clears the fault
signal until ΔT = TDMOS – TLogic < Tsw – Thys. Thermal swing function improves device reliability against repetitive
fast thermal variation, as shown in Figure 37. Multiple thermal swings are triggered before thermal shutdown
happens. Thermal shutdown is active when absolute temperature T > TSD. When active, the output is shut down,
and the ST pin goes low, or the CS pin is pulled up to VCS,h. The output is auto-recovered when T < TSD – Thys
;
the current limit is reduced to Ilim,tsd, or half of the programmable current limit value, to avoid repeated thermal
shutdown. However, the thermal shutdown fault signal and half-current limit value are not cleared until the
junction temperature decreases to less than TSD,rst
.
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In
TSD
TSD
Thys
Thys
TSD,r
st
TSD,rst
Thys
Tsw
Junction
Temperature
Ilim
1/2Ilim
Output
Current
Vcs,H
VCS
ST
Figure 37. Thermal Behavior
7.3.4.6 UVLO Protection
The device monitors the supply voltage VVS to prevent unpredicted behaviors in the event that the supply voltage
is too low. When the supply voltage falls down to VVS,UVF, the output stage is shut down automatically. When the
supply rises up to VVS,UVR, the device turns on.
24
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7.3.4.7 Loss of GND Protection
When loss of GND occurs, output is turned off regardless of whether the input signal is high or low.
Case 1 (loss of device GND): Loss of GND protection is active when the Tab, IC_GND, and current limit GND are
one trace connected to the board GND, as shown in Figure 38. Tab floating is also a choice.
VBAT
DRAIN
IN
5V
ST
Version A
DIAG_EN
SOURCE
MCU
CS
Version B
Load
NC
(Floating)
CL
Tab
GND
Figure 38. Loss of Device GND
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Case 2 (loss of module GND): When the whole ECU module GND is lost, protections are also active. At this
condition, the load GND remains connected.
VBAT
DRAIN
IN
5V
ST
Version A
DIAG_EN
SOURCE
MCU
CS
Version B
Load
NC
(Floating)
CL
Tab
GND
Figure 39. Loss of Module GND
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7.3.4.8 Loss of Power Supply Protection
When loss of supply occurs, output is turned off regardless of whether the input is high or low. For a resistive or
capacitive load, loss-o-supply protection is easy to achieve due to no more power. The worst case is a charged
inductive load. In this case, the current is driven from all of the IOs to maintain the inductance output loop. TI
recommends either the MCU serial resistor plus the GND network (diode and resistor in parallel) or external free-
wheeling circuitry.
VBAT
IN
DRAIN
5V
ST
DIAG_EN
CS
SOURCE
MCU
D
L
NC
(Floating)
CL
Z
GND
Rgnd
Dgnd
Figure 40. Loss of Battery
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www.ti.com.cn
7.3.4.9 Reverse Current Protection
Method 1: Block diode connected with VS. Both the device and load are protected when in reverse polarity.
VBAT
DRAIN
IN
Output
Clamp
Gate drive
and Clamp
STATUS
Version A
Logic and
Protection
DIAG_EN
SOURCE
CS
Version B
Current Sense/
Current Limit
Load
NC
(Floating)
CURRENT LIMIT
GND
Figure 41. Reverse Protection With Block Diode
28
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ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
Method 2 (GND network protection): Only the high-side device is protected under this connection. The load
reverse loop is limited by the load itself. Note when reverse polarity happens, the continuous reverse current
through the power FET should be less than Irev. Of the three types of ground pin networks, TI strongly
recommends type 3 (the resistor and diode in parallel). No matter what types of connection are between the
device GND and the board GND, if a GND voltage shift happens, ensure the following proper connections for the
normal operation:
•
•
Leave the NC pin floating or connect to the device GND. TI recommends to leave floating.
Connect the current limit programmable resistor to the device GND.
DRAIN
IN
Output
Clamp
Gate drive
and Clamp
STATUS
Version A
Logic and
Protection
DIAG_EN
SOURCE
CS
Version B
Current Sense/
Current Limit
Load
NC
(Floating)
CURRENT LIMIT
GND
VBAT
Rgnd
Dgnd
GND
Network
Figure 42. Reverse Protection With GND Network
•
Type 1 (resistor): The higher resistor value contributes to a better current limit effect when the reverse
battery or negative ISO pulses. However, it leads to higher GND shift during normal operation mode. Also,
consider the resistor’s power dissipation.
VGNDshift
RGND
Ç
Inom
œV
(9)
(
)
CC
RGND
í
œI
GND
where
•
VGNDshift is the maximum value for the GND shift, determined by the HSD and microcontroller. TI suggests a
value ≤ 0.6 V.
•
•
•
Inom is the nominal operating current.
–VCC is the maximum reverse voltage seen on the battery line.
–IGND is the maximum reverse current the ground pin can withstand, which is available in the Absolute
Maximum Ratings.
(10)
If multiple high-side power switches are used, the resistor can be shared among devices.
Type 2 (diode): A diode is needed to block the reverse voltage, which also brings a ground shift (≈ 600 mV).
•
Copyright © 2014–2019, Texas Instruments Incorporated
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ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
However, an inductive load is not acceptable to avoid an abnormal status when switching off.
•
Type 3 (resistor and diode in parallel (recommended)): A peak negative spike may occur when the
inductive load is switching off, which may damage the HSD or the diode. So, TI recommends a resistor in
parallel with the diode when driving an inductive load. The recommended selection are 1-kΩ resistor in
parallel with an IF > 100-mA diode. If multiple high-side switches are used, the resistor and diode can be
shared among devices.
7.3.4.10 Protection for MCU I/Os
In many conditions, such as the negative ISO pulse, or the loss of battery with an inductive load, a negative
potential on the device GND pin may damage the MCU I/O pins [more likely, the internal circuitry connected to
the pins]. Therefore, the serial resistors between MCU and HSD are required.
Also, for proper protection against loss of GND, TI recommends 4.7 kΩ when using 3.3-V MCU I/Os; 10 kΩ is for
5-V applications.
VBAT
DRAIN
IN
Output
Clamp
Gate drive
and Clamp
5V
STATUS
Version A
Logic and
Protection
DIAG_EN
SOURCE
MCU
CS
Version B
Current Sense/
Current Limit
Load
NC
(Floating)
CURRENT
LIMIT
GND
Rgnd
Dgnd
Figure 43. MCU IO Protections
7.3.5 Diagnostic Enable Function
The diagnostic enable pin, DIAG_EN, offers multiplexing of the microcontroller diagnostic input for current sense
or digital status, by sharing the same sense resistor and ADC line or I/O port among multiple devices.
30
Copyright © 2014–2019, Texas Instruments Incorporated
TPS1H100-Q1
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ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
In addition, during the output-off period, the diagnostic disable function lowers the current consumption for the
standby condition. The three working modes in the device are normal mode, standby mode, and standby mode
with diagnostic. If off-state power saving is required in the system, the standby current is <500 nA with DIAG_EN
low. If the off-state diagnostic is required in the system, the typical standby current is around 1 mA with
DIAG_EN high.
7.4 Device Functional Modes
7.4.1 Working Mode
The three working modes in the device are normal mode, standby mode, and standby mode with diagnostic. If an
off-state power saving is required in the system, the standby current is less than 500 nA with DIAG_EN low. If an
off-state diagnostic is required in the system, the typical standby current is around 1 mA with DIAG_EN high.
Note that to enter standby mode requires IN low and t > toff,deg. toff,deg is the standby-mode deglitch time, which is
used to avoid false triggering. Figure 44 shows a work-mode state-machine state diagram.
Standby Mode
(IN low, DIAG low)
DIAG_EN low and
IN high to low and
t > toff,deg
DIAG_EN
high to low
IN low to high
DIAG_EN
low to high
IN high to low and
DIAG_EN high and
t > toff,deg
Standby mode
with diagnostic
(IN low, DIAG high)
Normal Mode
(IN high)
IN low to high
Figure 44. Work-Mode State Machine
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31
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ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following discussion notes how to implement the device to distinguish the different fault modes and
implement a ? transient-pulse immunity test.
In some applications, open load, short to battery, and short to GND must be distinguished from each other. This
requires two steps.
8.2 Typical Application
Figure 45 shows an example of how to design the external circuitry parameters.
VBAT
RSER
DRAIN
IN
Output
Clamp
Gate drive
and Clamp
5V
ST
Version A
Logic and
Protection
DIAG_EN
SOURCE
MCU
RCS
CS
Version B
Current Sense/
Current Limit
Load
NC
(Floating)
CL
RCL
GND
Rgnd
Dgnd
GND Network
Figure 45. Typical Application Circuitry
32
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ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
Typical Application (continued)
8.2.1 Design Requirements
•
•
•
•
•
•
VS range from 9 V to 16 V
Nominal current of 2 A
Current sense for fault monitoring
Expected current limit value of 5 A
Full diagnostics with 5-V MCU
Reverse protection with GND network
8.2.2 Detailed Design Procedure
The RCS, VCS linear region is from 0 to 4 V. To keep the 2-A nominal current in the 0- to 3-V range, calculate the
RCS as in Equation 11. To achieve better current sense accuracy, a 1% accuracy or better resistor is preferred.
VCS VCS ì K
3 ì 500
RCS
=
=
=
= 750 W
ICS
IOUT
2
(11)
RCL, VCL,th is the current-limit internal threshold, 1.233 V. To set the programmable current limit value at 5 A,
calculate the RCL as in Equation 12.
Vcl,th ì KCL
1.233 ì 2000
RCL
=
=
= 493.2 W
IOUT
5
(12)
TI recommends RSER = 10 kΩ for 5-V MCU.
TI recommends a 1-kΩ resistor and 200-V, 0.2-A diode for the GND network.
8.2.2.1 Distinguishing of Different Fault Modes
Some applications require that open load, short to battery, and short to GND can be distinguished from each
other. This requires two steps:
1. In the on-state, for the current-sense version device (version B), on-state open load and short to battery are
recognized as an extremely-low voltage level on the current-sense pin, whereas short to GND is reported as
a pulled-up voltage VCS,h. Therefore, the user can find a short to GND (see Figure 46).
2. If reported as an on-state open-load or short-to-battery fault in the first step, turn off the input signal. In the
off-state, with an external pulldown resistor, open load and short to battery can be easily distinguished. When
the output pulls down, the short to battery is still reported as an off-state fault condition, whereas the open
load is ignored.
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TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
Typical Application (continued)
Current Sense
Voltage
Vcs,H
ADC Full Scale
Range
Max Normal
Operating Current
Open Load Current
Operating
Range
On-state: Current limit, thermal fault
Off-state: Open load/ short to battery
On-state:
open load/short to battery
Over
current
Normal
Figure 46. Step 1: Short-to-GND Detection in the On-State
VBAT
VS
OPEN LOAD
Vol,off
ST/CS
FAULT
OUT
Rpd
Figure 47. Step 2: Short-to-Battery Detection in the Off-State
8.2.2.2 AEC Q100-012 Test Grade A Certification
Short-circuit reliability is critical for smart high-side power switch devices. The AEC-Q100-012 standard is used to
determine the reliability of the devices when operating in a continuous short-circuit condition. Different grade
levels are specified according to the pass cycles. This device is qualified with the highest level, Grade A, 1
million times short-to-GND certification.
Three test modes are defined in the AEC Q100-012 standard. See Table 3 for cold repetitive short-circuit test –
long pulse, cold repetitive short-circuit test – short pulse, and hot repetitive short-circuit test.
34
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ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
Typical Application (continued)
Table 3. Tests
Test Items
Test Condition
–40°C, 10-ms pulse, cool down
Test Cycles
Cold repetitive short-circuit test – short pulse
Cold repetitive short-circuit test – long pulse
Hot repetitive short-circuit test
1M
–40°C, 300-ms pulse, cool down
25°C, continuous short
1M
1M
Different grade levels are specified according to the pass cycles. The TPS1H100-Q1 device gets the certification
of Grade A level, 1 million short-to-GND cycles, which is the highest test standard in the market.
Table 4. Grade Levels
Grade
Number of Cycles
>1000000
Lots,Samples Per Lot
Number of Fails
A
B
C
D
E
F
3, 10
3, 10
3, 10
3, 10
3, 10
3, 10
3, 10
3, 10
3, 10
0
0
0
0
0
0
0
0
0
>300000 to 1000000
>100000 to 300000
>30000 to 100000
>10000 to 30000
>3000 to 10000
>1000 to 3000
300 to 1000
G
H
O
<300
8.2.2.3 EMC Transient Disturbances Test
Due to the severe electrical conditions in the automotive environment, immunity capacity against electrical
transient disturbances is required, especially for a high-side power switch, which is connected directly to the
battery. Detailed test requirements are in accordance with the ISO 7637-2:2011 and ISO 16750-2:2010
standards. The TPS1H100-Q1 device is tested and certificated by a third-party organization.
Table 5. ISO 7637-2:2011(E) in 12-V System(1)(2)(3)(4)
Test Pulse Severity Level
and vs Accordingly
Minimum
Number of
Pulses or Test
Time
Burst-Cycle Pulse-
Repetition Time
Function
Performance
Status
Input
Resistance
(Ω)
Test
Item
Pulse
Duration (td)
Level
Vs/V
MIN
MAX
Classification
1
III
III
IV
IV
IV
–112
55
2 ms
50 µs
500 pulses
500 pulses
10 pulses
1h
0.5 s
0.2 s
e s
5 s
10
Status II
Status II
Status II
Status II
Status II
2a
2b
3a
3b
2
0 to 0.05
50
10
0.2 to 2 s
0.1 µs
0.5 s
5 s
–220
150
90 ms
90 ms
100 ms
100 ms
0.1 µs
1h
50
(1) Tested both under input low condition and high condition.
(2) Considering the worst test condition, it is tested without any filter capacitors in VS and VOUT
.
(3) GND pin network is a 1-kΩ resistor in parallel with a diode BAS21-7-F.
(4) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.
Table 6. ISO 16750-2:2010(E) Load Dump Test B in 12-V System(1)(2)(3)(4)(5)
Test Pulse Severity Level
and vs Accordingly
Minimum
Number of
Pulses or Test
Time
Burst Cycle/Pulse
Repetition Time
Function
Performance
Status
Input
Resistance
(Ω)
Test
Item
Pulse
Duration (td)
Level
Vs/V
MIN (s)
MAX (s)
Classification
Test B
45
40 to 400 ms
5 pulses
60
e
0.5 to 4
Status II
(1) Tested both under input low condition and high condition. [DIAG_EN, IN, and VS are all classified as inputs. Which one?
(2) Considering the worst test condition, the device is tested without any filter capacitors on VS and OUT.
(3) The GND pin network is a 1-kΩ resistor in parallel with a diode BAS21-7-F.
(4) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.
(5) Select a 45-V external suppressor.
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TPS1H100-Q1
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8.2.3 Application Curves
Figure 48 shows a test example of initial short-circuit inrush-current limit. Test conditions: VS = 13.5 V, input is
from low to high, load is short-to-GND or with a 470-µF capacitive load, external current limit is 2 A. CH1 is the
output current. CH3 is the input step.
Figure 49 shows a test example of a hard short-circuit inrush-current limit. Test conditions: VS= 13.5 V, input is
high, load is 5 µH + 100 mΩ, external current limit is 1 A. A short to GND suddenly happens.
Input Step
Fast loop response
1.8 A inrush
2 A inrush
Closed loop response
1 A inrush
Figure 49. Hard Short-to-GND Waveform
Figure 48. Initial Short-to-GND Waveform
36
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TPS1H100-Q1
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ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
9 Power Supply Recommendations
The device is qualified for both automotive and industrial applications. The normal power supply connection is a
12-V automotive system or 24-V industrial system. The supply voltage should be within the range specified in the
Recommended Operating Conditions.
10 Layout
10.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 150°C. If the output current is very high, the power
dissipation may be large. The HTSSOP package has good thermal impedance. However, the PCB layout is very
important. Good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability
of the device.
•
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the board opposite the
package.
•
•
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
10.2 Layout Example
10.2.1 Without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
14
NC
ST/CS
CL
1
2
3
4
5
6
7
13
GND
IN
DIAG_EN
12
11
Thermal
Pad
NC
NC
VS
VS
VS
10
OUT
OUT
OUT
9
8
Figure 50. Layout Without a GND Network
Copyright © 2014–2019, Texas Instruments Incorporated
37
TPS1H100-Q1
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
www.ti.com.cn
Layout Example (continued)
10.2.2 With a GND Network
With a GND network, tie the thermal pad with a single trace through the GND network to the board GND copper.
GND Network
14
NC
ST/CS
CL
1
3
4
5
6
7
13
GND
IN
DIAG_EN
12
11
Thermal
Pad
NC
NC
VS
VS
VS
10
OUT
OUT
OUT
9
8
Figure 51. Layout With a GND Network
10.3 Thermal Considerations
This device possesses thermal shutdown (TSD) circuitry as a protection from overheating. For continuous normal
operation, the junction temperature should not exceed the thermal-shutdown trip point. If the junction temperature
exceeds the thermal-shutdown trip point, the output turns off. When the junction temperature falls below the
thermal-shutdown trip point, the output turns on again.
Calculate the power dissipated by the device according to Equation 13.
PT = IOUT2 ì RDSON + VS ìInom
where
•
PT = Total power dissipation of the device
(13)
After determining the power dissipated by the device, calculate the junction temperature from the ambient
temperature and the device thermal impedance.
TJ = TA + RqJA ìPT
(14)
38
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TPS1H100-Q1
www.ti.com.cn
ZHCSDD8D –OCTOBER 2014–REVISED DECEMBER 2019
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2019, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS1H100AQPWPRQ1
TPS1H100BQPWPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
14
14
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
1H100AQ
1H100BQ
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS1H100AQPWPRQ1 HTSSOP PWP
TPS1H100BQPWPRQ1 HTSSOP PWP
14
14
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS1H100AQPWPRQ1
TPS1H100BQPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
14
14
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
www.ti.com
PACKAGE OUTLINE
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
12X 0.65
14
1
2X
5.1
4.9
3.9
NOTE 3
7
8
0.30
14X
0.19
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X (0.6)
NOTE 5
2X (0.4)
NOTE 5
THERMAL
PAD
7
8
0.25
1.2 MAX
GAGE PLANE
2.59
1.89
15
0.15
0.05
0.75
0.50
0 -8
A
20
1
14
DETAIL A
TYPICAL
2.6
1.9
4229706/A 06/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.6)
METAL COVERED
BY SOLDER MASK
SYMM
14X (1.5)
(1.2) TYP
14
14X (0.45)
1
(5)
NOTE 9
(R0.05) TYP
SYMM
(0.6)
15
(2.59)
12X (0.65)
7
8
(
0.2) TYP
VIA
SEE DETAILS
(1.1) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4229706/A 06/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.6)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
14X (1.5)
14X (0.45)
14
1
(R0.05) TYP
(2.59)
SYMM
15
BASED ON
0.125 THICK
STENCIL
12X (0.65)
7
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 12X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 2.90
2.60 X 2.59 (SHOWN)
2.37 X 2.36
0.125
0.15
0.175
2.20 X 2.19
4229706/A 06/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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