TPS1H200AQDGNRQ1 [TI]
具有可调节电流限制的 40V、200mΩ、汽车类单通道智能高侧开关 | DGN | 8 | -40 to 125;
| 型号： | TPS1H200AQDGNRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节电流限制的 40V、200mΩ、汽车类单通道智能高侧开关 | DGN | 8 | -40 to 125 开关 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总38页 (文件大小：3020K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS1H200A-Q1
ZHCSHN4D –FEBRUARY 2018 –REVISED SEPTEMBER 2021
TPS1H200A-Q1 40V 200mΩ 单通道智能高侧开关
• 诊断：
– 过载和接地短路检测
1 特性
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
– 开路负载和电池短路检测（开启或关闭状态下）
– 热关断和热振荡
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
2 应用
– 器件人体放电模型(HBM) 静电防护(ESD) 分类
等级H2
– 器件CDM ESD 分类等级C4B
• 提供功能安全
• 车身照明
• 信息娱乐系统
• 高级驾驶辅助系统(ADAS)
• 单通道高侧子模块开关
• 一般阻性、感性和容性负载
– 可帮助进行功能安全系统设计的文档
• 单通道200mω智能高侧开关
• 宽工作电压：3.4 V 至40 V
• 低于500nA 的超低待机电流
• 可调节电流限制（利用外部电阻器）
3 说明
TPS1H200A-Q1 器件是受到全面保护的单通道高侧电
源开关，具有集成式200mΩ NMOS 功率FET。
– ≥500mA 时为±15%
– ≥1.5A 时为±10%
• 可配置电流限制后的行为
– “保持”模式
可调节电流限制可通过限制浪涌或过载电流来提高系统
可靠性。高精度电流限制可增强过载保护，从而简化前
沿电源设计。除了电流限制之外，其他可配置特性还能
够在功能、成本和热耗散方面提供设计灵活性。
– “闭锁”模式（具有可调节的延迟时间）
– “自动重试”模式
• 支持独立操作（无需MCU）
• 保护：
该器件支持对数字状态输出进行全面诊断。在开启和关
闭状态下皆可进行开路负载检测。无论是否有 MCU，
该器件都能正常工作。独立模式允许隔离型系统使用此
器件。
– 接地短路和过载保护
– 热关断和热振荡
– 用于电感负载的负电压钳位
– 接地失效保护和失电保护
器件信息(1)
封装尺寸（标称值）
器件型号
封装
TPS1H200A-Q1
HVSSOP (8)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
3.5 œ 40 V
Supply Voltage
VS
Up to 40 V
IN
LED Strings Bulbs
Up to 40 V
DIAG_EN
Relays, Solenoids
FAULT
OUT
CL
Submodule
Cameras, Sensors
General Resistive Capacitive,
DELAY
Inductive Loads
自动重试模式下的电流限制保护
典型方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEE0
TPS1H200A-Q1
ZHCSHN4D –FEBRUARY 2018 –REVISED SEPTEMBER 2021
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Table of Contents
7.4 Device Functional Modes..........................................24
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Application.................................................... 25
9 Power Supply Recommendations................................27
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Documentation Support.......................................... 28
11.2 接收文档更新通知................................................... 28
11.3 支持资源..................................................................28
11.4 Trademarks............................................................. 28
11.5 Electrostatic Discharge Caution..............................28
11.6 术语表..................................................................... 28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (December 2019) to Revision D (September 2021)
Page
• Changed the nominal operating current (I(OP)) VDIAG_EN variable to "X" for do not care in the Electrical
Characteristics table........................................................................................................................................... 6
Changes from Revision B (December 2019) to Revision C (December 2019)
Page
• 向特性部分添加了“提供功能安全”................................................................................................................. 1
Changes from Revision A (April 2018) to Revision B (December 2019)
Page
• Changed the Logic high-level voltage from 2 V to 1.8 V in the Electrical Characteristics table..........................6
• Changed the IN and DIAG_EN from high to low in the Standby Mode section................................................24
Changes from Revision * (February 2018) to Revision A (April 2018)
Page
• 将数据表状态从“预告信息”更改为“生产数据”.............................................................................................1
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5 Pin Configuration and Functions
IN
DIAG_EN
FAULT
CL
1
2
3
4
8
7
6
5
VS
OUT
GND
DELAY
Thermal
Pad
Not to scale
图5-1. DGN PowerPAD™ Package 8-Pin HVSSOP With Exposed Thermal Pad Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
CL
NO.
4
O
I/O
I
Adjustable current limit. Connect to device GND if external current limit is not used.
Function configuration when current limit; internal pullup
Enable the diagnostic function
DELAY
DIAG_EN
FAULT
GND
5
2
3
O
Open-drain diagnostic status output. Leave floating if not used.
Ground
6
—
I
IN
1
Input control for output activation; internal pulldown
Output, source of the high-side switch, connected to the load
Power supply, drain for the high-side switch
OUT
7
O
I
VS
8
Thermal pad
Thermal pad. Connect to device GND or leave floating.
—
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1) (2)
MIN
—
MAX
UNIT
V
Supply voltage VS pin
t < 400 ms
42
Reverse polarity voltage (3)
t < 1 minute
t < 2 minutes
V
–36
–100
–0.3
–10
–0.3
–60
–0.3
–30
–0.3
—
—
250
VS
Current on GND
mA
V
Voltage on IN and DIAG_EN pins
Current on IN and DIAG_EN pins
Voltage on DELAY pin
mA
V
—
7
Current on DELAY pin
mA
V
—
7
Voltage on FAULT pin
Current on FAULT pin
10
7
mA
V
Voltage on CL pin
Current on CL pin
6
mA
V
Voltage on OUT pin
42
40
150
150
—
Inductive load switch-off energy dissipation single pulse(4)
Operating junction temperature, TJ
Storage temperature, Tstg
mJ
°C
°C
—
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to ground.
(3) Reverse polarity condition: VIN = 0 V, reverse current < IR(2), GND pin 1-kΩresistor in parallel with diode.
(4) Test condition: VVS = 13.5 V, L = 8 mH, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 × 35-μm Cu. 600 mm2 thermal pad copper
area.
6.2 ESD Ratings
VALUE
UNIT
All pins except VS, OUT,
and GND
±2000
Human-body model (HBM), per AEC
Q100-002(1)
V(ESD)
Electrostatic discharge
V
Pins VS, OUT, and GND
±3000
±750
Charged-device model (CDM), per AEC Q100-011
(1) AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
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6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
40
UNIT
V
VS
Operating voltage
4
0
Voltage on IN and DIAG_EN pins
Voltage on FAULT pin
40
V
0
5
V
Io,nom
TJ
Nominal DC load current
Operating junction temperature
0
2.5
150
A
°C
–40
6.4 Thermal Information
TPS1H200A-Q1
THERMAL METRIC(1)
DGN (HVSSOP)
UNIT
8 PINS
47.4
49.2
18.3
0.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
18.4
5.6
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
VVS(nom)
VVS(uvr)
VVS(uvf)
V(uv,hys)
Nominal operating voltage
Undervoltage restart
4
3.5
3
40
4
V
V
V
V
VVS rising
VVS falling
3.7
3.2
0.5
Undervoltage shutdown
3.4
Undervoltage shutdown, hysteresis
OPERATING CURRENT
VVS = 13.5 V, VIN = 5 V
VDIAG_EN = X V, IOUT = 0.5 A
ICL = 2 A
I(op) Nominal operating current
5
mA
µA
VVS = 13.5 V
VIN = VDIAG_EN = VCL = VOUT = 0 V
TJ = 25°C
0.5
I(off)
Standby current
VVS = 13.5 V
VIN = VDIAG_EN = VCL = VOUT = 0 V
TJ = 125°C
3
3
VVS = 13.5 V
VIN = 0 V, VDIAG_EN = 5 V
I(off,diag)
t(off,deg)
Ilkg(out)
Standby current with diagnostics enabled
Standby-mode deglitch time(1)
mA
ms
µA
IN from high to low
if deglitch time ≥t(off,deg), then
the device enters into standby
mode.
12.5
200
VVS = 13.5 V
VIN = VDIAG_EN = VOUT = 0 V
Output leakage current in OFF state
3
POWER STAGE
VVS ≥3.5 V, TJ = 25°C
VVS ≥3.5 V, TJ = 150°C
CL pin connected to GND
rDS(on)
ON state resistance
mΩ
400
6
ICL(int)
Internal current limit
3.5
4.8
A
Current-limit value percentage
during thermal shutdown
ICL(TSD)
60%
Drain−to−source voltage
internally clamped
VDS(clamp)
45
65
V
OUTPUT DIODE CHARACTERISTICS
VF
0.3
0.7
1
2
V
A
Drain−to-source diode voltage
IN = 0, IOUT = −0.15 A
Continuous reverse current from
source to drain during a
IR(1)
t < 60 s, VIN= 0 V, TJ = 25°C.
short-to-battery condition(1)
t < 60 s, VIN= 0 V, TJ = 25°C
GND pin 1-kΩresistor in
parallel with diode.
Continuous reverse current from
source to drain during a
IR(2)
2
A
reverse-polarity condition(1)
LOGIC INPUT (IN, DIAG_EN)
VIH
VIL
Logic high-level voltage
1.8
V
V
Logic low-level voltage
0.8
400
850
IN. VIN = 5 V
150
350
Rpd,in
Logic-pin pulldown resistor
kΩ
DIAG_EN. VVS = VDIAG_EN = 5 V
DIAGNOSTICS
Ilkg(loss,GND) Loss of ground output leakage current
100
450
µA
µs
VIN = 5 V, VDIAG_EN = 5 V
when IOUT < I(ol,on), duration longer
than td(ol,on), open load is detected.
td(ol,on)
Open-load deglitch time in ON state
200
300
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6.5 Electrical Characteristics (continued)
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 5 V, VDIAG_EN = 5 V
when IOUT < I(ol,on)
duration longer than td(ol,on)
open load is detected.
Open-load detection threshold
in ON state
I(ol,on)
10
20
mA
VIN = 0 V, VDIAG_EN = 5 V
when VVS –VOUT < V(ol,off)
duration longer than td(ol,off)
open load is detected.
Open-load detection threshold in OFF
state
V(ol,off)
1.4
2.6
V
VIN = 0 V, VDIAG_EN = 5 V
when VVS –VOUT < V(ol,off)
duration longer than td(ol,off)
open load is detected.
Open-load deglitch time
in OFF state
td(ol,off)
200
300
450
µs
VIN = 0 V, VDIAG_EN = 5 V
VVS = VOUT = 13.5 V
I(ol,off)
OFF state output sink current
µA
–75
VFAULT
tFAULT
T(SD)
FAULT low output voltage
IFAULT = 2 mA
0.2
V
FAULT signal holding time(1)
Thermal shutdown threshold(1)
Thermal shutdown status reset(1)
Thermal swing shutdown threshold(1)
8.5
175
155
60
ms
°C
°C
°C
T(SD,rst)
T(sw)
Hysterisis for resetting the thermal
shutdown and swing(1)
T(hys)
10
°C
CURRENT LIMIT AND DELAY CONFIGURATION
K(CL)
Current-limit current ratio(1)
2500
0.8
VCL(th)
Current-limit internal threshold voltage(1)
V
20%
15%
I
I
I
limit ≥0.25 A, VVS –VOUT ≥2.5 V
limit ≥0.5 A, VVS –VOUT ≥2.5 V
limit ≥1.5 A, Ilimit < 5 A
–20%
–15%
External current limit accuracy
(IOUT –ICL × K(CL) × 100 /
dK(CL)
K(CL)
/
(ICL × K(CL)
)
10%
–10%
VVS –VOUT ≥2.5 V
Delay pin charging current
in latch-off mode(1)
Idl(chg)
Vdl(th)
Vdl(ref)
tdl1
4.5
µA
V
Pulling up threshold in auto-retry mode
2.7
Internal reference voltage
in latch-off mode
1.45
400
V
Internal fixed delay time(1)
300
500
µs
ms
Adjustable delay time by external
capacitor on DELAY pin(1)
Connect with 3.3 µF capacitor
as the maximum value.
tdl2
1000
IN low to high or IN keeps high but
thermal shutdown recovery,
VDIAG_EN = 5 V
the deglitch time from IN rising
edge to FAULT reporting out.
300
80
550
200
tCL(deg)
Deglitch time when current limit (1)
µs
IN keeps high, VDIAG_EN = 5 V
the deglitch time from CL start-point
to FAULT reporting out.
thic(on)
thic(off)
On-time when in auto-retry mode(1)
Off-time when in auto-retry mode(1)
35
40
1
45
ms
s
0.8
1.2
(1) Value specified by design, not subject to production test.
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6.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Turnon delay time
IN rising edge to 10% of VOUT
td(on)
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT = 0.1 A
20
50
90
90
µs
(1)
(1)
Turnoff delay time
IN falling edge to 90% of VOUT
td(off)
20
0.1
0.1
50
0.3
µs
Slew rate on
dV/dt(on)
dV/dt(off)
0.6
0.6
V/µs
V/µs
VOUT from 10% to 90% (1)
Slew rate off
0.35
VOUT from 90% to 10% (1)
(1) Value specified by design, not subject to production test.
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6.7 Typical Characteristics
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
VVS Rising
VVS Falling
IN High
IN Low
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D002
D001
图6-2. IN Voltage Threshold
图6-1. UVLO Voltage Threshold
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1
0.9
0.8
0.7
0.6
DIAG_EN High
DIAG_EN Low
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D003
D004
图6-3. DIAG_EN Voltage Threshold
图6-4. Body-Diode Forward Voltage
55
54
53
52
51
50
0.4
rDS(on)_3.5V
rDS(on)_13.5V
rDS(on)_40V
0.35
0.3
0.25
0.2
0.15
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D0076
D005
图6-6. FET On-Resistance
图6-5. Drain-to-Source Clamp Voltage
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6.7 Typical Characteristics (continued)
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-2.5
-3
-2.5
-3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D007
D007
图6-7. Current-Limit Accuracy at 250 mA
图6-8. Current-Limit Accuracy at 500 mA
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D007
图6-9. Current-Limit Accuracy at 1 A
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7 Detailed Description
7.1 Overview
The TPS1H200A-Q1 device is a smart high-side switch with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current limit function improves the reliability of the whole system.
Full diagnostic features enable intelligent control of the load.
The external high-accuracy current limit sets the current limit value for the application. When overcurrent occurs,
the device improves system reliability by clamping the inrush current effectively. The device saves system cost
by reducing the size of PCB traces and connectors, and the capacity of the preceding power stage. The
TPS1H200A-Q1 device allows three modes when a current limit occurs. Users can set the output to consistently
hold the current, to immediately latch off, or to automatically retry through the configuration on the DELAY pin.
The configurable behaviors during a current limit provide design flexibility. This includes functionality, cost, and
thermal dissipation.
This device supports full diagnostics with the digital status output. High-accuracy and low-threshold open-load
detection enables real-time ON state monitoring. The device supports operation without an MCU (stand-alone
mode) which allows the system to locally implement full functionality.
The TPS1H200A-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive
loads, including LEDs, bulbs, relays, solenoids, and submodules.
7.2 Functional Block Diagram
VS
VDS Clamp
Internal Reference
Charge Pump
Gate Driver
IN
DIAG_EN
FAULT
Diagnostics
& Protection
Thermal Monitor
OUT
ON/OFF State
Open Load Detection
Short-to-GND and Overload
Current Limit
CL
GND
DELAY
GND
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7.3 Feature Description
7.3.1 Current limit
A high-accuracy current limit allows high reliability of the design. The current limit protects the load and the
power supply from overstressing during short-circuit-to-GND or power-up conditions. The current limit can also
save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power
stage.
When a current limit threshold is hit, a closed loop immediately activates. The output current is clamped at the
set value, and a fault is reported. The device heats up because of high power dissipation on the power FET.
The device has two current limit thresholds.
• Internal current limit: The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
• External adjustable current limit: An external resistor is used to set the current limit threshold. Use 方程式1 to
calculate R(CL). The external adjustable current limit allows the flexibility to set the current limit value by
application.
V
ìK
(CL)
CL(th)
R
=
CL
I
OUT
(1)
where
• VCL(th) is the internal band-gap voltage.
• K(CL) is the ratio of the output current and the current limit set value.
• K(CL) is constant across temperature and supply voltage.
Note
When a GND network is used, that causes a level shift between the device GND and board GND, so
the CL pin must be connected to the device GND.
For better protection from a hard short-to-GND condition (when the IN pin is enabled, a short-to-GND occurs
suddenly), the device will implement a fast-trip protection to turn off the output before the current limit closed
loop is set up. Typically, the fast-trip response time is less than 1 µs. With a fast response like this, the device
can achieve a better inrush current-suppression performance.
vs
IOUT/K(CL)
Internal Current Limit
-
+
-
+
+
IOUT
VCL(th)
OUT
External Current Limit
-
+
VCL(th)
CL
图7-1. Current Limit
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7.3.2 DELAY Pin Configuration
When a current limit occurs, the TPS1H200A-Q1 device supports three different outcomes of the output. 表 7-1
lists the current limit configurations and these outcomes behaviors.
表7-1. Current Limit Configurations
DELAY
CONFIGURATION
MODE
OUTPUT CURRENT BEHAVIOR
FAULT RECOVERY
FAULT clears when IN turns low for a
When hitting a current limit, the output current
Connects to GND
directly
Holding
holds at the setting current. The device enters into duration of time longer than t FAULT or when
thermal shutdown mode when TJ > T(SD)
.
the current limit is removed when IN is high.
When hitting a current limit, the output current
holds at the setting current, but latches off after a
preset DELAY time (tdl1+ tdl2). tdl1 is the default
delay time, and tdl2 is a capacitor-configurable
delay time.
FAULT clears when IN turns low for a
Connects to GND
through a capacitor
Latch-off
duration of time longer than t FAULT
.
The output stays latched off regardless of whether
the current limit is removed. The output recovers
only when IN is toggling.
FAULT clears when IN turns low for a
When hitting a current limit, the output current
Auto-retry
External pullup
holds at the setting current, but periodically comes duration of time longer than t FAULT OR when
on for thic(on) and turns off for thic(off)
.
the current limit is removed for thic(on)
.
7.3.2.1 Holding Mode
Holding mode is active when the DELAY pin connects directly to GND. When a current limit is reached, the
output current holds at the setting current. The device then enters thermal shutdown mode when TJ > T(SD)
.
DELAY
TPS1H200-Q1
GND
图7-2. Holding Mode Connection
I
OUT
t
CL(deg)
Holding the current
VFAULT
Current Limit
图7-3. Holding Mode Example
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7.3.2.2 Latch-Off Mode
Latch-off mode is active when the DELAY pin connects to GND through a capacitor. When a current limit is
reached, the output current holds at the setting current, but latches off after a preset DELAY time (tdl1+ tdl2). tdl1 is
the default delay time, and tdl2 is a configurable delay time set by a capacitor. Regardless of whether the current
limit is removed or not, the output remains latched off. The output only recovers when IN is toggling.
tdl2 can be calculated by 方程式2.
Idl chg ì t dl2
(
)
CDELAY
=
Vdl ref
(2)
where
• CDELAY is the capacitor connected on the DELAY pin.
• The Idl(chg) is the device that charges the current in latch-off mode.
• tdl2 is the user-setting delay time.
• Vdl(ref) is the internal reference voltage in latch-off mode.
DELAY
TPS1H200-Q1
图7-4. Latch-Off-Mode Connection
I
OUT
tdl2
t
CL(deg) tdl1
Latch off
VFAULT
Current Limit
图7-5. Latch-Off-Mode Example
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7.3.2.3 Auto-Retry Mode
Auto-retry mode is active when the DELAY pin is externally pulled up. The pullup voltage must be higher than
Vdl(th). When the current limit is reached, the output current holds at the setting current, but periodically turns on
for thic(on) and turns off for thic(off). The device checks the current limit status at the falling edge of thic(on) clock. If
current limit status is captured, the device shuts down for thic(off). If the current limit status is not captured
because of the off window during the thermal conditions, the device keeps turning on for additional thic(on) or
more until the current limit status is captured.
DELAY
TPS1H200-Q1
图7-6. Auto-Retry-Mode Connection
I
OUT
tCL(deg)
tCL(deg)
thic(on)
thic(on)
t
hic(off)
thic(off)
VFAULT
Current Limit
图7-7. Auto-Retry-Mode Example
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7.3.3 Stand-alone Operation
In a typical application, the TPS1H200A-Q1 device is controlled by a microcontroller. The device also supports
stand-alone operation. IN and DIAG_EN have a 40-V maximum DC rating, and can be connected to the VS pin
directly. When in auto-retry mode, the DELAY pin is connected to the VS pin through a 100-kΩresistor.
3.4 V œ 40 V
VS
IN
1
2
3
8
7
6
DIAG_EN
OUT
GND
Load
Tab
FAULT
CL
DELAY
4
5
图7-8. Stand-Alone Operation in Latch-Off Mode
3.4 V œ 40 V
VS
IN
1
2
3
8
7
6
DIAG_EN
OUT
GND
Load
Tab
FAULT
CL
DELAY
4
5
图7-9. Stand-Alone Operation in Auto-Retry Mode
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7.3.4 Fault Truth Table
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the microcontroller uses GPIOs to set DIAG_EN high to enable the
diagnostics of one device, and disables the diagnostics of the other devices by setting DIAG_EN low.
Additionally, the device can keep power consumption to a minimum by setting DIAG_EN and IN low.
表7-2 applies when the DIAG_EN pin is enabled, and 表7-3 applies when the DIAG_EN pin is disabled.
表7-2. Fault Truth Table
CONDITION
IN
OUT
CRITERION
FAULT
FAULT RECOVERY
L
L
H
L
N/A
N/A
H
H
L
Normal
N/A
H
H
Overload or short to GND
current limit triggered
See 表7-1.
FAULT clears when IN turns low
for a duration longer than t FAULT
OR FAULT clears when the open
load is removed.
.
H
L(1)
H
H
H
IOUT < l(ol,on)
L
L
L
Open load or short to
battery
FAULT clears when IN is toggling
OR FAULT clears when the open
load is removed.
VVS –VOUT < V(ol,off)
FAULT clears when IN turns low
Thermal shutdown
triggered
for a duration longer than t FAULT
OR FAULT clears when thermal
shutdown quits.
.
Thermal shutdown
Thermal swing
N/A
FAULT clears when IN turns low
for a duration longer than t FAULT
OR FAULT clears when thermal
swing quits.
.
H
N/A
Thermal swing triggered
L
(1) An external pullup is required for open-load detection.
表7-3. DIAG_EN Disabled Condition
DIAG_EN
IN CONDITION
PROTECTIONS AND DIAGNOSTICS
Diagnostics disabled, full protections
Diagnostics disabled, no protection
ON
LOW
OFF
7.3.5 Full Diagnostics
7.3.5.1 Short-to-GND and Overload Detection
When the output is on, a short-to-GND or overload condition causes an overcurrent. If the overcurrent triggers
the internal or external current limit threshold, the fault condition is reported as FAULT pin = low.
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7.3.5.2 Open-Load Detection
7.3.5.2.1 Output On
When the output is on, the device recognizes an open-load fault if the current flowing through the output IOUT
l(ol,on). For open-load detection when output is on, no external circuitry is required.
<
7.3.5.2.2 Output Off
When the output is off, the output is pulled down to GND if a load is connected. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUT < V(ol,off)), and the device recognizes an open-load
fault.
There is always a leakage current I(ol,off) on the output due to the internal logic control path or external humidity,
corrosion, and so forth. As a result, TI recommends using an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 15 kΩ.
V(OL,off)
R(PULLUP)
VDS
Load
图7-10. Open-Load Detection in Output OFF State
7.3.5.3 Short-to-Battery Detection
Short-to-battery has the same detection mechanism and behavior as open-load detection in the ON state and
the OFF state.
7.3.5.4 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing).
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Thermal behaviors after Short to GND
IN
TJ
T(SD)
T(hys)
T(SD,rst)
T(hys)
T(SW)
ICL
ICL(TSD)
IOUT
FAULT
图7-11. Thermal Behavior Diagram
7.3.5.4.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thermal shutdown occurs, the
output turns off.
7.3.5.4.2 Thermal Swing
Thermal swing activates when the power FET temperature sharply increases, that is, when ΔT = T(FET)
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
(FET) –T(Logic) < T(sw) –T(hys). The thermal swing function improves the reliability of the device when subjected
–
T
to repetitively fast thermal variation.
7.3.5.4.3 Fault Report Holding
When using PWM dimming, FAULT is easily cleared by the PWM falling edge. Even if the fault condition remains
all the time, FAULT is discontinuous. To avoid this unexpected fault report behavior, the device implements fault
report holding time. 图 7-12 shows an issue that typically occurs during PWM dimming, the FAULT is cleared
unexpectedly even when the short-to-GND still exists. The TPS1H200A-Q1 device with fault-report holding
function allows the right behavior as shown in 图7-13.
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Short-to-GND
IN
Fault cleared
FAULT
图7-12. Without Fault-Report Holding
Short-to-GND
IN
Fault not cleared
FAULT
t < tFAULT
图7-13. With Fault-Report Holding
7.3.6 Full Protections
7.3.6.1 UVLO Protection
The device monitors the supply voltage, VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
drops down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
7.3.6.2 Inductive Load Switching Off Clamp
When an inductive load is switched off, the inductive reactance pulls the output voltage negative. However,
excessive negative voltage can cause the power FET to break down. To protect the power FET from breaking
down, an internal clamp (VDS(clamp)) is implemented.
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VS
VDS(clamp)
-
L
OUT
R
GND
+
图7-14. Drain-to-Source Clamping Structure
IN
VVS
VOUT
VDS(clamp)
IOUT
t(decay)
图7-15. Inductive-Load Switching-Off Diagram
7.3.6.3 Loss-of-GND Protection
When a loss-of-GND occurs, the output shuts down, regardless of whether the IN pin is high or low. The device
can protect against two ground-loss conditions, loss of device GND and loss of module GND.
7.3.6.4 Loss-of-Power-Supply Protection
When a loss-of-power-supply occurs, the output shuts down, regardless of whether the IN pin is high or low. For
a resistive or a capacitive load, the loss-of-power-supply has no risk. But for a charged inductive load, the
current is driven from all the logic control pins to maintain the inductance current. To protect the system in this
condition, TI recommends protection with an external free-wheeling diode.
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Vs
VS
High-Side Switch
IOs
MCU
OUT
D
L
图7-16. Protection for Loss of Power Supply
7.3.6.5 Reverse-Current Protection
Reverse current occurs in two conditions: short to supply and reverse polarity.
• When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
• In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current.
To protect the device, TI recommends using two types of external circuitry.
• Adding a blocking diode (method 1). The device and load are protected when in reverse polarity.
• Adding a GND network (method 2). The reverse current through the device GND is blocked. The reverse
current through the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a
GND network. The recommended configuration is a 1-kΩresistor in parallel with a diode that is less than 100
mA.
Load
图7-17. Reverse-Current External Protection Method 1
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Load
图7-18. Reverse-Current External Protection Method 2
7.3.6.6 MCU I/O Protection
TI recommends using series resistors to protect the microcontroller, for example, 4.7 kΩ when using a 3.3-V
microcontroller and 10 kΩfor a 5-V microcontroller.
IOs
TPS1H200-Q1
MCU
图7-19. MCU I/O External Protection
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7.4 Device Functional Modes
7.4.1 Working Modes
The device has three working modes: the normal mode, the standby mode, and the standby mode with
diagnostics, as shown in 图7-20.
Standby Mode
(IN low, DIAG_EN low)
DIAG_EN low
AND
IN high to low
DIAG_EN high to low
AND
t > t(off,deg)
IN low to high
DIAG_EN low to high
Standby Mode
With DIAG
IN low to high
Normal Mode
(IN high)
(IN low, DIAG_EN high)
IN high to low
AND
DIAG_EN high
AND
t > t(off,deg)
图7-20. Working Modes
7.4.1.1 Normal Mode
When IN is high, the device enters normal mode.
7.4.1.2 Standby Mode
When IN is low and DIAG_EN is low, the device enters standby mode with ultra-low power consumption.
7.4.1.3 Standby Mode With Diagnostics
When IN is low and DIAG_EN is high, the device enters standby mode with diagnostics. The device still supports
open-load and short-to-battery detection even when IN is low.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS1H200A-Q1 device is a smart high-side switch, with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current limit function greatly improves the reliability of the whole
system. Full diagnostic features enable intelligent control of the load. The TPS1H200A-Q1 device applies for a
wide variety of resistive, inductive, and capacitive loads, including LEDs, relays, and submodules.
8.2 Typical Application
图8-1 shows an example of how to design the external circuitry parameters.
Supply Voltage
R(SER)
VS
IN
R(SER)
General Resistive, Capacitive,
Inductive Loads
DIAG_EN
OUT
3.3/5V
R(pullup)
MCU
R(SER)
FAULT
DELAY
C(DELAY)
GND
CL
R(CL)
图8-1. Typical Application Circuitry
8.2.1 Design Requirements
• VVS range from 6 V to 18 V
• Nominal current of 500 mA
• Expected current limit value of 2 A
• Thermal sensitive system. When current limit occurs, the output latches off after 0.2 seconds. The 0.2
seconds is to ensure the safe start-up for a capacitive load, clamping the inrush current but without latch-off
during start-up.
• Full diagnostics with 5-V MCU, including ON state open-load detection, short-to-GND, or overcurrent
detection, and thermal shutdown detection
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8.2.2 Detailed Design Procedure
To set the adjustable current limit value at 2 A, calculate R(CL) as follows:
VCL th ì K(
0.8 ì 2500
CL
)
(
)
R(
=
=
= 1000 Ö
CL
)
IOUT
2
(3)
(4)
To set the adjustable latch-off delay at 0.2 s, calculate C(DELAY) as follows:
t dl = t CL deg + tdl1 + tdl2 = 0.2»t dl2
(
)
Idl chg ì t dl2
4.5ì0.2
1.45
(
)
CDELAY
=
=
ì 10 -6 = 0.62 mF
Vdl ref
(
)
TI recommends R(SER) = 10 kΩfor a 5-V MCU, and R(pullup) = 10 kΩas the pullup resistor.
8.2.3 Application Curves
The following curves are test examples of hard-short conditions. The load is 0.1 A and the current limit value is
0.6 A. 图8-2 shows a waveform of the latch-off mode. 图8-3 shows a waveform of the auto-retry mode.
图8-2. Hard-Short Condition in Latch-Off Mode
图8-3. Hard-Short Condition in Auto-Retry Mode
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9 Power Supply Recommendations
The device applies to 12-V and 24-V applications. The normal power supply connection is a 12-V or 24-V
system.
10 Layout
10.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 175°C. If the output current is high, the power dissipation can
be large. However, the PCB layout is very important. A good PCB design optimizes heat transfer, which is
essential for the long-term reliability of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when no heat sinks are attached to the PCB on the other side of the board opposite the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias must either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage must be at least 85%.
10.2 Layout Example
IN
1
2
VS
8
7
DIAG_EN
OUT
Thermal Pad
3
4
GND
FAULT
CL
6
5
DELAY
图10-1. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS1H000-Q1 Evaluation Module (EVM) User's Guide
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS1H200AQDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1EWX
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS1H200AQDGNRQ1 HVSSOP DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HVSSOP DGN
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS1H200AQDGNRQ1
8
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/B 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/B 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225480/B 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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