TLV571_14_技术文档

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

features

applications

Fast Throughput Rate: 1.25 MSPS at 5 V,

625 KSPS at 3 V

Mass Storage and HDD

Automotive

Wide Analog Input: 0 V to AV

DD

Digital Servos

Differential Nonlinearity Error: < ± 0.5 LSB

Process Control

Integral Nonlinearity Error: < ± 0.5 LSB

Single 2.7-V to 5.5-V Supply Operation

Low Power: 12 mW at 3 V and 35 mW at 5 V

Auto Power Down of 1 mA Max

Software Power Down: 10 µA Max

Internal OSC

General-Purpose DSP

Image Sensor Processing

DW OR PW PACKAGE

(TOP VIEW)

CS

WR

1

24

23

22

21

20

19

18

17

16

15

14

13

NC

AIN

2

Hardware Configurable

RD

3

AV

DD

4

CLK

AGND

REFM

REFP

CSTART

A1/D7

A0/D6

D5

DSP and Microcontroller Compatible

Parallel Interface

5

DGND

6

DV

DD

7

INT/EOC

DGND

D0

Binary/Twos Complement Output

8

Hardware Controlled Extended Sampling

Hardware or Software Start of Conversion

9

10

11

12

D1

D2

D4

D3

description

The TLV571 is an 8-bit data acquisition system

that combines a high-speed 8-bit ADC and a

NC – No internal connection

parallel interface. The device contains two on-chip control registers allowing control of software conversion start

and power down via the bidirectional parallel port. The control registers can be set to a default mode using a

dummy RD while WR is tied low allowing the registers to be hardware configurable.

The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to

AV

and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only

DD

12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that

automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the

ADC is further powered down to only 10 µA.

Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal

choice for high-speed digital signal processing.

AVAILABLE OPTIONS

PACKAGE

T

A

24 TSSOP

(PW)

24 SOIC

(DW)

–40°C to 85°C

TLV571IPW

TLV571IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

functional block diagram

REFP

REFM

DV

DD

AV

DD

AIN

D0 – D5

Three

State

Latch

8-BIT

SAR ADC

D6/A0

D7/A1

Internal

Clock

MUX

CLK

CS

RD

WR

Input Registers

and Control Logic

INT/EOC

CSTART

AGND

DGND

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

AGND

AIN

AV

NO.

21

Analog ground

23

I

ADC analog input

22

Analog supply voltage, 2.7 V to 5.5 V

DD

A0/D6

16

I/O Bidirectional 3-state data bus. D6/A0 along with D7/A1 is used as address lines to access CR0 and CR1 for

initialization.

A1/D7

17

I/O Bidirectional 3-state data bus. D7/A1 along with D6/A0 is used as address lines to access CR0 and CR1 for

initialization.

CLK

4

1

I

External clock input

CS

Chip select. A logic low on CS enables the TLV571.

CSTART

18

Hardware sample and conversion start input. The falling edge of CSTART starts sampling and the rising edge

of CSTART starts conversion.

DGND

5, 8, 9

Digital ground

DV

6

10–15

7

Digital supply voltage, 2.7 V to 5.5 V

DD

D0 – D5

I/O Bidirectional 3-state data bus

O

End-of-conversion/interrupt

INT/EOC

NC

24

Not connected

3

I

Read data. A falling edge on RD enables a read operation on the data bus when CS is low.

Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be grounded.

RD

REFM

REFP

20

19

Upper reference voltage (nominally AV ). The maximum input voltage range is determined by the difference

DD

between the voltage applied to REFP and REFM.

2

I

Write data. A rising edge on the WR latches in configuration data when CS is low. When using software

conversion start, a rising edge on WR also initiates an internal sampling start pulse. When WR is tied to ground,

the ADC in nonprogrammable (hardware configuration mode).

WR

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

detailed description

analog-to-digital SAR converter

Ain

Charge

Redistribution

DAC

_

+

SAR

ADC Code

Register

REFM

Control

Logic

Figure 1

The TLV571 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a

simplified version of the ADC.

The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process

starts, theSARcontrollogicandchargeredistributionDACareusedtoaddandsubtractfixedamountsofcharge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

sampling frequency, f

s

The TLV571 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling frequency

achievable with a given CLK frequency is:

f

= (1/16) f

CLK

s(max)

The TLV571 is software configurable. The first two MSB bits, D(7,6) are used to address which register to set.

The remaining six bits are used as control data bits. There are two control registers, CR0 and CR1, that are user

configurable. All of the register bits are written to the control register during write cycles. A description of the

control registers is shown in Figure 2.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

detailed description (continued)

control registers

A1

A0

D5

D4

D3

D2

D1

D0

Control Register Zero (CR0)

D5 D4

STARTSEL PROGEOC CLKSEL

D1

D0

Don’t Care

A(1:0)=00

SWPWDN Don’t Care

0:

HARDWARE INT

START

NORMAL

Internal

Clock

Don’t Care

(CSTART)

1:

EOC

Powerdown

1:

SOFTWARE

START

External

Clock

Control Register One (CR1)

D5

Reserved

D4

D1

D0

Reserved

D3

D2

A(1:0)=01

OSCSPD 0 Reserved 0 Reserved OUTCODE

0:

INT. OSC.

SLOW

1:

INT. OSC.

FAST

Reserved Binary

Bit,

Always

Reserved

Bit

Always

Write 0

Reserved

Bit

Always

Write 0

Reserved

Bit,

Always

Write 0

1:

2’s

Complement

Figure 2. Input Data Format

hardware configuration option

The TLV571 can configure itself. This option is enabled when the WR pin is tied to ground and a dummy RD

signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control registers.

The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz and hardware

start of conversion using CSTART.

ADC conversion modes

The TLV571 provides two start of conversion modes. Table 1 explains these modes in more detail.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

detailed description (continued)

Table 1. Conversion Modes

START OF

CONVERSION

OPERATION

COMMENTS – FOR INPUT

Hardware start • Repeated conversions from AIN

CSTART rising edge must be applied

a minimum of 5 ns before or after CLK

rising edge.

(CSTART)

• CSTART falling edge to start sampling

CR0.D5 = 0

• CSTART rising edge to start conversion

• If in INT mode, one INT pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion, and return high

at end of conversion.

Software start

CR0.D5 = 1

• Repeated conversions from AIN

• WR rising edge to start sampling initially. Thereafter, sampling occurs at the edge must be a minimum 5 ns before

With external clock, WR and RD rising

rising edge of RD.

or after CLK rising edge.

• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT

mode, one INT pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion and return high at

end of conversion.

configure the device

The device can be configured by writing to control registers CR0 and CR1.

Table 2. TLV571 Programming Examples

INDEX

REGISTER

D5

D4

D3

D2

D1

D0

COMMENT

D7

D6

EXAMPLE1

CR0

0

1

0

Normal, INT OSC

Binary

CR1

EXAMPLE2

CR0

0

1

0

1

0

1

0

1

0

1

0

Power down, EXT OSC

2’s complement output

CR1

power down

The TLV571 offers two power down modes, auto power down and software power down. This device will

automaticallyproceedtoautopowerdownmodeifRDisnotpresentoneclockafterconversion. Softwarepower

down is controlled directly by the user by pulling CS to DV

.

DD

Table 3. Power Down Modes

SOFTWARE POWER DOWN

(CS = DV

PARAMETERS/MODES

AUTO POWER DOWN

)

DD

10 µA

Maximum power down dissipation current

Comparator

1 mA

Power down

Saved

Power down

Saved

Clock buffer

Control registers

Minimum power down time

Minimum resume time

1 CLK

2 CLK

1 CLK

2 CLK

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

detailed description (continued)

reference voltage input

The TLV571 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish

the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The

values of REFP, REFM, and the analog input should not exceed the positive supply or be less than GND

consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal

is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.

sampling/conversion

All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or

CSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and

CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay

close to the rising edge of the external clock (if it is used as CLK). The minimum setup and hold time with respect

to the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this is not an

issue since these two edges will start the internal clock automatically. Therefore, the setup time is always met.

Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal oscillator if

enabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from 0.6 µs to

0.3 µs. The internal oscillator frequency is 9 MHz minimum (ocillator frequency is between 9 MHz to 22 MHz),

translating into a sampling time from 0.6 µs to 0.3 µs. Conversion begins immediately after sampling and lasts

10 clock cycles. This is again done using the external clock input (1 MHz–20 MHz) or the internal oscillator

(9 MHz minimum) if enabled. Hardware controlled sampling, via CSTART, begins on falling CSTART lasts the

length of the active CSTART signal. This allows more control over the sampling time, which is useful when

sampling sources with large output impedances. On rising CSTART, conversion begins. Conversion in

hardwarecontrolledmodealsolasts10clockcycles. Thisisdoneusingtheexternalclockinput(1MHz–20MHz)

or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.

ExtClk

t

≥5 ns

h(WRL_EXTCLKH)

t

≥5 ns

su(WRH_EXTCLKH)

WR

RD

OR

t

≥5 ns

h(RDL_EXTCLKH)

t

≥5 ns

su(RDH_EXTCLKH)

t

≥5 ns

h(CSTARTL_EXTCLKH)

t

su(CSTARTH_EXTCLKH)

t

≥5 ns

d(EXTCLK_CSTARTL)

≥5 ns

CSTART

NOTE: t = setup time, t = hold time

su

h

Figure 3. Trigger Timing – Software Start Mode Using External Clock

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

start of conversion mechanism

There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins

sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start

mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion

process lasts only 16 clocks in this case. If RD is not detected during the next clock cycle, the ADC automatically

proceeds to a power-down state. Data is valid on the rising edge of INT in both conversion modes.

hardware CSTART conversion

external clock

With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and

conversion begins at the rising edge of CSTART. At the end of conversion, EOC goes from low to high, telling

the host that conversion is ready to be read out. The external clock is active and is used as the reference at all

times. With this mode, it is required that CSTART is not applied at the rising edge of the clock (see Figure 4).

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

software START conversion (continued)

system clock source

The TLV571 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used for most

conversion subtasks. The source of SYSCLK is programmable via control register zero, bit 3. The source of

SYSCLK is changed at the rising edge of WR of the cycle when CR0.D3 is programmed.

internal clock (CR0.D3 = 0, SYSCLK = internal OSC)

The TLV571 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of SYSCLK, the

internal clock starts with a delay (one half of the OSC period max) after the falling edge of the conversion trigger

(either WR, RD, or CSTART). The OSC speed can be set to 10 ± 1 MHz or 20 ± 2 MHz by setting register bit

CR1.D4.

external clock (CR0.D3 = 1, SYSCLK = external clock)

The TLV571 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from 1 MHz to

20 MHz.

host processor interface

The TLV571 provides a generic high-speed parallel interface that is compatible with high-performance DSPs

and general-purpose microprocessors. The interface includes D(0–7), INT/EOC, RD, and WR.

output format

The data output format is unipolar (code 0 to 255). The output code format can be either binary or twos

complement by setting register bit CR1.D1.

power up and initialization

After power up, CS must be low to begin an I/O cycle. INT/EOC is initially high. The TLV571 requires two write

cycles to configure the two control registers. The first conversion after the device has returned from the power

down state may be invalid and should be disregarded.

definitions of specifications and terminology

integral nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.

The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level

1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to

the true straight line between these two points.

differential nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.

A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

zero offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition

should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual

difference between first and last code transitions and the ideal difference between first and last code transitions.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

software START conversion (continued)

signal-to-noise ratio + distortion (SINAD)

Signal-to-noise ratio + disortion is the ratio of the rms value of the measured input signal to the rms sum of all

other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

effective number of bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective

number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its

measured SINAD.

total harmonic distortion (THD)

Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the

measured input signal and is expressed as a percentage or in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak

spurious signal.

DSP interface

The TLV571 is a 8-bit single input channel analog-to-digital converter with throughput up to 1.25 MSPS at 5 V

and up to 625 KSPS at 3 V. To achieve 1.25 MSPS throughput, the ADC must be clocked at 20 MHz. Likewise

to achieve 625 KSPS throughout, the ADC must be clocked at 10 MHz. The TLV571 can be easily interfaced

to microcontrollers, ASICs, and DSPs. Figure 8 shows the pin connections to interface the TLV571 to the

TMS320C6x DSP.

TMS320C6X

A0–A15

TLV571

Address

Decoder

EN

AIN

CS

REF

WR

HW

HR

REFP

REFM

RD

EOC

D0–D7

INTx

D0–D15

Figure 8. TMS320C6x DSP Interface

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

grounding and decoupling considerations

General practices should apply to the PCB design to limit high frequency transients and noise that are fed back

into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.

In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency

range. Since their effectiveness depends largely on the proximity to the individual supply pin, they should be

placed as close to the supply pins as possible.

To reduce high frequency and noise coupling, it is highly recommended that digital and analog grounds be

shorted immediately outside the package. This can be accomplished by running a low impedance line between

DGND and AGND under the package.

DV

AV

DD

TLV571

AV

DD

100 nF

DV

DD

AGND

REFP

REFM

V

REFP

100 nF

V

REFM

DGND

100 nF

Figure 9. Placement for Decoupling Capacitors

power supply ground layout

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.

Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected

together at the low-impedance power-supply source. The best ground connection may be achieved by

connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground

currents are well managed.

†

Driving Source

TLV571

V

R

C

= Input Voltage at AIN

= External Driving Source Voltage

= Source Resistance

I

S

s

R

s

i(ADC)

V

I

AIN

= Input Resistance of ADC

= Input Capacitance

i(ADC)

V

S

V

C

i

V

C

= Capacitance Charging Voltage

C

i

15 pF

†

Driving source requirements:

•

Noise and distortion for the source must be equivalent to the resolution of the converter.

R must be real at the input frequency.

s

Figure 10. Equivalent Input Circuit Including the Driving Source

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

simplified analog input analysis

Using the equivalent circuit in Figure 10, the time required to charge the analog input capacitance from 0 to V

S

within 1/2 LSB, t (1/2 LSB), can be derived as follows.

ch

The capacitance charging voltage is given by:

–t

R C

t

ch

1–e

i

V

C(t)

R = R + R

i

S

Where

(1)

t

s

R = R

i

i(ADC)

t

= Charge time

ch

The input impedance R is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given

i

by:

(2)

V (1/2 LSB) = V – (V /512)

C

S

Equating equation 1 to equation 2 and solving for cycle time t gives:

c

–t

R C

t

ch

1–e

i

V

512

V

S

(3)

and time to change to 1/2 LSB (minimum sampling time) is:

(1/2 LSB) = R × C × ln(512)

t

ch

t

i

Where

ln(512) = 6.238

Therefore, with the values given, the time for the analog input signal to settle is:

(1/2 LSB) = (R + 718 Ω) × 15 pF × ln(512)

(4)

(5)

(6)

t

ch

s

This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.

(1/2 LSB) ≤ 6x 1/f

t

ch

(SCLK)

Therefore the maximum SCLK frequency is:

Max(f ) = 6/t (1/2 LSB) = 6/(ln(512) × R × C )

(SCLK)

ch

t

i

15

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TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, GND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V

CC

Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV

+ 0.3 V

DD

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C

J

Operating free-air temperature range, T , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN

2.7

MAX

5.5

UNIT

V

Analog supply voltage, AV

DD

Digital supply voltage, DV

2.7

5.5

V

DD

NOTE 1: Abs (AV

– DV ) < 0.5 V

DD

analog inputs

MIN

MAX

UNIT

Analog input voltage, AIN

AGND VREFP

V

digital inputs

MIN NOM

MAX

UNIT

V

High-level input voltage, V

DV

= 2.7 V to 5.5 V

= 4.5 V to 5.5 V

= 2.7 V to 3.3 V

= 4.5 V to 5.5 V, f

= 2.7 V to 3.3 V, f

= 4.5 V to 5.5 V, f

= 2.7 V to 3.3 V, f

2.1

2.4

IH

DD

Low level input voltage, V

0.8

20

10

V

IL

MHz

ns

Input CLK frequency

= 20 MHz

= 10 MHz

= 20 MHz

= 10 MHz

23

46

23

46

4

CLK

Pulse duration, CLK high, t

w(CLKH)

ns

Pulse duration, CLK low, t

w(CLKL)

ns

Rise time, I/O and control, CLK, CS

Fall time, I/O and control, CLK, CS

50 pF output load

ns

4

reference specifications

MIN

2

NOM

MAX

UNIT

AV

= 3 V

AV

V

DD

VREFP

= 5 V

2.5

DD

External reference voltage

= 3 V

= 5 V

AGND

2

1

VREFM

2

VREFP – VREFM

AV –AGND

DD

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

electrical characteristics over recommended operating free-air temperature range, supply

voltages, and reference voltages (unless otherwise noted)

digital specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic inputs

I

High-level input current

Low-level input current

Input capacitance

DV

= 5 V, DV

= 3 V, Input = DV

DD

= 3 V, Input = 0 V

–1

1

µA

pF

IH

DD

= 5 V, DV

–1

IL

C

10

15

i

Logic outputs

V

High-level output voltage

I

= 50 µA to 0.5 mA

DV –0.4

DD

V

OH

Low-level output voltage

0.4

1

V

OL

I

High-impedance-state output current

Low-impedance-state output current

Output capacitance

DV

= 5 V, DV

= 3 V, Input = DV

DD

= 3 V, Input = 0 V

µA

pF

OZ

DD

–1

OL

C

5

10

20

o

3 V, AV

5 V, AV

= DV

9

11

22

DD

Internal clock

MHz

18

DD

dc specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

8

Bits

Accuracy

Integral nonlinearity, INL

Best fit

±0.3

±0.5

LSB

Differential nonlinearity, DNL

Missing codes

0

E

Offset error

±0.15%

±0.2%

±0.3%

±0.4%

FSR

O

Gain error

G

Analog input

AIN, AV

= 3 V, AV

= 5 V

15

25

pF

µA

DD

= 3 V, AV

C

Input capacitance

i

MUX input, AV

DD

= 5 V

DD

I

Input leakage current

V

AIN

= 0 to AV

DD

±1

lkg

Voltage reference input

r

Input resistance

2

kΩ

i

C

Input capacitance

300

pF

i

Power supply

AV

= DV

= 3 V, f

= 5 V, f

= 10 MHz

= 20 MHz

4

7

5.5

8.5

17

43

8

mA

mW

µA

DD

CLK

Operating supply current, I

+ I

DD REF

DD

AV +DV

DD

= 3 V

= 5 V

12

35

1

DD

PD

Power dissipation

AV +DV

DD

AV

= 3 V

= 5 V

= 3 V

= 5 V

DD

Software

I + I

DD REF

AV

2

10

1

µA

I

Supply current in power-down mode

PD

0.5

mA

Auto

I + I

DD REF

1

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

electrical characteristics over recommended operating free-air temperature range, supply

voltages, and reference voltages (unless otherwise noted) (continued)

ac specifications, AV

= DV

= 5 V (unless otherwise noted)

DD

PARAMETER

TEST CONDITIONS

MIN

47

TYP

49

MAX

UNIT

dB

f = 1.25 MSPS, AV

s

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

f = 100 kHz,

I

DD

Signal-to-noise ratio, SNR

80% of FS

f = 625 KSPS, AV

s

47

49

dB

f = 1.25 MSPS, AV

s

47

49

dB

f = 100 kHz,

I

80% of FS

Signal-to-noise ratio + distortion, SINAD

Total harmonic distortion, THD

f = 625 KSPS, AV

s

47

49

dB

f = 1.25 MSPS, AV

s

–64

–62

7.9

–65

–64

–52

dB

f = 100 kHz,

I

80% of FS

f = 625 KSPS, AV

s

dB

f = 1.25 MSPS, AV

s

7.5

Bits

dB

f = 100 kHz,

I

80% of FS

Effective number of bits, ENOB

f = 625 KSPS, AV

s

f = 1.25 MSPS, AV

s

–51

f = 100 kHz,

I

80% of FS

Spurious free dynamic range, SFDR

f = 625 KSPS, AV

s

dB

Analog input

–1 dB

–3 dB

–1 dB

–3 dB

Full-scale 0 dB input sine wave

–20 dB input sine wave

12

15

18

30

20

35

MHz

Full-power bandwidth

Small-signal bandwidth

–20 dB input sine wave

AV

= 4.5 V to 5.5 V

= 2.7 V to 3.3 V

0.0625

1.25 MSPS

0.625 MSPS

DD

Sampling rate, f

s

DD

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

timing requirements, AV

= DV

= 5 V (unless otherwise noted)

DD

PARAMETER

TEST CONDITIONS

MIN

50

TYP

MAX

UNIT

ns

DV

= 4.5 V to 5.5 V

DD

t

Input clock Cycle time

c(CLK)

DV

= 2.7 V to 3.3 V

100

ns

SYSCLK

Cycles

t

Reset and sampling time

Total conversion time

6

10

1

(sample)

SYSCLK

Cycles

c

SYSCLK

Cycles

Pulse width, end of conversion, EOC

Pulse width, interrupt

wL(EOC)

wL(INT)

SYSCLK

Cycles

t

Start-up time, internal oscillator

100

ns

(STARTOSC)

Delay time, CS high to CSTART low

10

20

40

5

d(CSH_CSTARTL)

DV

= 5 V at 50 pF

= 3 V at 50 pF

= 5 V at 50 pF

= 3 V at 50 pF

DD

t

Enable time, data out

Disable time, data out

en(RDL_DAV)

dis(RDH_DAV)

10

t

Setup time, CS to WR

Hold time, CS to WR

5

su(CSL_WRL)

h(WRH_CSH)

Clock

t

Pulse width, write

Pulse width, read

1

w(WR)

Period

Clock

Period

w(RD)

t

Setup time, data valid to WR

Hold time, data valid to WR

Setup time, CS to RD

10

5

ns

su(DAV_WRH)

h(WRH_DAV)

5

su(CSL_RDL)

Hold time, CS to RD

h(RDH_CSH)

Hold time WR to clock high

Hold time RD to clock high

5

h(WRL_EXTXLKH)

h(RDL_EXTCLKH)

h(CSTARTL_EXTCLKH)

su(WRH_EXTCLKH)

su(RDH_EXTCLKH)

su(CSTARTH_EXTCLKH)

d(EXTCLK_CSTARTL)

Hold time CSTART to clock high

Setup time WR high to clock high

Setup time RD high to clock high

Setup time CSTART high to clock high

Delay time clock low to CSTART low

NOTE: Specifications subject to change without notice.

Data valid is denoted as DAV.

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

FREE AIR TEMPERATURE

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

AV

= DV

= 5 V, 20 MHz

DD

AV

= DV

= 3 V, 10 MHz

DD

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

T

A

– Free Air Temperature – °C

Figure 11

ANALOG INPUT BANDWIDTH

SUPPLY CURRENT

vs

FREQUENCY

CLOCK FREQUENCY

1

0

7

6

5

4

3

2

1

0

AV

DD

= DV

= 5 V

DD

–1

–2

–3

AV

= DV

= 5 V,

DD

AV

DD

= DV

= 3 V

DD

–4

AIN = 90% of FS,

REF = 5 V,

–5

–6

T

A

= 25°C

0.1

1

10

100

0

2

4

6

8

10 12 14 16 18 20

f – Frequency – MHz

f

– Clock Frequency – MHz

clock

Figure 12

Figure 13

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.15

0.10

AV

DD

External Ref = 3 V,

= DV

= 3 V,

DD

CLK = 10 MHz,

T

= 25°C

A

0.05

–0.00

–0.05

–0.10

–0.15

0

64

128

192

256

Digital Output Code

Figure 14

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

–0.02

–0.04

AV

DD

External Ref = 3 V,

= DV

= 3 V,

DD

CLK = 10 MHz,

T

= 25°C

A

–0.06

0

64

128

192

256

Digital Output Code

Figure 15

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.12

0.10

AV

DD

External Ref = 5 V,

= DV

= 5 V,

DD

0.08

CLK = 20 MHz,

T

= 25°C

0.06

A

0.04

0.02

0.00

–0.02

–0.04

–0.06

–0.08

0

64

128

192

256

Digital Output Code

Figure 16

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.14

0.12

AV

DD

External Ref = 5 V,

= DV

= 5 V,

DD

0.10

CLK = 20 MHz,

0.08

T

= 25°C

A

0.06

0.04

0.02

0.00

–0.02

–0.04

–0.06

–0.08

0

64

128

192

256

Digital Output Code

Figure 17

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

10

9

AV

DD

= DV

= 3 V,

DD

External Ref = 3 V

8

7

6

5

0

100

200

300

f – Frequency – kHz

Figure 18

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

10

9

AV

DD

= DV

= 5 V,

DD

External Ref = 5 V

8

7

6

5

0

200

400

600

f – Frequency – kHz

Figure 19

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM

vs

FREQUENCY

20

0

AIN = 200 KHz

CLK = 10 MHz

–20

–40

–60

–80

–100

–120

–140

AV

DD

External Ref = 3 V

= DV

= 3 V

DD

0

100000

200000

300000

f – Frequency – Hz

Figure 20

FAST FOURIER TRANSFORM

vs

FREQUENCY

20

0

AIN = 200 KHz

CLK = 20 MHz

–20

–40

–60

–80

–100

–120

–140

AV

DD

= DV

= 5 V

DD

External Ref = 5 V

0

200000

400000

600000

f – Frequency – Hz

Figure 21

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

0.050 (1,27)

16

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

M

9

0.419 (10,65)

0.400 (10,15)

0.010 (0,25) NOM

0.299 (7,59)

0.293 (7,45)

Gage Plane

0.010 (0,25)

1

8

0°–8°

0.050 (1,27)

0.016 (0,40)

A

Seating Plane

0.004 (0,10)

0.012 (0,30)

0.004 (0,10)

0.104 (2,65) MAX

PINS **

16

20

24

28

0.710

DIM

0.410

0.510

0.610

A MAX

A MIN

(10,41) (12,95) (15,49) (18,03)

0.400

0.500

0.600

0.700

(10,16) (12,70) (15,24) (17,78)

4040000/C 07/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-013

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device

TLV571IDW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

24

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLV571IDWG4

TLV571IDWR

TLV571IDWRG4

TLV571IPW

SOIC

DW

PW

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TLV571IPWG4

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Use of such information may require a license from a third party under the patents or other intellectual property

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

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www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Low Power Wireless www.ti.com/lpw

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TLV571_14
厂家：	TEXAS INSTRUMENTS
描述：	2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT PARALLEL ANALOG-TO-DIGITAL CONVERTER
文件：	总28页 (文件大小：420K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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