TLV5734_10 [TI]
TRIPLE 8 BIT 30 MSPS ADC WITH HIGH -PRECISION CLAMP FOR YUV/RGB VIDEO;
| 型号： | TLV5734_10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE 8 BIT 30 MSPS ADC WITH HIGH -PRECISION CLAMP FOR YUV/RGB VIDEO |
| 文件： | 总20页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
features
applications
D
3-Channel CMOS ADC
D
Digital TV
D
D
D
D
D
D
D
D
D
Single 3.3-V Supply
D
D
D
D
D
Digital Video
8-Bit 30-MSPS A/D Conversion
Very Low Power: <300 mW Typical
Differential Linearity Error: < ±0.5 LSB Max
Integral Linearity Error: < ±0.75 LSB Max
Analog Input Voltage Range: 1 Vpp Max
64-Pin Thin QFP Package
Multimedia
Video Capture
Video Editing
Security Applications
Analog Input Bandwidth: >130 MHz
Selectable Clamping Function for YUV or
RGB Applications
D
High-Precision Clamp: ±0.5 LSB
D
Selectable Output Data Format for 4:4:4
(RGB, YUV), 4:2:2 and 4:1:1 (YUV) Format
D
NTSC or PAL Compliant
description
The TLV5734 is a triple 8-bit converter with high-precision clamp for digitizing video signals in RGB or YUV color
spaces. The device supports pixel rates up to 30 MSPS. The TLV5734 is powered from a single 3.3-V supply.
Separate clamping levels are provided for the RGB and YUV analog component video inputs. The clamp timing
window is provided by an external pulse. The output-data formatter selects from output formats of 4:4:4, 4:1:1,
and 4:2:2. For RGB applications, the 4:4:4 output format with clamp can be used. The TLV5734 is characterized
for operation from –20°C to 75°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
T
A
64-PIN THIN QUAD FLATPACK
–20°C to 75°C
TLV5734PAG
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
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1
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
pin assignments
PAG PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
RT A
RB A
CLP OUT C
RT C
1
2
47
46
45
44
43
42
41
40
39
EXTCLP
OEB A
QA DGND
AD8
RB C
3
AGND
QC DGND
CD1
4
5
6
AD7
CD2
7
AD6
CD3
8
AD5
CD4
9
AD4
CD5
10
11
AD3
38 CD6
37 CD7
36 CD8
AD2 12
AD1 13
14
15
16
35
34
33
QC DV
OEB C
G/Y
QA DV
DD
DD
DGND
QB DV
DD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
functional block diagram
DV
DGND
DD
CLK A
8
8
8
AD[8:1]
QA DV
AIN(G/Y)
RT A
ADC
DD
Data
8
8
8
Latch
QA DGND
OEB A
RB A
Clamp
Circuit
CLPV A
CLP OUT A
A AV
CC
CLK B
ADC
GND A
8
8
8
BD[8:1]
BIN(B/U)
RT B
QB DV
DD
Output
Formatter
Data
Latch
QB DGND
OEB B
RB B
Clamp
Circuit
CLPV B
CLP OUT B
B AV
CC
CLK C
ADC
GND B
8
8
8
CIN(R/V)
RT C
CD[8:1]
QC DV
DD
Data
Latch
QC DGND
OEB C
RB C
Clamp
Circuit
CLPV C
CLP OUT C
C AV
CC
MODE0
MODE1
GND C
CLK A
CLK B
CLK C
Output
Format
Selector
Clock
Generator
EXTCLP
Clamp
Control
G/Y
CLK
INIT
3
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
Terminal Functions
TERMINAL
†
I/O
TYPE
DESCRIPTION
NAME
NO.
62
A AV
I
O
I
A
D
A
A
A
D
Analog supply (3.3 V) for ADC A
CC
AD8–AD1
6–13
45
Data output of ADC A (MSB:AD8, LSB:AD1) (format 1, format 2, format 3)
Substrate ground
AGND
AIN
63
I
Analog input of ADC A. Used for G/Y
Analog supply (3.3 V) for ADC B
B AV
CC
55
I
BD8–BD1
17–24
O
Data output of ADC B (MSB:BD8, LSB:BD1) (format 2)
Data output of ADC B, C (format 1, format 3)
BIN
56
50
I
I
A
A
D
Analog input of ADC B. Uses for B/U
Analog supply (3.3 V) for ADC C
C AV
CC
CD8–CD1
36–43
O
Data output of ADC C (MSB:CD8, LSB:CD1) (format 2)
When MODE1 = L, MODE0 = L, CD8 outputs MSB flag of BD8–BD5 (format 1)
When MODE1 = L, MODE0 = L, CD7 outputs LSB flag of BD8–BD5 (format 1)
When MODE1 = H, MODE0 = L, CD8 outputs B channel flag of BD8–BD1 (format 3)
When MODE1 = H, MODE0 = L, CD7 outputs B channel flag of BD8–BD1 (CD8–CD1) (format 3)
CIN
51
31
I
I
A
D
Analog input of ADC C. Used for R/V
CLK
Clock input. The clock frequency is four times the frequency subcarrier (fsc) for most video
systems (see Table 3).
CLP OUT A
CLP OUT B
CLP OUT C
CLPV A
60
53
48
61
54
49
15
26
O
O
O
I
A
A
A
A
A
A
D
D
Clamp bias current of ADC A. A resistor-capacitor network sets the clamp settling time.
Clamp bias current of ADC B. A resistor-capacitor network sets the clamp settling time.
Clamp bias current of ADC C. A resistor-capacitor network sets the clamp settling time.
Clamp level of ADC A (see Table 1)
CLPV B
I
Clamp level of ADC B (see Table 1)
CLPV C
I
Clamp level of ADC C (see Table 1)
DGND
I
Digital ground for all logic
‡
DV
I
Digital supply (3.3 V) for all logic. DV , QA DV , QB DV , and QC DV are tied together
DD DD DD DD
internally.
DD
EXTCLP
GND A
GND B
GND C
G/Y
3
I
I
I
I
D
A
A
A
D
External clamp pulse input (active high)
Analog ground of ADC A
64
57
52
33
Analog ground of ADC B
Analog ground of ADC C
Video input mode selector, low for RGB, high for YUV
I
INIT
30
I
D
Output initialized. The output data is synchronized with the first falling edge of CLK after INIT
changes from low to high (see Figure 1). INIT is a control terminal that allows the external system
to initialize the TLV5734 data conversion cycle.
MODE1,0
NC
28,29
32
4
I
I
I
I
I
I
I
D
D
D
D
D
D
D
Output format mode selector (see Table 4)
NC should be tied low when using this device.
Output enable of ADC A (active low)
OEB A
OEB B
OEB C
QA DGND
27
34
5
Output enable of ADC B (active low)
Output enable of ADC C (active low)
Digital ground for output driver of ADC A
‡
QA DV
DD
14
Digital supply (3.3 V) for output driver of ADC A. DV , QA DV , QB DV , and QC DV
are
DD
DD
DD
DD
tied together internally.
QB DGND
25
I
D
Digital ground for output driver of ADC B
†
‡
A = analog pin, D = digital pin
These pins should be driven from the same power supply.
4
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
Terminal Functions (Continued)
TERMINAL
NAME
†
I/O
TYPE
DESCRIPTION
Digital supply (3.3 V) for output driver of ADC B. DV , QA DV , QB DV , and QC DV
NO.
‡
QB DV
16
I
D
are
are
DD
DD
DD
DD
DD
tied together internally.
QC DGND
44
35
I
I
D
D
Digital ground for output driver of ADC C
‡
QC DV
Digital supply (3.3 V) for output driver of ADC C. DV , QA DV , QB DV , and QC DV
DD DD DD
DD
DD
tied together internally.
RB A
RB B
RB C
RT A
RT B
RT C
2
I
I
I
I
I
I
A
A
A
A
A
A
Bottom reference voltage level for ADC A
Bottom reference voltage level for ADC B
Bottom reference voltage level for ADC C
58
46
1
Top reference voltage level for ADC A (nominal RT A – RB A = 1 V for video signals)
Top reference voltage level for ADC B (nominal RT B – RB B = 1 V)
Top reference voltage level for ADC C (nominal RT C – RB C = 1 V)
59
47
†
‡
A = analog pin, D = digital pin
These pins should be driven from the same power supply.
5
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
detailed description
ADC
The TLV5734 includes three 8-bit A/D channels. Each ADC employs a three-stage switched capacitor-pipelined
architecture to achieve high accuracy and high throughput with low power consumption. The analog input is
sampled when the external clock, CLK, goes from low to high. The INIT signal is used to initialize the order of
output data when operating in the 4:2:2 or 4:1:1 output format mode. After INIT changes from low to high, the
first reinitialized output data is available after a 5-clock-cycle delay from the rising edge of the CLK (see the
timing diagram, Figure 1).
Pulling the OEB pin (pin 4, 27 or 34) high puts the corresponding ADC output in the high-impedance state.
t
w(H)
t
w(L)
CLK
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
t
su
t
h
t
reset
INIT
Analog Input
Sampling Instance
N+3
N+5
N+1
N–1
N+7
N+6
Analog Input
N
N+4
N+2
Output Re-initialized
Data Latency = 5 CLKs
t
pd
Digital Output
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
Figure 1. Timing Diagram
6
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
detailed description (continued)
clamp function
The TLV5734 employs a clamp feedback circuit on each channel to correct the clamp level mismatch
contributed by the offset of each channel. The clamp levels are used for either the YUV or RGB video signal.
Figure 2 shows the clamp circuit and the external R and C required for the clamp operation. The clamp circuit
also requires an externally generated active-high clamp pulse to be applied to input EXTCLP. The clamp pulse
defines the timing window during which the clamp circuit is enabled. For video applications, the clamp pulse
must be applied during the back porch of the sync portion of the horizontal blanking interval. For an embedded
sync video input (G/Y), the external clamp high must start after the gap A between sync and clamp start (see
Figure 3 and Table 3).
The clamp is enabled by applying a logic high on the EXTCLP input. This closes switch SW1 and enables the
digital comparator. The output of the ADC is then compared digitally with the preset clamp level (as defined in
Table 1), then the voltage on clamp capacitor C2 is charged/discharged through the 3-state buffer and resistor
R to make the ADC output equal to the desired clamp level. Once the desired clamp level is attained, the 3-state
buffer is put in the high-impedance mode and the clamp voltage is stored on input capacitor C1 until the next
clamp pulse.
TLV5734
C1
0.1 µF
ADC
ADC_OUT
Video Input
SW1
CLPV
EXTCLP
CLP_OE
C_OUT
Digital
Comparator
R
15 kΩ
CLP OUT
Preset Clamp Level
(See Table 1)
C2
0.1 µF
3-State
Buffer
Figure 2. Clamp Feedback Circuit
Table 1. Preset Clamp Level
YUV (G/Y = HIGH)
RGB (G/Y = LOW)
OUTPUT CODE APPLICATION
ADC CHANNEL
OUTPUT CODE
APPLICATION
CHANNEL A
CHANNEL B
CHANNEL C
00010000b
10000000b
10000000b
Y
00010000b
00010000b
00010000b
R, G, B
R, G, B
R, G, B
U, V
U, V
7
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
clamp function (continued)
Table 2. Clamp Operation
ADC_OUT
<REF
CLP_OE
CLP_OUT
HIGH
BUFFER
RC
Charge
Hold
1
0
1
H
Z
L
= REF
HIGH
> REF
LOW
Discharge
AIN
Active Video
A
B
EXTCLP
Figure 3. Clamp Timing Diagram
Table 3. Clamp Timing
TIME INTERVAL
A (Min.)
NTSC 4fsc = 14.318 MHz
PAL 4fsc = 17.745 MHz
BT 601 × 2 = 27 MHz (NTSC)
16 clocks (0.59 µs)
8 clocks (0.56 µs)
16 clocks (1.12 µs)
8 clocks (0.45 µs)
16 clocks (0.90 µs)
B (Min.)
32 clocks (1.19 µs)
output data format
The TLV5734 can select three output data formats for different video data processing by the combination of
MODE0 and MODE1 (see Table 4). The output is synchronous with the rising edge of CLK that comes after INIT
is pulled high. Timing diagrams and output data tables for formats 1, 2, and 3 are shown in Figure 4 through
Figure 6 and Table 5 through Table 7.
Table 4. Output Data Format Selection
CONDITION
OUTPUT DATA
MODE 1
MODE 0
OUTPUT DATA FORMAT
RATIO OF Y:U:V
L
L
L
H
L
Format 1
Format 2
Format 3
Not used
4:1:1
4:4:4
4:2:2
N/A
H
H
H
8
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SLES026A – APRIL 2002 – REVISED JANUARY 2003
output data format (continued)
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
INIT
OEB A
OEB B
OEB C
5 CLK
OUTPUT DATA A
A0
A1
A2
A3
A4
A5
A6
A7
OUTPUT DATA B
BD[8:5]
B08
B07
C08
C07
B06
B05
C06
C05
B04
B03
C04
C03
B02
B01
C02
C01
B48
B47
C48
C47
B46
B45
C46
C45
B44
B43
C44
C43
B42
B41
C42
C41
BD[4:1] HI-Z
t
pd
OUTPUT DATA C
CD8
MSB
CD7
LSB
CD[6:1] HI-Z
Figure 4. Format 1 (4:1:1) Timing Diagram
Table 5. Output Format 1 (4:1:1)
OUTPUT DATA
†
CLK
CHANNEL OF ADC
BIT
6
7
8
9
10
11
12
13
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
A08
A07
A06
A05
A04
A03
A02
A01
A18
A17
A16
A15
A14
A13
A12
A11
A28
A27
A26
A25
A24
A23
A22
A21
A38
A37
A36
A35
A34
A33
A32
A31
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
A77
A76
A75
A74
A73
A72
A71
A
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
B08
B07
C08
C07
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B06
B05
C06
C05
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B04
B03
C04
C03
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B02
B01
C02
C01
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B48
B47
C48
C47
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B46
B45
C46
C45
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B44
B43
C44
C43
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B42
B41
C42
C41
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
H
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
C
†
The first ADC sampling clock is denoted as CLK 0.
A06 is an example entry in the table where A shows the ADC channel, 0 represents the sampling order, and 6 is the bit number.
9
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
ꢀ ꢇꢈ ꢉ ꢁ ꢊ ꢋ ꢌꢍ ꢈ ꢀ ꢅ ꢎꢌꢏꢐ ꢉ ꢐ ꢑꢒ ꢓ ꢔ ꢈ ꢀꢕ ꢕꢈ ꢖ ꢕꢌ
ꢉ ꢇꢊꢓ ꢈ ꢐꢈ ꢗꢘ ꢓ ꢁ ꢑꢏ ꢉ ꢙꢗ ꢇ ꢚ ꢛꢂ ꢜ ꢇꢖ ꢍ ꢂ ꢈ ꢒꢊ ꢗ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
INIT
OEB A
OEB B
OEB C
5 CLK
t
t
t
pd
OUTPUT DATA A
OUTPUT DATA B
OUTPUT DATA C
A0
B0
C0
A1
B1
C1
A2
B2
C2
A3
B3
C3
A4
B4
C4
A5
B5
C5
A6
B6
C6
A7
B7
C7
pd
pd
Figure 5. Format 2 (4:4:4) Timing Diagram
Table 6. Output Format 2 (4:4:4)
OUTPUT DATA
†
CLK
CHANNEL OF ADC
BIT
6
7
8
9
10
11
12
13
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
A08
A07
A06
A05
A04
A03
A02
A01
A18
A17
A16
A15
A14
A13
A12
A11
A28
A27
A26
A25
A24
A23
A22
A21
A38
A37
A36
A35
A34
A33
A32
A31
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
A77
A76
A75
A74
A73
A72
A71
A
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
B08
B07
B06
B05
B04
B03
B02
B01
B18
B17
B16
B15
B14
B13
B12
B11
B28
B27
B26
B25
B24
B23
B22
B21
B38
B37
B36
B35
B34
B33
B32
B31
B48
B47
B46
B45
B44
B43
B42
B41
B58
B57
B56
B55
B54
B53
B52
B51
B68
B67
B66
B65
B64
B63
B62
B61
B78
B77
B76
B75
B74
B73
B72
B71
B
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
C08
C07
C06
C05
C04
C03
C02
C01
C18
C17
C16
C15
C14
C13
C12
C11
C28
C27
C26
C25
C24
C23
C22
C21
C38
C37
C36
C35
C34
C33
C32
C31
C48
C47
C46
C45
C44
C43
C42
C41
C58
C57
C56
C55
C54
C53
C52
C51
C68
C67
C66
C65
C64
C63
C62
C61
C78
C77
C76
C75
C74
C73
C72
C71
C
†
The first ADC sampling clock is denoted as CLK 0.
A06 is an example entry in the table where A shows the ADC channel, 0 represents the sampling order, and 6 is the bit number.
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ꢀꢁꢂ ꢃꢄ ꢅꢆ
ꢀ ꢇꢈꢉ ꢁꢊ ꢋ ꢌꢍꢈ ꢀ ꢅ ꢎ ꢌꢏꢐ ꢉꢐ ꢑꢒꢓ ꢔꢈ ꢀꢕ ꢕ ꢈꢖ ꢕ ꢌ
ꢉꢇꢊ ꢓꢈꢐ ꢈꢗ ꢘ ꢓꢁ ꢑꢏ ꢉ ꢙ ꢗꢇ ꢚꢛꢂ ꢜꢇꢖ ꢍ ꢂ ꢈꢒ ꢊ ꢗ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
INIT
OEB A
OEB B
OEB C
5 CLK
t
t
t
pd
OUTPUT DATA A
OUTPUT DATA B
A0
B0
A1
A2
B2
A3
C2
A4
B4
A5
C4
A6
B6
A7
C6
pd
pd
C0
OUTPUT DATA C
CD8
B
CD7
C
CD[6:1] HI-Z
Figure 6. Format 3 (4:2:2) Timing Diagram
Table 7. Output Format 3 (4:2:2)
OUTPUT DATA
†
CLK
CHANNEL OF ADC
BIT
6
7
8
9
10
11
12
13
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
A08
A07
A06
A05
A04
A03
A02
A01
A18
A17
A16
A15
A14
A13
A12
A11
A28
A27
A26
A25
A24
A23
A22
A21
A38
A37
A36
A35
A34
A33
A32
A31
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
A77
A76
A75
A74
A73
A72
A71
A
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
B08
B07
B06
B05
B04
B03
B02
B01
C08
C07
C06
C05
C04
C03
C02
C01
B28
B27
B26
B25
B24
B23
B22
B21
C28
C27
C26
C25
C24
C23
C22
C21
B48
B47
B46
B45
B44
B43
B42
B41
C48
C47
C46
C45
C44
C43
C42
C41
B68
B67
B66
B65
B64
B63
B62
B61
C68
C67
C66
C65
C64
C63
C62
C61
B
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
C
†
The first ADC sampling clock is denoted as CLK 0.
A06 is an example entry in the table where A shows the ADC channel, 0 represents the sampling order, and 6 is the bit number.
11
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
ꢀ ꢇꢈ ꢉ ꢁ ꢊ ꢋ ꢌꢍ ꢈ ꢀ ꢅ ꢎꢌꢏꢐ ꢉ ꢐ ꢑꢒ ꢓ ꢔ ꢈ ꢀꢕ ꢕꢈ ꢖ ꢕꢌ
ꢉ ꢇꢊꢓ ꢈ ꢐꢈ ꢗꢘ ꢓ ꢁ ꢑꢏ ꢉ ꢙꢗ ꢇ ꢚ ꢛꢂ ꢜ ꢇꢖ ꢍ ꢂ ꢈ ꢒꢊ ꢗ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
‡
§
Supply voltage, V
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.6 V
CC
DD
Reference voltage input range: V
V
V
V
,
ref(RT A), ref(RT B), ref(RT C), ref(RB A)
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+0.3 V
+0.3 V
ref(RB B), ref(RB C)
CC
CC
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Digital input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.6 V
Digital output voltage range, V
Operating free-air temperature range, T
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+0.3 V
O
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
§
V
CC
V
DD
refers to all analog supplies: A AV , B AV , and C AV .
refers to all digital supplies: DV , QA DV , QB DV , and QC DV
DD DD DD
CC CC CC
DD.
recommended operating conditions
MIN NOM
MAX
3.6
3.6
2.2
1.2
1
UNIT
(Analog) V
3
3
3.3
3.3
2
CC
¶
Supply voltage
V
(Digital) V
DD
V
, V
, V
1.8
0.8
ref(RT A) ref(RT B) ref(RT C)
Reference input voltage
– V
V
V
, V , V
1
ref(RB A) ref(RB B) ref(RB C)
– V , V – V
V
, V
ref(RB A) ref(RT B)
V
V
ref(RT A)
ref(RB B) ref(RT C) ref(RB C)
High-level digital input voltage, V
IH
2
Low-level digital input voltage, V
IL
0.8
V
High-level pulse duration, t
(at 50% of amplitude level)
(at 50% of amplitude level)
16.7
16.7
ns
ns
ns
w(H)
Low-level pulse duration, t
Setup time for INIT input, t
w(L)
3
0
su
Hold time for INIT input, t
h
Reset time for INIT input, t
33.3
–20
ns
reset
Operating free-air temperature, T
75
°C
A
¶
Within the electrical and operating characteristics table, when the term V
DD
is used, DV
and all X DV terminals are tied together, and when
DD
DD
the term V
is used, all X AV terminals are tied together.
CC
CC
12
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ꢀꢁꢂ ꢃꢄ ꢅꢆ
ꢀ ꢇꢈꢉ ꢁꢊ ꢋ ꢌꢍꢈ ꢀ ꢅ ꢎ ꢌꢏꢐ ꢉꢐ ꢑꢒꢓ ꢔꢈ ꢀꢕ ꢕ ꢈꢖ ꢕ ꢌ
ꢇꢊ ꢓꢈꢐ ꢈꢗ ꢘ ꢓꢁ ꢑꢏ ꢉ ꢙ ꢗꢇ ꢚꢛꢂ ꢜꢇꢖ ꢍ ꢂ ꢈꢒ ꢊ ꢗ
ꢉ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
electrical characteristics at V
= V
= 3.3 V, V
= 2.0 V, V
= 1.0 V, f(CLK) = 30 MHz,
DD
CC
ref(RT)
ref(RB)
T = 25°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.5
450
5
MAX
UNIT
LSB
Ω
Clamp level accuracy
±1
R
C
Reference resistance
Measured between RT and RB
REF
I
Analog input capacitance
pF
I
I
High-level digital input current
Low-level digital input current
High-level digital output voltage
Low-level digital output voltage
High-level digital output leakage current
Low-level digital output leakage current
Supply current
V
V
V
V
= V
DD
+ 0.3 V
10
10
µA
µA
V
IH
IH
= 0 V
IL
IL
V
V
= 3 V to 3.6 V, I
= 3 V to 3.6 V, I
= –50 µA
= 50 µA
V –0.7
DD
OH
DD
DD
OH
0.5
10
V
OL
OL
I
I
OEB A = OEB B = OEB C = HI, V
= V
DD
µA
µA
mA
mW
OH(lkg)
OH
OL
OEB A = OEB B = OEB C = HI, V
= 0 V
10
OL(lkg)
f
f
= 30 MSPS, NTSC ramp wave input
73
82
91
S
Power dissipation
= 30 MSPS, NTSC ramp wave input
240
270
300
S
operating characteristics V
= V
= 3.3 V, V
= 2.0 V, V
= 1.0 V, f(CLK) = 30 MHz,
DD
CC
ref(RT)
ref(RB)
T = –20°C to 75°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LSB
LSB
MSPS
MHz
ns
DNL
INL
Differential nonlinearity
Integral nonlinearity
Maximum conversion rate
Analog input bandwidth
Digital output delay time
Zero-scale error
f
f
= 30 MSPS
= 30 MSPS
±0.2
±0.5
S
±0.3 ±0.75
S
f
S
30
BW
At –3 dB, T = 25°C
130
18
A
t
pd
C = 10 pF (by design)
L
V
= REFT – REFB = 1 V
= REFT – REFB = 1 V
–16
–13
–2
2
15
17
mV
ref
Full-scale error
V
mV
ref
Sampling delay time
By design
4.3
ns
13
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
ꢀ ꢇꢈ ꢉ ꢁ ꢊ ꢋ ꢌꢍ ꢈ ꢀ ꢅ ꢎꢌꢏꢐ ꢉ ꢐ ꢑꢒ ꢓ ꢔ ꢈ ꢀꢕ ꢕꢈ ꢖ ꢕꢌ
ꢉ ꢇꢊꢓ ꢈ ꢐꢈ ꢗꢘ ꢓ ꢁ ꢑꢏ ꢉ ꢙꢗ ꢇ ꢚ ꢛꢂ ꢜ ꢇꢖ ꢍ ꢂ ꢈ ꢒꢊ ꢗ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS
POWER
vs
CURRENT
vs
FREQUENCY
FREQUENCY
290
270
250
230
210
100
80
60
40
20
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
f – Frequency – MHz
f – Frequency – MHz
Figure 7
Figure 8
14
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ꢀꢁꢂ ꢃꢄ ꢅꢆ
ꢀ ꢇꢈꢉ ꢁꢊ ꢋ ꢌꢍꢈ ꢀ ꢅ ꢎ ꢌꢏꢐ ꢉꢐ ꢑꢒꢓ ꢔꢈ ꢀꢕ ꢕ ꢈꢖ ꢕ ꢌ
ꢉꢇꢊ ꢓꢈꢐ ꢈꢗ ꢘ ꢓꢁ ꢑꢏ ꢉ ꢙ ꢗꢇ ꢚꢛꢂ ꢜꢇꢖ ꢍ ꢂ ꢈꢒ ꢊ ꢗ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS
0.4
0.2
0.0
–0.2
–0.4
0
0
0
50
100
150
200
250
250
250
Code
Figure 9. Typical Differential Nonlinearity, Channel A
0.4
0.2
0.0
–0.2
–0.4
50
100
150
200
Code
Figure 10. Typical Integral Nonlinearity, Channel A
0.4
0.2
0.0
–0.2
–0.4
50
100
150
200
Code
Figure 11. Typical Differential Nonlinearity, Channel B
15
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
ꢀ ꢇꢈ ꢉ ꢁ ꢊ ꢋ ꢌꢍ ꢈ ꢀ ꢅ ꢎꢌꢏꢐ ꢉ ꢐ ꢑꢒ ꢓ ꢔ ꢈ ꢀꢕ ꢕꢈ ꢖ ꢕꢌ
ꢉ ꢇꢊꢓ ꢈ ꢐꢈ ꢗꢘ ꢓ ꢁ ꢑꢏ ꢉ ꢙꢗ ꢇ ꢚ ꢛꢂ ꢜ ꢇꢖ ꢍ ꢂ ꢈ ꢒꢊ ꢗ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS
0.4
0.2
0.0
–0.2
–0.4
0
0
0
50
100
150
200
250
250
250
Code
Figure 12. Typical Integral Nonlinearity, Channel B
0.4
0.2
0.0
–0.2
–0.4
50
100
150
200
Code
Figure 13. Typical Differential Nonlinearity, Channel C
0.4
0.2
0.0
–0.2
–0.4
50
100
150
200
Code
Figure 14. Typical Integral Nonlinearity, Channel C
16
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ꢀꢁꢂ ꢃꢄ ꢅꢆ
ꢀ ꢇꢈꢉ ꢁꢊ ꢋ ꢌꢍꢈ ꢀ ꢅ ꢎ ꢌꢏꢐ ꢉꢐ ꢑꢒꢓ ꢔꢈ ꢀꢕ ꢕ ꢈꢖ ꢕ ꢌ
ꢉꢇꢊ ꢓꢈꢐ ꢈꢗ ꢘ ꢓꢁ ꢑꢏ ꢉ ꢙ ꢗꢇ ꢚꢛꢂ ꢜꢇꢖ ꢍ ꢂ ꢈꢒ ꢊ ꢗ
SLES026A – APRIL 2002 – REVISED JANUARY 2003
MECHANICAL DATA
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,50
48
M
0,08
0,17
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–ā7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
17
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLV5734PAG
ACTIVE
TQFP
PAG
64
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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