TLV320AIC1110_14 [TI]
PCM CODEC;
| 型号： | TLV320AIC1110_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCM CODEC PC |
| 文件： | 总39页 (文件大小：505K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV320AIC1110
SLAS359 – DECEMBER 2001
PCM CODEC
ꢀ
ꢀ
Capable of Driving 32 Ω Down to a 8-Ω
Speaker
FEATURES
ꢀ
ꢀ
2.7-V to 3.3-V Operation
Programmable Power Down Modes
Designed for Analog and Digital Wireless
ꢀ
Pin Compatible to the TLV320AIC1103 and
TLV320AIC1109 Devices for TQFP Only
Handsets and Telecommunications
Applications
ꢀ
Available in a 32-Pin Thin Quad Flatpack
ꢀ
ꢀ
Two Differential Microphone Inputs
(TQFP) Package and MicroStar Junior
ꢂ
B
G
A
Differential Earphone Outputs and One
Single-Ended Earphone Output
APPLICATIONS
ꢀ
ꢀ
Earphone and Microphone Mute
ꢀ
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Digital Handset
Digital Headset
Programmable Transmit, Receive, and
Sidetone Paths With Extended Gain and
Attenuation Ranges
Cordless Phones
Digital PABX
ꢀ
ꢀ
ꢀ
ꢀ
Programmable for 15-Bit Linear Data or 8-Bit
Companded (µ-law and A-law) Mode
Digital Voice Recording
Supports PCM Clock Rates of 128 kHz and
2.048 MHz
DESCRIPTION
The TLV320AIC1110 provides extended gain and
attenuation flexibility for transmit, receive, and sidetone
paths. A differential earphone output is capable of
driving speaker loads as low as 8 Ω for use in speaker
phone applications. The single tone function on the
TLV320AIC1110 generates a single tone output of up to
8 kHz. The resolution of the DTMF tone is also
selectableto7.8125Hz, 15.625Hz, or31.25Hzthrough
the interface control. The analog switch provides more
control capabilities for voice-band audio processor
(PCM codec).
Pulse Density Modulated (PDM) Buzzer
Output
2
On-Chip I C Bus, Which Provides Simple,
Standard, Two-Wire Serial Interface With
Digital ICs
ꢀ
ꢀ
Dual-Tone Multifrequency (DTMF) and
Single-Tone Generator Capable of up to 8-kHz
Tone With Three Selectable Resolutions of
7.8125 Hz, 15.625 Hz, and 31.25 Hz
2-Channel Auxiliary Multiplexer (MUX) (Analog
ꢁ
Switch)
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either V
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
CC
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
These options are available on some devices. Please see the table of comparison for the last two generations of PCM codecs.
MicroStar Junior is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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TLV320AIC1110
SLAS359 – DECEMBER 2001
DESCRIPTION (Continued)
The PCM codec is an analog-digital interface for voice band signals designed with a combination of coders and
decoders (codecs) and filters. It is a low-power device with companding options and programming features, and
it meets the requirements for communication systems, including the cellular phone. The device operates in
2
either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I C interface.
A coder, an analog-to-digital converter or ADC, digitizes the analog voice signal, and a decoder, a
digital-to-analog converter or DAC, converts the digital-voice signal to an analog output. The PCM codec
provides a companding option to overcome the bandwidth limitations of telephone networks without degrading
the sound quality. The human auditory system is a logarithmic system in which high amplitude signals require
less resolution than low amplitude signals. Therefore, an 8-bit code word with nonuniform quantization (µ-law
or A-law) has the same quality as 13-bit linear coding. The PCM codec provides better digital code words by
generating a 15-bit linear coding option.
The human voice is effective from a frequency range of 300 Hz to 3300 Hz in telephony applications. In order
to eliminate unwanted signals, the PCM codec design has two types of filters that operate in both the transmit
and receive path. A low-pass filter attenuates the signals over 4 kHz. A selectable high-pass filter cleans up the
signals under 100 Hz. This reduces noise that may have coupled in from 50/60-Hz power cables. The high-pass
filter is bypassed by selecting the corresponding register bit.
2
ThePCMcodechasmanyprogrammingfeaturesthatarecontrolledusinga2-wirestandardserialI Cinterface.
This allows the device to interface with many digital ICs such as a DSP or a microprocessor. The device has
seven registers: power control, mode control, transmit PGA, receive PGA, high DTMF, low DTMF, and auxiliary
2
mode control. Some of the programmable features that can be controlled by I C interface include:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
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ꢀ
Transmit amplifier gain
Receive amplifier gain
Sidetone gain
Volume control
Earphone control
PLL power control
Microphone selection
Transmit channel high-pass filter control
Receive channel high-pass filter control
Companding options and selection control
PCM loopback
DTMF control
Pulse density modulated control
The PCM codec is also capable of generating its own internal clocks from a 2.048-MHz master clock input.
2
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PBS PACKAGE
(TOP VIEW)
24 23 22 21 20 19 18 17
16
25
26
27
28
PLLV
PCMO
PCMI
DD
15
14
13
EARV
SS
EAR1ON
EARV
DV
DV
SS
DD
DD
12
EAR1OP
EARV
SCL
29
30
31
32
11 SDA
10
9
SS
EAR2O
AV
MUXOUT2
MUXOUT1
DD
1
2
3
4
5
6
7
8
3
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TLV320AIC1110
SLAS359 – DECEMBER 2001
MicroStar Junior (GQE) PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
AV
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
MBIAS
MIC1P
MIC1N
MIC2P
MIC2N
REXT
MCLK
NC
NC
NC
NC
NC
RESET
PWRUPSEL
BUZZCON
PCMSYN
PCMCLK
PCMO
G
H
J
MUXIN
AV
SS
4
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PCMIN
PCMSYN
PCMCLK
PCMOUT
MIC1P
MIC1N
RX Vol
Control
g = –18 dB
to
Voice
PCM
Interface
0 dB
or
EAR1OP
EAR1ON
6 dB
Ear
Amp1
0 dB
MIC
Amplifier
2
g = 6
or
RX Filter
and PGA
g = – 6 dB
to
MIC
Amplifier
1
g =
TX Filter
and PGA
g = –10 dB
to
Digital
Modulator
and Filter
DTMF
GAIN
MUX
Analog
Modulator
23.5 dB
+6 dB
0 dB
18 dB
Sidetone
g = –24 db
to
DTMF
–12 to
12 dB
in 6dB
Steps
Ear
Amp2
EAR2O
MIC2P
MIC2N
–12 dB
Control Bus
DTMF
OUT
OUT
Buzzer
Control
IN
MUX
BUZZCON
Generator
REF
2
I C
PLL
Power and RESET
I/F
TLV320AIC1110
SLAS359 – DECEMBER 2001
detailed description
power on/reset
The power for the various digital and analog circuits is separated to improve the noise performance of the
device. An external reset must be applied to the active low RESET terminal to assure reset upon power on and
to bring the device to an operational state. After the initial power-on sequence, the device can be functionally
2
powered up and powered down by writing to the power control register through the I C interface. The device
has a pin-selectable power up in the default mode option. The hardwired pin-selectable PWRUPSEL function
allows the PCM codec to power up in the default mode and to be used without a microcontroller.
reference
A precision band gap reference voltage is generated internally and supplies all required voltage references to
operate the transmit and receive channels. The reference system also supplies bias voltage for use with an
electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting
at terminal REXT.
2
I C control interface
2
2
The I C interface is a two-wire bidirectional serial interface. The I C interface controls the PCM codec by writing
data to seven control registers:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power control
Mode control
Transmit PGA and sidetone control
Receive PGA gain and volume control
DTMF routing
Tone selection control
Auxiliary control
There are two power-up modes which may be selected at the PWRUPSEL terminal: (1) The PWRUPSEL state
2
(V
at terminal 20) causes the device to power up in the default mode when power is applied. Without an I C
DD
interface or controlling device, the programmable functions are fixed at the default gain levels, and functions
such as the sidetone and DTMF are not accessible. (2) The PWRUPSEL state (ground at terminal 20) causes
2
the device to go to a power-down state when power is applied. In this mode, an I C interface is required to power
up the device.
phase-locked loop (PLL)
The phase-lock loop generates the internal clock frequency required for digital filters and modulators by phase
locking to 2.048-MHz master clock input.
PCM interface
The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is
transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly
to the 128-kHz or 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or
derived from the master clock and used as an interrupt to the host controller.
microphone amplifiers
The microphone input is a switchable interface for two differential microphone inputs. The first stage is a
low-noise differential amplifier that provides a gain of 23.5 dB. The second-stage amplifier has a selectable gain
of 6 dB or 18 dB.
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TLV320AIC1110
SLAS359 – DECEMBER 2001
detailed description (continued)
analog modulator
The transmit channel modulator is a third-order sigma-delta design.
transmit filter and PGA
The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates either in
2
the 15-bit linear or 8-bit companded µ-law or in the A-law mode, which is selectable through the I C interface.
The transmit PGA defaults to 0 dB.
sidetone
A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path.
The sidetone path defaults to the mute condition. The default gain of -12 dB is set in the sidetone control register.
The sidetone path can be enabled by writing to the power control register.
receive volume control
The receive volume control block acts as an attenuator with a range of –18 dB to 0 dB in 2-dB steps for control
of the receive channel volume. The receive volume control gain defaults to 0 dB.
receive filter and PGA
The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable
2
through the I C interface. The device operates either in the 15-bit linear or the 8-bit µ-law or the A-law
2
companded mode, which is selectable through the I C interface. The gain defaults to –4 dB, representing a
3-dBm level for a 32-Ω load impedance and the corresponding digital full scale PCMI code.
digital modulator and filter
Thesecond-orderdigitalmodulatorandfilterconvertthereceiveddigitalPCMdatatotheanalogoutputrequired
by the earphone interface.
earphone amplifiers
The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and
EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential
output only.
tone generator
The tone generator provides generation of standard DTMF tones which are output to (1) the buzzer driver, as
a PDM signal, (2) the receive path DAC for outputting through the earphone, or (3) as PCMO data. The integer
value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05) (see the
Register Map Addressing section). The tone output is 2 dB higher when applied to the high tone register (04).
ThehighDTMFtonesmustbeappliedtothehigh-toneregister, andthelowDTMFtonestothelow-toneregister.
The tone signals can be generated with three different resolutions at ∆F= 7.8125 Hz, 15.625 Hz, and 31.250 Hz.
The resolution option can be selected by setting the register (06).
analog mux
The analog switch can be used to source an analog signal to two different loads. The output can be reselected
by setting the auxiliary register (06).
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TLV320AIC1110
SLAS359 – DECEMBER 2001
detailed description (continued)
DTMF gain MUX
The DTMF gain MUX selects the signal path and applies the appropriate gain setting. Therefore the device is
either in tone mode or in voice mode. When set in the voice mode, the gain is controlled by the auxiliary register
and is set to 0 dB or 6 dB. When set in the tone mode, the gain is from –12 dB to 12 dB in 6-dB steps which
is set by the volume control register. The gain setting is controlled by the RXPGA register. This will not create
any control contention since the device is working in one mode at a time.
Terminal Functions
†
TERMINAL
NO.
I/O
DESCRIPTION
NAME
µBGA
A1
J1
TQFP
32
8
AV
AV
I
I
Analog positive power supply
DD
Analog negative power supply (use for ground connection)
Buzzer output, a pulse-density modulated signal to apply to external buzzer driver
Digital positive power supply
Digital negative power supply
Earphone 1 amplifier output (–)
Earphone 1 amplifier output (+)
Earphone 2 amplifier output
SS
BUZZCON
F9
19
13
14
27
29
31
28
30, 26
1
O
I
DV
DV
J6
DD
SS
J7
I
EAR1ON
EAR1OP
EAR2O
A6
A4
A2
A5
A3, A7
B1
C9
C1
D1
E1
F1
O
O
O
I
EARV
EARV
Analog positive power supply for the earphone amplifiers
Analog negative power supply for the earphone amplifiers
Microphone bias supply output, no decoupling capacitors
Master system clock input (2.048 MHz, digital)
MIC1 input (+)
DD
I
SS
MBIAS
O
I
MCLK
22
2
MIC1P
I
MIC1N
3
I
MIC1 input (–)
MIC2P
4
I
MIC2 input (+)
MIC2N
5
I
MIC2 input (–)
MUXIN
MUXOUT1
MUXOUT2
PCMI
H1
J2
7
I
Analog MUX input
9
I
Analog MUX output
J3
10
15
16
18
17
24
25
20
6
I
Analog MUX output
J8
I
Receive PCM input
PCMO
J9
O
I
Transmit PCM output
PCMSYN
PCMCLK
G9
H9
A9
A8
E9
G1
D9
J5
PCM frame sync
I
PCM data clock
PLLV
PLLV
I
PLL negative power supply
SS
I
PLL digital power supply
DD
PWRUPSEL
REXT
I
Selects the power-up default mode
I/O Internalreferencecurrentsettingterminal(useprecision100-kΩ resistor and no filtering capacitors)
RESET
SCL
21
12
11
I
I
Active low reset
2
I C-bus serial clock. This input is used to synchronize the data transfer from and to the PCM codec.
2
SDA
J4
I/O I C-bus serial address/data input/output. This is a bidirectional terminal used to transfer register
control addresses and data into and out of the codec. It is an open-drain terminal and therefore
requires a pullup resistor to V
(typical 10 kΩ for 100 kHz).
DD
V
SS
B9
23
I
Ground return for bandgap internal reference (use for ground connection)
†
All MicroStar Junior BGAꢂ pins that are not mentioned have no internal connection.
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TLV320AIC1110
SLAS359 – DECEMBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, AV , DV , PLLV , EARV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
DD
DD
DD
DD
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
O
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
I
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free air temperature range (industrial temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
COMMENTS
POWER RATING
ABOVE T = 25°C
A
TQFP
702 mW
7.2 mW/°C
270 mW
Low dissipation printed
circuit board (PCB)
MicroStar Junior BGA
MicroStar Junior BGA
660 mW
2.75 W
164 mW/°C
36 mW/°C
220 mW
917 mW
Low dissipation PCB
High dissipation PCB
recommended operating conditions (see Notes 1 and 2)
MIN
NOM
MAX
UNIT
V
Supply voltage, AV , DV , PLLV , EARV
2.7
3.3
DD
DD
DD
DD
High-level input voltage, V
0.7xV
V
IH
DD
Low-level input voltage, V
0.3xV
V
IL
Load impedance between EAR1OP and EAR1ON-R
DD
8 to 32
32
Ω
L
Load impedance for EAR2OP-R
Ω
L
Operating free-air temperature, T
–40
85
ꢃ
C
A
NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, follow the power-on initialization paragraph,
described in the Principles of Operation.
2. Voltages are with respect to AV , DV , PLLV , and EARV
.
SS SS SS SS
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted)
supply current
PARAMETER
TEST CONDITIONS
Operating, EAR1 selected, MicBias disabled
Operating, EAR2 selected, MicBias disabled
MIN
TYP
4.5
MAX
UNIT
mA
6
6
4.5
mA
Power down room temperature, V
not present (see Note 3)
= 3 V, Reg 6 bit 7 = 1, MClk
DD
I
t
Supply current from V
2
10
5
10
30
10
µA
µA
ms
DD
DD
Power down room temperature, V
MClk not present (see Note 3)
= 3 V, , Reg 6 bit 7 = 0,
DD
Power-up time from
power down
on(i)
NOTE 3:
V
= V
V
= V
IHMIN
DD, ILMAX SS.
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TLV320AIC1110
SLAS359 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
digital interface
PARAMETER
High-level output voltage PCMO (BUZZCON)
Low-level output voltage PCMO
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
I
I
= –3.2 mA,
V
= 3 V DV –0.25
OH
OH
DD
DD
DD
= 3.2 mA,
V
= 3 V
0.25
10
10
10
20
5
V
OL
OL
I
V = V
µA
µA
pF
pF
kΩ
IH
IL
I
DD
SS
I
V = V
I
C
C
R
i
Output capacitance
o
L
Load impedance (BUZZCON)
microphone interface
PARAMETER
TEST CONDITIONS
See Note 4
MIN
–5
TYP
MAX
5
UNIT
mV
nA
V
IO
Input offset voltage at MIC1N, MIC2N
Input bias current at MIC1N, MIC2N
Input capacitance at MIC1N, MIC2N
I
IB
–300
300
C
5
3
pF
i
Microphone input referred noise, psophometrically weighted,
(C-message weighted is similar)
MIC amp 1 gain = 23.5 dB
MIC amp 2 gain = 0 dB
V
n
4.7 µV
rms
I
O
max
Output source current—MBIAS
1
1.2
mA
V
Microphone bias supply voltage (see Note 5)
2.3
2.5
60
2.65
V
(mbias)
MICMUTE
–80
dB
Input impedance
Fully differential
35
100
kΩ
NOTES: 4. Measured while MIC1P and MIC1N are connected together. Less than 0.5-mV offset results in 0 value code on PCMOUT.
5. Not a JEDEC symbol.
10
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TLV320AIC1110
SLAS359 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
speaker interface
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
DD
= 2.7 V, fully differential, 8-Ω load,
3-dBm0 output, volume control = –3 dB,
RXPGA = –4 dB level
161
200
V
= 2.7 V, fully differential, 16-Ω load,
DD
3-dBm0 output, volume control = –3 dB,
RXPGA = –2 dB level
128
160
Earphone AMP1 output power (see Note 6)
mW
V
= 2.7 V, fully differential, 32-Ω load,
DD
3-dBm0 output, volume control = –3 dB,
RXPGA = –1 dB level
81
10
100
V
= 2.7 V, single-ended, 32-Ω load,
DD
Earphone AMP2 output power (see Note 6)
Output offset voltage at EAR1
12.5
mW
mV
3-dBm0 output
V
OO
Fully differential
±5
141
90
±30
178
112
63
3-dBm0 input, 8-Ω load
3-dBm0 input, 16-Ω load
3-dBm0 input, 32-Ω load
3-dBm0 input
Maximum output current for EAR1 (rms)
I
O
max
mA
dB
50
Maximum output current for EAR2 (rms)
EARMUTE
17.7
22.1
–80
NOTE 6: Maximum power is with a load impedance of –25%.
transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope
filter bypassed (see Notes 7 and 8)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit reference-signal level (0 dB)
Differential
87.5 mV
124
pp
Differential, normal mode
Differential, extended mode
Overload-signal level (3 dBm0)
Absolute gain error
mV
pp
31.5
0-dBm0 input signal, V
DD
±10%
–1
–0.5
–1
1
0.5
1
dB
MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0
MIC1N, MIC1P to PCMO at –31 dBm0 to –45 dBm0
MIC1N, MIC1P to PCMO at –46 dBm0 to –55 dBm0
Gain error with input level relative to gain at
–10 dBm0 MIC1N, MIC1P to PCMO
dB
–1.2
1.2
NOTES: 7. Unlessotherwisenoted,theanaloginputis0dB,1020-Hzsinewave,where0dBisdefinedasthezero-referencepointofthechannel
under test.
8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mV
rms
.
transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope
filter enabled (see Notes 7 and 8)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit reference-signal level (0 dB)
Differential
87.5 mV
124
pp
Differential, normal mode
Differential, extended mode
Overload-signal level (3 dBm0)
Absolute gain error
mV
pp
31.5
0-dBm0 input signal, V
DD
±10%
–1
–0.5
–1
1
0.5
1
dB
MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0
MIC1N, MIC1P to PCMO at –31 dBm0 to –45 dBm0
MIC1N, MIC1P to PCMO at –46 dBm0 to –55 dBm0
Gain error with input level relative to gain at
–10 dBm0 MIC1N, MIC1P to PCMO
dB
–1.2
1.2
NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the
channel under test.
8
The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mV
.
rms
11
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TLV320AIC1110
SLAS359 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter
bypassed (MCLK = 2.048 MHz)
PARAMETER
TEST CONDITIONS
MIN
–0.5
–0.5
–0.5
–1.5
TYP
MAX
0.5
UNIT
f
f
f
f
f
f
f
f
f
or f
or f
or f
or f
or f
or f
or f
or f
or f
<100 Hz
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
= 200 Hz
= 300 Hz to 3 kHz
= 3.4 kHz
= 4 kHz
0.5
0.5
Gain relative to input signal gain at 1020 Hz, internal high-pass
filter disabled
0
dB
–14
–35
–47
–15
–5
= 4.6 kHz
= 8 kHz
< 100 Hz
= 200 Hz
Gain relative to input signal gain at 1020 Hz, internal high-pass
filter enabled
dB
transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter
selected, transmit high-pass filter enabled (MCLK = 2.048 MHz) (see Note 9)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–27
–8
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
=100 Hz
= 200 Hz
= 250 Hz
= 300 Hz
= 400 Hz
= 500 Hz
= 600 Hz
= 700 Hz
= 800 Hz
= 900 Hz
= 1000 Hz
= 1500 Hz
= 2000 Hz
= 2500 Hz
= 3000 Hz
= 3100 Hz
= 3300 Hz
= 3500 Hz
= 4000 Hz
= 4500 Hz
= 5000 Hz
= 8000 Hz
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
–4
–1.8
–1.5
–1.3
–1.1
–0.8
–0.57
–0.25
0
Gain relative to input signal gain at 1.02 kHz, with slope filter
selected
1.8
4.0
6.5
7.6
7.7
8
6.48
–13
–35
–45
–50
NOTE 9: The pass-band tolerance is ±0.25 dB from 300 Hz to 3500 Hz.
12
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TLV320AIC1110
SLAS359 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter bypassed
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit idle channel noise, psophometrically
weighted
TXPGA gain= 0 dB, MIC Amp 1 gain = 23.5 dB,
MIC Amp 2 gain = 6 dB
–83.5
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at – 30 dBm0
MIC1N, MIC1P to PCMO at – 40 dBm0
MIC1N, MIC1P to PCMO at – 45 dBm0
CCITT G.712 (7.1), R2
27
30
33
36
35
26
24
19
49
51
Transmit signal-to-distortion ratio with
1020-Hz sine-wave input
dBm0
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
dB
CCITT G.712 (7.2), R2
transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter enabled
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit idle channel noise, psophometrically
weighted
TXPGA gain= 0 dB, MIC Amp 1 gain = 23.5 dB,
MIC Amp 2 gain = 6 dB
–83.5
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
CCITT G.712 (7.1), R2
27
30
33
36
35
26
24
19
49
51
Transmit signal-to-total distortion ratio with 1020-Hz
sine-wave input
dBm0
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
dB
CCITT G.712 (7.2), R2
transmit idle channel noise and distortion, linear mode selected, slope filter bypassed
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXPGA gain = 0 dB, MIC Amp 1 gain = 23.5 dB,
MIC Amp 2 gain = 6 dB
Transmit idle channel noise
–83.5
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
50
50
52
56
50
51
43
38
50
65
61
65
59
63
55
52
Transmit signal-to-total distortion ratio with 1020-Hz
sine-wave input
dB
13
www.ti.com
TLV320AIC1110
SLAS359 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
transmit idle channel noise and distortion, linear mode selected, slope filter enabled
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXPGA gain = 0 dB, MIC Amp 1 gain = 23.5 dB,
MIC Amp 2 gain = 6 dB
Transmit idle channel noise
–83.5
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
40
50
50
64
58
50
38
30
50
65
68
70
65
60
50
45
Transmit signal-to-total distortion ratio with
1020-Hz sine-wave input
dB
receive gain and dynamic range, EAR1 selected, linear or companded (µ-law or A-law) mode selected (see
Note 10)
PARAMETER
TEST CONDITIONS
8-Ω load RXPGA = –4 dB
MIN
TYP
3.2
MAX
UNIT
16-Ω load RXPGA = –4 dB
32-Ω load RXPGA = –4 dB
4.05
4.54
Overload signal level (3 dB)
Absolute gain error
V
pp
0 dBm0 input signal, V
DD
±10%
–1
–0.5
–1
1
0.5
1
dB
dB
PCMIN to EAR1ON, EAR1OP at 3 dBm0 to –40 dBm0
PCMIN to EAR1ON, EAR1OP at –41 dBm0 to –50 dBm0
PCMIN to EAR1ON, EAR1OP at –51 dBm0 to –55 dBm0
Gain error with output level relative to gain
at –10 dBm0
–1.2
1.2
NOTE 10: RXPGA = –4 dB for 32 Ω, 16 Ω, or 8 Ω, RXVOL = 0 dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON
and EAR1OP
receive gain and dynamic range, EAR2 selected, linear or companded (µ-law or A-law) mode selected (see
Note 11)
PARAMETER
Receive reference signal level (0 dB)
Overload-signal level (3 dB)
Absolute gain error
TEST CONDITIONS
0 dBm0 PCM input signal
MIN
TYP
1.36
MAX
UNIT
V
V
pp
1.925
pp
0 dBm0 input signal, V
DD
±10%
–1
–0.5
–1
1
0.5
1
dB
PCMIN to EAR2O at 3 dBm0 to –40 dBm0
PCMIN to EAR2O at –41 dBm0 to –50 dBm0
PCMIN to EAR2O at –51 dBm0 to –55 dBm0
Gain error with output level relative to gain
at –10 dBm0
dB
–1.2
1.2
NOTE 11: RXPGA = –1 dB, RXVOL = 0 dB
14
www.ti.com
TLV320AIC1110
SLAS359 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
receive filter transfer, companded mode (µ-law or A-law) or linear mode selected (MCLK = 2.048 MHz) (see
Note 11)
PARAMETER
TEST CONDITIONS
MIN
–0.5
–0.5
–0.5
–1.5
TYP
MAX
0.5
0.5
0.5
0
UNIT
f
f
f
f
f
f
f
f
f
or f
or f
or f
or f
or f
or f
or f
or f
or f
<100 Hz
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
= 200 Hz
= 300 Hz to 3 kHz
= 3.4 kHz
= 4 kHz
Gain relative to input signal gain at 1020 Hz, internal
high-pass filter disabled
dB
–14
–35
–47
–15
–5
= 4.6 kHz
= 8 kHz
<100 Hz
Gain relative to input signal gain at 1020 Hz, internal
high-pass filter enabled
dB
= 200 Hz
NOTE 11. RXPGA = –1 dB, RXVOL = 0 dB
receive idle channel noise and distortion, EAR1 selected, companded mode (µ-law or A-law) selected (see
Note 10)
PARAMETER
Receive noise, psophometrically weighted
Receive noise, C-message weighted
TEST CONDITIONS
PCMIN = 11010101 (A-law)
MIN
TYP
–89
36
MAX
UNIT
–86 dBm0
p
PCMIN = 11111111 (µ-law)
50 µV
rms
PCMIN to EAR1ON, EAR1OP at 3 dBm0
PCMIN to EAR1ON, EAR1OP at 0 dBm0
PCMIN to EAR1ON, EAR1OP at –5 dBm0
PCMIN to EAR1ON, EAR1OP at –10 dBm0
PCMIN to EAR1ON, EAR1OP at –20 dBm0
PCMIN to EAR1ON, EAR1OP at –30 dBm0
PCMIN to EAR1ON, EAR1OP at –40 dBm0
PCMIN to EAR1ON, EAR1OP at –45 dBm0
21
25
36
43
40
38
28
23
Receive signal-to-distortion ratio with 1020-Hz
sinewave input
dB
NOTE 10: RXPGA = –4 dB for 32 Ω, RXVOL = 0 dB, 1020-Hz input signalatPCMI, outputmeasureddifferentiallybetweenEAR1ONandEAR1OP.
receive idle channel noise and distortion, EAR1 selected, linear mode selected (see Note 10)
PARAMETER
TEST CONDITIONS
MIN
TYP
–88
61
MAX
UNIT
Receive noise, (20-Hz to 20-kHz brickwall window)
PCMIN = 000000000000000
–83 dBm0
PCMIN to EAR1ON, EAR1OP at 3 dBm0
PCMIN to EAR1ON, EAR1OP at 0 dBm0
PCMIN to EAR1ON, EAR1OP at –5 dBm0
PCMIN to EAR1ON, EAR1OP at –10 dBm0
PCMIN to EAR1ON, EAR1OP at –20 dBm0
PCMIN to EAR1ON, EAR1OP at –30 dBm0
PCMIN to EAR1ON, EAR1OP at –40 dBm0
PCMIN to EAR1ON, EAR1OP at –45 dBm0
CCITT G.712 (7.1), R2
53
63
60
56
50
45
40
38
50
54
75
72
67
Receive signal-to-distortion ratio with 1020-Hz
sine-wave input
dB
63
50
51
49
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
dB
CCITT G.712 (7.2), R2
NOTE 10: RXPGA = –4 dB for 32 Ω, RXVOL = 0 dB, 1020-Hz input signalatPCMI, outputmeasureddifferentiallybetweenEAR1ONandEAR1OP.
15
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TLV320AIC1110
SLAS359 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
receive idle channel noise and distortion EAR2 selected, companded mode (µ-law or A-law) selected
(see Note 11)
PARAMETER
Receive noise, psophometrically weighted
Receive noise, C-message weighted
TEST CONDITIONS
PCMIN = 11010101 (A-law)
PCMIN = 11111111 (µ-law)
MIN
TYP
–82
36
MAX
UNIT
–78 dBmo
p
50 µV
rms
PCMIN to EAR2O at 3 dBm0
PCMIN to EAR2O at 0 dBm0
PCMIN to EAR2O at –5 dBm0
PCMIN to EAR2O at –10 dBm0
PCMIN to EAR2O at –20 dBm0
PCMIN to EAR2O at –30 dBm0
PCMIN to EAR2O at –40 dBm0
PCMIN to EAR2O at –45 dBm0
21
25
36
43
40
38
28
23
Receive signal-to-distortion ratio with 1020-Hz sinewave input
dB
NOTE 11. RXPGA = –1 dB, RXVOL = 0 dB
receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 11)
PARAMETER
TEST CONDITIONS
PCMIN = 000000000000000
PCMIN to EAR2O at 3 dBm0
PCMIN to EAR2O at 0 dBm0
PCMIN to EAR2O at –5 dBm0
PCMIN to EAR2O at –10 dBm0
PCMIN to EAR2O at –20 dBm0
PCMIN to EAR2O at –30 dBm0
PCMIN to EAR2O at –40 dBm0
PCMIN to EAR2O at –45 dBm0
CCITT G.712 (7.1), R2
MIN
TYP
–83
60
MAX
UNIT
Receive noise, (20-Hz to 20-kHz brickwall window)
–86 dBm0
53
60
58
55
53
51
50
48
50
54
65
62
Receive signal-to-noise + distortion ratio with 1020-Hz sinewave
input
60
dB
60
58
57
52
Intermodulation distortion, 2-tone CCITT method
dB
CCITT G.712 (7.2), R2
NOTE 11: RXPGA = –1 dB, RXVOL = 0 dB
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MIC1N, MIC1P =0 V,
= 3 V + 100 mV
peak to peak
Supply voltage rejection, transmit channel
– 86
–70
dB
V
, f = 0 to 50 kHz
dc
PCM code = positive zero,
= 3 V + 100 mV , f = 0 to 50 kHz
peak to peak
DD
Supply voltage rejection, receive channel,
EAR1 selected (differential)
– 98
–70
dB
dB
dB
V
DD
dc
Crosstalk attenuation, transmit-to-receive
(differential)
MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured
differentially between EAR1ON and EAR1OP
70
70
PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at
PCMO, EAR1 amplifier
Crosstalk attenuation, receive-to-transmit
16
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TLV320AIC1110
SLAS359 – DECEMBER 2001
timing requirements
clock (2.048-MHz CLK)
PARAMETER
MIN NOM
2.048
MAX
UNIT
ns
t
f
Transition time, MCLK
MCLK frequency
MCLK jitter
10
t
MHz
(mclk)
37%
Number of PCMCLK clock cycles per PCMSYN frame
PCMCLK clock period
256
256 cycles
t
156
488
512
ns
c(PCMCLK)
Duty cycle, PCMCLK
45%
50%
68%
transmit (2.048-MHz CLK) (see Figure 1)
PARAMETER
MIN
MAX
UNIT
t
t
Setup time, PCMSYN high before falling edge of PCMCLK
Hold time, PCMSYN high after falling edge of PCMCLK
20
20
t
t
–20
–20
su(PCMSYN)
c(PCMCLK)
ns
h(PCMSYN)
c(PCMCLK)
receive (2.048-MHz CLK) (see Figure 2)
PARAMETER
MIN
20
MAX
UNIT
ns
t
t
t
t
Setup time, PCMSYN high before falling edge of PCMCLK
Hold time, PCMSYN high after falling edge of PCMCLK
Setup time, PCMI high or low before falling edge of PCMCLK
Hold time, PCMI high or low after falling edge of PCMCLK
t
t
–20
–20
su(PCSYN)
h(PCSYN)
su(PCMI)
h(PCMI)
c(PCMCLK)
20
ns
c(PCMCLK)
20
ns
20
ns
clock (128-kHz CLK)
PARAMETER
MIN
NOM
MAX
UNIT
ns
t
f
Transition time, MCLK
MCLK frequency
MCLK jitter
10
t
128
kHz
(mclk)
5%
16
Number of PCMCLK clock cycles per PCMSYN frame
PCMCLK clock period
16
t
t
742.19 781.25 820.31
ns
c(PCMCLK)
Duty cycle, PCMCLK
40%
50%
125
60%
PCMSYN clock period
µs
c(PCMSYN)
Duty cycle, PCMCLK
49.5%
50% 50.5%
transmit (128-kHz CLK) (see Figure 5)
PARAMETER
MIN
20
MAX
UNIT
ns
t
t
Setup time, PCMSYN high before PCMCLK↑
Hold time, PCMSYN high after PCMCLK↓
t
t
/4
/4
su(PCMSYN)
c(PCMCLK)
20
h(PCMSYN)
c(PCMCLK)
t
Data valid time after the rising edge of PCMSYNC
50
ns
v(PCMO)
receive (128-kHz CLK) (see Figure 4)
PARAMETER
MIN
20
MAX
UNIT
ns
t
t
t
t
Setup time, PCMSYN high before rising edge of PCMCLK
Hold time, PCMSYN high after falling edge of PCMCLK
Setup time, PCMI high or low before falling edge of PCMCLK
Hold time, PCMI high or low after falling edge of PCMCLK
t
t
/4
/4
su(PCSYN)
h(PCSYN)
su(PCMI)
h(PCMI)
c(PCMCLK)
20
ns
c(PCMCLK)
20
ns
20
ns
17
www.ti.com
TLV320AIC1110
SLAS359 – DECEMBER 2001
timing requirements (continued)
2
I C bus timing requirements (see Figure 3)
PARAMETER
MIN
MAX
UNIT
kHz
ns
SCL
Clock frequency
400
t
t
t
t
t
t
t
t
t
t
Pulse duration, SCL high
Pulse duration, SCL low
600
1300
600
600
0
w(SCLH)
w(SCLL)
h(STA)
su(STA)
h(DAT)
su(DAT)
su(STO)
w(SDAT)
r
ns
†
Hold time, SCL high after SDA↓ (repeated START condition)
ns
Setup time, for SCL high before SDA↓ repeated START condition
Hold time, SDA valid after SCL low
Setup time, SDA valid before SCL↑
Setup time, STOP condition
ns
ns
100
600
1300
ns
ns
Pulse duration, SDA high (bus free time)
Rise time (SDA and SCL)
ns
300
300
ns
Fall time (SDA and SCL)
ns
f
†
After this period, the first block pulse is generated.
switching characteristics over recommended ranges of supply voltages and operating free-air
temperature
propagation delay times, C
= 10 pF (see Figure 1)
L(max)
PARAMETER
MIN
MAX
35
UNIT
ns
t
t
t
PCMCLK bit 1 high to PCMO bit 1 valid
PCMCLK high to PCMO valid, bits 2 to n
PCMCLK bit n low to PCMO bit n Hi-Z
pd1
pd2
pd3
35
ns
30
ns
DTMF generator
PARAMETER
TEST CONDITIONS
MIN
1.5
TYP
MAX
2.5
UNIT
DTMF high to low tone relative amplitude (preemphasis)
Tone frequency accuracy (for DTMF)
2
dB
Resolution of 7.8125 Hz
–1.5%
1.5%
Measured from lower tone group to
highest parasitic
Harmonic distortion
–20
dB
MICBIAS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Load impedance (bias mode)
5
kΩ
18
www.ti.com
TLV320AIC1110
SLAS359 – DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
Transmit Time Slot
0
1
2
3
4
N–2
N–1
N
N+1
80%
80%
PCMCLK
20%
20%
t
su(PCMSYN)
t
h(PCMSYN)
PCMSYN
See Note B
t
See Note A
PCMO
pd2
t
pd3
1
2
3
4
N–2
N–1
N
See Note C
t
pd1
t
See Note D
su(PCMO)
NOTES: A. This window is allowed for PCMSYN high.
B. This window is allowed for PCMSYN low (t
C. Transitions are measured at 50%.
max determined by data collision considerations).
h(PCMSYN)
D. Bit 1 = MSB, Bit N = LSB
Figure 1. Transmit Timing Diagram (2.048 MHz)
Receive Time Slot
0
1
2
3
4
N –2
N –1
N
N +1
80%
80%
PCMCLK
t
20%
20%
t
su(PCMSYN)
h(PCMSYN)
PCMSYN
See Note B
See Note A
See Note D
2
t
h(PCMI)
1
3
4
N –2
N –1
N
PCMI
See Note C
t
su(PCMI)
NOTES: A. This window is allowed for PCMSYN high.
B. This window is allowed for PCMSYN low.
C. Transitions are measured at 50%.
D. Bit 1 = MSB, Bit N = LSB
Figure 2. Receive Timing Diagram (2.048 MHz)
SDA
t
w(SDAH)
t
t
t
h(STA)
t
w(SCLH)
r
f
SCL
t
t
hd(STA)
w(SCLH)
t
t
su(STO)
su(STA)
t
t
h(DAT)
su(DAT)
STO
STA
STA
STO
2
Figure 3. I C-Bus Timing Diagram
19
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
PCMCLK
t
h(PCMSYN)
t
su(PCMSYN)
PCMSYNC
t
h(PCMI)
MSB
PCMI
LSB
t
su(PCMI)
Figure 4. Receive Timing Diagram, 128 kHz
PCMCLK
t
t
h(PCMSYN)
su(PCMSYN)
PCMSYNC
PCMO
t
v(PCMO)
MSB
LSB
Figure 5. Transmit Timing Diagram, 128 kHz
t
c(PCMSYNC)
Figure 6. PCMSYNC Timing, 128 kHz
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
SCL
SDA
Start
A6
A5
A4
A0 R/W ACK
R7
R6
R5
R0 ACK
0
D7
D6
D5
D0 ACK
0
0
0
Stop
Slave Address
Register Address
Data
NOTE:SLAVE=VoiceCodec
2
Figure 7. I C-Bus Write to Voice Codec
SCL
A6
A5
A0 R/W ACK
R7 R6
R0 ACK
A6
A0 R/W ACK D7 D6
D0 ACK
SDA
Start
0
0
1
0
Stop
Slave Drives
The Data
Master
Drives
Slave Address
Register Address
Slave Address
Repeated
Start
ACK and Stop
NOTE: SLAVE = Voice Codec
2
Figure 8. I C Read From Voice Codec: Protocol A
SCL
SDA
R/W ACK
ACK
D0
A6 A5
A0 R/W ACK
R7 R6
R0 ACK
A6 A5
A0
D7
0
0
Start
Stop
Stop Start
Slave Drives
The Data
Master
Drives
Slave Address
Register Address
Slave Address
ACK and Stop
NOTE: SLAVE = Voice Codec
2
Figure 9. I C Read From Voice Codec: Protocol B
21
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TLV320AIC1110
SLAS359 – DECEMBER 2001
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
(Detector OFF)
FREE-AIR TEMPERATURE
(Detector ON)
45
40
35
30
25
20
15
30
25
V
DD
= 3.3 V
V
DD
= 3.3 V
20
15
10
5
V
DD
= 3.0 V
V
DD
= 3.0 V
10
5
0
V
DD
= 2.7 V
V
DD
= 2.7 V
0
–50
0
50
100
–50
0
50
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
RELATIVE GAIN
vs
RELATIVE GAIN
vs
FREQUENCY
FREQUENCY
5
20
0
Both Filters
Disabled
Both Filters
Disabled
0
–5
–20
–40
–60
High-Pass
Filter Selected
and Slope Filter
Disabled
–10
–15
High-Pass
Filter Selected
and Slope Filter
Disabled
High-Pass
Filter and
Slope Filter
Selected
–20
–25
–30
High-Pass
Filter and
Slope Filter
Selected
–80
–100
100
1k
10k
100
1k
f – Frequency – Hz
f – Frequency – Hz
Figure 10. Transmit Gain Response With Respect to Gain of 1-kHz Tone
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TLV320AIC1110
SLAS359 – DECEMBER 2001
TYPICAL CHARACTERISTICS
RELATIVE GAIN RESPONSE
vs
FREQUENCY
5
0
–5
–10
–15
–20
–25
–30
–35
10
100
1k
10k
f – Frequency – Hz
Figure 11. Receive Gain Response With Respect to Gain of 1-kHz Tone
With High-Pass Filter Selected and High-Pass Filter Disabled
23
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
power-on initialization
An external reset with a minimum pulse width of 500 ns must be applied to the active low RESET terminal to
assure reset upon power on. All registers are set with default values upon external reset initialization.
The desired selection for all programmable functions can be initialized prior to a power-up command using the
control interface.
Table 1. Power-Up and Power-Down Procedures (V
= 2.7 V, earphone amplifier unloaded)
DD
MAXIMUM POWER
CONSUMPTION
DEVICE STATUS
Power up
PROCEDURE
Set bit 1 = 1 in power control register, EAR1 enabled
Set bit 1 = 0 in power control register, EAR2 enabled
Set bit 7 = 1 in TXPGA control register and bit 0 = 0
Set bit 7 = 0 in TXPGA control register and bit 0 = 0
16.2 mW
14.6 mW
1.35 µW
67.5 µW
Power down
In addition to resetting the power down bit in the power control register, loss of MCLK (no transition detected)
automatically enters the device into a power-down state with PCMO in the high impedance state. If during a
pulse code modulation (PCM) data transmit cycle an asynchronous power down occurs, the PCM interface
remains powered up until the PCM data is completely transferred.
An additional power-down mode overrides the MCLK detection function. This allows the device to enter the
power down state without regard to MCLK. Setting bit 7 of the TXPGA sidetone register to logic high enables
this function.
internal reference current setting terminal
Use a 100-kΩ precision resistor to connect the REXT pin to GND.
conversion laws
The device can be programmed for either a 15-bit linear or and 8-bit (µ-law or A-law) companding mode. The
companding operation approximates the CCITT G.711 recommendation. The linear mode operation uses a
15-bit twos-complement format.
transmit operation
microphone input
The microphone input stage is a low-noise differential amplifier that provides a preamplifier gain of 23.5 dB. It
is recommended that a microphone capacitively connected to the MIC1N and MIC1P inputs, while the MIC2N
and MIC2P inputs can be used to capacitively connect a second microphone or an auxiliary audio circuit.
24
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
transmit operation (continued)
_
MBIAS
+
V
ref
R
R
mic
510 kΩ
C MIC1N
i
34 kΩ
34 kΩ
_
+
M
I
C
C MIC1P
i
510 kΩ
mic
Figure 12. Typical Microphone Interface
microphone mute function
Transmit channel muting provides 80-dB attenuation of the input microphone signal. The MICMUTE function
2
can be selected by setting bit 6 of the power control register through the I C interface.
transmit channel gain control
The values in the transmit PGA control registers control the gain in the transmit path. The total TX channel gain
can vary from 41.5 dB to 19.5 dB. The default total TX channel gain is 23.5 dB.
Table 2. Transmit Gain Control
GAIN
MODE
BIT NAME
TP2 TP1
MIC AMP1 MIC AMP2
TX PGA
TOTAL TX GAIN
TP3
0
TP0
0
GAIN
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
GAIN
18
18
18
18
18
18
6
GAIN
0
MIN
41.3
39.3
37.3
35.3
33.3
31.3
29.3
27.3
25.3
23.3
21.3
19.3
TYP
41.5
39.5
37.5
35.5
33.5
31.5
29.5
27.5
25.5
23.5
21.5
19.5
MAX
41.7
39.7
37.7
35.7
33.7
31.7
29.7
27.7
25.7
23.7
21.7
19.7
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
Extended
Extended
Extended
Extended
Extended
Extended
Normal
0
1
–2
–4
–6
–8
–10
0
0
0
0
1
0
0
0
1
1
0
1
1
6
–2
–4
–6
–8
–10
Normal
1
0
6
Normal
1
1
6
Normal
1
0
6
Normal
1
1
6
Normal
25
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
receive operation
receive channel gain control
The values in the receive PGA control registers control the gain in the receive path. PGA gain is set from
2
– 6 dB to 6 dB in 1-dB steps through the I C interface. The default receive channel gain is –4 dB.
Table 3. Receive PGA Gain Control
BIT NAME
RP2
RELATIVE GAIN, VOICE MODE
DTMF GAIN, TONE NODE
RP3
0
RP1
0
RP0
0
MIN
5.8
TYP
6
MAX
6.2
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
12
12
12
6
0
0
1
4.8
5
5.2
0
1
0
3.8
4
4.2
0
1
1
2.8
3
3.2
0
0
0
1.8
2
2.2
6
0
0
1
0.8
1
1.2
6
0
1
0
–0.2
–1.2
–2.2
–3.2
–4.2
–5.2
–6.2
0
0.2
0
0
1
1
–1
–2
–3
–4
–5
–6
X
–0.8
–1.8
–2.8
–3.8
–4.8
–5.8
0
1
0
0
0
1
0
1
–6
–6
–6
–12
–12
–12
1
1
0
1
1
1
1
0
0
1
0
1
1
1
0
X
sidetone gain control
The values in the sidetone PGA control registers control the sidetone gain. Sidetone gain is set from –12 dB
2
to –24 dB in 2-dB steps through the I C interface. Sidetone can be muted by setting bit 7 of the power control
register. The default sidetone gain is –12 dB.
Table 4. Sidetone Gain Control
BIT NAME
RELATIVE GAIN
ST2
0
ST1
0
ST0
0
MIN
TYP
–12
–14
–16
–18
–20
–22
–24
MAX
UNIT
dB
–12.2
–14.2
–16.2
–18.2
–20.2
–22.2
–24.2
–11.8
–13.8
–15.8
–17.8
–19.8
–21.8
–23.8
0
0
1
dB
0
1
0
dB
0
1
1
dB
1
0
0
dB
1
0
1
dB
1
1
0
dB
26
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
receive operation (continued)
receive volume control
The values in the volume control PGA control registers provide volume control for the earphone. Volume control
2
gain is set from 0 dB to –18 dB in 2-dB steps through the I C interface. The default RX volume control gain
is 0 dB.
Table 5. RX Volume Control
BIT NAME
RV1
RELATIVE GAIN
RV3
0
RV2
0
RV0
0
MIN
–0.2
TYP
0
MAX
0.2
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0
0
1
1
0
0
1
1
0
0
0
0
1
–2.2
–2
–1.8
0
0
0
–4.2
–4
–3.8
–5.8
–7.8
0
0
1
–6.2
–6
0
1
0
–8.2
–8
0
1
1
–10.2
–12.2
–14.2
–16.2
–18.2
–10
–12
–14
–16
–18
–9.8
–11.8
–13.8
–15.8
–17.8
0
1
0
0
1
1
1
0
0
1
0
1
earphone amplifier
The analog signal can be routed to either of two earphone amplifiers: one with a differential output (EAR1ON
and EAR1OP) capable of driving a 8-Ω load, or one with a single-ended output (EAR2O) capable of driving a
8-Ω load.
earphone mute function
2
Muting can be selected by setting bit 3 of the power control register through the I C interface.
receive PCM data format
ꢀ
ꢀ
Companded mode: 8 bits are received, the most significant (MSB) first.
Linear mode: 15 bits are received, MSB first.
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
receive operation (continued)
Table 6. Receive-Data Bit Definitions
BIT NO.
COMPANDED
MODE
LINEAR
MODE
1
2
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
–
LD14
LD13
LD12
LD11
LD10
LD9
LD8
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
––
3
4
5
6
7
8
9
10
11
12
13
14
15
16
–
–
–
–
–
–
–
Transmit channel gain control bits always follow the PCM data in time:
CD7-CD0 = data word in companded mode
LD14-LD0 = data word in linear mode
DTMF generator operation and interface
The DTMF circuit generates the summed DTMF tones for push button dialing and provides the PDM output for
the BUZZCON user-alert tone. The integer value is determined by the formula round tone [Freq (Hz)/resolution
(Hz)]. The integer value is loaded into one of two 8-bit registers, high-tone register (04) or low-tone register (05).
The tone output is 2 dB higher when applied to the high-tone register (04). When generating DTMF tones, the
high-frequency value must be applied to the high tone register (04) and the low DTMF value to the low-tone
register.
The DTMF frequency resolution is controlled by the auxiliary register (06) bits 2, 3, 4, and 5. When the resolution
is set to 7.8125 Hz, the frequency range can be up to 1992.2 Hz. A wider range can be accomplished (for
example, 2x or 4x) by selecting lower resolutions of 15.625 Hz or 31.250 Hz. The gain setting is controlled by
the RXPGA gain control. This register applies the required gain to obtain MUX control during tone mode
operation. Table 3 shows the relationship of the two gain settings.
28
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
DTMF generator operation and interface (continued)
Table 7. Typical DTMF and Single Tone Control
INTEGER
VALUE
TONE
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
TONE/HZ
FUNCTION
DTMF Low
DTMF Low
DTMF Low
DTMF Low
DTMF HIgh
DTMF HIgh
DTMF HIgh
DTMF HIgh
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
0
1
1
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
89
697
770
99
109
120
155
171
189
209
852
941
1209
1336
1477
1633
Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the
individual output ports. The values that determine the tone frequency are loaded into the tone registers (high
and low) as two separate values.
The values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in
twos-complement value into the the tone registers. There is a 2-dB difference in the resulting output of the two
registers, the high-tone register having the greater result.
In the case of low-tone signal, the tone generator outputs a 6-bit integer with a maximum code of 31 (011111).
However, the DTMF output is an 8-bit integer. Therefore, two zeros are padded to the MSB position, which
results in 31 (00011111). On the other hand, the receive channel requires a 15-bit integer, the input 3968
(000111110000000). Since the maximum digital value of receive channel is 16383 (011111111111111), the
maximum low-tone signal is designed to be –12.32 dB below the full digital scale.
2
3968
16383
(1)
20 log ǒ Ǔ
+ –12.32 dB
In the case of high-tone signal, the tone generator outputs a 7-bit integer with a maximum code of 39 (0100111).
The DTMF, therefore, pads a zero to the MSB and generates an 8-bit integer (00100111). In order to send the
digital code to receive channel, it is converted to a 15-bit integer with seven more zeros padded to LSB position
andbiasedas4992(001001110000000). Therefore, themaximumhigh-tonesignalisdesignedtobe–10.32 dB
below the full digital scale.
2
(2)
4992
16383
20 log ǒ Ǔ
+ –10.32 dB
In the case of DTMF output, the tone generator outputs an 8-bit integer with the maximum code level of 70
(01000110). This output is converted to a 15-bit code with the value of 8960 (010001100000000). Therefore,
the maximum output of DTMF is designed to be –5.24 dB below the full digital scale.
2
(3)
8960
16383
20 log ǒ Ǔ
+ –5.24 dB
29
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
buzzer logic section
The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver
transistor. The PDM begins as a selected DTMF tone, generated and passed through the receive D/A channel
and fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the
BUZZCON output.
Digital
DTMF
Analog
Modulator
Buzzer
Control
Modulator
and
Gain
Mux
DTMF
Filter
Buzzcon
Figure 13. Buzzer Driver System Architecture
support section
The clock generator and control circuit use the master clock input (MCLK) to generate internal clocks to drive
internal counters, filters, and convertors. Register control data is written into and read back from the PCM codec
registers via the control interface.
2
I C-bus protocols
2
The PCM codec serial interface is designed to be I C bus-compatible and operates in the slave mode when CE
is high. This interface consists of the following terminals:
2
SCL:
SDA:
I C-bus serial clock. This input synchronizes the control data transfer to and from the codec.
2
I C-bus serial address/data input/output. This is a bidirectional terminal that transfers register
control addresses and data into and out of the codec. It is an open drain terminal and therefore
requires a pullup resistor to V
(typical 10 kΩ for 100 kHz).
CC
TLV320AIC1110 has a fixed device select address of (E2)HEX for write mode and (E3)HEX for read mode.
For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are
reserved for indicating the start and stop conditions.
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted
as a start or stop condition.
2
Table 8. I C-Bus Conditions
CONDITION
STATUS
DESCRIPTION
Both data and clock lines remain at high.
A
Bus not busy
A high to low transition of the SDA line while the clock (SCL) is high determines a start condition.
All commands must proceed from a start condition.
B
C
D
Start data transfer
Stop data transfer
Data valid
A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition.
All operations must end with a stop condition.
Thestateofthedatalinerepresentsvaliddatawhen, afterastartcondition, thedatalineisstable
for the duration of the high period of the clock signal.
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit of data.
30
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
2
I C-bus protocols (continued)
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data
bytes, transferred between the start and stop conditions, is determined by the master device (microprocessor).
When addressed, the PCM codec generates an acknowledge after the reception of each byte. The master
device must generate an extra clock pulse that is associated with this acknowledge bit.
ThePCMcodecmustpulldowntheSDAlineduringtheacknowledgeclockpulsesothattheSDAlineisatstable
low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken
intoaccount. Duringreadoperations, themasterdevicemustsignalanendofdatatotheslavebynotgenerating
an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (PCM codec) must
leave the data line high to enable the master device to generate the stop condition.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate.
register map addressing
BITS
REG
07
06
05
04
03
02
01
00
EAROUT
Sel
Power control
Mode control
00
01
Sidetone En
TXEn
RX TX En
MICSEL
BIASEn
RXEn
PWRUP
TXFLTR
En
Comp Sel
TMEn
PCMLB
Comp En
BUZZEn
RXFLTR En
TXSLOPE En
TXPGA
RXPGA
02
03
X
TP3
RP2
TP2
RP1
TP1
RP0
TP0
RV3
ST2
RV2
ST1
RV1
ST0
RV0
RP3
HIFREQ
Sel4
HIFREQ
Sel7
HIFREQ
Sel6
HIFREQ
Sel5
HIFREQ
Sel3
HIFREQ
Sel2
HIFREQ
Sel1
High DTMF
Low DTMF
AUX
04
05
06
HIFREQ Sel0
LOFREQ
Sel4
LOFREQ
Sel7
LOFREQ
Sel6
LOFREQ
Sel5
LOFREQ
Sel3
LOFREQ
Sel2
LOFREQ
Sel1
LOFREQ
Sel0
MCLK
Detect
†
RXPGA2
DTMFH1
DTMFH0
DTML1
DTMFL0
AMVX
MCLK sel
†
For voice mode only
register power-up defaults
BITS
REG
07
06
1
05
04
03
02
1
01
1
00
0
†
‡
Power control (1)
Power control (2)
Mode control
TXPGA
00
00
01
02
03
04
05
06
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
0
RXPGA
0
0
0
0
High DTMF
Low DTMF
AUX
0
0
0
0
0
0
0
0
0
0
0
0
†
‡
1. Value when PWRUPSEL = 0
2. Value when PWRUPSEL = 1
31
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
register map
Table 9. Power Control Register: Address (00) HEX
BIT NUMBER
DEFINITIONS
7
1
6
1
5
1
4
1
3
0
2
1
1
1
0
0
Default setting PWRUPSEL = 0
Default setting PWRUPSEL = 1
Reference system, power down
Reference system, power up
EAR AMP1 selected, EAR AMP2 power down
EAR AMP2 selected, EAR AMP1 power down
Receive channel enabled
Receive channel muted
1
0
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
1
X
X
X
X
0
X
X
1
0
1
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
Receive channel, power down
Micbias enable
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Micbias disable
X
X
X
X
X
X
X
MIC1 selected
0
MIC2 selected
X
X
X
X
X
Transmit channel enabled
Transmit channel muted
Transmit channel power down
Sidetone enabled
1
1
1
X
X
X
X
1
Sidetone muted
Table 10. Mode Control Register: Address (01) HEX
BIT NUMBER
DEFINITIONS
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
0
Default setting
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
0
X
X
X
X
0
0
0
TX channel high-pass filter enabled and slope filter enabled
TX channel high-pass filter enabled and slope filter disabled
TX channel high-pass filter disabled and slope filter enabled
TX channel high-pass filter disabled and slope filter disabled
RX channel high-pass filter disabled (low pass only)
RX channel high-pass filter enabled
BUZZCON disabled
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
1
BUZZCON enabled
X
X
X
X
X
X
X
Linear mode selected
1
A-law companding mode selected
µ-law companding mode selected
TX and RX channels normal mode
PCM loopback mode
0
1
X
X
X
X
X
X
X
X
1
X
X
Tone mode disabled
1
Tone mode enabled
32
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
register map (continued)
Transmit PGA and sidetone control register: Address (02)HEX
Bit definitions:
7
X
0
6
TP3
1
5
TP2
0
4
TP1
0
3
TP0
0
2
ST2
0
1
ST1
0
0
ST0
0
DEFINITION
See Table 2 and Table 4
Default setting
Receive volume control register: Address (03)HEX
Bit definitions:
7
RP3
1
6
RP2
0
5
RP1
1
4
RP0
0
3
RV3
0
2
RV2
0
1
RV1
0
0
RV0
0
DEFINITION
See Table 3 and Table 5
Default setting
High tone selection control register: Address (04)HEX
Bit definitions:
7
X
0
6
X
0
5
X
0
4
X
0
3
X
0
2
X
0
1
X
0
0
X
0
DEFINITION
DTMF (see Table 7)
Default setting
Low tone selection control register: Address (05)HEX
Bit definitions :
7
X
0
6
X
0
5
X
0
4
X
0
3
X
0
2
X
0
1
X
0
0
X
0
DEFINITION
DTMF (see Table 7)
Default setting
Auxiliary register: Address (06)HEX
Bit definitions:
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DEFINITION
0
X
X
0
Default
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
0
MCLK is set to 2.048 MHz
MCLK is set to 128 MHz
1
X
X
X
X
X
X
X
X
X
X
X
X
Analog switch output is set to OUT2
1
Analog switch output is set to OUT1
X
X
X
X
X
X
X
X
X
X
Low tone frequency resolution is set to 7.8125 Hz
Low tone frequency resolution is set to 15.625 Hz
Low tone frequency resolution is set to 31.250 Hz
High tone frequency resolution is set to 7.8125 Hz
High tone frequency resolution is set to 15.625 Hz
High tone frequency resolution is set to 31.250 Hz
Receiver channel gain, RXPGA2 is equal to 0 dB, voice mode only
Receiver channel gain, RXPGA2 is equal to 6 dB, voice mode only
MCLK detector is powered ON
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
0
X
X
X
X
X
X
X
X
1
X
X
1
MCLK detector is powered OFF
33
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
using PCM codec as a general-purpose PCM codec
In situations when a general-purpose PCM codec is needed and programming features are not necessary, the
receiveandtransmitchannelscanbeenabledforvoicemodeonlybysettingthepowerupselectpintoV level.
CC
When set to default, the following features are activated:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
REF is powered up
Ear amp1 selected, Ear amp 2 = OFF
Receive channel enabled
MIC bias enabled
MIC 2 selected
Transmit channel enabled
Side tone enabled, Gain = –12 dB
TX channel high pass filter disabled
TX channel slope filter enabled
RX channel HP filter disabled (low pass only)
Buzzcon disabled
Linear mode only
TX and RX channel normal mode (no loopback)
Tone mode disabled (voice mode only)
MIC amp 1 gain
MIC amp 2 gain
TX PGA gain
=
=
=
=
23.5 dB
6 dB
0 dB
29.5 dB
Total TX gain
ꢀ
ꢀ
Receive PGA
Receive PGA 2
Volume
=
=
=
=
–4 dB
0 dB
0 dB
Total RX gain
–4 dB
Clock = 2.048 MHz
34
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TLV320AIC1110
SLAS359 – DECEMBER 2001
PRINCIPLES OF OPERATION
PCM codec device comparisons
TLV320AIC1103
To 2 kHz
TLV320AIC1110
Single tone frequency range
Transmit channel gain range
Receive channel gain range
PCMCLK rate
To 8 kHz
13.5 dB to 35.5 dB
– 24 dB to 6 dB
2.048 MHz
19.5 dB to 41.5 dB
– 24 dB to 12 dB
128 kHz or 2.048 MHz
Device pin out
Backward compatible (TQFP)
Backward compatible
Control registers
Number of registers
Control interface
6
7
2
I C
2
I C
Analog switch
No
Yes
Earout driving impedance
DTMF
32 Ω
Yes
8-32 Ω
Yes
7.8125
15.625
31.25
Tone resolution (Hz)
Packages
7.8125
TQFP
TQFP,
MicroStar Junior BGAꢂ
35
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TLV320AIC1110
SLAS359 – DECEMBER 2001
MECHANICAL DATA
PBS (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,23
M
0,50
0,08
0,17
17
24
25
32
16
9
0,13 NOM
1
8
3,50 TYP
Gage Plane
5,05
SQ
4,95
0,25
7,10
SQ
0,10 MIN
6,90
0°–ā7°
0,70
0,40
1,05
0,95
Seating Plane
0,08
1,20 MAX
4087735/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
36
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TLV320AIC1110
SLAS359 – DECEMBER 2001
MECHANICAL DATA
GQE (S-PBGA-N80)
PLASTIC BALL GRID ARRAY
5,20
4,80
SQ
4,00 TYP
0,50
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
0,68
0,62
1,00 MAX
Seating Plane
0,08
0,35
0,25
0,05
M
0,21
0,11
4200461/B 04/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
MicroStar Junior BGA is a trademark of Texas Instruments.
37
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
VFBGA
TQFP
TQFP
Drawing
TLV320AIC1110GQER
TLV320AIC1110PBS
TLV320AIC1110PBSR
ACTIVE
ACTIVE
ACTIVE
GQE
80
32
32
2500
250
TBD
TBD
TBD
SNPB
Level-2A-235C-4 WKS
PBS
CU NIPDAU Level-2-235C-1 YEAR
CU NIPDAU Level-2-235C-1 YEAR
PBS
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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