TLV320AIC12CDBTR [TI]
LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC; 低功耗，高集成，可编程的16位， 26 - KSPS单声道编解码器
| 型号： | TLV320AIC12CDBTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC |
| 文件： | 总63页 (文件大小：1160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE
16-Bit, 26-KSPS MONO CODEC
FEATURES
–
–
–
Analog and Digital Sidetone
•
•
•
Mono 16-Bit Oversampling Sigma-Delta A/D
Converter
Antialiasing Filter (AAF)
Programmable Input and Output Gain
Control (PGA)
Mono 16-Bit Oversampling Sigma-Delta D/A
Converter
–
–
–
Microphone/Handset/Headset Amplifiers
Support Maximum Master Clock of 100 MHz to
Allow the DSP Output Clock to be Used as a
Master Clock
AIC12K has an 8-Ω Speaker Driver
Power Management With
Hardware/Software Power-Down Modes
30 µW
•
•
Selectable FIR/IIR Filter With Bypassing
Option
•
•
Separate Software Control for ADC and DAC
Power Down
Programmable Sampling Rate up to:
–
–
Max 26 Ksps With On-Chip IIR/FIR Filter
Max 104 Ksps With IIR/FIR Bypassed
Fully Compatible With Common TMS320™
DSP Family and Microcontroller Power
Supplies
•
•
On-Chip FIR Produced 84-dB SNR for ADC
and 92-dB SNR for DAC
–
–
–
1.65 V - 1.95 V Digital Core Power
1.1 V - 3.6 V Digital I/O
Smart Time Division Multiplexed
(SMARTDM™) Serial Port
2.7 V - 3.6 V Analog
–
–
Glueless 4-Wire Interface to DSP
•
Power Dissipation (PD)
Automatic Cascade Detection (ACD)
Self-Generates Master/Slave Device
Addresses
–
–
11.2 mW at 3.3 V in Standard Operation
17.8 mW at 3.3 V With Headphone Drivers
•
•
•
Internal Reference Voltage (Vref
)
–
–
–
–
Programming Mode to Allow On-the-Fly
Reconfiguration
2s Complement Data Format
Test Modes Which Include Digital Loopback
and Analog Loopback
Continuous Data Transfer Mode to
Minimize Bit Clock Speed
Support Different Sampling Rate for Each
Device
APPLICATIONS
•
•
•
•
•
Digital Still Cameras
Wireless Accessories
Hands-Free Car Kits
VOIP
Turbo Mode to Maximize Bit Clock for
Faster Data Transfer and Allow Multiple
Serial Devices to Share the Same Bus
–
Allows up to 16 Devices to be Connected
to a Single Serial Port
Cable Modem
•
Host Port
–
–
2-Wire Interface
Selectable I2C or S2C
•
•
Differential and Single-Ended Analog
Input/Output
Built-In Analog Functions:
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SMARTDM, TMS320C5000, TMS320C6000 are trademarks of Texas Instruments.
TMS320 is a trademark of Texas Instrument.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The TLV320AIC1x is a true low-cost, low-power, high-integrated, high-performance, mono voice codec. It
features one 16-bit analog-to-digital (A/D) channel and one 16-bit digital-to-analog (D/A) channel.
The TLV320AIC1x provides high-resolution signal conversion from digital-to-analog (D/A) and from
analog-to-digital (A/D) using oversampling sigma-delta technology with programmable sampling rate.
The TLV320AIC1x implements the smart time division multiplexed serial port (SMARTDM™). The SMARTDM
port is a synchronous 4-wire serial port in TDM format for glue-free interface to TI DSPs (i.e. TMS320C5000™,
TMS320C6000™) and microcontrollers. The SMARTDM supports both continuous data transfer mode and
on-the-fly reconfiguration programming mode. The TLV320AIC1x can be gluelessly cascaded to any
SMARTDM-based device to form multichannel codec and up to 16 TLV320AIC1x codecs can be cascaded to a
single serial port.
The TLV320AIC1x also provides a flexible host port. The host port interface is a two-wire serial interface that
can be programmed to be either an industrial standard I2C or a simple S2C (start-stop communication protocol).
The TLV320AIC1x also integrates all of the critical functions needed for most voice-band applications including
MIC preamplifier, handset amplifier, headset amplifier, antialiasing filter (AAF), input/output programmable gain
amplifier (PGA), and selectable low-pass IIR/FIR filters. The AIC12K also includes an 8-Ω speaker driver.
The TLV320AIC1x implements an extensive power management; including device power-down, independent
software control for turning off ADC, DAC, operational-amplifiers, and IIR/FIR filter (bypass) to maximize system
power conservation. The TLV320AIC1x consumes only 11.2 mW at 3.3 V.
The TLV320AIC1x low power operation from 2.7 V to 3.6 V power supplies, along with extensive power
management, make it ideal for portable applications including wireless accessories, hands free car kits, VOIP,
cable modem, and speech processing. Its low group delay characteristic makes it suitable for single or
multichannel active control applications.
The TLV320AIC1x is characterized for commercial operation from 0°C to 70°C and industrial operation from
-40°C to 85°C. The TLV320AIC1xk is characterized for industrial operation from -40°C to 85°C.
ORDERING INFORMATION
OPERATING
TEMPERATURE
RANGE, TA
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
(1)
PRODUCT
PACKAGE
TLV320AIC1xCDBT
TLV320AIC1xCDBTR
TLV320AIC1xIDBT
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
TLV320AIC1xC
TLV320AIC1xI
TLV320AIC12K
TLV320AIC14K
TSSOP-30
TSSOP-30
QFN-32
DBT
DBT
RHB
RHB
0°C to 70°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
TLV320AIC1xIDBTR
TLV320AIC12KIRHBT
TLV320AIC12KIRHBR
TLV320AIC14KIRHBT
TLV320AIC14KIRHBR
QFN-32
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
2
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
AIC12/13/12K DBT PACKAGE
(TOP VIEW)
AIC14/15/14K DBT PACKAGE
(TOP VIEW)
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IOVSS
IOVDD
FSD
FS
DOUT
DIN
DVSS
DVDD
SCLK
SDA
IOVSS
IOVDD
FSD
FS
DOUT
DIN
DVSS
DVDD
SCLK
SDA
2
2
3
3
4
4
5
5
SCL
SCL
6
6
MCLK
RESET
INP1
INM1
BIAS
INM2
INP2
MICIN
AVDD
AVSS
MCLK
RESET
INP1
INM1
BIAS
INM2
INP2
MICIN
AVDD
AVSS
7
7
M/S
M/S
8
8
PWRDN
OUTM1
OUTP1
DRVDD
DRVSS
OUTP2
OUTMV
OUTP3
PWRDN
OUTM1
OUTP1
DRVDD
DRVSS
NC
9
9
10
11
12
13
14
15
10
11
12
13
14
15
NC
NC
AIC12K RHB PACKAGE
(TOP VIEW)
AIC14K RHB PACKAGE
(TOP VIEW)
24 23 22 21 20 19 18 17
24 23 22 21 20 19 18 17
N/C
INM2
N/C
25
16
15
14
N/C
INM2
N/C
25
16
15
14
DRVDD
26
27
28
29
30
31
31
DRVDD
26
27
28
29
30
31
31
BIAS
INM1
OUTP1
OUTM1
BIAS
INM1
OUTP1
OUTM1
13
12
13
12
INP1
RESET
MCLK
SCL
PWRDN
M/S
INP1
RESET
MCLK
SCL
PWRDN
M/S
11
10
9
11
10
9
DIN
DIN
DOUT
DOUT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
NOTE: For the RHB package, connect the device thermal pad to DRVDD.
3
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Terminal Functions
TERMINAL
NAME
AIC12/13/12K AIC14/15/14K
AIC12K
RHB
NO.
AIC14K
RHB
NO.
I/O DESCRIPTION
DBT
NO.
DBT
NO.
IOVSS
IOVDD
1
2
1
2
5
6
5
6
I
I
Digital I/O ground
Digital I/O power supply
Frame sync delayed output. The FSD output synchronizes a slave
device to the frame sync of the master device. FSD is applied to the
slave FS input and is the same duration as the master FS signal. This
pin must be pulled low if AIC1x is a stand-alone slave. It must be
pulled high if the AIC1x is a stand-alone master or the last slave in the
cascade.
FSD
3
3
7
7
O
Frame sync. When FS goes low, DIN begins receiving data bits and
FS
4
5
4
5
8
9
8
9
I/O DOUT begins transmitting data bits. In master mode, FS is internally
generated. In slave mode, FS is externally generated.
Data output. DOUT transmits the ADC output bits and registers data,
DOUT
O
and is synchronized to SCLK and FS. Data is sent out at the rising
edge of SCLK. Outside data/control frame, DOUT is put in 3-state.
Data input. DIN receives the DAC input data and register data from the
external DSP (digital signal processor) and is synchronized to SCLK
and FS. Data is latched at the falling edge of SCLK.
DIN
M/S
6
7
6
7
10
11
10
11
I
I
Master/slave select input. When M/S is high, the device is the master,
and when low it is a slave.
Power down. When PWRDN is pulled low, the device goes into a
power-down mode, the serial interface is disabled, and most of the
high-speed clocks are disabled. However, all the register values are
sustained and the device resumes full-power operation without
reinitialization when PWRDN is pulled high again. PWRDN resets the
counters only and preserves the programmed register contents.
PWRDN
8
8
12
12
I
Inverting output of the DAC. OUTM1 is functionally identical with and
complementary to OUTP1. This differential output can drive a
maximum load of 600 Ω. This output can also be used alone for
single-ended operation.
OUTM1
OUTP1
9
9
13
14
13
14
O
O
Noninverting output of the DAC. This differential output can drive a
maximum load of 600 Ω. This output can also be used alone for
single-ended operation.
10
10
DRVDD
DRVSS
11
12
11
12
15
17
15
17
I
I
Analog power supply for the 16-Ω drivers OUTP2 and OUTP3
Analog ground for the 16-Ω drivers OUTP2 and OUTP3
Analog output number 2 from the 16-Ω driver. This output can drive a
maximum load of 16 Ω, and also can be configured as either
single-ended output or differential output by the control register 6.
OUTP2
OUTMV
OUTP3
13
14
15
–
–
–
18
19
20
–
–
–
O
O
O
Programmable virtual ground for the output of OUTP2 and OUTP3
(see the Register Map).
Analog output number 3 from the 16-Ω driver. This output can drive a
maximum load of 16 Ω, and also be configured as either single-ended
output or differential output by the control register 6.
AVSS
AVDD
MICIN
INP2
16
17
18
19
20
16
17
18
19
20
21
22
23
24
25
21
22
23
24
25
I
I
I
I
I
Analog ground
Analog power supply
MIC preamplifier input. It must be connected to AVSS if not used.
Noninverting analog input 2. It must be connected to AVSS if not used.
Inverting analog input 2. It must be connected to AVSS if not used.
INM2
Bias output voltage is software selectable between 1.35 V and 2.35 V.
Its output current is 5 mA.
BIAS
21
21
27
27
O
INM1
INP1
22
23
22
23
28
29
28
29
I
I
Inverting analog input 1. It must be connected to AVSS if not used.
Noninverting analog input 1. It must be connected to AVSS if not used.
Hardware reset. The reset function is provided to initialize all of the
internal registers to their default values. The serial port is configured to
the default state accordingly.
RESET
MCLK
24
25
24
25
30
31
30
31
I
I
Master clock. MCLK derives the internal clocks of the sigma-delta
analog interface circuit.
Programmable host port (I2C or S2C) clock input.
Programmable host port (I2C or S2C) data line.
SCL
SDA
26
27
26
27
32
1
32
1
I
I/O
4
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Terminal Functions (continued)
TERMINAL
AIC12/13/12K AIC14/15/14K
NAME
AIC12K
RHB
NO.
AIC14K
RHB
NO.
I/O DESCRIPTION
DBT
NO.
DBT
NO.
Shift clock. SCLK signal clocks serial data into DIN and out of DOUT
during the frame-sync interval. When configured as an output (M/S
high), SCLK is generated internally by multiplying the frame-sync signal
I/O frequency by 16 and the number of codecs in cascade in standard and
continuous mode. When configured as an input (M/S low), SCLK is
generated externally and must be synchronous with the master clock
and frame sync.
SCLK
28
28
2
2
DVDD
DVSS
29
30
29
30
3
4
3
4
I
I
Digital power supply
Digital ground
16, 18, 19, 20,
26
NC
–
13, 14, 15
16, 26
No connection
Electrical Characteristics
AIC12, AIC13, AIC14, AIC15, AIC12K, AIC14K: Over Recommended Operating Free-Air Temperature Range
AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V (Unless Otherwise Noted)
Absolute Maximum Ratings
Over Operating Free-Air Temperature Range (Unless Otherwise Noted)(1)
UNITS
VCC
Supply voltage range:
DVDD(2)
-0.3 V to 2.25 V
-0.3 V to 4 V
(2)
AVDD, DRVDD, IOVDD
VO
VI
Output voltage range, all digital output signals
Input voltage range, all digital input signals
Operating free-air temperature range
Junction temperature
-0.3 V to IOVDD + 0.3 V
-0.3 V to IOVDD + 0.3 V
-40°C to 85°C
105°C
TA
TJ
Tstg
Storage temperature range
-65°C to 150°C
(TJmax - TA ) / θJA
44°C/W
Power dissipation
θJA
Thermal impedance
Case temperature for 10 seconds: Package
260°C
AIC12, AIC13, AIC14, AIC15, AIC12k and AIC14k all
pins
CDM
HBM
500 V
2 kV
AIC12, AIC13, AIC14, AIC15, AIC12k and AIC14k all
pins except for the following:
ESD Characteristics
DVDD, SDA
DOUT
HBM
HBM
1.3 kV
1.9 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS
.
5
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Recommended Operating Conditions
MIN
NOM
MAX
MIN
NOM
AIC12K/14K
3.3
MAX
UNIT
AIC12/13/14/15
Supply voltage for analog, AVDD
2.7
3.3
3.6
3.6
1.95
3.6
2
2.7
2.7
3.6
3.6
1.95
3.6
2
V
Supply voltage for analog output driver, DRVDD
2.7
1.65
1.1
VSS
Supply voltage for digital core, DVDD
1.8
3.3
1.65
1.1
1.8
3.3
V
V
V
Supply voltage for digital I/O, IOVDD
VI(analog)
Analog single-ended peak-to-peak input voltage
Between OUTP1 and
OUTM1 (differential)
600
16
16
32
32
600
16
16
32
32
Between OUTP2 and
OUTMV (single-ended)
Between OUTP3 and
Output load resistance,
RL
Ω
OUTMV (single-ended)
Between OUTP2 and
OUTMV (differential)
Between OUTP3 and
OUTMV (differential)
CL
Analog output load capacitance
Digital output capacitance
Master clock
20
20
20
20
pF
pF
100
26
100
26
MHz
kHz
°C
ADC or DAC conversion rate
Operating free-air temperature
TA
-40
85
-40
85
6
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Digital Inputs and Outputs
Fs = 8 kHz, Outputs Not Loaded
PARAMETER(1)
High-level output voltage, DOUT
MIN
TYP
MAX
UNIT
V
VOH
VOL
IIH
0.8 IOVDD
Low-level output voltage, DOUT
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
0.1 IOVDD
V
0.5
0.5
3
µA
µA
pF
pF
IIL
CI
Co
Output capacitance
5
(1) For VIH (Input high level), when IOVDD < 1.6 V, minimum VIH is 1.1V.
ADC Path Filter
(1)(2)
Fs = 8 KHz
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
MIN
TYP
IIR FILTER
MAX
UNIT
FIR FILTER
0 Hz to 30 Hz
300 Hz to 3 Hz
3.3 Hz
-0.5
0.2
0.25
0.3
-3
-0.5
-0.5
-1.5
0.2
-0.5
-0.5
0.25
0.3
-3
Filter gain relative to gain
at 1020 Hz
dB
3.6 KHz
4 kHz
-35
-74
-20
-60
≥ 4.4 KHz
(1) The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test signal is a sine wave with
0 dB = 4 VI(PP) as the reference level for the analog input signal. The pass band is 0 to 3600 Hz for an 8-KHz sample rate. This pass
band scales linearly with the sample rate.
(2) The filter characteristics are specified by design and are not tested in production.
7
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
ADC DYNAMIC PERFORMANCE
(1)
Fs = 8 KHz
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
AIC12/13/14/15
AIC12K/14K
VI = -1 dB
VI = -9 dB
VI = -40 dB
VI = -1 dB
VI = -9 dB
VI = -40 dB
VI = -1 dB
VI = -9 dB
VI = -40 dB
82
88
82
46
90
88
67
87
79
48
75
88
82
SNR
THD
Signal-to-noise ratio
78
84
82
75
90
88
Total harmonic distortion
dB
79
73
87
79
Signal-to-harmonic
distortion + noise
THD+N
(1) The test condition is a differential 1020-Hz input signal with an 8-KHz conversion rate. Input and output common mode is 1.35 V.
ADC CHANNEL CHARACTERISTICS
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
AIC12/13/14/15
AIC12K/14K
Preamplifier gain = 6
dB
VI(pp)
Single-ended input level
2
2
V
VIO
IB
Input offset voltage
Input bias current
Common-mode voltage
Dynamic range
MICIN, INPx, INMx
MICIN, INPx, INMx
±10
±10
mV
µA
V
34
34
1.35
85
1.35
85
VI = -1 dB
dB
dB
dB
dB
mV
Mute attenuation
PGA = MUTE
80
80
Intrachannel isolation
Gain error
87
87
EG
VI = -1 dB at 1020 Hz
0.6
±10
0.6
±10
EO(ADC)
ADC converter offset error
Common-mode rejection
ratio at INMx and INPx
CMRR
VI = -1 dB at 1020 Hz
50
50
dB
Idle channel noise
Input resistance
Input capacitance
V(INP,INM,MICIN) = 0 V
50
30
100
50
30
µVrms
kΩ
pF
RI
CI
TA = 25°C
TA = 25°C
IIR
2
2
5/fs
17/fs
5/fs
17/fs
S
Channel delay
FIR
S
8
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
DAC Path Filter
(1)(2)
Fs = 8 KHz
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX UNIT
FIR FILTER
IIR FILTER
0 Hz to 30 Hz
300 Hz to 3 Hz
3.3 Hz
-0.5
0.2
0.25
0.3
-3
-0.5
0.2
0.35
0.3
-3
-0.25
-0.35
-0.25
-0.75
Filter gain relative to gain
at 1020 Hz
dB
3.6 KHz
4 kHz
-40
-74
-20
-60
≥ 4.4 KHz
(1) The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the digital equivalent of a
sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition = 4 VI(PP). The pass band is 0
to 3600 Hz for an 8-KHz sample rate. This pass band scales linearly with the sample rate.
(2) The filter characteristics are specified by design and are not tested in production.
DAC DYNAMIC PERFORMANCE
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
AIC12/13/14/15
AIC12k/14k
DAC Line Output (OUTP1, OUTM1)(1)
VI = 0 dB
VI = -9 dB
VI = -40 dB
VI = 0 dB
VI = -9 dB
VI = -40 dB
VI = 0 dB
VI = -9 dB
80
92
83
51
85
83
62
82
77
44
75
70
92
83
SNR
THD
Signal-to-noise ratio
75
78
74
85
83
Total harmonic
distortion
dB
75
70
82
77
Signal-to-total harmonic
distortion + noise
THD+N
VI = -40 dB
(1) (2)
DAC Headphone Output (OUTP2, OUTP3)
VI = 0 dB
VI = -9 dB
VI = 0 dB
VI = -9 dB
VI = 0 dB
VI = -9 dB
78
71
78
73
75
69
89
81
82
80
80
78
89
81
82
80
80
78
SNR
THD
Signal-to-noise ratio
dB
dB
dB
Total harmonic
distortion
Signal-to-total harmonic
distortion + noise
THD+N
(1) (3)
DAC Speaker Output (OUTP2, OUTMV)
SNR
THD
Signal-to-noise ratio
VI = 0 dB
VI = 0 dB
91
80
dB
dB
Total harmonic
distortion
(1) The test condition is the digital equivalent of a 1020 Hz input signal with an 8-kHz conversion rate. The test is measured at output of
application schematic low-pass filter. The test is conducted in 16-bit mode.
(2) The DAC headphone output spec between OUTP2, OUTP3, and OUTMV is valid only for the AIC12/13 and the AIC12K
(3) The DAC speaker output spec between OUTP2, OUTP3, and OUTMV is valid only for the AIC12K.
9
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
DAC Channel Characteristics
PARAMETER
Dynamic range
TEST CONDITIONS
VI = 0 dB at 1020 Hz
MIN
TYP
92
MAX
UNIT
dB
Interchannel isolation
120
0.5
1.35
80
dB
EG
Gain error, 0 dB
VO = 0 dB at 1020 Hz
dB
Common mode voltage
V
(1)
Idle channel narrow band noise
Output offset voltage at OUT (differential)
Analog output voltage, (3.3 V)
0 kHz-4 kHz
125(2)
2.35
µVrms
mV
V
VOO
VO
DIN = All zeros
OUTP
10
0.35
600 Ω load at 3.3 V between
OUTP1 and OUTM1
6.7
16 Ω load at 3.3 V between
single-ended OUTP2/OUTMV and
OUTP3/OUTMV(3)
62.5
P(O)
Maximum output power
mW
16 Ω load at 3.3 V between
differential OUTP2/OUTP3 and
OUTMV(4)
125
190
8 Ω load at 3.3 V between
differential OUTP2/OUTP3 and
OUTMV(4)
IIR
5/fs
Channel delay
s
FIR
18/fs
(1) The conversion rate is 8 kHz.
(2) The Max value is valid only for the AIC12/13/14/15.
(3) The specification for maximum power output for single ended load between OUTP2/OUTMV and OUTP3/OUTMV is valid only for the
AIC12/13 and AIC12K.
(4) The specification for maximum power output for differential load between OUTP2/OUTP3 and OUTMV is valid only for the AIC12/13 and
AIC12K.
BIAS Amplifier Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
AIC12/13/14/15
AIC12K/14K
VO Output voltage
Integrated noise
Offset voltage
2.2
2.35
20
2.4
2.35
20
V
µV
300 Hz-13 kHz
10
10
mV
mA
MHz
dB
Current drive
10
10
Unity gain bandwidth
DC gain
1
1
140
120
OUTMV Amplifier Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
AIC12/13/14/15
AIC12K/14K
VO Output voltage
Integrated noise
Offset voltage
1.3
1.35
20
1.4
1.35
20
V
µV
300 Hz-13 kHz
10
10
mV
mA
MHz
dB
Current drive
62.5
1
62.5
1
Unity gain bandwidth
DC gain
120
120
10
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Power-Supply Rejection(1)
PARAMETER
TEST CONDITIONS
Differential
MIN
TYP
75
MAX UNIT
AVDD
DVDD
Supply-voltage rejection ratio, analog supply (fj = 0 to fs/2) at 1 kHz
dB
Single-ended
50
DAC channel
Supply-voltage rejection ratio, DAC channel
ADC channel
95
fj = 0 kHz to 30 kHz
dB
86
(1) Power supply rejection measurements are made with both the ADC and DAC channels idle and a 200 mV peak-to-peak signal applied
to the appropriate supply.
Power Supply
PARAMETER
Power dissipation(1)
Total current(1)
TEST CONDITIONS
MIN
TYP
MAX MIN
TYP
MAX
UNIT
AIC12/13/14/15
AIC12K/14K
All sections on
Without 16-Ω drivers
All sections on
Without 16-Ω drivers
Power down
ADC
17.8
11.2
5.4
3.4
0.01
2
23.1
16.5
7
17.8
11.2
5.4
3.4
0.01
2
PD
mW
mA
mA
I(total)
5
DAC
1
1
analog
IDD
Supply current
Ref
0.4
2
0.4
2
mA
mA
16-Ω drivers
digital(2) Coarse sampling
1
1
IDD Analog
1.4
1
1.4
1
IDD
Supply current, PLL
IDD Digital
(1) Excludes digital
(2) All section ON except the PLL condition.
11
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Functional Block Diagram AIC12/13/12k
s2d
MICIN
Preamplifier
24, 12, 6, 0 dB
INP2
INM2
Decimation Filter
SMARTDM
Serial
Port
M/S
Sigma-
Delta
ADC
FIR Filter
IIR Filter
Anti-
Aliasing
Filter
Sinc
Filter
PGA
MUX
INP1
INM1
- 42 dB to 20 dB
Step Size = 1 dB
DOUT
DIN
Digital Loopback
w/ Sidetone Control
and Mute
-3 dB to -21 dB
FS
SCLK
FSD
Analog
Loopback
Interpolation Filter
Sigma-
Delta
DAC
FIR Filter
IIR Filter
Low Pass
Filter
Sinc
Filter
OUTP1
(600 ΩDriver)
OUTM1
PGA
- 42 dB to 20 dB
Step Size = 1 dB
OUTP2
(16 ΩDriver)
d2s
d2s
V
ref
SCL
SDA
OUTP3
(16 ΩDriver)
Host Port
OUTMV
Div
16xMxNxP
Internal Clock Circuit
MCLK
BIAS
1.35 V/2.35 V @ 5 mA max
12
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Functional Block Diagram AIC14/15/14k
2
MICIN
s d
Preamplifier
24, 12, 6, 0 dB
INP2
INM2
Decimation Filter
SMARTDM
Serial
M/S
Sigma-
Delta
ADC
FIR Filter
IIR Filter
Anti-
Sinc
Filter
Port
Aliasing
PGA
MUX
Filter
INP1
INM1
− 42 dB to 20 dB
Step Size = 1 dB
DOUT
DIN
Digital Loopback
w/ Sidetone Control
and Mute
−3 dB to −21 dB
FS
SCLK
FSD
Analog
Loopback
Interpolation Filter
Sigma-
Delta
DAC
FIR Filter
IIR Filter
Low-Pass
Filter
Sinc
Filter
OUTP1
(600 ΩDriver)
OUTM1
PGA
− 42 dB to 20 dB
Step Size = 1 dB
V
ref
SCL
SDA
Host Port
BIAS
1.35 V/2.35 V @ 5 mA max
Div
16xMxNxP
Internal Clock Circuit
MCLK
13
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Definitions and Terminology
Term
Definition
Data Transfer
Interval
The time during which data is transferred from DOUT and to DIN. The interval
is 16 shift clocks and the data transfer is initiated by the falling edge of the FS
signal in standard and continuous mode.
Signal Data
Frame Sync
This refers to the input signal and all of the converted representations through
the ADC channel and the signal through the DAC channel to the analog output.
This is contrasted with the purely digital software control data.
Frame sync refers only to the falling edge of the signal FS that initiates the data
transfer interval
Frame Sync and Sampling
Period
Frame sync and sampling period is the time between falling edges of
successive FS signals.
fs
The sampling frequency
ADC Channel
ADC channel refers to all signal processing circuits between the analog input
and the digital conversion result at DOUT.
DAC channel
DAC channel refers to all signal processing circuits between the digital data
word applied to DIN and the differential output analog signal available at OUTP
and OUTM.
Dxx
DSxx
PGA
IIR
Bit position in the primary data word (xx is the bit number)
Bit position in the secondary data word (xx is the bit number)
Programmable gain amplifier
Infinite impulse response
FIR
Finite impulse response
14
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Timing Requirements
t
wH
2.4 V
2.4 V
MCLK
t
wL
t
su1
t
h1
2.4 V
RESET
Figure 1. Hardware Reset Timing
SCLK
t
d1
t
d2
t
d1
t
d2
FS
FSD
t
d3
t
en
t
dis
DOUT
DIN
D15
t
su2
t
h2
D15
Figure 2. Serial Communication Timing
TEST CONDITIONS
MIN
5
TYP
MAX
UNIT
twH
twL
Pulse duration, MCLK high
Pulse duration, MCLK low
5
Setup time, RESET, before MCLK high
(see Figure 1)
tsu1
3
2
th1
td1
td2
td3
ten
tdis
tsu2
th2
Hold time, RESET, after MCLK high (see Figure 1)
Delay time, SCLK↑ to FS/FSD↓
Delay time, SCLK↑ to FS/FSD↑
Delay time, SCLK↑ to DOUT
CL = 20 pF
5
5
ns
15
15
15
Enable time, SCLK↑ to DOUT
Disable time, SCLK↑ to DOUT
Setup time, DIN, before SCLK↓
Hold time, DIN, after SCLK↓
10
10
15
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
SDA
t
SU;OAT
t
r
t
BUF
t
f
t
t
f
t
t
r
LOW
HD;STA
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
HIGH
HD;DAT
Figure 3. I2C / S2C Timing
TEST CONDITIONS
MIN
0
MAX
UNIT
kHz
ns
tSCL
SCL clock frequency
900
tHD;STA
Hold time (repeated START condition. After this
period, the first clock pulse is generated.
100
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
Low period of the SCL clock
560
560
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
CL = 20 pF
Data set-up time
50
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
300
100
tf
tSU;STO
tBUF
100
500
Parameter Measurement Information
0
Sampling Rate at 8 kHz
-20
-40
-60
-80
-100
-120
-140
-160
0
500
1000
1500
2000
2500
3000
3500
4000
f - Frequency - Hz
Figure 4. FFT—ADC Channel (-1 dB Input)
16
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Parameter Measurement Information (continued)
0
Sampling Rate at 8 kHz
-20
-40
-60
-80
-100
-120
-140
-160
0
0
0
500
500
500
1000
1500
2000
2500
3000
3500
4000
4000
4000
f - Frequency - Hz
Figure 5. FFT—ADC Channel (-9 dB Input)
0
Sampling Rate at 8 kHz
-20
-40
-60
-80
-100
-120
-140
-160
1000
1500
2000
2500
3000
3500
f - Frequency - Hz
Figure 6. FFT—DAC Channel (0 dB Input)
0
Sampling Rate at 8 kHz
-20
-40
-60
-80
-100
-120
-140
-160
1000
1500
2000
2500
3000
3500
f - Frequency - Hz
Figure 7. FFT—DAC Channel (-9 dB Input)
17
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Parameter Measurement Information (continued)
0
-20
ADC at 8 kHz
Fs = 32 kHz
-40
-60
-80
-100
-120
-140
0
2000
4000
6000
8000
10000
12000
14000
16000
f - Frequency - Hz
Figure 8. FFT—ADC Channel in FIR/IIR Bypass Mode (-1 dB Input)
0
DAC at 8 kHz
Fs = 32 kHz
-20
-40
-60
-80
-100
-120
-140
0
2000
4000
6000
8000
10000
12000
14000
16000
f - Frequency - Hz
Figure 9. FFT—DAC Channel in FIR/IIR Bypass Mode (0 dB Input)
18
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
ADC FILTER GAIN
vs
FREQUENCY RESPONSE (FIR)
ADC FILTER GAIN
vs
FREQUENCY RESPONSE (IIR)
5
0
5
0
−5
−10
−15
−20
−5
−10
−15
−20
−25
−25
−30
−35
−40
−45
−30
0
500 1000 1500 2000 2500 3000 3500 4000
f − Frequency − Hz
0
500 1000 1500 2000 2500 3000 3500 4000
f − Frequency − Hz
Figure 10.
Figure 11.
ADC IIR FILTER GROUP DELAY
DAC IIR FILTER GROUP DELAY
vs
vs
FREQUENCY
FREQUENCY RESPONSE
9
8
9
8
7
6
5
4
7
6
5
4
3
2
3
2
1
1
0
0
0
500 1000 1500 2000 2500 3000 3500 4000
f - Frequency - Hz
0
500 1000 1500 2000 2500 3000 3500 4000
f - Frequency - Hz
Figure 12.
Figure 13.
19
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
ADC FILTER GAIN
vs
FREQUENCY (FIR/IIR BYPASS)
DAC FILTER GAIN
vs
FREQUENCY (FIR/IIR BYPASS)
4
2
4
2
0
-2
-4
-6
0
-2
-4
-6
-8
-8
-10
-10
-12
-14
-12
-14
0
2000 4000 6000 8000 10 k 12 k 14 k 16 k
f - Frequency - Hz
0
2000 4000 6000 8000 10 k 12 k 14 k 16 k
f - Frequency - Hz
Figure 14.
Figure 15.
DAC IIR
vs
FREQUENCY RESPONSE
DAC FIR
vs
FREQUENCY RESPONSE
20
20
OSR = 512
OSR = 128
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−100
−120
−120
−140
0
1000 2000 3000 4000 5000 6000 7000 8000
f − Frequency − Hz
0
1000 2000 3000 4000 5000 6000 7000 8000
f − Frequency − Hz
Figure 16.
Figure 17.
20
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
DAC FIR
vs
FREQUENCY RESPONSE
DAC FIR
vs
FREQUENCY RESPONSE
20
0
20
0
OSR = 128
OSR = 256
−20
−40
−20
−40
−60
−60
−80
−80
−100
−100
−120
−140
−120
−140
0
0
1000 2000 3000 4000 5000 6000 7000 8000
f − Frequency − Hz
1000 2000 3000 4000 5000 6000 7000 8000
f − Frequency − Hz
Figure 18.
Figure 19.
Functional Description
Operating Frequencies (see Notes)
The sampling frequency is the frequency of the frame sync (FS) signal whose falling edge starts digital-data
transfer for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by the
following equations:
•
•
Coarse sampling frequency (default):
–
The coarse sampling is selected by programming P = 8 in the control register 4, which is the default
configuration of AIC1x on power-up or reset.
–
FS = Sampling (conversion) frequency = MCLK ÷ (16 × M × N × 8)
Fine sampling frequency (see step 5):
–
FS = Sampling (conversion) frequency = MCLK ÷ (16 × M × N × P)
NOTES:
1. Use control register 4 to set the following values of M, N, and P
2. M = 1, 2, . . . , 128
3. N = 1, 2,..., 16
4. P = 1, 2, ..., 8
5. The fine sampling rate needs an on-chip Phase Lock Loop (frequency multiplier) to generate
internal clocks. The PLL requires the relationship between MCLK and P to meet the following
condition:
10 MHz ≤ (MCLK ÷ P) ≤ 25 MHz. The output of the PLL is only used to generate internal clocks
that are needed by the data converters. Other clocks such as the serial interface clocks in master
mode are not generated from the PLL output. The clock generation scheme is as shown in
Figure 20.
21
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Functional Description (continued)
X 8
(DLL)
Digital
128 FS
MCLK
1/(MN)
1/P
en_dll
*
SCLK
FS
(no_dev x mode) / (MNP)
1 / (16 x mode x no_dev)
*
SCLK may not be an uniform clock depending upon values of devnum, mode, and MNP
When P = 8, DLL(PLL) is enabled
M = 1 - 128
N = 1 - 16
P = 1- 8
devnum = number of devices in cascade
mode = 1 (for continious data tranfer mode)
mode = 2 (for programming mode)
Figure 20. AIC1x Clock Tree Architecture
6. Both equation of FS require that the following conditions be met:
–
–
(M × N × P) ≥ (devnum × mode) if the FIR/IIR filter is not bypassed.
[Integer (M ÷ 4) × N × P] ≥ (devnum × mode) if the FIR/IIR filter is bypassed.
Where:
–
–
devnum is the number of codec channels connecting in cascade mode.
mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
7. If the DAC OSR is set to 512, then M needs to be a multiple of 4. If the DAC OSR is set to 256,
then M needs to be a multiple of 2. M can take any value between 1 and 128 if the OSR is set to
128.
EXAMPLE:
The MCLK that comes from the DSP 'C5402 CLKOUT equals to 20.48 MHz, and the conversion rate
of 8 kHz is desired. First, set P = 1 to satisfy condition step 5 above so that (MCLK ÷ P) = 20.48 MHz
÷ 1 = 20.48 MHz. Next, pick M = 10 and N = 16 to satisfy step 6 above and derive 8 kHz for FS.
20.48 MHz
FS +
+ 8 kHz
(16 10 16 1)
Internal Architecture
Analog Low-Pass Filter
The built-in analog low-pass filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.
Sigma-Delta ADC
The analog-to-digital converter is a sigma-delta modulator with 128-x oversampling. The ADC provides
high-resolution, low-noise performance using oversampling techniques. Due to the oversampling employed, only
single pole R-C filters are required on the analog inputs.
22
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Functional Description (continued)
Decimation Filter
The decimation filters are either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter
provides linear-phase output with 17/fs group delay, whereas the IIR filter generates nonlinear phase output with
negligible group delay. The decimation filters reduce the digital data rate to the sampling rate. This is
accomplished by decimating with a ratio of 1:128. The output of the decimation filter is a 16-bit 2s-complement
data word clocking at the sample rate selected. The BW of the filter is (0.45 × FS) and scales linearly with the
sample rate.
Sigma-Delta DAC
The digital-to-analog converter is a sigma-delta modulator with 128/256/512-x oversampling. The DAC provides
high-resolution, low-noise performance using oversampling techniques. The oversampling ratio in DAC is
programmable to 256/512 using bits D4-D3 of control register 3, the default being 128. Oversampling ratio of
512 can be used when FS is a maximum of 8 Ksps and an oversampling ratio of 256 can be used when FS is a
maximum of a 16 Ksps. M should be a multiple of 2 for an oversampling ratio of 256 and 4 for oversampling
ratio of 512.
Interpolation Filter
The interpolation filters are either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter
provides linear-phase output with 18/fs group delay, whereas the IIR filter generates nonlinear phase output with
negligible group delay. The interpolation filter resamples the digital data at a rate of 128/256/512 times the
incoming sample rate, based on the oversampling rate of DAC. The high-speed data output from the
interpolation filter is then used in the sigma-delta DAC. The BW of the filter is (0.45 × FS) and scales linearly
with the sample rate.
Analog/Digital Loopback
The analog and digital loopbacks provide a means of testing the data ADC/DAC channels and can be used for
in-circuit system level tests. The analog loopback always has the priority to route the DAC low pass filter output
into the analog input where it is then converted by the ADC to a digital word. The digital loopback routes the
ADC output to the DAC input on the device. Analog loopback is enabled by writing a 1 to bit D2 in the control
register 1. Digital loopback is enabled by writing a 1 to bit D1 in control register 1.
Side-Tone Loopback
The side-tone digital loopback attenuates the ADC output and mixes it with the input of the DAC. The level of the
side tone is set by DSTG, bits D5-D3 of the control register 5C.
ADC PGA
TLV320AIC1x has a built-in PGA for controlling the signal levels at ADC outputs. ADC PGA gain setting can be
selected by writing into bits D5-D0 of register 5A. The PGA range of the ADC channel is 20 dB to -42 dB in
steps of 1 dB and mute. To avoid sudden jumps in signal levels with PGA changes, the gains are applied
internally with zero-crossovers.
DAC PGA
TLV320AIC1x has a built-in PGA for controlling the analog output signal levels in DAC channel. DAC PGA gain
setting can selected by writing into bits D5-D0 of register 5B. The PGA range of the DAC channel is 20 dB to -42
dB in steps of 1 dB, and mute. To avoid sudden pop-sounds with power-up/down and gain changes the
power-up/down and gain changes for DAC channel are applied internally with zero-crossovers.
Analog Input/Output
The TLV320AIC1x has three programmable analog inputs and three programmable analog outputs. Bits D2-D1
of control register 6 select the analog input source from MICIN, INP1/M1, or INP2/M2. All analog I/O are either
single-ended or differential. All analog input signals are self-biased to 1.35 V. The three analog outputs are
configured by bits D7, D6, D5, and D4-D3 of control register 6.
23
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Functional Description (continued)
MIC Input
TLV320AIC1x supports single ended microphone input. This can be used by connecting the external single
ended source through ac coupling to the MICIN pin. This channel is selected by writing 01 or 10 into bits D2-D1
in control register 6. The single ended input is supported in two modes.
Writing 01 into bits D2-D1 chooses self biased MICIN mode. In this mode, the device internally self-biases the
input at 1.35V. For best noise performance, the user should bias the microphone circuit using the BIAS voltage
generated by the device as shown in Figure 21.
Writing 10 into bits D2-D1 chooses pseudo-differential MICIN mode. In this mode, the single ended input is
connected through ac-coupling to MICIN and the bias voltage used to generate the signal is also ac coupled to
INM1 as shown in Figure 22. For best noise performance, the MICIN and INM1 lines must be routed in similar
fashion from the microphone to the device for noise cancellation.
For high quality performance, the single ended signal is converted internally into differential signal before being
converted. To improve the dynamic range with different types of microphones, the device supports a preamplifier
with gain settings of 0/6/12/24 dB. This can be chosen by writing into bits D1-D0 of control register 5C.
0.1 µF
10 kΩ
0.1 µF
Electret
Microphone
BIAS
INM1
BIAS
10 kΩ
0.1 µF
Electret
Microphone
MICIN
MICIN
TLV320AIC12
TLV320AIC12
(a) Single Ended
(b) Pseudo -Differential (High Quality)
Figure 21. Microphone Interface
INP and INM Input
To produce common-mode rejection of unwanted signal performance, the analog signal is processed
differentially until it is converted to digital data. The signal applied to the terminals INM1/2 and INP1/2 are
differential to preserve device specifications (see Figure 22). The signal source driving analog inputs (INP1/2
and INM1/2) should have low source impedance for lowest noise performance and accuracy. To obtain
maximum dynamic range, the signal should be ac-coupled to the input terminal.
INP1 or INP2
V
(INP)
1.35 V
INM1 or INM2
V
(INM)
TLV320AIC12
Figure 22. INP and INM Internal Self-Biased Circuit
Single-Ended Analog Input
The two differential inputs of (INP1/M1 and INP2/M2) can be configured to work as single-ended inputs by
connecting INP to the analog input and INM to ground (see Figure 23).
24
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Functional Description (continued)
C
INP1 or INP2
INM1 or INM2
Analog Input
C
Figure 23. Single-Ended Input
Analog Output
The OUTP and OUTM are differential output from the DAC channel. The OUTP1 and OUTM1 can drive a load
of 600-Ω directly and be either differential or single-ended (see Figure 24). The OUTP2 and OUTP3 are output
from two audio amplifiers to drive low-voltage speakers like those in the handset and headset. They can drive a
load of 16-Ω directly and be configured as either differential output or single-ended output as by bit D7 of the
control register 6 (see Figure 25). If OUTP2 and OUTP3 are differential output, the OUTMV pin becomes the
common inverting output. Both OUTP2 and OUTP3 can be used simultaneously if each differential load RL >
32Ω . This is because OUTMV amplifier can drive a maximum load of 16 Ω only (only one driver used) or a
parallel combination of two 32-Ω loads (both drivers used). If both OUTP2 and OUTP3 are used simultaneously,
they are muted at the same time if MUTE is selected.
Otherwise, the OUTMV pin is configured as the virtual ground for single-ended output and equal to the common
mode voltage at 1.35 V.
C
OUTP1
OUTP1
RL
RL
OUTM1
OUTM1
Differential Output OUTP/OUTM
Single-Ended Output OUTP/OUTM
Figure 24. OUTP1/OUTM1 Output
OUTP2
RL
OUTMV
RL
OUTP3
Figure 25. Single-Ended/Differential Connection of OUTP2/OUTP3 Output
Analog Output Configuration
SPEAKER DRIVER CONFIGURATION
NO. OF SPEAKER DRIVERS ON
MIN LOAD
16-Ω
Single-ended
Single-ended
Differential
1
2
1
32-Ω
16-Ω
25
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Functional Description (continued)
Analog Output Configuration (continued)
SPEAKER DRIVER CONFIGURATION
Differential
NO. OF SPEAKER DRIVERS ON
MIN LOAD
2
32-Ω
IIR/FIR Control
Overflow Flags
The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog
signal has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an
overflow flag (bit D4) of control register 1 indicating that the digital input has exceeded the range of internal
interpolation filter calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user
reads the register. Reading this value resets the overflow flag. These flags need to be reset after power-up by
reading the register. If FIR/IIR overflow occurs, the input signal is attenuated by either the PGA or some other
method.
IIR/FIR Bypass Mode
An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This
mode is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to
four times normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS =
8 kHz) with IIR/FIR, if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4×8 kHz = 32 kHz. The sinc
filters of the two paths can not be bypassed. A maximum of eight devices in cascade can be supported in the
IIR/FIR bypassed mode.
In this mode , the ADC channel outputs data which has been decimated only until 4Fs. Similarly DAC channel
input needs to be preinterpolated to 4Fs before being given to the device. This mode allows users the flexibility
to implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR
Bypass mode. The frequency responses of the IIR/FIR bypass modes are shown in Figure 14 and Figure 15.
System Reset and Power Management
Software and Hardware Reset
The TLV320AIC1x resets internal counters and registers in response to either of two events:
•
•
A low-going reset pulse is applied to terminal RESET
A 1 is written to the programmable software reset bits (D5 of control register 3)
•
NOTE: The TLV320AIC1x requires a power-up reset applied to the RESET pin before normal operation is
started.
Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active
low) signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC1x
enters the initialization cycle that lasts for 132 MCLKs, during which the serial port of the DSP must be tristated.
The initialization sequence performed by the 'AIC1x is known as auto cascade detection (ACD). ACD is a
mechanism that allows a device to know its address in a cascade chain. Up to 16 'AIC1x devices can be
cascaded together. The master device is the first device on the chain (i.e. the FS of the master is connected to
the FS of the DSP). During ACD, each device gets to know the number of devices in the chain as well as its
relative position in the chain. This is done on hardware reset. Therefore, after power up, a hardware reset must
be done. ACD requires 132 MCLKs after reset to complete operation. The number of MCLKs is independent of
the number of devices in the chain. Adjacent devices in the chain have their FS and FSD pins connected to
each other. The master device FS is connected to the FS pin of the DSP. The FSD pin on the last device in the
chain is pulled high. The master device has the highest address (i.e. 0, the next device in the chain has an
address of 1, followed by 2 etc.).
During the first 64 MCLKs, FS is configured as an output and FSD as an input. During the next 64 MCLKs, FS is
configured as an input and FSD as an output. The master device always has FS configured as an output and
the last slave in the cascade (i.e. channel with address 0) always has FSD configured as an input.
26
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks between
ACD starting (reset) and the FSD going high. During the next 64 MCLKs, the device counts the number of
clocks till FS is pulled low. The sum total of the counts in the first phase and the second phase is the number of
devices in the channel.
For a cascaded system, the rise time of H/W RESET needs to be less than the MCLK period and should satisfy
setup time requirement of 2 ns with respect to MCLK rise-edge. In stand-alone-slave mode SCLK must be
running during RESET. If more than one codec is cascaded, RESET must be synchronized to MCLK.
Additionally, all devices must see the same edge of MCLK within a window of 0.5 ns The reset signal need not
be synchronized with MCLK when the codec is in stand-alone master or slave configuration.
Power Management
Most of the device (all except the digital interface) enters the power-down mode when D7 and D6, in control
register 3, are set to 1. When the PWRDN pin is low, the entire device is powered down. In either case, register
contents are preserved.
The amount of power drawn during software power down is higher than during a hardware power down because
of the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs.
Software Power-Down
Data bits D7 and D6 of control register 3 are used by TLV320AIC1x to turn on or off the software power-down
mode, which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In the
software power-down, the digital interface circuit is still active while the internal ADC and DAC channel and
differential outputs OUTPx and OUTMx are disabled, and DOUT is put in 3-state in the data frame only. Register
data in the control frame is still accepted via DIN, but data in the data frame is ignored. The device returns to
normal operation when D7 and D6 of control register 3 are reset.
Hardware Power-Down
The TLV320AIC1x requires the PWRDN signal to be synchronized with MCLK. When PWRDN is held low, the
device enters hardware power-down mode. In this state, the internal clock control circuit and the differential
outputs are disabled. All other digital I/Os are disabled and DIN cannot accept any data input. The device can
only be returned to normal operation by holding PWRDN high. Getting out of the power-down mode (i.e. bringing
PWRDN from low to high state) requires that the low-to-high transition of PWRDN be synchronous to the rising
edge of MCLK. If there is no need for the hardware power-down mode feature of the device, the PWRDN pin
must be tied high.
Host Port Interface
The host port uses a 2-wire serial interface (SCL, SDA) to program the AIC1x's six control registers and
selectable protocol between S2C mode and I2C mode. The S2C is a write-only mode and the I2C is a read-write
mode selected by setting the bits D1 and D0 of control register 2 to 00 or 01. If the host interface is not needed
the two pins of SCL and SDA can be programmed to become general-purpose I/Os by setting the bits D1 and
D0 of control register 2 to 10 or 11. If selected to be used as I/O pins, the SDA and SCL pins become output
and input pins respectively, determined by D1 and D0.
Both S2C and I2C require a SMARTDM device address to communicate with the AIC1x. One of SMARTDMs
advanced features is the automatic cascade detection (ACD) that enables SMARTDM to automatically detect
the total number of codecs in the serial connection and use this information to assign each codec a distinct
SMARTDM device address. Table 1 lists device addresses assigned to each codec in the cascade by the
SMARTDM. The master always has the highest position in the cascade. For example, if there is a total of 8
codecs in the cascade (i.e., one master and 7 slaves), then the device addresses in row 8 are used in which the
master is codec 7 with a device address of 0111.
Table 1. SMARTDM Device Addresses
TOTAL
CODEC POSITION IN CASCADE
CODECS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0000
27
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Table 1. SMARTDM Device Addresses (continued)
TOTAL
CODEC POSITION IN CASCADE
CODECS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
3
0001 0000
0010 0001 0000
0011 0010 0001 0000
0100 0011 0010 0001 0000
0101 0100 0011 0010 0001 0000
0110 0101 0100 0011 0010 0001 0000
0111 0110 0101 0100 0011 0010 0001 0000
1000 0111 0110 0101 0100 0011 0010 0001 0000
1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
4
5
6
7
8
9
10
11
12
13
14
15
16
S2C (Start-Stop Communication)
The S2C is a write-only interface selected by programming bits D1-D0 of control register 2 to 01. The SDA input
is normally in a high state, pulled low (START bit) to start the communication, and pulled high (STOP bit) after
the transmission of the LSB. SCLK and FS must be active during register programming. Figure 26 shows the
timing diagram of S2C. The S2C also supports a broadcast mode in which the same register of all devices in
cascade is programmed in a single write. To use S2Cs broadcast mode, execute the following steps:
1. Write 111 1000 1111 1111 after the start bit to enable the broadcast mode.
2. Write data to program control register as specified in Figure 26 with bits D14-D11 = XXXX (don't care).
3. Write 111 1000 0000 0000 after the start bit to disable the broadcast mode.
SCL
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDA
SMARTDM Device
Address
Register
Address
Register Content
Start Bit = 0
Stop Bit = 1
(see Table 1)
Figure 26. S2C Programming
I2C
•
•
Each I2C read-from or write-to 'AIC1xs control register is given by index register address.
Read/write sequence always starts with the first byte as I2C address followed by 0. During the second byte,
default/broadcast mode is set and the index register address is initialized. For write operation control register,
data to be written is given from the third byte onwards. For read operation, stop-start is performed after the
second byte. Now the first byte is I2C address followed by 1. From the second byte onwards, control register
data appears.
•
•
Each time read/write is performed, the index register address is incremented so that next read/write is
performed on the next control register.
During the first write cycle and all write cycles in the broadcast, only the device with address 0000 issues
ACK to the I2C.
28
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
2
I C Write Sequence
SCL
SDA
A4
A1
A6 A5
A3 A2
A0
B7 B6 B5 B4 B3 R2 R1 R0
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0
ACK
ACK
ACK
ACK
0
D7
I2C I2C I2C
4
6
5
Start Bit = 0
SMARTDM Device
Address
Index Register Address
(Index)
11111 = Broadcast Mode
Control Register Data for Write
(Index+1)
00000 = Default
Control Register Data for Write
(Index)
(see Table 1)
Programmable I2C Device Address
Set by Control Register 2
Figure 27. I2C Write Sequence
2
I C Read Sequence
SCL
ACK
A6
A5
A4
A3
A2
A0
0
B7
B6
B5
B4
B3
R2
R1
R0
ACK
A1
SDA
I2C I2C I2C
Start Bit = 0
Stop Bit = 1
xxxxx = Don't Care
6
5
4
Index Register Address
(Index)
SMARTDM Device Address
(see Table 1)
Programmable 12C Device Address
Set by Control Register 2
SCL
ACK
ACK
A6
A5
A2
A0
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
A4
A3
A1
ACK
SDA
I2C I2C I2C
4
6
5
Start Bit = 0
Control Register Data
(Index)
Control Register Data
(Index+1)
SMARTDM Device Address
(see Table 1)
Programmable 12C Device Address
Set by Control Register 2
Figure 28. I2C Read Sequence
Each AIC has an index register address. To perform a write operation, make the LSB of the first byte as 0 (write)
(see Figure 29). During the second byte, the index register address is initialized and mode (broadcast/default) is
set. From the third byte onwards, write data to the control register (given by index register) and increment the
index register until stop or repeated start occurs. For operation, make the LSB of the first byte as 1 (read). From
the second byte onwards, AIC starts transmitting data from the control register (given by the index register) and
increments the index register. For setting the index register perform operation the same as write case for 2
bytes, and then give a stop or repeated start.
•
S/Sr -> Start/Repeated Start.
29
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Write Mode
Default/Broadcast
(00000/11111)
Increment Index Reg. Address
8 Bit
7 Bit
1 Bit
R/W
8 Bit
8 Bit
2
S/Sr I C Device Address (3 Bit)+
Mode (5 Bit) + Index Reg
Address
Ack
Ack Control Reg. Data
(Write)
Ack
Control Reg. Data
(Write)
Dtdmsp Device Address (+)
= 0
(3 Bit)
To the Address Given
by Index Reg. Address
To the Address Given
by Index Reg. Address
Read Mode
Increment Index Reg. Address
8 Bit
Increment Index Reg. Address
7 Bit
1 Bit
R/W
8 Bit
2
S/Sr I C Device Address (3 Bit)+
Control Reg. Data
(Read)
Ack
Ack Control Reg. Data
(Read)
Ack
Dtdmsp Device Address (+)
= 1
From the Address Given
by Index Reg. Address
From the Address Given
by Index Reg. Address
For Initializing Index Reg Address
Stop
7 Bit
1 Bit
R/W
8 Bit
2
S/Sr I C Device Address (3 Bit)+
Mode (5 Bit) + Index Reg.
Ack
Ack
Address
(3 Bit)
Dtdmsp Device Address (+)
= 0
Figure 29. Index Register Addresses
Smart Time Division Multiplexed Serial Port (SMARTDM)
The Smart time division multiplexed serial port (SMARTDM) uses the 4 wires of DOUT, DIN, SCLK, and FS to
transfer data into and out of the AIC1x. The TLV320AIC1x's SMARTDM supports three serial interface
configurations (see Table 2): stand-alone master, stand-alone slave, and master-slave cascade, employing a
time division multiplexed (TDM) scheme (a cascade of only-slaves is not supported). The SMARTDM allows for
a serial connection of up to 16 codecs to a single serial port. Data communication in the three serial interface
configurations can be carried out in either standard operation (Default) or turbo operation. Each operation has
two modes; programming mode (default mode) and continuous data transfer mode. To switch from the
programming mode to the continuous data transfer mode, set bit D6 of control register 1 to 1, which is reset
automatically after switching back to programming mode. The TLV320AIC1x can be switched back from the
continuous data transfer mode to the programming mode by setting the LSB of the data on DIN to 1, only if the
data format is (15+1), as selected by bit 0 of control register 1. The SMARTDM automatically adjusts the number
of time slots per frame sync (FS) to match the number of codecs in the serial interface so that no time slot is
wasted. Both the programming mode and the continuous data transfer mode of the TLV320AIC1x are
compatible with the TLV320AIC10. The TLV320AIC1x provides primary/secondary communication and
continuous data transfer with improvements and eliminates the requirements for hardware and software requests
for secondary communication as seen in other devices. The TLV320AIC1x continuous data transfer mode now
supports both master/slave stand alone and cascade.
Table 2. Serial Interface Configurations
M/S PIN
FSD PIN
MASTER
TLV320AIC1x CONNECTIONS
COMMENTS
MASTER
SLAVE
NA
SLAVE
NA
Stand-alone master
Stand-alone slave
High
NA
Pull high
NA
Low
Pull-low
Connect to the next slave's FS
(see Figure 32)
Master-slave cascade
Slave-slave cascade
High
NA
Low
NA
Last slave's FSD pin is pulled high
Not supported
NA
NA
30
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Digital Interface
Clock Source (MCLK, SCLK)
MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout
the device. SCLK is the bit clock used to receive and transmit data synchronously. When the device is in the
master mode, SCLK and FS are output and derived from MCLK in order to provide clocking the serial
communications between the device and a digital signal processor (DSP). When in the slave mode, SCLK and
FS are inputs. In the non-turbo mode (TURBO = 0), SCLK frequency is defined by:
•
SCLK = (16 × FS × #Devices × mode)
Where:
FS is the frame-sync frequency. #Device is the number of the device in cascade. Mode is equal to 1 for
•
continuous data transfer mode and 2 for programming mode.
In turbo mode, see the Turbo Mode Operation section of this data sheet.
Serial Data Out (DOUT)
DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data
word is the ADC conversion result. In the control frame, the data is the register read results when requested by
the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all
zeroes. Valid data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The
first bit transmitted on the falling edge of FS is the MSB of valid data.
Serial Data In (DIN)
The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of FS. In
a data frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is used, the
LSB (D0) is set to 1 to switch from the continuous data transfer mode to the programming mode. In a control
frame, the data is the control and configuration data that sets the device for a particular function as described in
the Control Register Programming section.
Frame-Sync FS
The frame-sync signal (FS) indicates the device is ready to send and receive data. The FS is an output if the
M/S pin is connected to HI (master mode), and an input if the M/S pin is connected to LO (slave mode).
The start of valid data is synchronized on the falling edge of the FS signal. In nonturbo mode, the FS signal
must be present every (16 SCLK × mode). However, in turbo mode, the number of SCLK per FS cycle can vary.
The frequency of FS is defined as the sampling rate of the TLV320AIC1x and derived from the master clock,
MCLK, as follows (see Operating Frequencies section for details):
•
FS = MCLK ÷ (16 × P × N × M)
0
1
14
15
16
SCLK
16 SCLKs
FS
DIN/DOUT
(16 Bit)
D15
MSB
D14
D1
D0
LSB
D15
Figure 30. Timing Diagram of FS
Cascade Mode and Frame-Sync Delayed (FSD)
In cascade mode, the DSP should be in slave mode, it receives all frame-sync pulses from the master though
31
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
the master's FS. The master FSD is output to the first slave and the first slave's FSD is output to the second
slave device and so on. When the codecs are configured in cascade mode, MCLK must be connected in star
configuration to ensure that MCLK can propagate simultaneously to all the codecs in the chain in less then 2 ps.
Figure 32 shows the cascade of 4 TLV320AIC1xs in which the closest one to DSP is the master and the rest are
slaves. The FSD output of each device is input to the FS terminal of the succeeding device. Figure 30 shows the
FSD timing sequence in the cascade.
Stand-Alone Slave
In the stand-alone slave connection, the FS and SCLK are input in which they need to be synchronized to each
other and programmed according to the Operating Frequencies section of this data sheet. The FS and SCLK
input are not required to synchronize to the MCLK input but must remain active at all times to assure continuous
sampling in the data converter. FS is output for initial 132 MCLK and it is kept low. DSP needs to keep FS low or
high-impedance state for this period to avoid contention on FS.
In addition, SCLK must be running at all times when the device is put into reset when in slave mode.
32
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Asynchronous Sampling (Codecs in cascade are sampled at different sampling frequency)
The 'AIC1x SMARTDM supports a different sampling frequency between the codecs in cascade connecting to a
single serial port. All codecs are required to have a common frame synch frequency. The FS signal is calculated
using step 1. The desired sampling frequencies of the individual codecs are then calculated using bits D2-D0 of
control register 3 as shown in step 2 and step 3.
1. FS = MCLK ÷ (16 × M × N × P)
2. FS = n1 × fs1 (n1 = 1,2, 8 defined in the control register 3 of CODEC1)
3. FS = n2 × fs2 (n2 = 1,2, 8 defined in the control register 3 of CODEC2)
The DSP should transfer data at the common FS rate used by the serial interface. The task of decimating and
interpolating the data suitably for each codec is left to the DSP.
0
1
13
14
15
SCLK
FS
16 SCLKs
FSD
(Output)
DIN/DOUT
(16 Bit)
D15
MSB
D14
D2
D1
LSB
D0
Figure 31. Timing Diagram for FSD Output
100 MHz Max
CLKOUT
DX
DR
Master
MCLK
Slave 2
MCLK
Slave 1
MCLK
Slave 0
MCLK
FSX
FSR
DIN
DOUT
FSD
DIN
DIN
DIN
IOVDD
1 kΩ
FS
DOUT
FS
DOUT
FS
DOUT
FS
FSD
M/S
FSD
M/S
FSD
M/S
CLKX
CLKR
IOVDD
M/S
SCLK
SCLK
SCLK
SCLK
TMS320C5x
Figure 32. Cascade Connection (To DSP Interface)
33
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Master FS
Master
Slave2
Slave1
Slave0
Master
Slave2
DIN/DOUT
Master FSD,
Slave 2 FS
Slave 2 FSD,
Slave 1 FS
Slave 1 FSD,
Slave 0 FS
Slave 0 FSD,
(see Note)
A. NOTE: Slave 0 FSD should be pulled high for stand-alone-master or cascade configuration. FSD must be pulled low
for stand-alone-slave configuration.
Figure 33. Master-Slave Frame-Sync Timing in Continuous Data Transfer Mode
Programming Mode
In the programming mode, the FS signal starts the input/output data stream. Each period of FS contains two
frames as shown in Figure 34 and Figure 35: data frame and control frame. The data frame contains data
transmitted from the ADC or to the DAC. The control frame contains data to program the AIC1xs control
registers. The SMARTDM automatically sets the number of time slots per frame equal to 2 times the number of
AIC1x codecs in the interface. Each time slot contains 16-bit data. The SCLK is used to perform data transfer for
the serial interface between the AIC1x codecs and the DSP. The frequency of SCLK varies depending on the
selected mode of serial interface. In the stand alone-mode, there are 32 SCLKs (or two time slots) per sampling
period. In the master-slave cascade mode, the number of SLCKs equals 32 x (Number of codecs in the
cascade). The digital output data from the ADC is taken from DOUT. The digital input data for the DAC is
applied to DIN. The synchronization clock for the serial communication data and the frame-sync is taken from
SCLK. The frame-sync signal that starts the ADC and DAC data transfer interval is taken from FS. The
SMARTDM also provides a turbo mode, in which the FS's frequency is always the device's sampling frequency,
but SCLK is running at a much higher speed. Thus, there are more than 32 SCLKs per sampling period, in
which the data frame and control frame occupy only the first 32 SCLKs from the falling edge of the frame-sync
FS (see the Digital Interface Section for more details).
Slot Number 0
Slot Number 1
SCLK
FS
DIN
16-Bit DAC Data
16-Bit ADC Data
Register Data Write
Register Data Read
DOUT
Figure 34. Standard Operation/Programming Mode: Stand-Alone Timing
34
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Slot
Number
0
1
2
2n-3 2n-2 2n-1
SCLK
FS
16 SCLKs Per Slot
DIN/
DOUT
Master Slave Slave
n-2 n-3
Slave Slave
Slave Master Slave Slave
n-2 n-3
Slave Slave Slave
2
1
0
2
1
0
Data Frame
NOTE: n is the total number of AIC12s in the cascade
Control Frame
(Register R/W)
Figure 35. Standard Operation/Programming Mode: Master-Slave Cascade Timing
Continuous Data Transfer Mode
The continuous data transfer mode, selected by setting bit D6 of the control register 1 to 1, contains conversion
data only. In continuous data transfer mode, the control frame is eliminated and the period of FS signal contains
only the data frame in which the 16-bit data is transferred contiguously, with no inactivity between bits. The
control frame can be reactivated by setting the LSB of DIN data to 1 if the data is in the 15+1 format. To return
the programming mode in the 16-bit DAC data format mode, write 0 in bit D6 of control register 1 using I2C or
S2C, or do a hardware reset to come out of continuous data transfer mode. If continuous data transfer mode is
used with the turbo mode, the codec should first be set in turbo mode before it is switched from the default
programming mode to the continuous data transfer mode.
Slot Number 0
Slot Number 0
SCLK
FS
Data Frame
Data Frame
DIN
(Sample 3)
(Sample 3)
16-Bit DAC Data (Sample 2)
16-Bit DAC Data (Sample 1)
16-Bit ADC Data (Sample 2)
DOUT
16-Bit ADC Data (Sample 1)
Figure 36. Standard Operation/Continuous Data Transfer Mode: Stand-Alone Timing
35
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Slot
Number
0
1
2
n-3
n-2
n-1
0
1
2
n-3
n-2
n-1
SCLK
16 SCLKs Per Time Slot
FS
DIN/
DOUT
Master Slave Slave
n-2 n-3
Slave Slave Slave Master Slave Slave
n-2 n-3
Slave Slave Slave
2
1
0
2
1
0
Data Frame / Sample 1
NOTE: n is the total number of AIC12s in the cascade
Data Frame / Sample 2
Figure 37. Standard Operation/Continuous Data Transfer Mode: Master-Slave Cascade Timing
Turbo Operation (SCLK)
Setting TURBO = 1 (bit D7) in control register 2 enables the turbo mode that requires the following condition to
be met:
•
For master with SCLK as output, M × N > #Devices × mode
Where:
•
M, N, and P are clock divider values defined in the control register 4. #Device is the number of the device in
cascade. Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
For slave, SCLK is the input with max allowable speed of 25 MHz (no condition is required).
The number of SCLKs per FS can be ≥ (16 × mode).
•
•
The turbo operation is useful for applications that require more bandwidth for multitasking processing per
sampling period. In the turbo mode (see Figure 38), the FSs frequency is always the device's sampling
frequency but the SCLK is running at much higher speed than that described in Section 3.6.1. The output SCLK
frequency is equal to (MCLK/P) in master mode and up to a maximum speed of 25 MHz for both master and
slave AIC1x. The data/control frame is still 16-SCLK long and the FS is one-SCLK pulse. If the 'AIC1x is in slave
mode, and the device is not set to turbo mode, only the first FS is used to synchronize the data transfer. The
'AIC1x ignores all subsequent FS signals and utilizes an internally generated FS. However, if the 'AIC1x is set to
turbo mode while in slave mode, then the data transfer synchronizes on every FS signal. Therefore, it is
recommended that if the 'AIC1x is set to slave mode, then turbo mode is used. Also note that in turbo mode, it is
recommended that SCLK be a multiple of 32 x FS
36
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
TURBO PROGRAMMING MODE
Stand-Alone Case:
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Turbo SCLK
One SCLK
Sampling Period
FS
Data Frame Control Frame
Data Frame Control Frame
Hi-Z
...
...
...
...
15 14
1
0
15 14
1
0
15 14
1
0
15 14
1 0
DIN / DOUT
Cascade Case (Master + 4 Slaves):
Turbo SCLK
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Sampling Period
FS
Control Frame
Data Frame
Control Frame
Data Frame
Hi-Z
DIN / DOUT
TURBO CONTINUOUS DATA TRANSFER MODE
Stand-Alone Case:
•••••••••••••••••••••••••••••••••••••••••••••••••••••
Turbo SCLK
One SCLK
Sampling Period
Hi-Z
FS
Data Frame
Data Frame
Hi-Z
...
...
1
0
15 14
1 0
DIN / DOUT
15 14
Cascade Case (Master + 4 Slaves):
•••••••••••••••••••••••••••••••••••••••••••••••••
Turbo SCLK
FS
Sampling Period
Data Frame
Data Frame
Hi-Z
Hi-Z
DIN / DOUT
Figure 38. Turbo Programming Mode (SCLK Is Not Drawn To Scale)
Control Register Programming
The TLV320AIC1x contains six control registers that are used to program available modes of operation. All
register programming occurs during the control frame through DIN. New configuration takes effect after a delay
of one frame sync FS except the software reset, which happens after 6 MCLKs from the falling edge of the next
frame sync FS. The TLV320AIC1x is defaulted to the programming mode upon power up. Set bit 6 in control
register 1 to switch to continuous data transfer mode. If the 15+1 data format of DIN has been selected, the LSB
of the DIN to 1 to switch from continuous data transfer mode to programming set mode. Otherwise, either the
device needs to be reset or the host port writes 0 to bit D6 of control register 1 during the continuous data
transfer mode to switch back to the programming mode.
37
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Data Frame Format
DIN
(15+1) Bit Mode
D0
D15 - D1
(Continuous Data Transfer Mode Only)
Control Frame
Request
A/D and D/A Data
DOUT
(16 Bit A/D Data)
D15 - D0
DIN
16 Bit Mode
D15 - D0
A/D and D/A Data
DOUT
16 Bit Mode
D15 - D0
Figure 39. Data Frame Format
Control Frame Format (Programming Mode)
During the control frame, the DSP sends 16-bit words to the SMARTDM through DIN to read or write control
registers shown in Table 4. The upper byte (Bits D15-D8) of the 16-bit control-frame word defines the read/write
command. Bits D15-D13 define the control register address with register content occupied the lower byte D7-D0.
Bit D12 is set to 0 for a write or to 1 for a read. Bit D11 in the write command is used to perform the broadcast
mode. During a register write, the register content is located in the lower byte of DIN. During a register read, the
register content is output in the lower byte of DOUT in the same control frame, whereas the lower byte of DIN is
ignored.
Broadcast Register Write
Broadcast operation is very useful for a cascading system of SMARTDM DSP codecs in which all register
programming can be completed in one control frame. During the control frame and in any register-write time slot,
if the broadcast bit (D11) is set to 1, the register content of that time slot is written into the specified register of
all devices in cascade (see Figure 40). This reduces the DSP's overhead of doing multiple writes to program
same data into cascaded devices.
Data to be Written Into Register
D7 - D0
DIN (Write) D15 D14 D13
Register
0
D11
1
1
1
R/W Broadcast
Don’t care
D7 - D0
Address
DIN (Read) D15 D14 D13
1
1
1
1
0
0
Register
Address
SMARTDM Device
Address
Register Content
D7 - D0
DOUT (Read) D15 D14 D13 D12 D11 D10 D9
Figure 40. Control Frame Data Format
38
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Master FS
Data Frame
Control Frame
Slave0 Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0
DIN
Time Slot
Reg Addr (D15-D13) 001(1) 010(2) 100(4) 110(6)
Write
Command
R/W (D12)
Broadcast (D11)
D10-D8
0
1
0
1
0
1
0
1
111
111
111
111
A. NOTE: In this example, the broadcast operation (D11 = 1) is used to program the four control registers of Reg.1,
Reg.2, Reg.4, and Reg.6 in all 4 DSP codecs (Master, Slave2, Slave1, and Slave0) shown in Figure 33. These
registers are programmed during the same frame.
Figure 41. Control Frame Data Format
Register Map
Bits D15 through D13 represent the control register address that is written with data carried in D7 through D0.
Bit D12 determines a read or a write cycle to the addressed register. When D12 = 0, a write cycle is selected.
When D12 = 1, a read cycle is selected. Bit D11 controls the broadcast mode as described above, in which the
broadcast mode is enabled if D11 is set to 1. Always write 1s to the bits D10 through D8.
Table 3 shows the register map.
Table 3. Register Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register Address
RW
BC
1
1
1
Control Register Content
Table 4. Register Addresses
REGISTER NO.
D15
D14
0
D13
0
REGISTER NAME
0
1
2
3
4
5
6
0
0
0
0
1
1
1
No operation
control 1
control 2
control 3
control 4
control 5
control 6
0
1
1
0
1
1
0
0
0
1
1
0
39
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Control Register Content Description
Control Register 1(1)
D7
ADOVF
R
D6
CX
D5
IIR
D4
DAOVF
R
D3
D2
D1
D0
DAC16
R/W
BIASV
R/W
ALB
R/W
DLB
R/W
R/W
R/W
(1) NOTE: R = Read, W = Write
Control Register 1 Bit Summary
RESET
VALUE
BIT
NAME
FUNCTION
D7
ADOVF
0
ADC over flow. This bit indicates whether the ADC is overflow.
ADOVF = 0 No overflow.
ADOVF = 1 A/D is overflow.
D6
CX
0
Continuous data transfer mode. This bit selects between programming mode and continuous data transfer
mode.
CX = 0 Programming mode.
CX = 1 Continuous data transfer mode.
D5
D4
D3
D2
D1
D0
IIR
0
0
0
0
0
0
IIR Filter. This bit selects between FIR and IIR for decimation/interpolation low-pass filter.
IIR = 0 FIR filter is selected.
IIR = 1 IIR filter is selected.
DAOVF
BIASV
ALB
DAC over flow. This bit indicates whether the DAC is overflow
DAOVF = 0 No overflow.
DAOVF = 1 DAC is overflow
Bias voltage. This bit selects the output voltage for BIAS pin
BIASV = 0 BIAS pin = 2.35 V
BIASV = 1 BIAS pin = 1.35 V
Analog loop back
DLB = 0 Analog loopback disabled
DLB = 1 Analog loopback enabled
DLB
Digital loop back
DLB = 0 Digital loopback disabled
DLB = 1 Digital loopback enabled
DAC16
DAC 16-bit data format. This bit applies to the continuous data transfer mode only to enable the 16-bit data
format for DAC input.
DAC16 = 0 DAC input data length is 15 bits. Writing a 1 to the LSB of the DAC input to switch from
continuous data transfer mode to programming mode.
DAC16 = 1 DAC input data length is 16 bit.
Control Register 2(1)
D7
TURBO
R/W
D6
D5
I2C6
D4
I2C5
D3
I2C4
D2
D1
D0
DIFBP
R/W
GPO
R/W
HPC
R/W
R/W
R/W
R/W
R/W
(1) NOTE: R = Read, W = Write
Control Register 2 Bit Summary
RESET
VALUE
BIT
NAME
FUNCTION
D7
TURBO
0
Turbo mode. This bit is used to set the SCLK rate.
TURBO = 0 SCLK = (16 × FS × #Device × mode)
TURBO = 1 SCLK = MCLK/P (P is determined in register 4) (MCLK/P is valid only for master mode)
D6
DIFBP
I2Cx
0
Decimation/interpolation filter bypass. This bit is used to bypass both decimation and interpolation filters.
DIFBP = 0 Decimation/interpolation filters are operated.
DIFBP = 1 Decimation/interpolation filters are bypassed.
I2C device address. These three bits are programmable to define three MSBs of the I2C device address
(reset value is 100). These three bits are combined with the 4-bit SMARTDM device address to form 7-bit
I2C device address.
D5-D3
100
40
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Control Register 2 Bit Summary (continued)
RESET
VALUE
BIT
NAME
FUNCTION
D2
GPO
HPC
0
General-purpose output
Host port control bits.
D1-D0
00
Write the following values into D1-D0 to select the appropriate configuration for two pins SDA and SCL. The
SDA pin is set to be equal to D2 if D1-D0 = 10.
D1-D0
0 0 SDA and SCL pins are used for I2C interface
0 1 SDA and SCL pins are used for S2C interface
1 0 SDA pin = D2, input going into SCL pin is output to DOUT
1 1 SDA pin = Control frame flag.
Control Register 3(1)
D7
D6
D5
D4
D3
D2
D1
D0
PWDN
R/W
SWRS
R/W
OSR-option
R/W
ASRF
R/W
(1) NOTE: R = Read, W = Write
Control Register 3 Bit Summary
RESET
VALUE
BIT
NAME
FUNCTION
D7-D6
PWDN
00
Power Down,
PWDN = 00 No power down
PWDN = 01 Power-down A/D
PWDN = 10 Power-down D/A
PWDN = 11 Software power down the entire device
D5
SWRS
0
Software Reset. Set this bit to 1 to reset the device.
D4-D3
OSR
00
OSR option.
option
D4 - D3 = X1 OSR for DAC Channel is 512 ( Max Fs = 8 Ksps)
D4 - D3 = 10 OSR for DAC Channel is 256 ( Max Fs = 16 Ksps)
D4 - D3 = 00 OSR for DAC Channel is 128 (Max Fs = 26 Ksps)
D2-D0
ASRF
001
Asynchronous Sampling Rate Factor. These three bits define the ratio n between FS frequency and the
desired sampling frequency Fs (Applied only if different sampling rate between CODEC1 and CODEC2 is
desired)
ASRF = 001 n = FS/Fs = 1
ASRF = 010 n = FS/Fs = 2
ASRF = 011 n = FS/Fs = 3
ASRF = 100 n = FS/Fs = 4
ASRF = 101 n = FS/Fs = 5
ASRF = 110 n = FS/Fs = 6
ASRF = 111 n = FS/Fs = 7
ASRF = 000 n = FS/Fs = 8
Control Register 4(1)
D7
D6
D5
D4
D3
D2
D1
D0
FSDIV
R/W
MNP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(1) NOTE: R = Read, W = Write
Control Register 4 Bit Summary
RESET
VALUE
BIT
NAME
FUNCTION
D7
FSDIV
0
Frame sync division factor
FSDIV = 0 To write value of P to bits D2-D0 and value of N to bits D6-D3
FSDIV = 1 To write value of M to bits D6-D0
41
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Control Register 4 Bit Summary (continued)
RESET
VALUE
BIT
NAME
FUNCTION
D6-D0 MNP(1)(2)
—
Divider values of M, N, and P to be used in junction with the FSDIV bit for calculation of FS frequency
(3)(4)
according to the formula FS = MCLK / (16 x M x N x P)
M = 1,2,…,128 Determined by D6-D0 with FSDIV = 1
D7-D0 = 10000000 M = 128
D7-D0 = 10000001 M = 1
to
D7-D0 = 11111111 M = 127
N = 1,2,…,16 Determined by D6-D3 with FSDIV = 0
D7-D0 = 00000xxx N = 16
D7-D0 = 00001xxx N = 1
to
D7-D0 = 01111xxx N = 15
P = 1,2,…,8 Determined by D2-D0 with FSDIV = 0
D7-D0 = 0xxxx000 P = 8
D7-D0 = 0xxxx001 P = 1
to
D7-D0 = 0xxxx111 P = 7
(1) It takes 2 sampling periods to update new values of M, N, and P.
(2) In register read operation, first read receives N and P values and second read receives M value.
(3) M(default) = 16, N(default) = 6, P(default) = 8
(4) If P = 8, the device enters the coarse sampling mode as described in operating frequencies section.
Control Register 5A(5)
D7
0
D6
0
D5
D4
D3
D2
D1
D0
ADGAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(5) NOTE: R = Read, W = Write
Control Register 5A Bit Summary(1)(2)
RESET
VALUE
BIT
NAME
FUNCTION
D7-D6
Control
Register 5A
00
ADC programmable gain amplifier
A/D converter gain (see Table 5)
D5-D0
ADGAIN
101010
(1) In register read operation, first read receives ADC gain value, second read receives DAC gain value, third read receives register 5C
contents, and fourth read receives register 5D contents.
(2) PGA default value = 101010b (0dB) for both ADC and DAC.
Table 5. A/D PGA Gain
D7
0
0
0
0
0
0
0
0
0
0
0
0
0
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
D5
1
1
1
1
1
1
1
1
1
1
1
1
1
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
ADC input PGA gain = MUTE
ADC input PGA gain = 20 dB
ADC input PGA gain = 19 dB
ADC input PGA gain = 18 dB
ADC input PGA gain = 17 dB
ADC input PGA gain = 16 dB
ADC input PGA gain = 15 dB
ADC input PGA gain = 14 dB
ADC input PGA gain = 13 dB
ADC input PGA gain = 12 dB
ADC input PGA gain = 11 dB
ADC input PGA gain = 10 dB
ADC input PGA gain = 9 dB
42
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Table 5. A/D PGA Gain (continued)
D7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D6
D5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D4
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DESCRIPTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC input PGA gain = 8 dB
ADC input PGA gain = 7 dB
ADC input PGA gain = 6 dB
ADC input PGA gain = 5 dB
ADC input PGA gain = 4 dB
ADC input PGA gain = 3 dB
ADC input PGA gain = 2 dB
ADC input PGA gain = 1 dB
ADC input PGA gain = 0 dB
ADC input PGA gain = -1 dB
ADC input PGA gain = -2 dB
ADC input PGA gain = -3 dB
ADC input PGA gain = -4 dB
ADC input PGA gain = -5 dB
ADC input PGA gain = -6 dB
ADC input PGA gain = -7 dB
ADC input PGA gain = -8 dB
ADC input PGA gain = -9 dB
ADC input PGA gain = -10 dB
ADC input PGA gain = -11 dB
ADC input PGA gain = -12 dB
ADC input PGA gain = -13 dB
ADC input PGA gain = -14 dB
ADC input PGA gain = -15 dB
ADC input PGA gain = -16 dB
ADC input PGA gain = -17 dB
ADC input PGA gain = -18 dB
ADC input PGA gain = -19 dB
ADC input PGA gain = -20 dB
ADC input PGA gain = -21 dB
ADC input PGA gain = -22 dB
ADC input PGA gain = -23dB
ADC input PGA gain = -24 dB
ADC input PGA gain = -25 dB
ADC input PGA gain = -26 dB
ADC input PGA gain = -27 dB
ADC input PGA gain = -28 dB
ADC input PGA gain = -29 dB
ADC input PGA gain = -30 dB
ADC input PGA gain = -31 dB
ADC input PGA gain = -32 dB
ADC input PGA gain = -33 dB
ADC input PGA gain = -34 dB
ADC input PGA gain = -35 dB
ADC input PGA gain = -36 dB
ADC input PGA gain = -37 dB
ADC input PGA gain = -38 dB
43
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Table 5. A/D PGA Gain (continued)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1
DESCRIPTION
ADC input PGA gain = -39 dB
ADC input PGA gain = -40 dB
ADC input PGA gain = -41 dB
ADC input PGA gain = -42 dB
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Control Register 5B(1)
D7
0
D6
1
D5
D4
D3
D2
D1
D0
DAGAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(1) NOTE: R = Read, W = Write
Control Register 5B Bit Summary(1)(2)
RESET
VALUE
BIT
NAME
FUNCTION
D7-D6
Control
NA
Register 5B
D5-D0
DAGAIN
101010
D/A converter gain (see Table 6)
(1) In register read operation, first read receives ADC gain value, second read receives DAC gain value, third receives register 5C and
fourth receives register 5D.
(2) PGA default value = 101010b (0dB) for both ADC and DAC.
Table 6. D/A PGA Gain
D7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
DAC input PGA gain = MUTE
DAC input PGA gain = 20 dB
DAC input PGA gain = 19 dB
DAC input PGA gain = 18 dB
DAC input PGA gain = 17 dB
DAC input PGA gain = 16 dB
DAC input PGA gain = 15 dB
DAC input PGA gain = 14 dB
DAC input PGA gain = 13 dB
DAC input PGA gain = 12 dB
DAC input PGA gain = 11 dB
DAC input PGA gain = 10 dB
DAC input PGA gain = 9 dB
DAC input PGA gain = 8 dB
DAC input PGA gain = 7 dB
DAC input PGA gain = 6 dB
DAC input PGA gain = 5 dB
DAC input PGA gain = 4 dB
DAC input PGA gain = 3 dB
DAC input PGA gain = 2 dB
DAC input PGA gain = 1 dB
DAC input PGA gain = 0 dB
DAC input PGA gain = -1 dB
DAC input PGA gain = -2 dB
DAC input PGA gain = -3 dB
44
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Table 6. D/A PGA Gain (continued)
D7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D6
D5
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DESCRIPTION
DAC input PGA gain = -4 dB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DAC input PGA gain = -5 dB
DAC input PGA gain = -6 dB
DAC input PGA gain = -7 dB
DAC input PGA gain = -8 dB
DAC input PGA gain = -9 dB
DAC input PGA gain = -10 dB
DAC input PGA gain = -11 dB
DAC input PGA gain = -12 dB
DAC input PGA gain = -13 dB
DAC input PGA gain = -14 dB
DAC input PGA gain = -15 dB
DAC input PGA gain = -16 dB
DAC input PGA gain = -17 dB
DAC input PGA gain = -18 dB
DAC input PGA gain = -19 dB
DAC input PGA gain = -20 dB
DAC input PGA gain = -21 dB
DAC input PGA gain = -22 dB
DAC input PGA gain = -23dB
DAC input PGA gain = -24 dB
DAC input PGA gain = -25 dB
DAC input PGA gain = -26 dB
DAC input PGA gain = -27 dB
DAC input PGA gain = -28 dB
DAC input PGA gain = -29 dB
DAC input PGA gain = -30 dB
DAC input PGA gain = -31 dB
DAC input PGA gain = -32 dB
DAC input PGA gain = -33 dB
DAC input PGA gain = -34 dB
DAC input PGA gain = -35 dB
DAC input PGA gain = -36 dB
DAC input PGA gain = -37 dB
DAC input PGA gain = -38 dB
DAC input PGA gain = -39 dB
DAC input PGA gain = -40 dB
DAC input PGA gain = -41 dB
DAC input PGA gain = -42 dB
45
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Control Register 5C(1)
D7
1
D6
0
D5
D4
D3
D2
Reserved
R
D1
D0
DSTG
R/W
INBG
R/W
R/W
R/W
R/W
R/W
R/W
(1) NOTE: R = Read, W = Write
Digital Sidetone Gain
D5
1
D4
1
D3
1
DSTG
Digital sidetone gain = Mute (Default)
Digital sidetone gain = -21 dB
Digital sidetone gain = -18 dB
Digital sidetone gain = -15 dB
Digital sidetone gain = -12 dB
Digital sidetone gain = -9 dB
Digital sidetone gain = -6 dB
Digital sidetone gain = -3 dB
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Input Buffer Gain
D1
D0
1
INBG
1
1
0
0
Input buffer gain = 24 dB
Input buffer gain = 12 dB
Input buffer gain = 6 dB
0
1
0
Input buffer gain = 0 dB (Default)
Control Register 5D(1)
D7
1
D6
1
D5
D4
D3
D2
D1
D0
Reserved
Chip Version-ID
R/W
R/W
R
R
R
R
R
R
(1) NOTE: R = Read, W = Write
46
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Control Register 6
D7
D6
MUTE2
R/W
D5
MUTE3
R/W
D4
D3
D2
D1
D0
Reserved
R/W
PSDO
R/W
ODRCT
AINSEL
R/W
R/W
R/W
R/W
Control Register 6 Bit Summary
RESET
VALUE
BIT
NAME
FUNCTION
D7
PSDO
0
Programmable single-ended/differential output. This bit configures the two pins of OUTP2 and OUTP3 as
single-ended or differential output. If the OUTP2 and OUTP3 are single-ended, the OUTMV is the virtual
ground. If the OUTP2 and OUTP3 are differential, the OUTMV is the common inverting output.
PSDO = 0 OUTP2 and OUTP3 are two differential output (1)
PSDO = 1 OUTP2 and OUTP3 are two single-ended output (2)
NOTE:
(1) The OUTP2 and OUTP3 pins are the noninverting output with common inverting output. The OUTMV is
their common inverting output
(2) The virtual ground pin OUTMV and the common mode of OUTP2 and OUTP3 are the same at 1.35 V.
D6
D5
MUTE2
MUTE3
0
0
Analog Output2 mute control. This bit sets MUTE for OUTP2
MUTE2 = 0 OUTP2 is not MUTE
MUTE2 = 1 OUTP2 is MUTE
Analog Output2 mute control. This bit sets MUTE for OUTP3
MUTE3 = 0 OUTP3 is not MUTE
MUTE3 = 1 OUTP3 is MUTE
D4-D3 ODRCT
00
Analog driver control. These two bits enable/disable the analog output drivers for the analog output pins of
OUTP2 and OUTP3
ODRCT =00 OUTP3 = OFF, OUTP2 = OFF
ODRCT =01 OUTP3 = OFF, OUTP2 = ON
ODRCT =10 OUTP3 = ON, OUTP2 = OFF
ODRCT =11 OUTP3 = ON, OUTP2 = ON
D2-D1 AINSEL
00
Analog input select. These bits select the analog input for the ADC
AINSEL = 00 The analog input is INP/M1
AINSEL = 01 The analog input is MICIN self-biased at 1.35 V
AINSEL =10 The analog input is MICIN with external common mode
AINSEL = 11 The analog input is INP/M2
NOTE: For AINSEL = 10, the external common mode is connected to INM1 via an ac-coupled capacitor.
D0
Reserved
47
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
IOVDD IOVDD
1 kΩ
TLV320AIC12
1 kΩ
Microphone
BIAS
M/S
TLV320C5X
FSK
FSD
FS
MICIN
INP1
0.1 µF
0.1 µF
FSR
DX
DIN
INM1
DR
DOUT
0.1 µF
0.1 µF
CLKR
INP2
SCLK
CLKX
INM2
From DSP or
Other Clock Source
MCLK
0.1 µF
OUTP1
OUTM1
From DSP
From DSP
RESET
IOVDD
1 kΩ
600 Ω
PWRDN
SDA
OUTP2
OUTMV
2
I C Master
2
S C
SCL
OUTP3
AVDD
DVDD
DVSS
To 1.8 V Digital Supply
To Digital GND
0.01 µF
0.01 µF
0.1 µF
0.1 µF
1 µF
3.3 V Analog Supply
0.1 µF
Analog GND
AVSS
To 3.3 V Digital Supply
To Digital GND
IOVDD
IOVSS
3.3 V Analog Supply
1 µF
DRVDD
DRVSS
0.1 µF
Analog GND
Figure 42. Single-Ended Microphone Input (Internal Common Mode)
48
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
IOVDD IOVDD
1 kΩ
TLV320AIC12
1 kΩ
Microphone
BIAS
M/S
TLV320C5X
FSK
FSD
FS
MICIN
INP1
0.1 µF
0.1 µF
FSR
DX
DIN
INM1
INP2
INM2
DR
DOUT
0.1 µF
0.1 µF
0.1 µF
CLKR
SCLK
CLKX
From DSP or
Other Clock Source
MCLK
OUTP1
OUTM1
From DSP
RESET
IOVDD
1 kΩ
600 Ω
1 µF
1 µF
From DSP
From DSP
PWRDN
SDA
600 Ω
OUTP2
OUTMV
SCL
DVDD
DVSS
To 1.8 V Digital Supply
To Digital GND
OUTP3
AVDD
0.01 µF
0.01 µF
0.1 µF
0.1 µF
1 µF
3.3 V Analog Supply
0.1 µF
0.1 µF
Analog GND
AVSS
To 3.3 V Digital Supply
To Digital GND
IOVDD
IOVSS
3.3 V Analog Supply
1 µF
DRVDD
DRVSS
Analog GND
Figure 43. Pseudo-Differential Microphone Input (External Common Mode)
49
Submit Documentation Feedback
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
www.ti.com
SLWS115E–OCTOBER 2001–REVISED JANUARY 2007
Layout and Grounding Guidelines for TLV320AIC1x
TLV320AIC1x has an in-built analog antialias filter, which provides rejection to external noise at high frequencies
that may couple into the device. Digital filters with high out-of-band attenuation also reject the external noise. If
the differential inputs are used for the ADC channel, then the noise in the common-mode signal is also rejected
by the high CMRR of TLV320AIC1x. Using external common-mode for microphone inputs also helps rejecting
the external noise. However to extract the best performance from TLV320AIC1x, care must be taken in board
design and layout to avoid coupling of external noise into the device.
TLV320AIC1x supports clock frequencies as high as 100 MHz. To avoid coupling of fast switching digital signals
to analog signals, the digital and analog sections should be separated on the board. In TLV320AIC1x the digital
and analog pins are kept separated to aid such a board layout. A separate analog ground plane should be used
for the analog section of the board. The analog and digital ground planes should be shorted at only one place as
close to TLV320AIC1x as possible. No digital trace should run under TLV320AIC1x to avoid coupling of external
digital noise into the device. It is suggested to have the analog ground plane running below the TLV320AIC1x.
The power-supplies should be decoupled close to the supply pins, preferably, with a 0.1 µF-ceramic capacitor
and a 10-µF tantalum capacitor following. The ground pin should be connected to the ground plane as close as
possible to the TLV320AIC1x, so as to minimize any inductance in the path. Since the MCLK is expected to be a
high frequency signal, it is advisable to shield it with digital ground. For best performance of ADC in differential
input mode, the differential signals should be routed close to each other in similar fashion, so that the noise
coupling on both the signals is same and can be rejected by the device.
Extra care has to be taken for the speaker driver outputs, as any trace resistance can cause a reduction in the
maximum swing that can be seen at the speaker.
For devices in the RHB package, connect the device thermal pad to DRVSS.
50
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
TLV32012KIDBTRG4
TLV32014KIDBTRG4
TLV320AIC12CDBT
TLV320AIC12CDBTG4
TLV320AIC12CDBTR
TLV320AIC12CDBTRG4
TLV320AIC12IDBT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM8
DBT
30
30
30
30
30
30
30
30
30
30
30
30
30
32
32
30
30
30
30
30
30
30
30
30
30
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
QFN
QFN
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
SM8
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
RHB
RHB
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC12IDBTG4
TLV320AIC12IDBTR
TLV320AIC12IDBTRG4
TLV320AIC12KIDBT
TLV320AIC12KIDBTG4
TLV320AIC12KIDBTR
TLV320AIC12KIRHBR
TLV320AIC12KIRHBT
TLV320AIC13CDBT
TLV320AIC13CDBTG4
TLV320AIC13CDBTR
TLV320AIC13CDBTRG4
TLV320AIC13IDBT
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC13IDBTG4
TLV320AIC13IDBTR
TLV320AIC13IDBTRG4
TLV320AIC14CDBT
TLV320AIC14CDBTG4
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
Orderable Device
TLV320AIC14CDBTR
TLV320AIC14CDBTRG4
TLV320AIC14IDBT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM8
DBT
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
48
48
48
48
48
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
SM8
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC14IDBTG4
TLV320AIC14IDBTR
TLV320AIC14IDBTRG4
TLV320AIC14KIDBT
TLV320AIC14KIDBTG4
TLV320AIC14KIDBTR
TLV320AIC15CDBT
TLV320AIC15CDBTG4
TLV320AIC15CDBTR
TLV320AIC15CDBTRG4
TLV320AIC15IDBT
SM8
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC15IDBTG4
TLV320AIC15IDBTR
TLV320AIC15IDBTRG4
TLV320AIC20CPFB
TLV320AIC20CPFBG4
TLV320AIC20CPFBR
TLV320AIC20CPFBRG4
TLV320AIC20IPFB
SM8
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC20IPFBG4
TLV320AIC20IPFBR
TLV320AIC20IPFBRG4
TLV320AIC21CPFB
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
Orderable Device
TLV320AIC21CPFBG4
TLV320AIC21CPFBR
TLV320AIC21CPFBRG4
TLV320AIC21IPFB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PFB
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
32
32
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
QFN
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
RHB
RHB
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC21IPFBG4
TLV320AIC21IPFBR
TLV320AIC21IPFBRG4
TLV320AIC24CPFB
TLV320AIC24CPFBG4
TLV320AIC24CPFBR
TLV320AIC24CPFBRG4
TLV320AIC24IPFB
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC24IPFBG4
TLV320AIC24IPFBR
TLV320AIC24IPFBRG4
TLV320AIC25CPFB
TLV320AIC25CPFBG4
TLV320AIC25CPFBR
TLV320AIC25CPFBRG4
TLV320AIC25IPFB
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLV320AIC25IPFBG4
TLV320AIC25IPFBR
TLV320AIC25IPFBRG4
TLVAIC12KIRHBRG4
TLVAIC12KIRHBTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
MLA
MLA
Reel
Diameter Width
(mm)
Reel
A0 (mm)
5.3
B0 (mm)
5.3
K0 (mm)
1.5
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
TLV320AIC12KIRHBR
TLV320AIC12KIRHBT
RHB
RHB
32
32
330
12
8
8
12 PKGORN
T2TR-MS
P
180
12
5.3
5.3
1.5
12 PKGORN
T2TR-MS
P
TLV320AIC20CPFBR
TLV320AIC20IPFBR
TLV320AIC21CPFBR
TLV320AIC21IPFBR
TLV320AIC24CPFBR
TLV320AIC24IPFBR
TLV320AIC25CPFBR
TLV320AIC25IPFBR
PFB
PFB
PFB
PFB
PFB
PFB
PFB
PFB
48
48
48
48
48
48
48
48
TAI
TAI
TAI
TAI
TAI
TAI
TAI
TAI
330
330
330
330
330
330
330
330
16
16
16
16
16
16
16
16
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
9.6
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
12
12
12
12
12
12
12
12
16
16
16
16
16
16
16
16
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TLV320AIC12KIRHBR
TLV320AIC12KIRHBT
TLV320AIC20CPFBR
TLV320AIC20IPFBR
TLV320AIC21CPFBR
TLV320AIC21IPFBR
TLV320AIC24CPFBR
TLV320AIC24IPFBR
RHB
RHB
PFB
PFB
PFB
PFB
PFB
PFB
32
32
48
48
48
48
48
48
MLA
MLA
TAI
TAI
TAI
TAI
TAI
TAI
346.0
190.0
341.0
341.0
341.0
341.0
341.0
341.0
346.0
212.7
159.0
159.0
159.0
159.0
159.0
159.0
29.0
31.75
123.5
123.5
123.5
123.5
123.5
123.5
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TLV320AIC25CPFBR
TLV320AIC25IPFBR
PFB
PFB
48
48
TAI
TAI
341.0
341.0
159.0
159.0
123.5
123.5
Pack Materials-Page 3
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明