THS3202 [TI]
2-GHZ, LOW DISTORTION, CURRENT FEEDBACK AMPLIFIERS; 2 - GHz的低失真，电流反馈放大器
| 型号： | THS3202 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-GHZ, LOW DISTORTION, CURRENT FEEDBACK AMPLIFIERS |
| 文件： | 总32页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
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FEATURES
DESCRIPTION
The THS3202 is part of the high performing current
feedback amplifier family developed in BiCOM−ΙΙ
technology. Designed for low-distortion with a high slew
rate of 9000 V/µs, the THS320x family is ideally suited for
applications driving loads sensitive to distortion at high
frequencies.
D
D
D
Unity Gain Bandwidth: 2 GHz
High Slew Rate: 9000 V/µs
IMD3 at 120 MHz: −89 dBc (G = 5, R = 100 Ω,
L
V
= 15 V)
CC
D
OIP3 at 120 MHz: 44 dBm (G = 5, R = 100 Ω,
L
CC
The THS3202 provides well-regulated ac performance
characteristics with power supplies ranging from
single-supply 6.6-V operation up to a 15-V supply. The
high unity gain bandwidth of up to 2 GHz is a major
contributor to the excellent distortion performance. The
THS3202 offers an output current drive of 115 mA and a
low differential gain and phase error that make it suitable
for applications such as video line drivers.
V
= 15 V)
D
D
High Output Current: 115 mA into 20 Ω R
L
Power Supply Voltage Range: 6.6 V to 15 V
APPLICATIONS
The THS3202 is available in an 8 pin SOIC and an 8 pin
D
D
D
D
D
High-Speed Signal Processing
Test and Measurement Systems
High-Voltage ADC Preamplifier
RF and IF Amplifier Stages
Professional Video
MSOP with PowerPAD packages.
RELATED DEVICES AND DESCRIPTIONS
THS3001
THS3061/2
THS3122
THS4271
15-V 420-MHz Low Distortion CFB Amplifier
15-V 300-MHz Low Distortion CFB Amplifier
15-V Dual CFB Amplifier With 350 mA Drive
+15-V 1.4-GHz Low Distortion VFB Amplifier
THS3202
HARMONIC DISTORTION
vs
OIP
vs
3
OUTPUT VOLTAGE
FREQUENCY
TEST CIRCUIT FOR
−50
50
48
46
44
42
Test Instrument Measurement Limit
IMD / OIP
3
3
−60
−70
G = 5
V
=
7.5 V
CC
R
V
= 500 Ω
Output Power
L
V
=
7 V
= 15 V
CC
CC
Spectrum Analyzer
R = 420 Ω
f
_
−80
f = 10 MHz
40
38
nd
2
Harmonic
V
= 6 V
CC
G = 5
+
50 Ω
−90
36
34
50 Ω
−100
−110
−120
R = 100 Ω,
L
G = 5,
32
30
rd
3
Harmonic
R
= 536 Ω,
= 2V _Envelope
PP
F
V
O
∆f = 200 kHz
28
26
V
=
5 V
160
f − Frequency − MHz
c
CC
0
2
4
6
8
10
12
10
60
110
210
260
V
− Output Voltage − V
O
pp
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
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Copyright 2002 − 2004, Texas Instruments Incorporated
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
UNIT
Supply voltage, V
16.5 V
S
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Input voltage, V
I
V
S
Differential Input voltage, V
3 V
ID
(2)
Output current, I
O
175 mA
Continuous power dissipation
See Dissipation Rating Table
PACKAGE DISSIPATION RATINGS
(3)
Maximum junction temperature, T
150°C
J
(2)
(1)
θ
JA
POWER RATING
θ
JC
(°C/W) (°C/W)
Maximum junction temperature, continuous
operation, long term reliability T
J
PACKAGE
125°C
(4)
T
A
≤ 25°C = 85°C
T
A
D (8 pin)
38.3
4.7
97.5
58.4
260
1.32 W
1.71 W
410 mW
685 mW
154 mW
Operating free-air temperature range, T
A
−40°C to 85°C
−65°C to 150°C
DGN (8 pin)
DGK (8 pin)
Storage temperature range, T
stg
54.2
385 mW
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
300°C
(1)
(2)
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermalmanagement of the final PCB should strive to keep the
junctiontemperature at or below 125°C for best performance and
long term reliability.
HBM
3000 V
1500 V
200 V
CDM
MM
ESD ratings:
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
The THS3202 may incorporate a PowerPAD on the underside
of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
(2)
Dual supply
3.3
7.5
Supply voltage,
(V and V
S+ S−
V
)
Single supply
6.6
15
Operating free-air temperature
range
−40
85
°C
(3)
(4)
The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
PACKAGE/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER
(1)
PLASTIC MSOP-8
PowerPAD
NUMBER OF
CHANNELS
(1)
PLASTIC MSOP-8
(1)
PLASTIC SOIC-8
(D)
(DGN)
THS3202DGN
SYM
(DGK)
THS3202DGK
SYM
BEV
2
THS3202D
BEP
(1)
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., THS3202DR).
PIN ASSIGNMENTS
TOP VIEW
D, DGN, DGK
1V
V +
S
1
2
3
4
8
7
6
5
OUT
1V
1V
2V
2V
IN−
OUT
IN−
IN+
V
2
VIN+
S−
2
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
V
S
=
5 V: R = 500 Ω, R = 100 Ω, and G = +2 unless otherwise noted
f
L
THS3202
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
−40°C
to 85°C
MIN/TYP/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = +1, R = 500 Ω
1800
975
780
550
f
G = +2, R = 402 Ω
Small-signal bandwidth, −3 dB
f
MHz
Typ
(V = 100 mV )
PP
G = +5, R = 300 Ω
O
f
G = +10, R = 200 Ω
f
G = +2, V = 100 mV
pp,
f
O
Bandwidth for 0.1 dB flatness
Large-signal bandwidth
380
MHz
MHz
Typ
Typ
R = 536 Ω
G = +2, V = 4 V
O
R = 536 Ω
f
875
5100
4400
0.45
19
pp,
G = −1, 5-V step
G = +2, 5-V step
Slew rate (25% to 75% level)
V/µs
ns
Typ
Typ
Typ
Rise and fall time
Settling time to 0.1%
0.01%
G = +2, V = 5-V step
O
G = −2, V = 2-V step
O
ns
G = −2, V = 2-V step
118
O
Harmonic distortion
G = +2, f = 16 MHz, V = 2 V
pp
O
R
L
R
L
R
L
R
L
= 100 Ω
= 500 Ω
= 100 Ω
= 500 Ω
−64
−67
−67
−69
nd
2
3
harmonic
harmonic
dBc
dBc
Typ
Typ
rd
G = +5, f = 120 MHz,
c
rd
3
∆f = 200 kHz,
order intermodulation distortion
−64
dBc
Typ
V
= 2 V
pp
O(envelope)
Input voltage noise
f > 10 MHz
f > 10 MHz
f > 10 MHz
1.65
13.4
nV/√Hz
pA/√Hz
pA/√Hz
dB
Typ
Typ
Typ
Typ
Typ
Typ
Input current noise (noninverting)
Input current noise (inverting)
Crosstalk
20
G = +2, f = 100 MHz
G = +2, R = 150 Ω
−60
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
0.008%
0.03°
L
G = +2, R = 150 Ω
L
DC PERFORMANCE
Open-loop transimpedance gain
Input offset voltage
V
V
V
V
V
V
V
=
1 V, R = 1 kΩ
300
0.7
200
3
140
3.8
10
120
4
kΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
O
L
= 0 V
CM
CM
CM
CM
CM
CM
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (−)
Input bias current (noninverting)
Average bias current drift (+)
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
13
µV/°C
µA
13
14
60
35
80
85
300
45
400
50
nA/°C
µA
300
400
nA/°C
3
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
V
S
=
5 V: R = 500 Ω, R = 100 Ω, and G = +2 unless otherwise noted
f
L
THS3202
OVER TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
0°C to
−40°C
to 85°C
MIN/TYP/
MAX
25°C
25°C
UNITS
70°C
INPUT
Common-mode input range
Common-mode rejection ratio
2.6
71
2.5
60
2.5
58
2.5
58
V
Min
Min
Typ
Typ
Typ
V
=
2.5 V
dB
kΩ
Ω
CM
Noninverting
Inverting
780
11
Input resistance
Input capacitance
Noninverting
1
pF
OUTPUT
R
R
R
R
= 1 kΩ
= 100 Ω
= 20 Ω
= 20 Ω
3.65
3.45
115
3.5
3.3
105
85
3.45
3.25
100
80
3.4
3.2
100
80
L
L
L
L
Voltage output swing
V
Min
Current output, sourcing
Current output, sinking
mA
mA
Ω
Min
Min
Typ
100
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
POWER SUPPLY
Minimum operating voltage
Maximum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (−PSRR)
Absolute minimum
Per amplifier
3
16.8
63
3
19
60
55
3
20
60
55
V
Min
Max
Min
Min
14
69
65
mA
dB
dB
V
S+
S−
= 4.5 V to 5.5 V
V
= −4.5 V to –5.5 V
58
4
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
V
S
= 15 V: R = 500 Ω, R = 100 Ω, and G = +2 unless otherwise noted
f
L
THS3202
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
−40°C
to 85°C
MIN/TYP/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = +1, R = 550 Ω
2000
1100
850
f
G = +2, R = 550 Ω
Small-signal bandwidth, −3dB
f
MHz
Typ
(V = 100 mV )
PP
G = +5, R = 300 Ω
O
f
G = +10, R = 200 Ω
750
f
G = +2, V = 100 mV
pp,
f
O
Bandwidth for 0.1 dB flatness
Large-signal bandwidth
500
MHz
MHz
Typ
Typ
R = 536 Ω
G = +2, V = 4 V , R = 536 Ω
1000
7500
9000
0.45
23
O
pp
f
G = +5, 5-V step
Slew rate (25% to 75% level)
V/µs
Typ
G = +2, 10-V step
G = +2, V = 10-V step
Rise and fall time
Settling time to 0.1%
0.01%
ns
ns
ns
Typ
Typ
Typ
O
G = −2, V = 2-V step
O
G = −2, V = 2-V step
112
O
Harmonic distortion
G = +2, f = 16 MHz, V = 2 V
pp
O
R
L
R
L
R
L
R
L
= 100 Ω
= 500 Ω
= 100 Ω
= 500 kΩ
−69
−73
−80
−90
nd
2
3
harmonic
harmonic
dBc
dBc
Typ
Typ
rd
G = +5, f = 120 MHz,
c
rd
3
∆f = 200 kHz,
order intermodulation distortion
−89
dBc
Typ
V
= 2 V
pp
O(envelope)
Input voltage noise
f > 10 MHz
f > 10 MHz
f > 10 MHz
1.65
13.4
nV/√Hz
pA/√Hz
pA/√Hz
dB
Typ
Typ
Typ
Typ
Typ
Typ
Input current noise (noninverting)
Input current noise (inverting)
Crosstalk
20
G = +2, f = 100 MHz
G = +2, R = 150 Ω
−60
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
0.004%
0.006°
L
G = +2, R = 150 Ω
L
DC PERFORMANCE
Open-loop transimpedance gain
Input offset voltage
V
V
V
V
V
V
V
= 6.5 V to 8.5 V, R = 1 kΩ
300
1.3
200
4
140
4.8
10
120
5
kΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
O
L
= 7.5 V
= 7.5 V
= 7.5 V
= 7.5 V
= 7.5 V
= 7.5 V
CM
CM
CM
CM
CM
CM
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (−)
Input bias current (noninverting)
Average bias current drift (+)
13
µV/°C
µA
16
14
60
35
80
85
300
45
400
50
nA/°C
µA
300
400
nA/°C
5
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS continued
V
S
= 15 V: R = 500 Ω, R = 100 Ω, and G = +2 unless otherwise noted
f L
THS3202
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
−40°C
to 85°C
MIN/TYP/
MAX
25°C
25°C
UNITS
70°C
INPUT
2.4 to
12.6
2.5 to
12.5
2.5 to
12.5
2.5 to
12.5
Common-mode input range
Common-mode rejection ratio
V
Min
V
= 5 V to 10 V
69
780
11
60
58
58
dB
kΩ
Ω
Min
Typ
Typ
Typ
CM
Noninverting
Inverting
Input resistance
Input capacitance
OUTPUT
Noninverting
1
pF
1.5 to
13.5
1.6 to
13.4
1.7 to
13.3
1.7 to
13.3
R
R
= 1 kΩ
L
Voltage output swing
V
Min
1.7 to
13.3
1.8 to
13.2
2.0 to
13.0
2.0 to
13.0
= 100 Ω
L
Current output, sourcing
Current output, sinking
R
R
= 20 Ω
= 20 Ω
120
115
105
95
100
90
100
90
mA
mA
Ω
Min
Min
Typ
L
L
Closed-loop output impedance
G = +1, f = 1 MHz
0.01
POWER SUPPLY
Maximum quiescent current/channel
Power supply rejection (+PSRR)
Power supply rejection (−PSRR)
Per amplifier
15
69
65
18
63
58
21
60
55
21
60
55
mA
dB
dB
Max
Min
Min
V
V
= 14.50 V to 15.50 V
= −0.5 V to +0.5 V
S+
S−
6
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
1−14
15−18
19−30
31−45
46, 47
48, 49
50
Small signal frequency response
Large signal frequency response
Harmonic distortion
vs Frequency
vs Output voltage
vs Frequency
vs Frequency
Harmonic distortion
IMD
3
OIP
3
Test circuit for IMD / OIP
3
3
S parameter
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
51−54
55
Input current noise density
Voltage noise density
Transimpedance
56
57
Output impedance
58
Impedance of inverting input
Supply current/channel
Input offset voltage
59
vs Supply voltage
60
vs Free-air temperature
vs Common-mode input voltage range
vs Free-air temperature
vs Input common-mode range
vs Positive power supply
vs Negative power supply
vs Free-air temperature
vs Free-air temperature
vs Power supply
61
Offset voltage
62
63
Input bias current
64
Positive power supply rejection ratio
Negative power supply rejection ratio
Positive output voltage swing
Negative output voltage swing
Output current sinking
65
66
67, 68
69, 70
71
Output current sourcing
vs Power supply
72
Overdrive recovery time
Slew rate
73, 74
75, 76, 77
78
vs Output voltage
Output voltage transient response
Settling time
79, 80
81
DC common-mode rejection ratio high
Power supply rejection ratio
Differential gain error
vs Input common-mode range
vs Frequency
82, 83
84, 85, 88
86, 87, 89
vs 150 Ω loads
Differential phase error
vs 150 Ω loads
7
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
4
3
6
R = 500 Ω
f
R = 500 Ω
G = 1
5
f
3
2
1
R
V
= 500 Ω
L
CC
O
4
3
2
=
5 V
V
= 100 mV
PP
1
0
2
0
R = 619 Ω
f
R = 619 Ω
f
−1
−2
−3
−4
−5
1
R = 619 Ω
f
−1
0
−2
G = 1
−1
−2
−3
−4
G = 1
−3
R
V
= 100 Ω
R
V
= 100 Ω
= 15 V
CC
= 100 mV
L
L
R = 750 Ω
f
=
5 V
CC
−4
V
= 100 mV
V
O
PP
10 M
O
PP
−5
0.1 M
1 M
100 M
1 G
10G
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1
Figure 2
Figure 3
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
12
11
10
9
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
G = 2
R
L
= 500 Ω
R = 402 Ω
R = 402 Ω
f
f
V
V
= 15 V
= 100 mV
CC
O
PP
R = 536 Ω
8
f
7
R = 536 Ω
f
R = 536 Ω
f
6
5
R = 650 Ω
f
R = 650 Ω
f
4
R = 649 Ω
f
3
G = 2
G = 2
R
V
= 100 Ω
R
L
= 100 Ω
L
2
= 15 V
V
=
5 V
= 100 mV
CC
CC
1
V
= 100 mV
V
O
O
PP
PP
0
0
0
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4
Figure 5
Figure 6
SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
16
16
9
R = 300 Ω
R = 300 Ω
f
f
8
15
14
13
12
11
10
9
15
14
13
12
11
10
R = 536 Ω
f
7
6
5
4
3
2
1
R = 402 Ω
f
R = 402 Ω
f
R = 649 Ω
f
R = 500 Ω
f
R = 500 Ω
f
G = 5
G = 5
G = 2
R
L
V
= 100 Ω
= 15 V
R
V
= 100 Ω
R
V
= 500 Ω
L
L
=
5 V
= 100 mV
=
5 V
CC
= 100 mV
CC
CC
V
V
V
= 100 mV
O
PP
O
PP
10 M
O
PP
10 M
8
0
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
100 M
1 G
10 G
0.1 M
1 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 7
Figure 8
Figure 9
8
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
16
15
14
13
12
11
10
9
3
17
R = 340 Ω
f
R = 340 Ω
f
2
R = 340 Ω
16
f
1
15
0
R = 420 Ω
f
14
−1
−2
−3
−4
−5
−6
R = 450 Ω
f
R = 500 Ω
f
13
R = 420 Ω
f
R = 500 Ω
f
12
R = 550 Ω
f
G = 5
G = −1
G = 5
R
V
= 500 Ω
R
L
= 100 Ω
R
V
= 500 Ω
= 15 V
CC
= 100 mV
L
L
11
=
5 V
V
= 15 V
CC
CC
= 100 mV
V
= 100 mV
V
V
O
PP
10 M
O
PP
O
PP
8
10
0.1 M
0.1 M
1 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 10
Figure 11
Figure 12
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
LARGE SIGNAL FREQUENCY RESPONSE
12
3
3
G = 1,
10
V
= 5 V
CC
= 100 Ω
V
= 2 V
R = 340 Ω
f
2
1
2
1
O
PP
V
= 15 V
8
6
CC
R
L
4
2
0
0
V
= 1 V
O
PP
−1
−2
−3
−4
−5
−6
0
−2
−4
−1
−2
−3
−4
−5
R = 450 Ω
f
V
= 5 V
V
= 0.5 V
PP
CC
O
−6
−8
R = 550 Ω
f
G = 1
= 500 Ω
G = −1
R
L
R
V
= 100 Ω
L
R = 450
f
Ω
=
5 V
−10
−12
100 K 1 M
CC
V
= 100 mV
V
= 100 mV
O
PP
O
PP
10 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 13
Figure 14
Figure 15
LARGE SIGNAL FREQUENCY RESPONSE
LARGE SIGNAL FREQUENCY RESPONSE LARGE SIGNAL FREQUENCY RESPONSE
14
14
12
10
12
12
10
V
= 4 V
PP
O
V
= 4 V
10
8
O
O
PP
PP
8
V
= 2 V
PP
O
8
6
4
2
0
6
4
2
6
V
= 2 V
= 1 V
O
O
PP
V
= 2 V
4
2
V
= 1 V
PP
O
0
−2
0
V
PP
−2
V
= 1 V
PP
O
−2
−4
−6
−8
−4
−6
−4
−6
−8
V
= 0.5 V
PP
O
V
= 0.25 V
O
PP
−8
V
= 0.5 V
PP
O
−10
V
= 15 V, G = 1, R = 100 Ω
L
−10
−12
−10
−12
100 K
CC
−12
−14
V
= 15 V, G = 2, R = 100 Ω
G = 2, V = 5, R = 100 Ω
CC L
CC
L
100 K
1 M
10 M
100 M
1 G
10 G
100 K 1 M
10 M
100 M
1 G
10 G
1 M
10 M 100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 16
Figure 17
Figure 18
9
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
−50
−60
G = −1
G = 2
G = −1
R
L
= 100 Ω
R
V
= 100 Ω
R
V
= 500 Ω
L
L
V
= 15 V
−60
CC
−60
= 15 V
= 15 V
CC
CC
nd
Harmonic
2
R = 450 Ω
−70
f
O
R = 500 Ω
R = 450 Ω
f
O
f
O
V
= 2V
PP
V
= 2V
V
= 2V
PP
PP
−70
−70
nd
2
Harmonic
−80
nd
2
Harmonic
−80
−80
−90
−90
−90
rd
3
rd
Harmonic
rd
3
Harmonic
100 M
3
Harmonic
100 M
−100
−100
−100
0.1 M
0.1 M
1 M
10 M
1 M
10 M 100 M
0.1 M
1 M
10 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 19
Figure 20
Figure 21
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−60
−60
−70
−50
−60
−70
−80
G = 2
G = 5
G = 5
R
V
= 500 Ω
R
L
= 100 Ω
R
V
= 500 Ω
L
L
= 15 V
V
= 15 V
= 15 V
CC
CC
CC
−70
R = 536 Ω
R = 500 Ω
R = 420 Ω
f
O
f
O
f
O
V
= 2V
V
= 2V
V
= 2V
PP
PP
PP
nd
2
Harmonic
−80
−90
−80
nd
2
Harmonic
nd
2
Harmonic
−90
−90
rd
3
Harmonic
rd
rd
3
Harmonic
3
Harmonic
−100
−100
−100
0.1 M
1 M
10 M 100 M
0.1 M
1 M
10 M
100 M
0.1 M
1 M
10 M 100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 22
Figure 23
Figure 24
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
−50
−60
−70
−80
−50
−55
G = −1
G = −1
G = 2
R
L
= 500 Ω
R
V
= 100 Ω
L
R
L
= 100 Ω
V
= 5 V
CC
=
5 V
−60
−70
−80
CC
V
= 5 V
−60
−65
CC
R = 450 Ω
f
O
R = 450 Ω
f
O
R = 500 Ω
f
O
V
= 2V
PP
V
= 2V
PP
V
= 2V
2
PP
nd
2
Harmonic
−70
−75
−80
−85
−90
nd
2
Harmonic
nd
Harmonic
rd
3
Harmonic
rd
3
Harmonic
rd
3
Harmonic
−90
−90
−95
−100
−100
−100
0.1 M
1 M
10 M
100 M
1 M
10 M
100 M
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 25
Figure 26
Figure 27
10
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ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
−60
−50
−50
−60
G = 5
G = 5
G = 2
R
V
= 100 Ω
L
R
L
= 500 Ω
R
L
= 500 Ω
=
5 V
−60
CC
V
= 5 V
CC
V
= 5 V
CC
R = 420 Ω
nd
f
O
R = 500 Ω
2
Harmonic
f
R = 536 Ω
f
O
V
= 2V
PP
V
= 2V
O PP
V
= 2V
PP
−70
−80
−70
−80
−70
−80
rd
3
Harmonic
nd
2
Harmonic
rd
3
Harmonic
rd
nd
3
Harmonic
2
Harmonic
−90
−90
−90
−100
0.1 M
−100
−100
0.1 M
0.1 M
1 M
10 M
100 M
1 M
10 M
100 M
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − MHz
Figure 28
Figure 29
Figure 30
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
−70
−50
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
G = 5
G = 5
G = 5
−75
−80
R
L
= 500 Ω
R
L
= 500 Ω
R
L
= 500 Ω
V
= 5 V
−60
−70
CC
V
= 15 V
V
= 5 V
CC
CC
nd
2
R = 420 Ω
f
R = 420 Ω
R = 420 Ω
f
f
Harmonic
f = 1 MHz
f = 10 MHz
f = 10 MHz
−85
−90
−80
−95
nd
2
Harmonic
nd
2
Harmonic
−100
−105
−110
−90
rd
3
Harmonic
6
rd
3
Harmonic
rd
3
Harmonic
−100
0
1
2
3
4
5
6
0
2
4
8
10
PP
12
0
1
2
3
4
5
V
− Output Voltage − V
O
PP
V
− Output Voltage − V
V
− Output Voltage − V
O
O
PP
Figure 31
Figure 32
Figure 33
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
−50
−60
−50
−60
−70
−80
G = 5
G = 5
G = 5
R
L
= 100 Ω
R
V
= 100 Ω
R
V
= 100 Ω
L
L
V
= 15 V
CC
= 15 V
=
5 V
CC
CC
R = 500 Ω
R = 500 Ω
f
R = 500 Ω
f
f
f = 1 MHz
f = 1 MHz
f = 1 MHz
−70
−70
nd
2
Harmonic
−80
−80
nd
nd
2
2
Harmonic
Harmonic
−90
−90
−90
rd
3
Harmonic
10
rd
3
Harmonic
rd
3
Harmonic
3
−100
−100
−100
0
2
4
6
8
12
0
2
4
6
8
10
0
1
2
4
5
V
− Output Voltage − V
V
− Output Voltage − V
O
V
− Output Voltage − V
O
PP
O
PP
Figure 34
Figure 35
Figure 36
11
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www.ti.com
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
−60
−70
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
−50
−60
G = 5
G = 2
G = 2
R
L
= 100 Ω
R
L
= 500 Ω
R
L
= 500 Ω
V
=
5 V
V
= 15 V
V
= 15 V
CC
CC
CC
R = 500 Ω
R = 536 Ω
R = 536 Ω
f
f
f
nd
2
f = 10 MHz
f = 1 MHz
f = 10 MHz
nd
Harmonic
2
Harmonic
−70
−80
nd
2
−80
Harmonic
−90
rd
4
3
Harmonic
−90
rd
3
Harmonic
2
rd
3
Harmonic
−100
−100
0
1
3
4
5
0
2
4
6
8
10
PP
12
0
2
6
8
10
10
5
V
− Output Voltage − V
V
− Output Voltage − V
V
− Output Voltage − V
PP
O
PP
O
O
Figure 37
Figure 38
Figure 39
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
−70
−75
−80
−85
−90
−95
−100
−50
−60
−50
−60
G = 2
G = 2
G = 2
R
V
= 500 Ω
R
V
= 100 Ω
= 15 V
R = 500 Ω
f = 1 MHz
R
V
= 500 Ω
5 V
R = 536 Ω
L
CC
L
CC
L
CC
=
5 V
=
R = 536 Ω
f
f
f
f = 1 MHz
nd
f = 10 MHz
2
nd
−70
2
−70
Harmonic
Harmonic
−80
−80
nd
2
Harmonic
rd
3
Harmonic
−90
−90
rd
2
rd
3
Harmonic
3
3
Harmonic
−100
−100
0
1
4
5
0
1
2
3
4
5
0
2
4
6 8
V
− Output Voltage − V
V
− Output Voltage − V
O
PP
V
− Output Voltage − V
O
PP
O
PP
Figure 40
Figure 41
Figure 42
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
−40
−50
−60
−70
−80
−90
−100
−70
−75
−80
−85
−90
−95
−100
G = 2
G = 2
G = 2
R
V
= 100 Ω
R
V
= 100 Ω
5 V
R = 500 Ω
L
CC
R
V
= 100 Ω
= 15 V
R = 500 Ω
f = 10 MHz
L
CC
L
CC
=
5 V
=
R = 500 Ω
f
f
f
f = 10 MHz
f = 1 MHz
nd
2
Harmonic
nd
2
Harmonic
nd
2
Harmonic
rd
3
Harmonic
rd
2
3
Harmonic
3
rd
3
4
Harmonic
6
0
1
2
3
4
0
2
8
10
0
1
4
5
V
− Output Voltage − V
V
− Output Voltage − V
V
− Output Voltage − V
PP
O
PP
O
PP
O
Figure 43
Figure 44
Figure 45
12
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ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
THS3202
THS3202
THS3202
IMD
3
vs
IMD
3
vs
OIP
3
vs
FREQUENCY
FREQUENCY
FREQUENCY
−70
−75
−80
−85
−55
50
R
= 100 Ω, G = 5,
L
Test Instrument Measurement Limit
48
R = 536 Ω,
f
O
−60
−65
−70
−75
−80
−85
V
= 2V _Envelope
PP
∆f = 200 kHz
46
V
= 7.5 V
CC
44
42
40
38
36
34
32
30
V
=
5 V
CC
G = 2
V
=
7 V
6 V
CC
V
=
CC
G = 5
V
=
6 V
CC
=
V
R
= 5 V
= 100 Ω,
R
G = 5,
= 100 Ω,
CC
L
f
V
7 V
L
CC
R = 536 Ω,
−90
−95
R = 536 Ω,
V
=
7.5 V
f
O
CC
∆f = 200 kHz
V
= 2V _Envelope
PP
−90
−95
V
= 2V _Envelope
PP
∆f = 200 kHz
O
28
26
Test Instrument Measurement Limit
60 110 160 210
V
= 5 V
CC
160
0
20
40
60
80
10
60
110
210
260
10
260
f
c
− Frequency − MHz
f
− Frequency − MHz
f
− Frequency − MHz
c
c
Figure 46
Figure 47
Figure 48
THS3202
S PARAMETER
vs
FREQUENCY
OIP
3
vs
TEST CIRCUIT FOR
IMD / OIP
3
3
FREQUENCY
20
0
47
45
43
V
=
5 V
C = 0 pF
= 100 Ω
CC
V
R
= 5 V
= 100 Ω,
CC
L
f
Output Power
S22
R
R = 536 Ω,
L
G = 5
∆f = 200 kHz
Spectrum Analyzer
G = 10
−20
−40
−60
−80
−100
−120
V
= 2V _Envelope
PP
_
O
G = 5
+
50 Ω
41
39
37
35
G = 2
S12
50 Ω
S11
C
+
_
This circuit applies to figures 46
through 49
0.1 M
1 M
10 M
100 M
1 G
10 G
0
20
40
60
80
f − Frequency − Hz
f
− Frequency − MHz
c
Figure 49
Figure 50
Figure 51
S PARAMETER
vs
FREQUENCY
S PARAMETER
vs
FREQUENCY
S PARAMETER
vs
FREQUENCY
20
0
20
0
20
0
V
= 15 V
V
= 15 V
CC
C = 0 pF
= 100 Ω
CC
C = 3 pF
= 100 Ω
V
=
5 V
CC
C = 3 pF
= 100 Ω
S22
S22
R
R
L
L
R
S22
L
−20
−40
−60
−80
−100
−120
−140
−20
−40
−60
−80
−100
−120
−140
G = 10
G = 10
G = 10
−20
−40
−60
−80
−100
−120
S12
S12
S11
S11
S12
S11
C
C
C
+
+
+
_
_
_
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 52
Figure 54
Figure 53
13
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
TRANSIMPEDANCE
INPUT CURRENT NOISE DENSITY
VOLTAGE NOISE DENSITY
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
50
45
40
4.5
4
120
100
80
60
40
20
0
V
=
5 V and 15 V
V
=
5 V and 15 V
T = 25°C
A
CC
CC
V
V
= 15 V,
=
CC
CC
T
A
= 25°C
5 V
3.5
3
35
30
Inverting
Noise Current
25
20
2.5
_
+
10 Ω
Noninverting
Current Noise
2
V
I
O
15
10
+
_
Gain W +
IB
1.5
100 K
100 K
1 M
10 M
100 M
1 M
10 M
100 M
0.1 M
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 55
Figure 56
Figure 57
OUTPUT IMPEDANCE
vs
SUPPLY CURRENT/CHANNEL
THS3202
vs
FREQUENCY
IMPEDANCE OF INVERTING INPUT
SUPPLY VOLTAGE
100
16
15
14
13
12
23
21
19
17
15
13
11
9
V
= +5 V
CC
G = 2
R
L
= 100 Ω
T
A
= 85°C
10
1
T
A
= 25°C
V
= 5 V
CC
T
A
= −40°C
0.1
11
10
7
V
= 15 V
1 M
CC
0.01
5
100 k 1 M
10 M
100 M
1 G
10 G
0.1 M
10 M
100 M
1 G
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
− Supply Voltage − V
f − Frequency − Hz
f − Frequency − Hz
V
CC
Figure 58
Figure 59
Figure 60
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE RANGE
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
−3.5
−4.0
50
45
40
35
30
25
20
15
6
4
2
V
= 5 V
CC
T
= −40°C
A
0
−2
T
A
= 25°C
V
= 15 V
CC
−4
V
5
= 15 V
CC
T
= 85°C
A
−6
V
= 5 V
CC
−8
R
= 100 Ω
= 7.5 V
L
V
CC
−10
−45−35−25−15−5
15 25 35 45 55 65 75 85
−40−30−20−10 0 10 20 30 40 50 60 70 80
−5 −4 −3 −2 −1
0
1
2
3
4
5
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
V
− Common-Mode Input Voltage Range − V
ICR
Figure 61
Figure 62
Figure 63
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NEGATIVE POWER SUPPLY
REJECTION RATIO
vs
POSITIVE POWER SUPPLY
REJECTION RATIO
vs
INPUT BIAS CURRENT
vs
INPUT COMMON MODE RANGE
NEGATIVE POWER SUPPLY
POSITIVE POWER SUPPLY
70
−10
−20
−30
75
70
T
V
= −40°C to 85°C
T
A
= −40°C
A
= 5 V
CC
T
A
= −40°C
65
60
T
A
= 25°C
T
A
= 25°C
65
60
T
A
= 85°C
T
A
= 85°C
55
55
50
45
50
45
R
6
= 100 Ω
R
= 100 Ω
L
L
−3
−2
−1
0
1
2
3
3
3.5
4
4.5
5
5.5
6.5
7
7.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
Input Common Mode Range − V
Negative Power Supply − V
Positive Power Supply − V
Figure 64
Figure 65
Figure 66
POSITIVE OUTPUT VOLTAGE SWING
POSITIVE OUTPUT VOLTAGE SWING
NEGATIVE OUTPUT VOLTAGE SWING
vs
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
13.7
13.6
13.5
13.4
13.3
13.2
13.1
1.8
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.30
V
= 15 V
V
=
5 V
V
= 15 V
CC
CC
CC
1.7
1.6
1.5
1.4
1.3
1.2
R
= 100 Ω
R
= 1 kΩ
L
L
R
= 1 kΩ
L
R
L
= 100 Ω
R
L
= 100 Ω
R
= 1 kΩ
L
−50 −30 −10
10
30
50
70
90
−45 −25
−5
15
35
55
75
95
−50 −30 −10
10
30
50
70
90
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 67
Figure 68
Figure 69
OUTPUT CURRENT SOURCING
NEGATIVE OUTPUT VOLTAGE SWING
OUTPUT CURRENT SINKING
vs
vs
vs
POWER SUPPLY
FREE-AIR TEMPERATURE
POWER SUPPLY
160
140
120
100
80
130
120
110
100
90
−3.45
−3.50
−3.55
−3.60
−3.65
−3.70
−3.75
−3.80
R = 10 Ω
L
R
= 10 Ω
V
=
5 V
L
CC
T
= −40°C
A
R
= 100 Ω
L
T
A
= 85°C
T
A
= 25°C
T
= 85°C
T
= 25°C
A
A
T
= −40°C
A
60
R
= 1 kΩ
80
L
40
70
3
3.5
4
4.5 5 5.5
6
6.5 7.5
7
−50 −30 −10
10
30
50
70
90
3
4
6
7.5
3.5
4.5
5
5.5
6.5
7
Power Supply − V
T
A
− Free-Air Temperature − °C
Power Supply − V
Figure 70
Figure 71
Figure 72
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
SLEW RATE
vs
OVERDRIVE RECOVERY TIME
OUTPUT VOLTAGE
OVERDRIVE RECOVERY TIME
10
8
10
8
10 k
V
I
V
I
G = −1
R
= 100 Ω
= 15 V,
L
6
6
V
V
CC
CC
=
5 V
4
4
2
2
0
0
1 k
V
O
−2
−4
−6
−8
−10
V
−2
−4
−6
−8
−10
O
R
V
= 100 Ω
R
V
= 100 Ω
L
L
= 15 V
=
5 V
CC
CC
100
0.0
0.2
0.4
0.6
0.8
1
0.0
0.2
0.4
0.6
0.8
1
0
1
2
3
4
5
t − Time − µs
t − Time − µs
V
− Output Voltage − V
O
Figure 73
Figure 74
Figure 75
SLEW RATE
vs
OUTPUT VOLTAGE
SLEW RATE
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
TRANSIENT RESPONSE
100 k
10 k
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10 k
V
R
= 15 V
= 100 Ω
CC
L
V
R
=
5 V
= 100 Ω
CC
L
G = −1
R
L
= 500 Ω
1 k
V
= 5 V
CC
−0.5
R = 250 Ω
f
O
1 k
−1.0
−1.5
−2.0
−2.5
−3.0
V
= 5 V
PP
100
100
0
2
4
6
8
10
12
0
10
20
30
40
50
60
0
1
2
3
4
5
6
V
− Output Voltage − V
O
t
s
− Settling Time − ns
V
− Output Voltage − V
O
Figure 76
Figure 77
Figure 78
DC COMMON-MODE REJECTION
RATIO HIGH
vs
SETTLING TIME
INPUT COMMON MODE RANGE
SETTLING TIME
1.5
1.05
1.04
1.03
70
1.4
1.3
1.2
1.1
V
V
= 15 V,
= 2 V
CC
O
V
V
= 15 V,
= 2 V
CC
O
60
50
40
,
PP
,
PP
G = −2,
R = 450 Ω
f
G = −2,
R = 450 Ω
f
1.02
R
L
= 100 Ω
1.01
1
1
30
20
10
0
0.9
0.99
0.98
0.8
0.7
0.97
0.96
0.95
0.6
0.5
0
10 20 30 40 50 60 70 80 90 100
10
30
50
70
90 110 130
150
−7.5 −5.5 −3.5 −1.5 0.5 2.5 4.5 6.5
Settling Time − ns
Settling Time − ns
Input Common Mode Range − V
Figure 79
Figure 80
Figure 81
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
POWER SUPPLY REJECTION RATIO
DIFFERENTIAL GAIN ERROR
POWER SUPPLY REJECTION RATIO
vs
vs
vs
FREQUENCY
150-Ω LOADS
FREQUENCY
−20
−25
−30
−35
−40
−45
−50
−55
−60
0.035
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
NTSC
G = 2
V
= 5 V
V
= 15 V
CC
CC
0.030
0.025
V
0.020
CC
V
CC
0.015
V
= 5 V
CC
V
EE
0.010
V
EE
V
= 15 V
CC
0.005
0.000
1
2
3
4
5
6
0.1 M
1 M
10 M
100 M
1 G
0.1 M
1 M
10 M
100 M
1 G
150-Ω Loads
f − Frequency − Hz
f − Frequency − Hz
Figure 82
Figure 83
Figure 84
DIFFERENTIAL PHASE ERROR
DIFFERENTIAL GAIN ERROR
DIFFERENTIAL PHASE ERROR
vs
vs
vs
150-Ω LOADS
150-Ω LOADS
150-Ω LOADS
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.035
0.030
NTSC
G = 2
NTSC
G = −2
NTSC
G = −2
0.030
0.025
V
=
5 V
CC
V
=
5 V
0.025
CC
0.020
V
= 5 V
CC
0.020
0.015
0.010
0.005
0.000
0.015
V
= 15 V
CC
V
= 15 V
CC
0.010
0.005
0.000
V
= 15 V
CC
3
1
2
4
5
6
1
2
3
4
1
2
3
4
150-Ω Loads
150-Ω Loads
150-Ω Loads
Figure 85
Figure 86
Figure 87
DIFFERENTIAL GAIN ERROR
DIFFERENTIAL PHASE ERROR
vs
vs
150-Ω LOADS
150-Ω LOADS
0.004
0.07
PAL
G = 2
0.035
0.06
0.05
0.04
0.03
0.02
0.01
0.00
V
= 5 V
CC
0.030
0.025
V
=
5 V
V
CC
0.020
0.015
V
= 15 V
CC
= 15 V
CC
0.010
0.005
0.000
PAL
G = 2
1
2
3
4
5
6
1
2
3
4
5
6
150-Ω Loads
150-Ω Loads
Figure 88
Figure 89
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
APPLICATION INFORMATION
INTRODUCTION
The THS3202 is a high-speed, operational amplifier configured in a current-feedback architecture. The device is built
using Texas Instruments BiCOM−ΙΙ process, a 15-V, dielectrically isolated, complementary bipolar process with NPN
and PNP transistors possessing fTs of several GHz. This configuration implements an exceptionally
high-performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion.
RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
As with all current-feedback amplifiers, the bandwidth of the THS3202 is an inversely proportional function of the
value of the feedback resistor. The recommended resistors for the optimum frequency response are shown in Table 1.
These should be used as a starting point and once optimum values are found, 1% tolerance resistors should be used
to maintain frequency response characteristics. For most applications, a feedback resistor value of 750 Ω is
recommendeda good compromise between bandwidth and phase margin that yields a very stable amplifier.
Table 1. Recommended Resistor Values for Optimum Frequency Response
THS3202 R for AC When R
= 100 Ω
F
load
GAIN
V
sup
R Value
F
Peaking
1
15
Optimum
619
619
536
536
402
402
200
200
450
450
5
15
5
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
2
5
15
5
10
−1
15
5
15
5
As shown in Table 1, to maintain the highest bandwidth with an increasing gain, the feedback resistor is reduced. The
advantage of dropping the feedback resistor (and the gain resistor) is the noise of the system is also reduced
compared to no reduction of these resistor values, see noise calculations section. Thus, keeping the bandwidth as
high as possible maintains very good distortion performance of the amplifier by keeping the excess loop gain as high
as possible.
Care must be taken to not drop these values too low. The amplifier’s output must drive the feedback resistance (and
gain resistance) and may place a burden on the amplifier. The end result is that distortion may actually increase due
to the low impedance load presented to the amplifier. Careful management of the amplifier bandwidth and the
associated loading effects needs to be examined by the designer for optimum performance.
The THS3202 amplifier exhibit very good distortion performance and bandwidth with the capability of utilizing up to
15 V power supplies. Their excellent current drive capability of up to 115 mA driving into a 20-Ω load allows for many
versatile applications. One application is driving a twisted pair line (i.e., telephone line). Figure 90 shows a simple
circuit for driving a twisted pair differentially.
18
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
+6 V
+
0.1 µF
10 µF
THS3202(a)
R
S
+
_
V +
I
R
Line
2
2n
499 Ω
1:n
0.1 µF
Telephone Line
R
Line
210 Ω
THS3202(b)
R
S
+
_
V −
I
R
Line
2
2n
499 Ω
0.1 µF
10 µF
+
−6 V
Figure 90. Simple Line Driver With THS3202
Due to the large power supply voltages and the large current drive capability, power dissipation of the amplifier must
not be neglected. To have as much power dissipation as possible in a small package, the THS3202 is available only
in a MSOP−8 PowerPAD package (DGN) and SOIC−8 package (D). Again, power dissipation of the amplifier must
be carefully examined or else the amplifiers could become too hot and performance can be severely degraded. See
the Power Dissipation and Thermal Considerations section for more information on thermal management.
NOISE CALCULATIONS
Noise can cause errors on very small signals. This is especially true for amplifying small signals coming over a
transmission line or an antenna. The noise model for current-feedback amplifiers (CFB) is the same as for voltage
feedback amplifiers (VFB). The only difference between the two is that CFB amplifiers generally specify different
current-noise parameters for each input, while VFB amplifiers usually only specify one noise-current parameter. The
noise model is shown in Figure 91. This model includes all of the noise sources as follows:
•
•
•
•
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN− = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
19
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
e
Rs
e
n
R
S
Noiseless
+
_
e
ni
e
no
IN+
IN−
e
Rf
R
f
e
Rg
R
g
Figure 91. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
2
2
2
Ǹ
ǒe Ǔ
) ǒIN ) R Ǔ ) ǒIN * ǒR ø R ǓǓ ) 4 kTR ) 4 kTǒR ø R
Ǔ
e
+
g
s
g
n
ni
f
f
S
where:
k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
Rf || Rg = Parallel resistance of Rf and Rg
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall
amplifier gain (AV).
R
f
e
+ e
A
+ e
ǒ
1 )
Ǔ
(Noninverting Case)
no
ni
V
ni
R
g
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop
gain is increased (by reducing RF and RG), the input noise is reduced considerably because of the parallel resistance
term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the
internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources
smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and
make noise calculations much easier.
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure
is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and
is typically 50 Ω in RF applications.
2
e
ȱ ȳ
ni
NF + 10log
ȧe ȧ
2
Rs
Ȳ ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage,
we can approximate noise figure as:
2
2
ȱ
ȳ
ȡ
ȣ
) ǒIN ) R
Ǔ
ǒe Ǔ
ȧ
ȧ
S
n
ȧ
ȧ
NF + 10log 1 )Ȣ
Ȥ
ȧ
ȧ
ȧ
ȧ
ȧ
ȧ
ȧ
ȧ
4 kTR
S
Ȳ
ȴ
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE
Achieving optimum performance with high frequency amplifier-like devices in the THS320x family requires careful
attention to board layout parasitic and external component types.
Recommendations that optimize performance include:
D
D
Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output
and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1-µF and 100 pF decoupling
capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal
I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 µF
or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply
pins. These may be placed somewhat farther from the device and may be shared among several devices in the
same area of the PC board. The primary goal is to minimize the impedance seen in the differential-current return
paths. For driving differential loads with the THS3202, adding a capacitor between the power supply pins
improves 2nd order harmonic distortion performance. This also minimizes the current loop formed by the
differential drive.
D
D
Careful selection and placement of external components preserve the high frequency performance of the
THS320x family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use
wirebound type resistors in a high frequency application. Since the output pin and inverting input pins are the most
sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as
possible to the inverting input pins and output pins. Other network components, such as input termination
resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero that can effect circuit
operation. Keep resistor values as low as possible, consistent with load driving considerations.
Connections to other wideband devices on the board may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power
planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the
outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an R since the THS320x family
S
is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R
S
are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and
the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched
impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion
as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material
and trace dimensions, a matching series resistor into the trace from the output of the THS320x is used as well as
a terminating shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input
impedance of the destination device: this total effective impedance should be set to match the trace impedance. If
the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve
signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is
some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
D
Socketing a high speed part like the THS320x family is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the THS320x family parts directly onto the board.
21
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
PowerPAD DESIGN CONSIDERATIONS
The THS320x family is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 92(a) and Figure 92(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 92(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can
be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During
the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a
copper area underneath the package. Through the use of thermal paths within this copper area, heat can be
conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 92. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
68 Mils x 70 Mils
(Via diameter = 10 mils)
Figure 93. DGN PowerPAD PCB Etch and Via Pattern
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PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown in Figure 93. There should be etch for the leads as well
as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 10 mils in diameter. Keep them small so
that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS320x family IC. These additional vias may be larger than the 10-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area
to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this
application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes
under the THS320x family PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes
exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder
from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
POWER DISSIPATION AND THERMAL CONSIDERATIONS
To maintain maximum output capabilities, the THS3202 does not incorporate automatic thermal shutoff protection.
The designer must take care to ensure that the design does not violate the absolute maximum junction temperature
of the device. Failure may result if the absolute maximum junction temperature of 150°C is exceeded. For best
performance, design for a maximum junction temperature of 125°C. Between 125°C and 150°C, damage does not
occur, but the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation
for a given package can be calculated using the following formula.
Tmax * TA
PDmax
+
qJA
where:
P
is the maximum power dissipation in the amplifier (W).
Dmax
T
is the absolute maximum junction temperature (°C).
max
T is the ambient temperature (°C).
A
θ
θ
θ
= θ + θ
JC CA
JA
JC
CA
is the thermal coefficient from the silicon junctions to the case (°C/W).
is the thermal coefficient from the case to ambient air (°C/W).
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For systems where heat dissipation is more critical, the THS320x family of devices is offered in an 8-pin MSOP with
PowerPAD and the THS3202 is available in the SOIC−8 PowerPAD package offering even better thermal
performance. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional
SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the
PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note number SLMA002. The following graph also illustrates the effect of not
soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat
and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.
4.0
T
J
= 125°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
θ
= 58.4°C/W
JA
θ
JA
= 98°C/W
θ
JA
= 158°C/W
−40 −20
0
20
40
60
80 100
T
A
− Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x3”
θ
JA
θ
JA
θ
JA
= 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
= 98°C/W for 8-Pin SOIC High Test PCB (D)
= 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
Figure 94. Maximum Power Dissipation vs Ambient Temperature
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important
to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility
into a possible problem.
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken.
The first is to realize that the THS3202 has been internally compensated to maximize its bandwidth and slew-rate
performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases
the device’s phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 95.
A minimum value of 10 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting
the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance
matching at the source end.
R
g
R
f
_
+
Input
10 Ω
Output
LOAD
THS3202
C
Figure 95. Driving a Capacitive Load
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
GENERAL CONFIGURATIONS
A common error for the first-time CFB user is creating a unity gain buffer amplifier by shorting the output directly to
the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS3202, like all
CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly from the
output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has a very low
impedance. This results in an unstable amplifier and should not be considered when using a current-feedback
amplifier. Because of this, integrators and simple low-pass filters, which are easily implemented on a VFB amplifier,
have to be designed slightly differently. If filtering is required, simply place an RC-filter at the noninverting terminal
of the operational-amplifier (see Figure 96).
R
g
R
f
1
f
+
–3dB
2pR1C1
V
R
−
+
O
f
1
ǒ
Ǔ
Ǔ
+
ǒ
1 )
V
O
V
R
1 ) sR1C1
g
I
V
I
R1
C1
Figure 96. Single-Pole Low-Pass Filter
If a multiple-pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is because
the filtering elements are not in the negative feedback loop and stability is not compromised. Because of their high
slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize distortion. An
example is shown in Figure 97.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
f
1
R
g
=
R
f
2 −
)
R
g
(
Q
Figure 97. 2-Pole Low-Pass Sallen-Key Filter
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SLOS242D − SEPTEMBER 2002 − REVISED JANUARY 2004
There are two simple ways to create an integrator with a CFB amplifier. The first, shown in Figure 98, adds a resistor
in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and the feedback
impedance never drops below the resistor value. The second, shown in Figure 99, uses positive feedback to create
the integration. Caution is advised because oscillations can occur due to the positive feedback.
C1
R
f
1
S )
ȡ
ȣ
R C1
V
R
R
g
f
O
f
+
ǒ Ǔ
−
+
ȧ
ȧ
V
I
V
R
S
g
I
V
O
Ȣ
Ȥ
THS3202
Figure 98. Inverting CFB Integrator
R
g
R
f
For Stable Operation:
R
R
R2
f
≥
R1 || R
−
+
g
A
THS320x
V
O
R
R
f
1 +
V
O
≅ V
g
I
)
(
R1
R2
sR1C1
V
I
C1
R
A
Figure 99. Noninverting CFB Integrator
The THS3202 may also be employed as a very good video distribution amplifier. One characteristic of distribution
amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the number
of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout the distribution
system to minimize reflections and capacitive loading.
R
g
R
f
75-Ω Transmission Line
75 Ω
−
+
V
O1
V
I
THS3202
75 Ω
75 Ω
N Lines
75 Ω
V
ON
75 Ω
Figure 100. Video Distribution Amplifier Application
26
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