THS3202DG4 [TI]
2GHz Current Feedback Amplifier 8-SOIC -40 to 85;
| 型号： | THS3202DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2GHz Current Feedback Amplifier 8-SOIC -40 to 85 放大器 光电二极管 商用集成电路 |
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THS3202
DGN-8 DGK-8
D-8
www.ti.com
SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
2-GHz, LOW DISTORTION, DUAL CURRENT-FEEDBACK AMPLIFIERS
Check for Samples: THS3202
1
FEATURES
DESCRIPTION
23
•
Unity-Gain Bandwidth: 2 GHz
The THS3202 is a dual current-feedback amplifier
developed with BiCOM-II technology. Designed for
low distortion with a high slew rate of 9000 V/µs, the
THS320x family is ideally suited for applications
driving loads sensitive to distortion at high
frequencies.
•
•
•
High Slew Rate: 9000 V/µs
High Output Current: ±115 mA into 20 Ω RL
Power-Supply Voltage Range: 6.6 V to 15 V
APPLICATIONS
The
THS3202
provides
well-regulated
ac
•
•
•
•
•
High-Speed Signal Processing
Test and Measurement Systems
High-Voltage ADC Preamplifier
RF and IF Amplifier Stages
Professional Video
performance characteristics with power supplies
ranging from single-supply 6.6-V operation up to a
15-V supply. The high unity-gain bandwidth of up to
2 GHz is a major contributor to the excellent distortion
performance. The THS3202 offers an output current
drive of ±115 mA and a low differential gain and
phase error that make it suitable for applications such
as video line drivers.
LARGE-SIGNAL
FREQUENCY RESPONSE
14
The THS3202 is available in an SOIC-8, an MSOP-8,
and an MSOP-8 with PowerPAD™ packages.
12
VO = 4 VPP
10
8
6
RELATED DEVICES AND DESCRIPTIONS
VO = 2 VPP
4
2
THS3001
THS3061/2
THS3122
THS4271
±15-V 420-MHz Low Distortion CFB Amplifier
±15-V 300-MHz Low Distortion CFB Amplifier
±15-V Dual CFB Amplifier With 350 mA Drive
+15-V 1.4-GHz Low Distortion VFB Amplifier
0
VO = 1 VPP
-2
-4
-6
VO = 0.25 VPP
-8
G = 2
-10
VCC = ±5
-12
RL = 100 W
-14
100 k
1 M
10 M
100 M
1G
10 G
f - Frequency - Hz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
THS3202
SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
ORDERABLE PACKAGE AND NUMBER
PLASTIC MSOP-8(2) PowerPAD
PLASTIC MSOP-8(2)
NUMBER OF
CHANNELS
PLASTIC SOIC-8(2)
(D)
(DGN)
MARKING
(DGK)
THS3202DGK
MARKING
2
THS3202D
THS3202DGN
BEP
BEV
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (that is, THS3202DR).
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage, VS
16.5 V
Input voltage, VI
±VS
Differential input voltage, VID
±3 V
(2)
Output current, IO
175 mA
Continuous power dissipation
See Package Dissipation Ratings Table
(3)
Maximum junction temperature, TJ
+150°C
+125°C
(4)
Maximum junction temperature, continuous operation, long-term reliability, TJ
Operating free-air temperature range, TA
–40°C to +85°C
–65°C to +150°C
3000 V
Storage temperature range, TSTG
HBM
ESD ratings: CDM
MM
1500 V
200 V
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The THS3202 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the
PowerPAD thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
2
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Product Folder Link(s): THS3202
THS3202
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SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
PACKAGE DISSIPATION RATINGS
POWER RATING(2)
(1)
qJC
qJA
PACKAGE
D (8 pin)
(°C/W)
38.3
4.7
(°C/W)
97.5
58.4
260
T
A ≤ +25°C
TA = +85°C
410 mW
685 mW
154 mW
1.32 W
DGN (8 pin)
DGK (8 pin)
1.71 W
54.2
385 mW
(1) These data were taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
±3.3
6.6
MAX
±7.5
15
UNIT
V
Dual supply
Supply voltage, (VS+ and VS–
)
Single supply
Operating free-air temperature range
–40
+85
°C
PIN ASSIGNMENTS
D, DGN, AND DGK PACKAGES
(TOP VIEW)
1VOUT
1VIN-
1VIN+
VS-
1
2
3
4
8
7
6
5
VS+
2VOUT
2VIN-
2VIN+
Copyright © 2002–2010, Texas Instruments Incorporated
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SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5 V
VS = ±5 V: RF = 500 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3202
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/TYP/
MAX
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
+25°C
+25°C
UNIT
G = +1, RF = 500 Ω
1800
975
780
550
380
875
5100
4400
0.45
19
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
G = +2, RF = 402 Ω
G = +5, RF = 300 Ω
G = +10, RF = 200 Ω
G = +2, VO = 100 mVPP, RF = 536 Ω
G = +2, VO = 4 VPP,RF = 536 Ω
G = –1, 5-V step
Small-signal bandwidth, –3 dB
(VO = 100 mVPP
)
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
Slew rate (25% to 75% level)
G = +2, 5-V step
Rise and fall time
G = +2, VO = 5-V step
G = –2, VO = 2-V step
G = –2, VO = 2-V step
G = +2, f = 16 MHz, VO = 2 VPP
RL = 100 Ω
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
ns
118
ns
–64
–67
–67
–69
dBc
dBc
dBc
dBc
Typ
Typ
Typ
Typ
2nd harmonic
RL = 500 Ω
RL = 100 Ω
3rd harmonic
RL = 500 Ω
G = +5, fC = 120 MHz, Δf = 200 kHz,
VO(envelope) = 2 VPP
3rd-order intermodulation distortion
–64
dBc
Typ
Input voltage noise
f > 10 MHz
1.65
13.4
20
nV/√Hz
pA/√Hz
pA/√Hz
dB
Typ
Typ
Typ
Typ
Typ
Typ
Input current noise (noninverting)
Input current noise (inverting)
Crosstalk
f > 10 MHz
f > 10 MHz
G = +2, f = 100 MHz
G = +2, RL = 150 Ω
G = +2, RL = 150 Ω
–60
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
DC PERFORMANCE
0.008
0.03
%
Degrees
Open-loop transimpedance gain
Input offset voltage
VO = ±1 V, RL = 1 kΩ
VCM = 0 V
300
200
±3
140
±3.8
±10
120
±4
kΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
±0.7
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
VCM = 0 V
±13
±85
±400
±50
±400
µV/°C
µA
VCM = 0 V
±13
±14
±60
±35
±80
VCM = 0 V
±300
±45
nA/°C
µA
VCM = 0 V
VCM = 0 V
±300
nA/°C
4
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SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
VS = ±5 V: RF = 500 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3202
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/TYP/
MAX
PARAMETER
TEST CONDITIONS
+25°C
+25°C
UNIT
INPUT
Common-mode input range
Common-mode rejection ratio
±2.6
71
±2.5
60
±2.5
58
±2.5
58
V
Min
Min
Typ
Typ
Typ
VCM = ±2.5 V
dB
kΩ
Ω
Noninverting
Inverting
780
11
Input resistance
Input capacitance
Noninverting
1
pF
OUTPUT
RL = 1 kΩ
±3.65
±3.45
115
±3.5
±3.3
105
85
±3.45
±3.25
100
±3.4
±3.2
100
80
V
V
Min
Min
Min
Min
Typ
Voltage output swing
RL = 100 Ω
RL = 20 Ω
Current output, sourcing
mA
mA
Ω
Current output, sinking
RL = 20 Ω
100
80
Closed-loop output impedance
POWER SUPPLY
G = +1, f = 1 MHz
0.01
Minimum operating voltage
Maximum quiescent current
Power-supply rejection (+PSRR)
Power-supply rejection (–PSRR)
Absolute minimum
Per amplifier
±3
16.8
63
±3
19
60
55
±3
20
60
55
V
Min
Max
Min
Min
14
69
65
mA
dB
dB
VS+ = 4.5 V to 5.5 V
VS– = –4.5 V to –5.5 V
58
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SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
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ELECTRICAL CHARACTERISTICS: VS = 15 V
VS = 15 V: RF = 500 Ω, RL = 100 Ω, and G = +2, unless otherwise noted.
THS3202
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/TYP/
MAX
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
+25°C
+25°C
UNITS
G = +1, RF = 550 Ω
2000
1100
850
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
G = +2, RF = 550 Ω
G = +5, RF = 300 Ω
G = +10, RF = 200 Ω
G = +2, VO = 100 mVPP, RF = 536 Ω
G = +2, VO = 4 VPP, RF = 536 Ω
G = +5, 5-V step
Small-signal bandwidth, –3 dB
(VO = 100 mVPP
)
750
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
500
1000
7500
9000
0.45
23
Slew rate (25% to 75% level)
G = +2, 10-V step
Rise and fall time
G = +2, VO = 10-V step
G = –2, VO = 2-V step
G = –2, VO = 2-V step
f > 10 MHz
Settling time to 0.1%
ns
Settling time to 0.01%
Input voltage noise
112
ns
1.65
13.4
20
nV/√Hz
pA/√Hz
pA/√Hz
dB
Input current noise (noninverting)
Input current noise (inverting)
Crosstalk
f > 10 MHz
f > 10 MHz
G = +2, f = 100 MHz
G = +2, RL = 150 Ω
G = +2, RL = 150 Ω
–60
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
DC PERFORMANCE
0.004
0.006
%
Degrees
Open-loop transimpedance gain
Input offset voltage
VO = 6.5 V to 8.5 V, RL = 1 kΩ
VCM = 7.5 V
300
200
±4
140
±4.8
±10
120
±5
kΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
±1.3
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
INPUT
VCM = 7.5 V
±13
±85
±400
±50
±400
µV/°C
µA
VCM = 7.5 V
±16
±14
±60
±35
±80
VCM = 7.5 V
±300
±45
nA/°C
µA
VCM = 7.5 V
VCM = 7.5 V
±300
nA/°C
2.4 to
12.6
2.5 to
12.5
2.5 to
12.5
2.5 to
12.5
Common-mode input range
Common-mode rejection ratio
V
Min
VCM = 5 V to 10 V
Noninverting
Inverting
69
780
11
1
60
58
58
dB
kΩ
Ω
Min
Typ
Typ
Typ
Input resistance
Input capacitance
Noninverting
pF
OUTPUT
1.5 to
13.5
1.6 to
13.4
1.7 to
13.3
1.7 to
13.3
RL = 1 kΩ
V
V
Min
Min
Voltage output swing
1.7 to
13.3
1.8 to
13.2
2.0 to
13.0
2.0 to
13.0
RL = 100 Ω
Current output, sourcing
RL = 20 Ω
120
115
0.01
105
95
100
90
100
90
mA
mA
Ω
Min
Min
Typ
Current output, sinking
RL = 20 Ω
Closed-loop output impedance
POWER SUPPLY
G = +1, f = 1 MHz
Maximum quiescent current/channel
Power-supply rejection (+PSRR)
Power-supply rejection (–PSRR)
Per amplifier
15
69
65
18
63
58
21
60
55
21
60
55
mA
dB
dB
Max
Min
Min
VS+ = 14.50 V to 15.50 V
VS– = –0.5 V to +0.5 V
6
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SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Figure 1-Figure 14
Figure 15-Figure 18
Figure 19-Figure 24
Figure 25-Figure 32
Figure 33, Figure 34
Figure 35, Figure 36
Figure 37
Small-signal frequency response
Large-signal frequency response
Harmonic distortion
Harmonic distortion
IMD3
vs Frequency
vs Output voltage
vs Frequency
vs Frequency
OIP3
Test circuit for IMD3/OIP3
S-parameter
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
Figure 38-Figure 41
Figure 42
Input current noise density
Voltage noise density
Transimpedance
Figure 43
Figure 44
Output impedance
Impedance of inverting input
Supply current/channel
Input offset voltage
Offset voltage
Figure 45
Figure 46
vs Supply voltage
Figure 47
vs Free-air temperature
vs Common-mode input voltage range
vs Free-air temperature
vs Input common-mode range
vs Positive power supply
vs Negative power supply
vs Free-air temperature
vs Free-air temperature
vs Power supply
Figure 48
Figure 49
Figure 50
Input bias current
Figure 51
Positive power-supply rejection ratio
Negative power-supply rejection ratio
Positive output voltage swing
Negative output voltage swing
Output current sinking
Figure 52
Figure 53
Figure 54, Figure 55
Figure 56, Figure 57
Figure 58
Output current sourcing
vs Power supply
Figure 59
Overdrive recovery time
Slew rate
Figure 60, Figure 61
Figure 62-Figure 64
Figure 65
vs Output voltage
Output voltage transient response
Settling time
Figure 66, Figure 67
Figure 68
DC common-mode rejection ratio high
Power-supply rejection ratio
Differential gain error
vs Input common-mode range
vs Frequency
Figure 69, Figure 70
Figure 71, Figure 72, Figure 75
Figure 73, Figure 74, Figure 76
vs 150-Ω loads
Differential phase error
vs 150-Ω loads
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TYPICAL CHARACTERISTICS
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
4
4
3
6
G = 1
R = 500 Ω
f
R = 500 Ω
5
f
3
2
1
R
V
= 500 Ω
L
4
= ±5 V
2
CC
V
= 100 mV
PP
O
3
1
0
2
0
R = 619 Ω
f
R = 619 Ω
f
−1
−2
−3
−4
1
R = 619 Ω
f
−1
0
−2
−1
−2
−3
−4
G = 1
G = 1
−3
R
L
= 100 Ω
R
L
= 100 Ω
R = 750 Ω
f
V
V
= ±5 V
= 100 mV
CC
V
V
= 15 V
= 100 mV
CC
−4
O
PP
O
PP
−5
−5
0.1 M
1 M
10 M
100 M
1 G
10G
10 G
10 G
0.1
M
1 M
10 M
100 M
1 G
10 G
10 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
10 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
Figure 3.
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
12
9
9
G = 2
R
V
V
11
10
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
= 500 Ω
= 15 V
= 100 mV
L
R = 402 Ω
f
R = 402 Ω
f
CC
O
PP
8
R = 536 Ω
f
7
R = 536 Ω
f
R = 536 Ω
f
6
5
R = 650 Ω
f
R = 650 Ω
f
4
R = 649 Ω
f
3
G = 2
G = 2
R
V
R
V
V
= 100 Ω
= 100 Ω
= ±5 V
L
L
2
= 15 V
CC
CC
1
= 100 mV
V = 100 mV
O PP
O
PP
0
0
0
0.1 M
1 M
10 M
100 M
1 G
0.1 M
1 M
10 M
100 M
1 G
0.1 M
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
16
9
16
R = 300 Ω
f
R = 300 Ω
f
8
7
6
5
4
3
2
1
15
14
13
12
11
10
9
15
14
13
12
11
10
R = 536 Ω
f
R = 402 Ω
f
R = 402 Ω
f
R = 649 Ω
f
R = 500 Ω
f
R = 500 Ω
f
G = 5
R
V
G = 2
G = 5
= 100 Ω
= 100 Ω
= 15 V
R
V
V
= 500 Ω
R
V
L
L
L
= ±5 V
= ±5 V
CC
CC
CC
V
= 100 mV
PP
= 100 mV
PP
V
= 100 mV
PP
O
O
O
0
8
0.1 M
1 M
10 M
100 M
1 G
0.1 M
1 M
10 M
100 M
1 G
0.1 M
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
Figure 9.
8
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TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL FREQUENCY
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
RESPONSE
7
17
16
3
R = 340 Ω
f
R = 340 Ω
f
2
1
15
14
13
12
11
10
9
R = 340 Ω
f
16
15
0
R = 420 Ω
f
14
−1
−2
−3
−4
−5
−6
R = 450 Ω
f
13
R = 500 Ω
f
R = 420 Ω
f
R = 500 Ω
f
12
R = 550 Ω
f
G = 5
G = 5
G = −1
R
V
= 500 Ω
R
V
= 500 Ω
R = 100 Ω
L
L
L
11
= 15 V
= ±5 V
V
= 15 V
CC
CC
CC
V
= 100 mV
PP
V
= 100 mV
V = 100 mV
O PP
O
O
PP
10
8
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 10.
Figure 11.
Figure 12.
SMALL-SIGNAL FREQUENCY
RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
LARGE-SIGNAL FREQUENCY
RESPONSE
3
3
2
12
10
G = 1,
R = 340 Ω
f
2
V
= ±5 V
CC
V
= 15 V
CC
V
= 2 V
PP
O
8
6
R
L
= 100 Ω
1
1
0
4
2
0
V
= 1 V
PP
O
−1
−2
−3
−4
−5
−6
−1
−2
−3
−4
−5
0
−2
−4
R = 450 Ω
f
V
= ±5 V
CC
V
= 0.5 V
PP
O
R = 550 Ω
f
−6
−8
G = −1
G = 1
= 500 Ω
R
V
= 100 Ω
R
L
L
= ±5 V
R = 450
f
Ω
CC
−10
−12
V
= 100 mV
PP
V
= 100 mV
PP
O
O
100 K 1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 13.
Figure 14.
Figure 15.
LARGE-SIGNAL FREQUENCY
RESPONSE
LARGE-SIGNAL FREQUENCY
RESPONSE
LARGE-SIGNAL FREQUENCY
RESPONSE
12
10
14
12
10
14
12
V
= 4 V
PP
O
V
= 4 V
O
O
PP
PP
10
8
8
V
O
= 2 V
PP
O
8
6
4
2
0
6
4
2
6
V
= 2 V
O
O
PP
V
= 2 V
4
V
O
= 1 V
PP
2
0
−2
0
−2
V
= 1 V
PP
PP
V
= 1 V
PP
O
−2
−4
−6
−8
−4
−6
−4
−6
−8
V
= 0.5 V
PP
V
= 0.25 V
O
−8
V
= 0.5 V
PP
O
−10
V
= 15 V, G = 1, R = 100 Ω
L
−10
−12
100 K 1 M
CC
−10
−12
100 K
V
= 15 V, G = 2, R = 100 Ω
L
−12
−14
G = 2, V = ±5, R = 100 Ω
CC
CC
L
10 M
100 M
1 G
10 G
100 K
1 M
10 M
100 M
1 G
10 G
1 M
10 M 100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
−60
−70
−80
−50
−60
−70
−80
−50
−55
G = −1
G = 2
G = −1
R
= 100 Ω
= ±5 V
R
L
= 100 Ω
L
R
V
= 500 Ω
= ±5 V
L
V
V
= ±5 V
CC
CC
CC
−60
−65
R = 450 Ω
f
R = 500 Ω
f
R = 450 Ω
f
V
= 2V
PP
V
= 2V
O
V
= 2V
O
PP
O
PP
−70
−75
−80
−85
−90
nd
nd
nd
2
Harmonic
2
Harmonic
2
Harmonic
rd
3
Harmonic
rd
3
Harmonic
rd
3
Harmonic
−90
−90
−95
−100
−100
−100
1 M
10 M
100 M
100 M
6
1 M
10 M
100 M
0.1 M
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 19.
Figure 20.
Figure 21.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
−60
−50
−60
−50
−60
G = 5
G = 5
G = 2
R
V
= 100 Ω
= ±5 V
R
L
= 500 Ω
= ±5 V
L
R
V
= 500 Ω
= ±5 V
L
V
CC
CC
CC
nd
2
Harmonic
R = 420 Ω
f
R = 500 Ω
f
R = 536 Ω
f
V
= 2V
PP
V
= 2V
PP
O
V
= 2V
O
O
PP
−70
−80
−70
−80
−70
−80
rd
3
Harmonic
nd
2
Harmonic
rd
3
Harmonic
rd
nd
Harmonic
3
Harmonic
2
−90
−90
−90
−100
−100
−100
0.1 M
1 M
10 M
100 M
0.1 M
1 M
10 M
0.1 M
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − MHz
f − Frequency − Hz
Figure 22.
Figure 23.
Figure 24.
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
−70
−50
−70
G = 5
G = 5
G = 5
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
−75
−80
R
L
= 500 Ω
R
L
= 500 Ω
R
L
= 100 Ω
V
= ±5 V
V
= ±5 V
V
= ±5 V
CC
CC
CC
R = 420 Ω
f
R = 420 Ω
f
R = 500 Ω
f
−80
−90
f = 1 MHz
f = 10 MHz
f = 1 MHz
−85
−90
nd
2
Harmonic
−95
nd
2
Harmonic
nd
2
Harmonic
−100
−105
−110
rd
3
Harmonic
rd
3
Harmonic
rd
3
Harmonic
3
−100
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
4
5
V
− Output Voltage − V
V
− Output Voltage − V
V − Output Voltage − V
O PP
O
PP
O
PP
Figure 25.
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
−70
−75
−80
−85
−90
−95
−100
−50
−60
G = 5
G = 2
G = 2
R
L
= 100 Ω
R
L
= 500 Ω
R
L
= 500 Ω
V
= ±5 V
V
= ±5 V
V
= ±5 V
CC
CC
CC
R = 500 Ω
f
R = 536 Ω
f
R = 536 Ω
f
nd
nd
f = 10 MHz
f = 1 MHz
f = 10 MHz
2
2
Harmonic
nd
−70
Harmonic
2
Harmonic
−80
rd
3
Harmonic
−90
rd
3
Harmonic
rd
2
3
Harmonic
3
−100
0
1
2
3
4
5
0
1
4
5
0
1
2
− Output Voltage − V
PP
3
4
5
V
− Output Voltage − V
V
− Output Voltage − V
V
O
PP
O
PP
O
Figure 28.
Figure 29.
Figure 30.
THS3202
IMD3
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
FREQUENCY
−55
−60
−65
−70
−75
−80
−85
−70
−75
−80
−85
−90
−95
−100
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
R
= 100 Ω, G = 5,
L
G = 2
G = 2
R = 536 Ω,
f
V
= 2V _Envelope
R
L
= 100 Ω
R
L
= 100 Ω
O
PP
∆f = 200 kHz
V
= ±5 V
V
= ±5 V
CC
CC
R = 500 Ω
f
R = 500 Ω
f
V
= ±5 V
CC
f = 1 MHz
f = 10 MHz
nd
2
Harmonic
V
= ±6 V
nd
CC
2
Harmonic
V
= ±7 V
CC
V
= ±7.5 V
CC
rd
3
Harmonic
−90
−95
rd
3
Harmonic
2
Test Instrument Measurement Limit
60 110 160 210
10
260
0
1
3
4
5
0
1
2
− Output Voltage − V
PP
3
4
5
f
c
− Frequency − MHz
V
− Output Voltage − V
V
O
PP
O
Figure 31.
Figure 32.
Figure 33.
THS3202
IMD3
vs
THS3202
OIP3
THS3202
OIP3
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
47
45
43
−70
−75
−80
−85
50
48
46
44
42
40
38
36
34
32
30
Test Instrument Measurement Limit
V
R
= ±5 V
= 100 Ω,
CC
L
R = 536 Ω,
∆f = 200 kHz
V
f
G = 5
V
= ±7.5 V
CC
= 2V _Envelope
O
PP
G = 2
V
= ±7 V
CC
V
= ±6 V
CC
41
39
37
35
G = 5
G = 2
R
= 100 Ω,
G = 5,
R = 536 Ω,
V
R
= ±5 V
= 100 Ω,
L
CC
L
R = 536 Ω,
∆f = 200 kHz
V
−90
−95
f
f
V
= 2V _Envelope
O
PP
∆f = 200 kHz
= 2V _Envelope
O
PP
28
26
V
= ±5 V
CC
10
60
110
f − Frequency − MHz
c
160
210
260
0
20
40
60
80
0
20
40
60
80
f
c
− Frequency − MHz
f
− Frequency − MHz
c
Figure 34.
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
S-PARAMETER
vs
FREQUENCY
S-PARAMETER
vs
FREQUENCY
TEST CIRCUIT FOR
IMD3/OIP3
20
0
20
0
TEST CIRCUIT FOR
V
= 15 V
V
= ±5 V
CC
CC
IMD / OIP
3
3
C = 0 pF
= 100 Ω
C = 0 pF
= 100 Ω
S22
S22
R
R
L
L
−20
−40
−60
−80
−100
−120
−140
G = 10
G = 10
−20
−40
−60
−80
−100
−120
Output Power
Spectrum Analyzer
_
G = 5
+
S12
S11
S12
50 Ω
S11
C
C
+
+
50 Ω
_
_
0.1 M
1 M
10 M
100 M
1 G
10 G
10 G
1 G
0.1 M
1 M
10 M
100 M
1 G
10 G
This circuit applies to figures 46
through 49
f − Frequency − Hz
f − Frequency − Hz
Figure 37.
Figure 38.
Figure 39.
S-PARAMETER
vs
FREQUENCY
S-PARAMETER
vs
FREQUENCY
INPUT CURRENT NOISE DENSITY
vs
FREQUENCY
20
0
20
0
50
V
T
= ±5 V and 15 V
CC
= 25°C
V
= 15 V
V
= ±5 V
C = 3 pF
= 100 Ω
CC
CC
45
40
C = 3 pF
= 100 Ω
A
S22
R
R
S22
L
L
−20
−40
−60
−80
−100
−120
−140
G = 10
G = 10
−20
−40
−60
−80
−100
−120
35
30
Inverting
Noise Current
S12
S12
S11
25
20
S11
C
C
+
+
_
_
Noninverting
Current Noise
15
10
100 K
1 M
10 M
100 M
0.1 M
1 M
10 M
100 M
1 G
10 G
0.1 M
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 40.
Figure 41.
Figure 42.
VOLTAGE NOISE DENSITY
TRANSIMPEDANCE
vs
OUTPUT IMPEDANCE
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
4.5
4
100
10
1
120
100
80
60
40
20
0
V
T
A
= ±5 V and 15 V
V
V
= 15 V,
=± 5 V
CC
= 25°C
CC
CC
G = 2
= 100 Ω
R
L
3.5
3
V
= ±5 V
CC
2.5
_
+
10 Ω
0.1
V
I
2
O
+
_
Gain W +
IB
V
= 15 V
1 M
CC
1.5
0.01
100 K
1 M
10 M
100 M
0.1 M
1 M
10 M
100 M
0.1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 43.
Figure 44.
Figure 45.
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SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT/CHANNEL
INPUT OFFSET VOLTAGE
vs
THS3202
vs
IMPEDANCE OF INVERTING INPUT
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
16
23
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
−3.5
−4.0
V
= +5 V
CC
21
19
17
15
13
11
9
15
14
13
12
T
= 85°C
A
V
= ±5 V
CC
T
A
= 25°C
V
5
= 15 V
T
= −40°C
CC
A
11
10
7
5
100 k 1 M
10 M
100 M
1 G
10 G
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
−45−35−25−15−5
15 25 35 45 55 65 75 85
f − Frequency − Hz
±V − Supply Voltage − V
CC
T
A
− Free-Air Temperature − °C
Figure 46.
Figure 47.
Figure 48.
OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
RANGE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
INPUT COMMON-MODE RANGE
50
45
40
35
30
25
20
15
−10
−20
−30
6
4
2
T
V
= −40°C to 85°C
A
=± 5 V
CC
T
= −40°C
A
0
−2
T
A
= 25°C
V
= 15 V
CC
−4
T
= 85°C
A
−6
V
= ±5 V
CC
−8
R
= 100 Ω
= ±7.5 V
L
V
CC
−10
−3
−2
−1
0
1
2
3
−40−30−20−10 0 10 20 30 40 50 60 70 80
−5 −4 −3 −2 −1
0
1
2
3
4
5
Input Common Mode Range − V
T
A
− Free-Air Temperature − °C
V
− Common-Mode Input Voltage Range − V
ICR
Figure 49.
Figure 50.
Figure 51.
POSITIVE POWER-SUPPLY
REJECTION RATIO
NEGATIVE POWER-SUPPLY
REJECTION RATIO
POSITIVE OUTPUT VOLTAGE SWING
vs
vs POSITIVE POWER SUPPLY
vs NEGATIVE POWER SUPPLY
FREE-AIR TEMPERATURE
13.7
75
70
70
V
= 15 V
CC
T
= −40°C
A
13.6
13.5
13.4
13.3
13.2
13.1
T
= −40°C
A
R
L
= 1 kΩ
65
60
T
A
= 25°C
T
A
= 25°C
65
60
T
A
= 85°C
T
= 85°C
A
55
55
R
L
= 100 Ω
50
45
50
45
R
= 100 Ω
L
R
6
= 100 Ω
L
−50 −30 −10
10
30
50
70
90
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
3
3.5
4
4.5
5
5.5
6.5
7
7.5
T
A
− Free-Air Temperature − °C
Positive Power Supply − V
Negative Power Supply − V
Figure 52.
Figure 53.
Figure 54.
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TYPICAL CHARACTERISTICS (continued)
POSITIVE OUTPUT VOLTAGE SWING
NEGATIVE OUTPUT VOLTAGE SWING
NEGATIVE OUTPUT VOLTAGE SWING
vs
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3.75
−3.45
1.8
V
= ±5 V
V
= ±5 V
CC
V
= 15 V
CC
CC
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.30
−3.50
−3.55
−3.60
−3.65
−3.70
−3.75
−3.80
1.7
1.6
1.5
1.4
1.3
1.2
R
= 100 Ω
L
R
= 100 Ω
L
R
= 1 kΩ
L
R
L
= 100 Ω
R
= 1 kΩ
L
R
= 1 kΩ
L
−45 −25
−5
15
35
55
75
95
7.5
5
−50 −30 −10
10
30
50
70
90
−50 −30 −10
10
30
50
70
90
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
T
− Free-Air Temperature − °C
A
Figure 55.
Figure 56.
Figure 57.
OUTPUT CURRENT SINKING
OUTPUT CURRENT SOURCING
vs
vs
POWER SUPPLY
POWER SUPPLY
OVERDRIVE RECOVERY TIME
130
120
110
100
90
160
140
120
100
80
10
V
I
R
= 10 Ω
R = 10 Ω
L
L
8
6
T
= −40°C
A
4
T
= 85°C
A
2
T
= 25°C
A
0
T
= 85°C
T
= 25°C
A
A
−2
−4
−6
−8
−10
V
O
T
= −40°C
A
80
60
R
L
= 100 Ω
V
= 15 V
CC
70
40
3
3.5
4
4.5
5
5.5
6
6.5
7
5
7
0.0
0.2
0.4
0.6
0.8
1
3
3.5
4
4.5
5.5
6
6.5
7.5
±Power Supply − V
±Power Supply − V
t − Time − µs
Figure 58.
Figure 59.
Figure 60.
SLEW RATE
vs
SLEW RATE
vs
OVERDRIVE RECOVERY TIME
OUTPUT VOLTAGE
OUTPUT VOLTAGE
10 k
10
10 k
V
I
V
=± 5 V
G = −1
CC
8
6
R
L
= 100 Ω
R
L
= 100 Ω
V
V
= 15 V,
= ±5 V
CC
CC
4
2
0
1 k
1 k
V
O
−2
−4
−6
−8
−10
R
V
= 100 Ω
L
= ±5 V
CC
100
100
0.0
0.2
0.4
0.6
0.8
10
0
1
2
3
4
0
1
2
3
4
5
6
t − Time − µs
V
− Output Voltage − V
V
− Output Voltage − V
O
O
Figure 61.
Figure 62.
Figure 63.
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TYPICAL CHARACTERISTICS (continued)
SLEW RATE
vs
OUTPUT VOLTAGE
TRANSIENT
OUTPUT VOLTAGE
RESPONSE
SETTLING TIME
100 k
10 k
1.05
1.04
1.03
3.0
2.5
V
R
= 15 V
= 100 Ω
CC
V
V
= 15 V,
CC
L
2.0
= 2 V
,
O
PP
1.5
G = −2,
R = 450 Ω
1.02
f
1.0
G = −1
1.01
1
0.5
R
L
= 500 Ω
0.0
V
= ±5 V
CC
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
R = 250 Ω
f
0.99
0.98
1 k
V
= 5 V
PP
O
0.97
0.96
0.95
100
0
2
4
6
8
10
12
10
30
50
70
90 110 130
150
0
10
20
t − Settling Time − ns
s
30
40
50
60
V
− Output Voltage − V
Settling Time − ns
O
Figure 64.
Figure 65.
Figure 66.
DC COMMON-MODE REJECTION
RATIO HIGH
POWER-SUPPLY REJECTION RATIO
vs
vs
SETTLING TIME
INPUT COMMON-MODE RANGE
FREQUENCY
1.5
1.4
1.3
1.2
1.1
−20
V
= ±5 V
CC
70
60
50
V
V
= 15 V,
CC
−25
−30
−35
−40
−45
−50
−55
−60
= 2 V
,
O
PP
G = −2,
R = 450 Ω
f
V
CC
R
L
= 100 Ω
1
40
0.9
30
20
10
0
V
EE
0.8
0.7
0.6
0.5
0
10 20 30 40 50 60 70 80 90 100
0.1 M
1 M
10 M
100 M
1 G
Settling Time − ns
f − Frequency − Hz
−7.5 −5.5 −3.5 −1.5 0.5 2.5 4.5 6.5
Input Common Mode Range − V
Figure 67.
Figure 68.
Figure 69.
POWER-SUPPLY REJECTION RATIO
DIFFERENTIAL GAIN ERROR
DIFFERENTIAL GAIN ERROR
vs
vs
vs
FREQUENCY
150-Ω LOADS
150-Ω LOADS
0.035
−10
0.030
NTSC
G = 2
V
= 15 V
NTSC
G = −2
CC
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
0.030
0.025
0.025
0.020
V
= ±5 V
CC
0.020
0.015
0.010
0.005
0.000
V
CC
0.015
V
= 15 V
CC
V
= ±5 V
CC
0.010
V
EE
V
= 15 V
CC
0.005
0.000
1
2
3
4
5
6
1
2
3
4
0.1 M
1 M
10 M
100 M
1 G
150-Ω Loads
f − Frequency − Hz
150-Ω Loads
Figure 70.
Figure 71.
Figure 72.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL PHASE ERROR
DIFFERENTIAL PHASE ERROR
DIFFERENTIAL GAIN ERROR
vs
vs
vs
150-Ω LOADS
150-Ω LOADS
150-Ω LOADS
0.035
0.004
0.06
NTSC
G = 2
NTSC
G = −2
PAL
G = 2
0.035
0.030
0.05
0.04
0.03
0.02
0.01
0.00
V
= ±5 V
CC
0.030
V
= ±5 V
0.025
CC
0.025
0.020
V
= ±5 V
CC
0.020
0.015
0.015
V
= 15 V
CC
V
= 15 V
0.010
0.005
0.000
CC
0.010
V
= 15 V
CC
0.005
0.000
1
2
3
4
5
6
1
2
3
4
1
2
3
4
5
6
150-Ω Loads
150-Ω Loads
150-Ω Loads
Figure 73.
Figure 74.
Figure 75.
DIFFERENTIAL PHASE ERROR
vs
150-Ω LOADS
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
V
= ±5 V
CC
V
= 15 V
CC
PAL
G = 2
1
2
3
4
5
6
150-Ω Loads
Figure 76.
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APPLICATION INFORMATION
INTRODUCTION
The THS3202 is a high-speed, operational amplifier configured in a current-feedback architecture. The device is
built using Texas Instruments BiCOM-II process, a 15-V, dielectrically isolated, complementary bipolar process
with NPN and PNP transistors possessing fTs of several GHz. This configuration implements an exceptionally
high-performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion.
RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
As with all current-feedback amplifiers, the bandwidth of the THS3202 is an inversely proportional function of the
value of the feedback resistor. The recommended resistors for the optimum frequency response are shown in
Table 1. These should be used as a starting point and once optimum values are found, 1% tolerance resistors
should be used to maintain frequency response characteristics. For most applications, a feedback resistor value
of 750 Ω is recommended—a good compromise between bandwidth and phase margin that yields a very stable
amplifier.
Table 1. Recommended Resistor Values for Optimum Frequency Response
THS3202 RF FOR AC WHEN RLOAD = 100 Ω
GAIN
VSUP
15
±5
PEAKING
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
Optimum
RF VALUE
619
1
619
15
±5
536
2
5
536
15
±5
402
402
15
±5
200
10
–1
200
15
±5
450
450
As shown in Table 1, to maintain the highest bandwidth with an increasing gain, the feedback resistor is reduced.
The advantage of dropping the feedback resistor (and the gain resistor) is that the noise of the system is also
reduced compared to no reduction of these resistor values (see the Noise Calculations section). Thus, keeping
the bandwidth as high as possible maintains very good distortion performance of the amplifier by keeping the
excess loop gain as high as possible.
Care must be taken to not drop these values too low. The amplifier output must drive the feedback resistance
(and gain resistance) and may place a burden on the amplifier. The end result is that distortion may actually
increase due to the low impedance load presented to the amplifier. Careful management of the amplifier
bandwidth and the associated loading effects must be examined by the designer for optimum performance.
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The THS3202 amplifier exhibits very good distortion performance and bandwidth with the capability of utilizing up
to 15-V supplies. Their excellent current drive capability of up to 115 mA driving into a 20-Ω load allows for many
versatile applications. One application is driving a twisted pair line (for example, a telephone line). Figure 77
shows a simple circuit for driving a twisted pair differentially.
+6 V
+
0.1 µF
10 µF
THS3202(a)
R
S
+
_
V +
I
R
Line
2
2n
499 Ω
1:n
0.1 µF
Telephone Line
R
Line
210 Ω
THS3202(b)
R
S
+
_
V −
I
R
Line
2
2n
499 Ω
10 µF
0.1 µF
+
−6 V
Figure 77. Simple Line Driver With THS3202
Due to the large power-supply voltages and the large current drive capability, power dissipation of the amplifier
must not be neglected. To have as much power dissipation as possible in a small package, the THS3202 is
available in an MSOP-8 package (DGK), an MSOP-8 PowerPAD package (DGN), and an SOIC-8 package (D).
Again, power dissipation of the amplifier must be carefully examined or else the amplifiers could become too hot
and performance can be severely degraded. See the Power Dissipation and Thermal Considerations section for
more information on thermal management.
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NOISE CALCULATIONS
Noise can cause errors on very small signals. This is especially true for amplifying small signals coming over a
transmission line or an antenna. The noise model for current-feedback amplifiers (CFB) is the same as for
voltage feedback amplifiers (VFB). The only difference between the two is that CFB amplifiers generally specify
different current-noise parameters for each input, while VFB amplifiers usually only specify one noise-current
parameter. The noise model is shown in Figure 78. This model includes all of the noise sources as follows:
•
•
•
•
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN− = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx )
e
Rs
e
n
R
S
Noiseless
+
_
e
ni
e
no
IN+
IN−
e
Rf
R
f
e
Rg
R
g
Figure 78. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
) ǒIN ) R Ǔ2 ) ǒIN * ǒR ø RgǓǓ2 ) 4 kTR ) 4 kTǒR ø RgǓ
2
Ǹ
ǒe Ǔ
e
+
s
n
ni
where:
f
f
S
k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
Rf || Rg = Parallel resistance of Rf and Rg
To get the equivalent output noise of the amplifier, multiply the equivalent input noise density (eni) by the overall
amplifier gain (AV).
R
f
e
+ e
A
+ e
ǒ
1 )
Ǔ
(Noninverting Case)
no
ni
V
ni
R
g
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RF and RG), the input noise is reduced considerably because of the
parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the
source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a
root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively
ignored. This can greatly simplify the formula and make noise calculations much easier.
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This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
2
e
ȱ ȳ
ni
NF + 10log
ȧe ȧ
2
Rs
Ȳ ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate the noise figure as:
2
2
ȱ
ȳ
ȣ
ȡ
) ǒIN ) R
Ǔ
ǒe Ǔ
ȧ
ȧ
S
n
ȧ
ȧ
ȧ
Ȣ
Ȥ
ȧ
NF + 10log 1 )
ȧ
ȧ
ȧ
ȧ
4 kTR
S
ȧ
ȧ
PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE
Achieving optimum performance with high-frequency amplifier-like devices in the THS320x family requires careful
attention to board layout parasitic and external component types.
Recommendations that optimize performance include:
•
Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O
pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the board.
•
Minimize the distance (< 0.25” or < 6,35 mm) from the power-supply pins to high-frequency 0.1-µF and 100
pF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power-supply connections should always be decoupled with these
capacitors. Larger (6.8 µF or more) tantalum decoupling capacitors, effective at lower frequency, should also
be used on the main supply pins. These may be placed somewhat farther from the device and may be shared
among several devices in the same area of the printed circuit board (PCB). The primary goal is to minimize
the impedance seen in the differential-current return paths. For driving differential loads with the THS3202,
adding a capacitor between the power-supply pins improves 2nd order harmonic distortion performance. This
also minimizes the current loop formed by the differential drive.
•
Careful selection and placement of external components preserve the high-frequency performance of the
THS320x family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Again, keep their leads and PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Because the output pin and inverting input pins are
the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any,
as close as possible to the inverting input pins and output pins. Other network components, such as input
termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic
capacitance shunting the external resistors, excessively high resistor values can create significant time
constants that can degrade performance. Good axial metal-film or surface-mount resistors have
approximately 0.2 pF in shunt with the resistor. For resistor values greater than 2.0 kΩ, this parasitic
capacitance can add a pole and/or a zero that can affect circuit operation. Keep resistor values as low as
possible, consistent with load driving considerations.
•
Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils or 1,27 mm to 2,54 mm) should be used,
preferably with ground and power planes opened up around them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (less than 4 pF)
may not need an RS because the THS320x family is nominally compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated
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transmission line is acceptable, implement a matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques).
A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves
distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on
board material and trace dimensions, a matching series resistor into the trace from the output of the THS320x
is used as well as a terminating shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input
impedance of the destination device: this total effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not
preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device
is low, there is some signal attenuation due to the voltage divider formed by the series output into the
terminating impedance.
•
Socketing a high-speed part like the THS320x family is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the THS320x family devices directly onto the board.
PowerPAD DESIGN CONSIDERATIONS
The THS320x family is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 79(a) and Figure 79(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 79(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 79. Views of Thermally-Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
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PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown in Figure 80. There should be etch for the leads as
well as etch for the thermal pad.
68 Mils x 70 Mils
(Via diameter = 10 mils)
Figure 80. DGN PowerPAD PCB Etch and Via Pattern
2. Place five holes in the area of the thermal pad. These holes should be 10 mils (0,254 mm) in diameter. Keep
them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS320x family IC. These additional vias may be larger than the 10-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS320x family PowerPAD package should make their connection to the internal ground
plane with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
POWER DISSIPATION AND THERMAL CONSIDERATIONS
To maintain maximum output capabilities, the THS3202 does not incorporate automatic thermal shutoff
protection. The designer must take care to ensure that the design does not violate the absolute maximum
junction temperature of the device. Failure may result if the absolute maximum junction temperature of +150°C is
exceeded. For best performance, design for a maximum junction temperature of +125°C. Between +125°C and
+150°C, damage does not occur, but the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by the package and the PCB. Maximum power dissipation
for a given package can be calculated using the following formula.
Tmax * TA
qJA
PDmax
+
where:
P
is the maximum power dissipation in the amplifier (W).
Dmax
T
is the absolute maximum junction temperature (°C).
max
T is the ambient temperature (°C).
A
θ
θ
θ
= θ + θ
JA
JC
CA
JC CA
is the thermal coefficient from the silicon junctions to the case (°C/W).
is the thermal coefficient from the case to ambient air (°C/W).
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For systems where heat dissipation is more critical, the THS320x family of devices is offered in an MSOP-8 with
PowerPAD. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional
SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the
PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note number SLMA002. The following graph also illustrates the effect of
not soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious
heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.
4.0
T
J
= 125°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
θ
= 58.4°C/W
JA
θ
= 98°C/W
JA
θ
= 158°C/W
JA
−40 −20
0
20
40
60
80 100
T
A
− Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x3”
θ
θ
θ
= 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
= 98°C/W for 8-Pin SOIC High Test PCB (D)
= 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
JA
JA
JA
Figure 81. Maximum Power Dissipation vs Ambient Temperature
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important
to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult
to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide
visibility into a possible problem.
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS3202 has been internally compensated to maximize its bandwidth and
slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 82. A minimum value of 10 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
R
g
R
f
_
+
Input
10 Ω
Output
THS3202
C
LOAD
Figure 82. Driving a Capacitive Load
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GENERAL CONFIGURATIONS
A common error for the first-time CFB user is creating a unity-gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS3202, like
all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly
from the output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has
a very low impedance. This results in an unstable amplifier and should not be considered when using a
current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily implemented
on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an RC-filter at the
noninverting terminal of the operational amplifier, as shown in Figure 83.
RG
RF
1
f–3dB
=
2pR1C1
VO
VI
RF
1
-
=
1 +
VO
RG
1 + sR1C1
+
VI
R1
C1
Figure 83. Single-Pole Low-Pass Filter
If a multiple-pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of
their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. An example is shown in Figure 84.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
f
R
g
=
1
R
f
2 −
)
(
R
g
Q
Figure 84. 2-Pole Low-Pass Sallen-Key Filter
There are two simple ways to create an integrator with a CFB amplifier. The first, shown in Figure 85, adds a
resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and
the feedback impedance never drops below the resistor value. The second, shown in Figure 86, uses positive
feedback to create the integration. Caution is advised because oscillations can occur due to the positive
feedback.
C1
R
f
1
S )
ȡ
ȣ
Ȥ
R C1
V
R
R
g
f
O
f
+
ǒ Ǔ
−
+
ȧ
ȧ
V
I
V
R
S
g
I
V
O
Ȣ
THS3202
Figure 85. Inverting CFB Integrator
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For Stable Operation:
www.ti.com
R
g
R
f
R
R
R2
f
≥
R1 || R
−
+
g
A
THS320x
V
O
R
R
f
1 +
V
O
V
I
g
)
(
R1
R2
sR1C1
V
I
C1
R
A
Figure 86. Noninverting CFB Integrator
The THS3202 may also be employed as a very good video distribution amplifier. One characteristic of distribution
amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the
number of lines increase and the closed-loop gain increases. Be sure to use termination resistors throughout the
distribution system to minimize reflections and capacitive loading.
R
g
R
f
75-Ω Transmission Line
75 Ω
−
+
V
O1
V
I
THS3202
75 Ω
75 Ω
N Lines
75 Ω
V
ON
75 Ω
Figure 87. Video Distribution Amplifier Application
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THS3202
SLOS242F –SEPTEMBER 2002–REVISED JANUARY 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2009) to Revision F
Page
•
•
•
Updated document format to current standards ................................................................................................................... 1
Deleted lead temperature specification from Absolute Maximum Ratings table .................................................................. 2
Changed first sentence of third paragraph of Power Dissipation and Thermal Considerations section ............................ 23
Changes from Revision D (January 2009) to Revision E
Page
•
•
•
•
•
Deleted feature bullets relating to IMD3 and OIP3 at VCC = 15 V ........................................................................................ 1
Replaced figures ................................................................................................................................................................... 1
Changed text in first sentence of Description section ........................................................................................................... 1
Deleted harmonic distortion specifications in AC Performance subsection for VCC = 15 V .................................................. 6
Deleted harmonic distortion graphs for VCC = 15 V ............................................................................................................ 10
26
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Product Folder Link(s): THS3202
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
THS3202D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
3202
3202
BEV
BEV
BEV
BEP
BEP
BEP
BEP
THS3202DG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
75
80
Green (RoHS
& no Sb/Br)
THS3202DGK
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGN
DGN
DGN
DGN
Green (RoHS
& no Sb/Br)
THS3202DGKG4
THS3202DGKR
THS3202DGN
THS3202DGNG4
THS3202DGNR
THS3202DGNRG4
80
Green (RoHS
& no Sb/Br)
2500
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
MSOP-
PowerPAD
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
MSOP-
Green (RoHS
& no Sb/Br)
CU NIPDAU
PowerPAD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Mar-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS3202DGKR
THS3202DGNR
VSSOP
DGK
DGN
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
MSOP-
Power
PAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Mar-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS3202DGKR
THS3202DGNR
VSSOP
DGK
DGN
8
8
2500
2500
358.0
364.0
335.0
364.0
35.0
27.0
MSOP-PowerPAD
Pack Materials-Page 2
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