THS3217IRGVR [TI]
直流至 800MHz、差分转单端、DAC 输出放大器 | RGV | 16 | -40 to 85;
| 型号： | THS3217IRGVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 直流至 800MHz、差分转单端、DAC 输出放大器 | RGV | 16 | -40 to 85 放大器 |
| 文件： | 总75页 (文件大小：2853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
THS3217 直流至 800MHz、差分转单端、DAC 输出放大器
1 特性
3 说明
1
•
输入级：2V/V 的内部增益
THS3217 整合了连接互补电流输出数模转换器 (DAC)
时所需的关键信号链组件。此双级放大器系统极具灵活
性，可广泛应用于各类系统中以提供低失真、直流耦合
的差分转单端信号处理。输入级会对 DAC 电阻端进行
缓冲，并以 2V/V 的固定增益对信号进行差分至单端转
换。差分转单端输出可在外部直接使用，也可经 RLC
滤波器或衰减器连接至内部输出功率级 (OPS) 的输入
端。宽带、电流反馈输出功率级可在外部为全部引脚灵
活设置增益。
–
–
–
经缓冲的差分输入
单端低阻抗输出
全功率带宽：500MHz (2 VPP
)
•
•
输出级：可从外部配置增益
–
–
–
全功率带宽：500MHz (5 VPP
转换率：5000V/μs
)
单刀双掷 (SPDT) 输入开关/多路复用器
完整信号路径：输入级 + 输出级
–
–
–
–
二次谐波 (HD2)（20MHz，5VPP 接至 100Ω 负
载）：–60dBc
输出功率级同相输入内部连接有一个 2×1 多路复用器
(mux)，方便选择内部差分转单端级 (D2S) 输出或外部
输入。
三次谐波 (HD3)（20MHz，5VPP 接至 100Ω 负
载）：–75dBc
可选片上中间电压缓冲器提供了宽带、低输出阻抗电
源，可在单电源运行期间通过信号路径级提供偏置。此
功能可为运行电源电压最高为 15.8V 的 应用 提供非常
简单的偏置方法。此缓冲器接外部输入后可实现直流纠
错环路或简单的输出直流偏移功能。
10VPP 输出接至 100Ω 负载，使用
±6.5V 分离电源
12VPP 输出接至高容性负载，使用 15V 单电源
•
•
内部直流 (DC) 基准缓冲器，具有低阻抗输出
电源范围：
–
–
分离电源：±4V 至 ±7.9V
单电源：8V 至 15.8V
一款配套器件，THS3215，能够以更低的静态功率和
带宽提供相同的功能 特性 。THS3217 和 THS3215 支
持面向 AWG 应用的德州仪器 (TI) 新上市的高速
DAC，例如 DAC38J82。
2 应用
•
•
•
•
数模转换器 (DAC) 输出放大器
器件信息(1)
宽带任意波形发生器 (AWG) 输出驱动器
器件型号
THS3217
封装
VQFN (16)
封装尺寸（标称值）
前置驱动器接至 > 20VPP 输出放大器 (THS3091)
适用于压电式元件的单电源、高容性负载驱动器
4.00mm x 4.00mm
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
增益 = 5V/V，带可选外部滤波器的差分转单端线路驱动器
VREF
162 ꢀ
249 ꢀ
THS3217
100 ꢀ
50 ꢀ
Output Power
Stage (OPS)
x1
D2S
Stage
25 ꢀ
25 ꢀ
SPDT
Switch
DAC
Input
Buffers
50 ꢀ
+
Complementary
Output Current
Vi
+
Vo = 5 Vi
50 ꢀ
Line
250 ꢀ
500 ꢀ
x1
RLC Filter
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS766
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
目录
8.3 Harmonic Distortion Measurement ......................... 24
8.4 Noise Measurement................................................ 25
8.5 Output Impedance Measurement ........................... 25
8.6 Step-Response Measurement ................................ 25
8.7 Feedthrough Measurement..................................... 26
8.8 Midscale Buffer ROUT Versus CLOAD Measurement 28
Detailed Description ............................................ 29
9.1 Overview ................................................................. 29
9.2 Functional Block Diagram ....................................... 30
9.3 Feature Description................................................. 30
9.4 Device Functional Modes........................................ 46
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics: D2S.................................. 5
7.6 Electrical Characteristics: OPS ................................. 7
7.7 Electrical Characteristics: D2S + OPS...................... 9
9
10 Application and Implementation........................ 52
10.1 Application Information.......................................... 52
11 Power Supply Recommendations ..................... 61
11.1 Thermal Considerations........................................ 62
12 Layout................................................................... 63
12.1 Layout Guidelines ................................................. 63
12.2 Layout Example .................................................... 64
13 器件和文档支持 ..................................................... 65
13.1 器件支持................................................................ 65
13.2 文档支持................................................................ 65
13.3 社区资源................................................................ 65
13.4 商标....................................................................... 66
13.5 静电放电警告......................................................... 66
13.6 Glossary................................................................ 66
14 机械、封装和可订购信息....................................... 66
7.8 Electrical Characteristics: Midscale (DC) Reference
Buffer........................................................................ 10
7.9 Typical Characteristics: D2S + OPS....................... 11
7.10 Typical Characteristics: D2S Only ........................ 13
7.11 Typical Characteristics: OPS only......................... 15
7.12 Typical Characteristics: Midscale (DC) Reference
Buffer........................................................................ 19
7.13 Typical Characteristics: Switching Performance... 20
7.14 Typical Characteristics: Miscellaneous Performance
................................................................................. 21
8
Parameter Measurement Information ................ 22
8.1 Overview ................................................................. 22
8.2 Frequency Response Measurement....................... 23
4 修订历史记录
Changes from Revision A (February 2016) to Revision B
Page
•
•
•
•
•
Deleted open-loop transimpedance gain max value .............................................................................................................. 7
Deleted external to internal input offset voltage match min and max values......................................................................... 7
Changed external to internal input offset voltage match test level from A to C .................................................................... 7
Deleted dc output impedance min and max values ............................................................................................................. 10
Changed dc output impedance test level from A to C.......................................................................................................... 10
Changes from Original (February 2016) to Revision A
Page
•
已从“产品预览”更改为“量产数据” ............................................................................................................................................ 1
2
Copyright © 2016, Texas Instruments Incorporated
THS3217
www.ti.com.cn
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
5 Device Comparison Table
SMALL-SIGNAL
BANDWIDTH
0.1 VPP
LARGE-SIGNAL
BANDWIDTH
5VPP
TOTAL HARMONIC
QUIESCENT
CURRENT, Icc
(±6-V SUPPLIES)
CONTINUOUS
OUTPUT
CURRENT
PEAK
OUTPUT
CURRENT
DISTORTION
(5 VPP, RLOAD = 100 Ω,
20 MHz)
DEVICE
(AV = 5 V/V)(1)
(AV = 5 V/V)
THS3217
THS3215
800 MHz
350 MHz
500 MHz
250 MHz
55 mA
35 mA
–60 dBc
–50 dBc
110 mA
80 mA
175 mA
125 mA
(1) AV is the voltage gain.
6 Pin Configuration and Functions
RGV Package
16-Pin VQFN
Top View
1
2
3
4
12
VMID_IN
+IN
VINœ
VOUT
DISABLE
VIN+
11
10
9
œIN
(Thermal Pad)
PATHSEL
Table 1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VMID_IN
+IN
Input
Input
DC reference buffer input
Positive signal input to D2S
Negative signal input to D2S
2
3
–IN
Input
4
PATHSEL
–VCC2(1)
VO1
Input
Internal SPDT switch control: low selects the internal path, and high selects the external path
5
Power
Output
Power
Power
Input
Negative supply for input stage
D2S external output
6
7
GND
–VCC1(1)
Ground for control pins reference
Negative supply for output stage
External OPS noninverting input
Output power stage shutdown control: low enables the OPS, and high disables the OPS
OPS output
8
9
VIN+
10
11
12
13
14
15
16
DISABLE
VOUT
Input
Output
Input
VIN–
+VCC1(1)
OPS inverting input
Power
Input
Positive supply for output stage
DC offsetting input to D2S
VREF
VMID_OUT
+VCC2(1)
Output
Power
DC reference buffer output
Positive supply for input stage
Connect the thermal pad to GND for single-supply and split-supply operation. See Thermal
Considerations section for more information.
Thermal Pad
—
(1) Throughout this document +VCC refers to the voltage applied at the +VCC1 and +VCC2 pins, and –VCC is the voltage applied at the
–VCC1 and –VCC2 pins
Copyright © 2016, Texas Instruments Incorporated
3
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
16.2
UNIT
Supply, +VCC – (–VCC
)
Voltage
Input/output
(–VCC) – 0.5
(+VCC) + 0.5
±8
V
Differential input voltage (IN+ – IN–)
Continuous input current (IN+, IN–, VMID_IN, VIN+,
VIN–)(2)
Continuous output current(2)
±10
Current
mA
°C
±30
105
150
150
Operating, TA
–55
–45
–65
Temperature
Junction, TJ
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Long-term continuous current for electromigration limits.
7.2 ESD Ratings
VALUE
±1500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4
NOM
6
MAX
7.9
UNIT
+VCC
–VCC
TA
Positive supply voltage
V
V
Negative supply voltage
Operating free-air temperature
–4
–6
–7.9
85
–40
25
°C
7.4 Thermal Information
THS3217
THERMAL METRIC(1)
RGV (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
45
45
22
1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
22
4
RθJC(bot)
(1) Thermal impedance reported with backside thermal pad soldered to heat spreading plane. For more information about traditional and
new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
THS3217
www.ti.com.cn
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
7.5 Electrical Characteristics: D2S
at +VCC = 6.0 V, –VCC = –6.0 V, AV = 2 V/V, 25-Ω source impedance, input common-mode voltage (VIC) = 0.25 V, external
OPS input selected (PATHSEL ≥ 1.3 V), VREF = GND, RLOAD = 100 Ω, and TJ ≈ 25˚C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL
(1)
(2)
AC PERFORMANCE (Power Stage Disabled: DISABLE pin ≥ 1.3 V)
Small-signal bandwidth (SSBW)
Large-signal bandwidth (LSBW)
Bandwidth for 0.2-dB flatness
Slew rate(3)
VOUT = 250 mVPP, peaking < 1.0 dB
VOUT = 2 VPP
800
500
250
2500
6%
1.2
MHz
MHz
MHz
V/µs
C
C
C
C
C
C
C
C
C
C
C
C
VOUT = 2 VPP
VOUT = 4-V step
Over- and undershoot
Rise and fall time
Input tr = 1 ns, VOUT = 2-V step
Input tr = 1 ns, VOUT = 2-V step
Input tr = 1 ns, VOUT = 2-V step
ns
ns
Settling time to 0.1%
5
2nd-order harmonic distortion (HD2) f = 20 MHz, VOUT= 2 VPP
3rd-order harmonic distortion (HD3) f = 20 MHz, VOUT= 2 VPP
–68
–86
18
dBc
dBc
Output voltage noise
f > 200 kHz
f > 200 kHz
f = 20 MHz
nV/√Hz
pA/√Hz
Ω
Input current noise (each input)
Output impedance
2.0
0.8
(2)
DC PERFORMANCE
Differential to single-ended gain
±100-mV output
1.975
0.985
2.0
2.025
–24
V/V
A
B
Differential to single-ended gain drift TJ = –40°C to +125°C
–20
ppm/°C
Differential inputs = 0 V,
VREF input pin gain
1.0
1.015
V/V
A
VREF = ±100 mV
VREF input pin gain drift
Output offset voltage
TJ = –40°C to +125°C
TJ = 25°C
–70
±8
–95
35
ppm/°C
mV
B
A
B
B
B
A
B
B
B
A
B
B
B
–35
–43
TJ = 0°C to 70°C
TJ = –40°C to +125°C
TJ = –40°C to +125°C
TJ = 25°C
40
mV
–54
47
mV
Output offset voltage drift
Input bias current – each input(4)
Input bias current drift
Input offset current
-40
–115
±2
–190
4
µV/°C
µA
–4
TJ = 0°C to 70°C
TJ = –40°C to +125°C
TJ = –40°C to +125°C
TJ = 25°C
–4.2
–4.3
1
4.2
4.5
5
µA
µA
3
nA/°C
nA
–400
–700
–1180
–12
±50
400
940
1600
12
TJ = 0°C to 70°C
TJ = –40°C to +125°C
TJ = –40°C to +125°C
nA
nA
Input offset current drift
INPUTS(5)
±1
1.8
1.3
nA/°C
TJ = 25°C
1.9
2.0
1.4
1.5
V
V
V
V
A
B
A
B
Common-mode input negative
supply headroom
TJ = –40°C to +85°C
TJ = 25°C
Common-mode input positive supply
headroom
TJ = –40°C to +125°C
Common-mode rejection ratio
(CMRR)
–1 V ≤ VIC ≤ 3 V
47
55
dB
A
Input impedance differential mode
Input impedance common mode
VCM = 0 V
VCM = 0 V
50 || 2.4
90 || 2.4
kΩ || pF
kΩ || pF
C
C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA≈ TJ≈ 25°C; over temperature limits by
characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for
information. DC limits tested with no self-heating. Add internal self heating to TA for TJ.
(2) Output measured at pin 6.
(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f–3dB
.
(4) Currents out of pin treated as a positive polarity.
(5) Applies to input pins 2 (IN+) and 3 (IN–).
Copyright © 2016, Texas Instruments Incorporated
5
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
Electrical Characteristics: D2S (continued)
at +VCC = 6.0 V, –VCC = –6.0 V, AV = 2 V/V, 25-Ω source impedance, input common-mode voltage (VIC) = 0.25 V, external
OPS input selected (PATHSEL ≥ 1.3 V), VREF = GND, RLOAD = 100 Ω, and TJ ≈ 25˚C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL
(1)
OUTPUT(6)
TJ = 25°C
1.1
50
1.35
1.55
V
V
A
B
A
A
Output voltage headroom to either
supply
TJ = –40°C to +125°C
Output current drive
TJ = 25°C, ±1.16 VPP, RLOAD = 20 Ω
Load current = ±20 mA
70
mA
Ω
DC Output Impedance
0.2
0.45
POWER SUPPLY (D2S Stage + Midsupply Buffer Only; Output Power Stage Disabled: DISABLE pin ≥ 1.3 V)
Bipolar-supply operating range
Single-supply operating range
Supply current
±4.0
8
±6.0
12
±7.9
15.8
36
V
V
A
B
A
±6-V supplies
31
34
mA
Supply current temperature
coefficient
7
µA/°C
C
(6) Output measured at pin 6.
6
Copyright © 2016, Texas Instruments Incorporated
THS3217
www.ti.com.cn
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
7.6 Electrical Characteristics: OPS
at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, D2S input common-mode voltage (VIC) = 0.25 V, VREF = GND,
RF = 249 Ω(1), RG = 162 Ω, AV = 2.5 V/V, OPS RLOAD = 100 Ω, OPS enabled (DISABLE ≤ 0.7 V or floated), external OPS input
selected (PATHSEL ≥ 1.3 V), and TJ ≈ 25˚C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL
(2)
(3)
AC PERFORMANCE
Small-signal bandwidth (SSBW)
Large-signal bandwidth (LSBW)
Bandwidth for 0.2-dB flatness
Slew rate(4)
VOUT = 100 mVPP, peaking < 1.0 dB
VOUT = 5 VPP
950
500
110
5500
8%
1.1
MHz
MHz
MHz
V/µs
C
C
C
C
C
C
C
C
C
C
C
C
C
VOUT = 5 VPP
VOUT = 5-V step
Over- and undershoot
Rise and fall time
Input tr = 1 ns, VOUT = 5-V step
Input tr = 1 ns, VOUT = 5-V step
Input tr = 1 ns, VOUT = 5-V step
ns
ns
Settling time to 0.1%
5
2nd-order harmonic distortion (HD2) f = 20 MHz, VOUT= 5 VPP
3rd-order harmonic distortion (HD3) f = 20 MHz, VOUT= 5 VPP
–69
–73
3.2
dBc
dBc
Noninverting input voltage noise
Noninverting input current noise
Inverting input current noise
f > 200 kHz
f > 200 kHz
f > 200 kHz
f = 20 MHz
nV/√Hz
pA/√Hz
pA/√Hz
Ω
2.8
30
Closed-loop ac output impedance
0.40
(3)
DC PERFORMANCE
Open-loop transimpedance gain(1)
VOUT = ±1 V, RLOAD= 500-Ω
600
1200
kΩ
A
A
Closed-loop gain
0.1% external RF and RG resistors
2.495
2.515
2.53
V/V
INPUT
TJ = 25°C
–12
–20
–31
±2.5
12
17
24
mV
mV
mV
A
B
B
External input offset voltage (pin 9 to
pin12)
TJ = 0°C to 70°C
TJ = –40°C to +125°C
External input offset voltage drift (pin
9 to pin12)
TJ = –40°C to +125°C
-45
–115
±2.5
–190
µV/°C
B
TJ = 25°C
–12
–23
–35
12
18
27
mV
mV
mV
A
B
B
Internal input offset voltage (pin 6 to
pin 12)
TJ = 0°C to 70°C
TJ = –40°C to +125°C
Internal input offset voltage drift (pin
6 to pin 12)
TJ = –40°C to +125°C
TJ = 25°C
–70
–150
–235
µV/°C
mV
B
C
External to internal input offset
voltage match
±1.2
±5
TJ = 25°C
–5
–5.2
–5.6
15
15.4
15.9
µA
µA
µA
A
B
B
External noninverting input bias
current (pin 9)(5)
TJ = 0°C to 70°C
TJ = –40°C to +125°C
External noninverting input bias
current drift (pin 9)
TJ = –40°C to +125°C
–3
3
9
nA/°C
B
TJ = 25°C
–40
–51
±5
40
46
µA
µA
A
B
B
B
Inverting input bias current – either
input selected(5)
TJ = 0°C to 70°C
TJ = –40°C to +125°C
TJ = –40°C to +125°C
–65
56
µA
Inverting input bias current drift
–250
–120
–10
nA/°C
(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω RF and 162-
Ω RG, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at TA≈ TJ≈ 25°C; over temperature limits by
characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for
information. DC limits tested with no self-heating. Add internal self heating to TA for TJ.
(3) Output measured at pin 11.
(4) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f–3dB
.
(5) Currents out of pin treated as a positive polarity.
Copyright © 2016, Texas Instruments Incorporated
7
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
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Electrical Characteristics: OPS (continued)
at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, D2S input common-mode voltage (VIC) = 0.25 V, VREF = GND,
RF = 249 Ω(1), RG = 162 Ω, AV = 2.5 V/V, OPS RLOAD = 100 Ω, OPS enabled (DISABLE ≤ 0.7 V or floated), external OPS input
selected (PATHSEL ≥ 1.3 V), and TJ ≈ 25˚C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
TJ = 25°C
MIN
TYP
MAX
UNIT
LEVEL
(2)
Input headroom to either supply
2.6
49
3.0
V
A
A
Common-mode rejection ratio
(CMRR)
47
dB
Noninverting input resistance
Noninverting input capacitance
Open-loop inverting input impedance
OUTPUT(6)
17.6
18.5
3.3
42
22.4
1.4
kΩ
pF
Ω
A
C
C
Output voltage headroom to either
supply
RLOAD = 500 Ω
1.1
1.3
V
A
Linear output current
Peak output current
DC output impedance
Internal RF
TJ = 25°C, ±2.5 V into 26-Ω RLOAD
0-V output, RLOAD < 0.2 Ω
95
120
170
mA
mA
Ω
A
A
A
A
135
0-V output, load current = ±40 mA
0.05
18.5
0.10
22.4
17.6
0.7
kΩ
PATHSEL (Pin 4; Logic Reference = Pin 7 = GND)
Input low logic level
Internal path selected
0.9
0.9
V
V
A
A
A
A
A
A
C
C
C
A
C
Input high logic level
External input selected at VIN (pin 9)
1.3
+VCC
40
Input voltage range
–0.5
0
V
PATHSEL voltage when floated
Internal input from D2S selected
0-V input
20
mV
µA
0
4
Input pin bias current(7)
3.3-V input
–150
–250
µA
Input pin impedance
18 || 1.5
80
kΩ || pF
ns
Switching time
To 1% of final value
Both inputs at GND
± 2-V input
Input switching glitch
Deselected input dc isolation
Deselected input ac isolation
50
mV
dB
70
55
80
2 VPP, at 20-MHz input
65
dB
DISABLE (Pin 10; Logic Reference = Pin 7 = GND)
Input low logic level
0.7
0.9
0.9
V
V
A
A
B
A
A
A
C
C
A
C
Input high logic level
1.3
+VCC
40
Shutdown control voltage range
–0.5
0
V
Shutdown voltage when floated
Input pin bias current(7)
Output stage enabled
20
mV
µA
0-V input
0
4
3.3-V input
–150
–250
µA
Input pin impedance
18 || 1.5
200
kΩ || pF
ns
Switching time (turn on or off)
To 10% of final value
Shutdown dc isolation (either input) ±2-V input
Shutdown ac isolation (either input) 2 VPP at 20-MHz input
POWER SUPPLY
70
55
80
dB
65
dB
Bipolar-supply operating range
±4.0
8
±6.0
12
±7.9
15.8
24.5
3.0
V
A
B
A
C
A
Single-supply operating range
V
Supply current (OPS only)
±6-V supplies
18.5
2.0
200
21
mA
mA
µA
Disabled supply current in OPS
Logic reference current at pin 7(7)
±6-V supplies
2.4
280
Pins 4, 7, and 10 held at 0 V
380
(6) Output measured at pin 11.
(7) Currents out of pin treated as a positive polarity.
8
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7.7 Electrical Characteristics: D2S + OPS
at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, D2S input VIC = 0.25 V, Internal path selected to OPS
(PATHSEL ≤ 0.7 V or floated), VREF = GND, combined AV = 5 V/V, D2S RLOAD= 200 Ω, RF = 249 Ω(1), RG = 162 Ω (OPS AV =
2.5 V/V), OPS enabled (DISABLE ≤ 0.7 V or floated), OPS RLOAD = 100 Ω, and TJ ≈ 25˚C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL
(2)
AC PERFORMANCE(3)
Small-signal bandwidth (SSBW)
Large-signal bandwidth (LSBW)
Bandwidth for 0.2-dB flatness
Slew rate(4)
VOUT = 100 mVPP, peaking < 1.5 dB
VOUT = 5 VPP
800
500
100
5000
8%
1.1
MHz
MHz
MHz
V/µs
C
C
C
C
C
C
C
C
C
C
VOUT = 2 VPP
VOUT = 8-V step
Over- and undershoot
Rise and fall time
Input tr = 1 ns, VOUT = 5-V step
Input tr = 1 ns, VOUT = 5-V step
Input tr = 1 ns, VOUT = 5-V step
ns
ns
Settling time to 0.1%
7
2nd-order harmonic distortion (HD2) f = 20 MHz, VOUT= 5 VPP
3rd-order harmonic distortion (HD3) f = 20 MHz, VOUT= 5 VPP
–60
–75
45
dBc
dBc
Output voltage noise
f > 200 kHz
nV/√Hz
DC PERFORMANCE(3)
0.1% tolerance, dc, ±100-mV output
test
Total gain D2S to OPS output(1)
4.92
5.02
5.12
V/V
A
POWER SUPPLY (Combined D2S, OPS, and Midscale Reference Buffer)
Bipolar-supply operating range
±4.0
8
±6.0
12
±7.9
15.8
57
V
V
A
B
A
Single-supply operating range
Supply current
±6-V supplies
51
54
mA
Supply current temperature
coefficient
10
µA/°C
C
(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω RF and 162-
Ω RG, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at TA≈ TJ≈ 25°C; over temperature limits by
characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for
information.
(3) Output measured at pin 11.
(4) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f–3dB
.
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7.8 Electrical Characteristics: Midscale (DC) Reference Buffer
at +VCC = 6.0 V, –VCC = –6.0 V, RLOAD = 150 Ω at pin 15, and TJ ≈ 25˚C (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL
(1)
AC PERFORMANCE (Output measured at pin 15)
Small-signal bandwidth (SSBW)
Large-signal bandwidth (LSBW)
Slew rate(2)
VOUT = 100 mVPP
400
110
250
4.4
MHz
MHz
C
C
C
C
C
C
VOUT = 1 VPP
VOUT = 4-V step
f > 200 kHz
V/µs
Input voltage noise
nV/√Hz
pA/√Hz
Ω
Input current noise
f > 200 kHz
2.3
AC output impedance
f = 20 MHz
1.0
DC AND I/O PERFORMANCE (RS = 25 Ω, and output measured at pin 15, unless otherwise noted)
Buffer gain
VI = ±1 V, RLOAD = 200 Ω
TJ = –40°C to +125°C
Input floating, pin 1 open
.9985
0.999
–1.5
30
1.001
–2.0
70
V/V
ppm/°C
mV
A
B
A
Buffer gain drift
Output offset from midsupply
–120
–1.0
TJ = 25°C, input driven to 0 V from
0-Ω source
Output offset voltage
4.0
3
15
10
mV
A
B
TJ = –40°C to +125°C, input driven
to 0 V
Input offset voltage drift
–4
µV/°C
Input bias current(3)
TJ = 25°C
–15
–8
±1
–2
15
3
µA
A
B
Input bias current drift
TJ = –40°C to +125°C
nA/°C
Input/output headroom to either
supply
TJ = 25°C, gain change < 1%
1.1
1.4
V
A
C
Internal 50-kΩ divider resistors to
each supply
Input impedance
22 || 1.5
kΩ || pF
Linear output current into resistive
load
±2.25 V into 36 Ω
40
65
mA
A
C
DC output impedance
Load current = ±30 mA
0.21
Ω
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA≈ TJ≈ 25°C; over temperature limits by
characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for
information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VPEAK / √2) × 2π × f–3dB
.
(3) Currents out of pin treated as a positive polarity.
10
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7.9 Typical Characteristics: D2S + OPS
at +VCC = 6 V, –VCC = –6 V, 25-Ω D2S source impedance , VIC = 0.25 V, Internal path selected (PATHSEL = GND), VREF
=
GND, D2S RLOAD = 200 Ω at pin 6, RF = 249 Ω, RG = 162 Ω, OPS AV = 2.5 V/V, OPS On (DISABLE = GND), and OPS RLOAD
= 100 Ω at pin 11 (unless otherwise noted)
17
15
13
11
9
4
3
500 mVPP
5 VPP
2
1
0
7
-1
-2
-3
-4
0.1 Vpp
0.5 Vpp
1 Vpp
2 Vpp
4 Vpp
5
3
5 Vpp
1
10M
100M
1G
Time (20ns/div.)
Frequency (Hz)
D001
D002
Figure 1. Frequency Response vs Output Voltage
Figure 2. Small and Large Signal Step Response
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
2 VPP
5 VPP
8 VPP
2 VPP
5 VPP
8 VPP
-100
-110
1M
10M
100M
1M
10M
100M
Test Frequency (Hz)
Test Frequency (Hz)
D003
D004
Figure 3. HD2 vs Frequency
Figure 4. HD3 vs Frequency
5.04
5.035
5.03
5.025
5.02
5.015
5.01
5.005
5
100
10
1
4.995
4.99
-55
-35
-15
5
25
45
65
85
105 125
100
1k
10k
100k
1M
10M
100M
Junction Temperature (èC)
Frequency (Hz)
D005
D006
26 units shown
25-Ω source impedance on each D2S input
Figure 5. Gain vs Temperature
Figure 6. Input Referred Differential Noise
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Typical Characteristics: D2S + OPS (continued)
at +VCC = 6 V, –VCC = –6 V, 25-Ω D2S source impedance , VIC = 0.25 V, Internal path selected (PATHSEL = GND), VREF
=
GND, D2S RLOAD = 200 Ω at pin 6, RF = 249 Ω, RG = 162 Ω, OPS AV = 2.5 V/V, OPS On (DISABLE = GND), and OPS RLOAD
= 100 Ω at pin 11 (unless otherwise noted)
4
4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-7
-1
-2
-3
-4
-5
-6
-7
3 V/V
5 V/V
10 V/V
20 V/V
5V/V
10V/V
20V/V
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D007
D008
VOUT = 500 mVPP, see Table 2
VOUT = 5 VPP, see Table 2
Figure 7. Small-Signal Frequency Response vs Gain
Figure 8. Large-Signal Frequency Response vs Gain
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
-100
3 V/V
5 V/V
10 V/V
20 V/V
3 V/V
5 V/V
10 V/V
20 V/V
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D009
D010
VOUT = 5 VPP
VOUT = 5 VPP
Figure 9. HD2 vs Gain
Figure 10. HD3 vs Gain
-40
-50
-40
-50
1 VPP
2 VPP
5 VPP
8 VPP
-60
-60
-70
-70
-80
-80
1 VPP
2 VPP
5 VPP
8 VPP
-90
-90
-100
-100
8
9
10
11
12
13
14
15
16
8
9
10
11
12
13
14
15
16
Total Balanced Supply Voltage (V)
Total Balanced Supply Voltage (V)
D011
D012
Test frequency = 20 MHz
Test frequency = 20 MHz
Figure 11. HD2 vs Supply Voltage
Figure 12. HD3 vs Supply Voltage
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7.10 Typical Characteristics: D2S Only
at +VCC = 6.0 V, –VCC = –6.0 V, fixed gain of 2 V/V, 25-Ω D2S source impedance, VIC = 0.25 V, external path selected
(PATHSEL = +VCC), VREF = GND, and D2S RLOAD = 100 Ω at pin 6 (unless otherwise noted)
7
6
7
6
5
5
4
4
3
3
2
2
VCM = -1 V
VCM = 0 V
VCM = 0.25 V
VCM = 1 V
VCM = 2 V
VCM = 3 V
1
1
500 W
200 W
100 W
50 W
0
0
-1
-1
-2
-2
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D013
D014
VOUT = 250 mVPP
VOUT = 2 VPP
Figure 14. Frequency Response vs Load Resistance
Figure 13. Frequency Response vs Input Common-Mode
Voltage
-20
-30
-40
-50
-60
-70
-20
-30
-40
-50
-60
-70
-80
-90
-100
1 VPP
2 VPP
4 VPP
-80
1 VPP
2 VPP
4 VPP
-90
-100
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D015
D016
RLOAD = 200 Ω
RLOAD = 200 Ω
Figure 15. HD2 vs Output Voltage
Figure 16. HD3 vs Output Voltage
100
10
1
60
55
50
45
40
35
30
25
RS = 0 W
RS = 25 W
RS = 100 W
RS = 1 kW
VCM = -1 V
VCM = 0 V
VCM = 0.25 V
VCM = 1 V
VCM = 2 V
VCM = 3 V
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
1M
10M
Frequency (Hz)
100M
D018
D017
Figure 18. Differential Input Noise vs Source Impedance
Figure 17. Common-Mode Rejection Ratio vs Input
Common-Mode Voltage
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Typical Characteristics: D2S Only (continued)
at +VCC = 6.0 V, –VCC = –6.0 V, fixed gain of 2 V/V, 25-Ω D2S source impedance, VIC = 0.25 V, external path selected
(PATHSEL = +VCC), VREF = GND, and D2S RLOAD = 100 Ω at pin 6 (unless otherwise noted)
20
15
10
5
10
7
5
3
2
0
-5
1
0.7
0.5
-10
-15
-20
-25
-30
0.3
0.2
ê4 V
ê5 V
ê6 V
ê7.5 V
0.1
-55
-35
-15
5
25
45
65
85
105 125
1M
10M
100M
Junction Temperature (èC)
Frequency (Hz)
D019
D020
30 units shown
Figure 19. Output DC Offset Voltage vs Die Temperature
Figure 20. Output Impedance vs Supply Voltage
1.2
1.1
1
100 W
200 W
500 W
1
100 W
200 W
500 W
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.9
0.8
-1.2
20 30 40 50 60 70 80 90 100 110 120 130 140
Time (ns)
Time (1 ns/div)
D021
D022
±1-V output pulse
±1-V output pulse
Figure 21. Large-Signal Step Response vs Load Resistance
Figure 22. Large-Signal Pulse Settling Response vs Load
Resistance
1
0
70
65
60
55
50
-1
-2
45
VCM = -1 V, PSRR+
VCM = -1 V, PSRR-
-3
0.1 Vpp
40
35
30
0.25 Vpp
0.5 Vpp
1 Vpp
VCM = 0 V, PSRR+
VCM = 0 V, PSRR-
VCM = 3 V, PSRR+
VCM = 3 V, PSRR-
-4
2 Vpp
-5
1M
10M
100M
Frequency (Hz)
1G
10k
100k
1M
10M
Frequency (Hz)
D023
D024
25-Ω D2S source impedance on each input
Figure 23. VREF Input Pin Frequency Response
Figure 24. Simulated Power-Supply Rejection Ratio vs Input
Common-Mode Voltage
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7.11 Typical Characteristics: OPS only
at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, VREF = GND, RF = 249 Ω, RG = 162 Ω, OPS AV = 2.5V/V, OPS
RLOAD = 100 Ω at pin 11, OPS enabled (DISABLE = GND), and external input path selected (PATHSEL = +VCC) (unless
otherwise noted)
6
4
6
4
AV = 1.5 V/V
AV = 2.5 V/V
AV = 5 V/V
AV = -1 V/V
AV = -2.5 V/V
AV = -5 V/V
AV = -10 V/V
AV = 10 V/V
2
2
0
0
-2
-4
-6
-2
-4
-6
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D025
D026
VOUT = 100 mVPP, see Table 2 for RF values vs gain
VOUT = 100 mVPP, see Table 4 for RF values vs gain
Figure 25. Frequency Response vs Noninverting Gain
Figure 26. Frequency Response vs Inverting Gain
10
10
8
8
6
6
4
4
2
2
0.5 VPP
2 VPP
5 VPP
6 VPP
0.5 VPP
2 VPP
5 VPP
6 VPP
0
0
-2
-2
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D027
D028
AV = –2.5 V/V, see Table 4 for RF value
Figure 27. Noninverting Response vs Output Voltage
Figure 28. Inverting Response vs Output Voltage
3.5
3
2
500 mVPP
5 VPP
500 mVPP
5 VPP
2.5
1.5
1
0.5
0
-0.5
-1.5
-2.5
-3.5
-1
-2
-3
Time (20ns/div.)
Time (20ns/div.)
D029
D030
AV = –2.5 V/V, see Table 4 for RF value
Figure 29. Noninverting Step Response
Figure 30. Inverting Step Response
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Typical Characteristics: OPS only (continued)
at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, VREF = GND, RF = 249 Ω, RG = 162 Ω, OPS AV = 2.5V/V, OPS
RLOAD = 100 Ω at pin 11, OPS enabled (DISABLE = GND), and external input path selected (PATHSEL = +VCC) (unless
otherwise noted)
-20
-20
1 VPP
2 VPP
5 VPP
8 VPP
1 VPP
2 VPP
5 VPP
8 VPP
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D031
D032
Figure 31. HD2 vs Output Voltage
Figure 32. HD3 vs Output Voltage
-35
-45
-55
-65
-75
-85
-95
-105
-35
-45
-55
-65
-75
-85
-95
-105
100 W
200 W
500 W
100 W
200 W
500 W
Frequency (Hz)
Frequency (Hz)
D033
D034
VOUT = 5 VPP
VOUT = 5 VPP
Figure 33. HD2 vs Load Resistance
Figure 34. HD3 vs Load Resistance
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
-100
±4 V
±5 V
±6 V
±7.5 V
±4 V
±5 V
±6 V
±7.5 V
Frequency (Hz)
Frequency (Hz)
D035
D036
VOUT = 5 VPP
VOUT = 5 VPP
Figure 35. HD2 vs Supply Voltage
Figure 36. HD3 vs Supply Voltage
16
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Typical Characteristics: OPS only (continued)
at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, VREF = GND, RF = 249 Ω, RG = 162 Ω, OPS AV = 2.5V/V, OPS
RLOAD = 100 Ω at pin 11, OPS enabled (DISABLE = GND), and external input path selected (PATHSEL = +VCC) (unless
otherwise noted)
-30
-40
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-80
-90
0.25 VPP
1 VPP
2.5 VPP
4 VPP
0.25 VPP
1 VPP
2.5 VPP
4 VPP
1
10
100
1
10
100
Center Frequency (MHz)
Center Frequency (MHz)
D037
D038
±100-kHz tone separation, output voltage for each tone
±100-kHz tone separation, output voltage for each tone
Figure 37. IMD2 vs Output Voltage
Figure 38. IMD3 vs Output Voltage
1000
5
4
Voltage Noise
Noninverting Current Noise
Inverting Current Noise
3
2
100
10
1
1
0
-1
-2
-3
0.1 Vpp
-4
0.25 Vpp
-5
100
1k
10k
100k
1M
10M
10
100
1k
Frequency (Hz)
Load Resistance (W)
D039
D040
Output swing with better than 0.1% linearity
Figure 39. Input-Referred Spot Noise vs Frequency
Figure 40. Linear Output Swing vs Load Resistance
21
20.5
20
5
4
VIN+ Input
VOUT
3
2
1
19.5
19
0
-1
-2
-3
-4
-5
18.5
18
-55
-35
-15
5
25
45
65
85
105 125
0
1
2
3
4
5
Junction Temperature (0C)
Time (ms)
D041
D042
30 units shown
±4.5-V input triangular wave, OPS AV = 2.5 V/V
Figure 41. Quiescent Supply Current vs Temperature
Figure 42. Output Overdrive Response
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Typical Characteristics: OPS only (continued)
at +VCC = 6.0 V, –VCC = –6.0 V, 25-Ω D2S source impedance, VREF = GND, RF = 249 Ω, RG = 162 Ω, OPS AV = 2.5V/V, OPS
RLOAD = 100 Ω at pin 11, OPS enabled (DISABLE = GND), and external input path selected (PATHSEL = +VCC) (unless
otherwise noted)
40
35
30
25
20
15
10
5
2
AV = 2.5 V/V
AV = 5 V/V
AV = 10 V/V
1
0
-1
-2
-3
-4
-5
-6
0 pF
4.7 pF
10 pF
22 pF
47 pF
100 pF
220 pF
470 pF
0
1
10
100
1k
1M
10M
100M
Frequency (Hz)
1G
Load Capacitance (pF)
D043
D044
See Table 7 for RF values vs OPS gain
VOUT = 500 mVPP, see Figure 43 for RS value
Figure 43. Series Output Resistance vs Load Capacitance
Figure 44. Frequency Response vs Load Capacitance
-20
-30
50 pF
100 pF
200 pF
300 pF
50 pF
-40
-50
100 pF
200 pF
300 pF
-30
-40
-60
-50
-60
-70
-80
-90
-70
-80
-90
-100
-110
-120
1M
10M
20M
1M
10M
20M
Frequency (Hz)
Frequency (Hz)
D045
D046
RF = 205 Ω, AV = 5 V/V, VOUT = 10 VPP, see Figure 43 for RS
RF = 205 Ω, AV = 5 V/V, VOUT = 10 VPP, see Figure 43 for RS
value
value
Figure 45. HD2 vs Load Capacitance
Figure 46. HD3 vs Load Capacitance
8
8
2 VPP
2 VPP
10 VPP
10 VPP
6
4
6
4
2
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
Time (25 ns/div.)
Time (25 ns/div)
D047
D048
CLOAD = 200 pF, RF = 205 Ω, AV = 5 V/V, see Figure 43 for RS
CLOAD = 300 pF, RF = 205 Ω, AV = 5 V/V, see Figure 43 for RS
value
value.
Figure 47. Pulse Response
Figure 48. Pulse Response
18
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7.12 Typical Characteristics: Midscale (DC) Reference Buffer
at +VCC = 6.0 V, –VCC = –6.0 V, RLOAD = 150 Ω, and TA ≈ 25˚C (unless otherwise noted)
1
0
0.6
0.4
0.2
0
100 mVPP
1 VPP
-1
-2
-3
-4
-5
-6
-7
-8
-0.2
-0.4
-0.6
0.1VPP
1.0VPP
1M
10M
Frequency (Hz)
100M
700M
Time (20 ns/div)
D049
D050
Figure 49. Frequency Response vs Output Voltage
Figure 50. Step Response
10
60
50
40
30
20
10
0
IO = -20 mA
IO = 0 mA
IO = 20 mA
GND I/P, ILOAD= 0 mA
GND I/P, ILOAD= -20 mA
GND I/P, ILOAD= 20 mA
Float I/P, ILOAD= 0 mA
Float I/P, ILOAD= -20 mA
Float I/P, ILOAD= 20 mA
1
0.1
-10
-40
-20
0
20
40
60
80
100
120
Frequency (Hz)
Junction Temperature (èC)
D051
D052
Figure 51. Buffer Output Impedance vs Load Current
Figure 52. Buffer Output Offset vs Load Current (ILOAD)
5
3
4.5
4
0
3.5
3
-3
2.5
2
-6
1.5
1
No Cap
1 nF
-9
10 nF
100 nF
0.5
0
-12
1M
1n
10n
100n
10M
Frequency (Hz)
100M
500M
Load Capacitance (F)
D053
D054
RLOAD = 150 Ω in parallel with CLOAD, see the Midscale Buffer
ROUT Versus CLOAD Measurement section for circuit setup
VOUT = 100 mVPP, RLOAD = 150 Ω in parallel with CLOAD, see
Midscale Buffer ROUT Versus CLOAD Measurement for circuit setup
Figure 53. Series Output Resistance vs Capacitive Load
Figure 54. Frequency Response vs Capacitive Load
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7.13 Typical Characteristics: Switching Performance
at +VCC = 6 V, –VCC = –6 V, 25-Ω D2S source impedance , VIC = 0.25 V, Internal path selected (PATHSEL = GND), VREF
=
GND, D2S RLOAD = 200 Ω at pin 6, RF = 249 Ω, RG = 162 Ω, OPS On (DISABLE = GND), and OPS RLOAD = 100 Ω at pin 11
(unless otherwise noted)
3.5
3
3.5
3
PATHSEL In
OPS Out
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
DISABLE In
OPS Out
-0.5
-1.5
Time (100 ns/div.)
Time (250 ns/div.)
D055
D056
D2S Inputs: IN+ = IN– = GND, OPS input: VIN+ = 1 V
PATHSEL = high, OPS input: VIN+ = 1 VPP , 10-MHz sine wave
Figure 55. PATHSEL Switching Time
Figure 56. OPS Enable and Disable Time
-20
-20
Ext Path, OPS AV = 2.5 V/V
Ext Path, OPS AV = 10 V/V
Int Path, OPS AV = 2.5 V/V
Int Path, OPS AV = 10 V/V
Ext Path, OPS AV = 2.5 V/V
Int Path, OPS AV = 2.5 V/V
-30
-40
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-80
-90
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D057
D058
Figure 57. OPS Forward Feedthrough in Disable
Figure 58. OPS Reverse Feedthrough in Disable
2.5
2
3
2.5
2
DISABLE In
ê5-V supply
ê6-V supply
ê7.5-V supply
1.5
1
1.5
1
0.5
0
0.5
0
PATHSEL In
ê5-V supply
ê6-V supply
ê7.5-V supply
-0.5
-0.5
Time (1 ms/div.)
Time (1 ms/div.)
D059
D060
D2S inputs: IN+ = IN– = GND, OPS input: VIN+ = 1 V
PATHSEL = high, OPS input: VIN+ = 1 V
Figure 59. PATHSEL Switching Threshold vs Power Supply
Figure 60. OPS Shutdown Threshold vs Power Supply
20
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7.14 Typical Characteristics: Miscellaneous Performance
at +VCC = 6 V, –VCC = –6 V, 50-Ω D2S source impedance , VIC = 0.25 V, internal path selected (PATHSEL = GND), VREF
=
GND, D2S RLOAD = 100 Ω at pin 6, RF = 249 Ω, RG = 162 Ω, OPS on (DISABLE = GND), and OPS RLOAD = 100 Ω at pin 11
(unless otherwise noted)
2
1.995
1.99
12
10
8
10
7
1.985
1.98
6
4
3
3
2
2
1.975
2
1
1
1
0
0
0
1.97
-55
-35
-15
5
25
45
65
85
105 125
Junction Temperature (0C)
D062
D061
Gain Drift (ppm/èC)
30 units shown
30 units from –40°C to +125°C
Figure 61. D2S Gain Over Temperature
Figure 62. D2S Gain Drift Histogram
2.522
2.52
7
6
5
4
3
2
1
0
6
6
5
5
2.518
2.516
2.514
2.512
2.51
3
1
1
1
1
0
0
-55
-35
-15
5
25
45
65
85
105 125
Junction Temperature (0C)
D063
D064
Gain Drift (ppm/èC)
29 units shown
29 units from –40°C to +125°C
Figure 63. OPS Gain Over Temperature
Figure 64. OPS Gain Drift Histogram
0.99955
0.99945
0.99935
0.99925
0.99915
0.99905
0.99895
8
7
6
5
4
3
2
1
0
7
7
6
5
3
1
1
0
0
0
-55
-35
-15
5
25
45
65
85
105 125
Junction Temperature (0C)
D065
D066
Gain Drift (ppm/èC)
30 units shown
30 units from –40°C to +125°C
Figure 66. Midscale Buffer Gain Drift Histograms
Figure 65. Midscale Buffer Gain Over Temperature
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8 Parameter Measurement Information
8.1 Overview
The THS3217 comprises three blocks of high-performance amplifiers. Each block requires both frequency-
response and step-response characterization. The midscale buffer and OPS use standard, single-ended I/O test
methods with network analyzers, pulse generators, and high-speed oscilloscopes. The differential to single-
ended input stage (D2S) requires a wideband differential source for test purposes. All ac characterization tests
were performed using the THS3217 evaluation module (EVM), the THS3217EVM, which offers many
configuration options. For most of the D2S-only tests, the OPS was disabled. Figure 67 shows a typical
configuration for an ac frequency-response test of the D2S.
The THS3217EVM includes unpopulated, optional, passive elements at the D2S inputs to implement a
differential filter. These elements were not used in the D2S characterization and the two input pins were
terminated to ground through 49.9-Ω resistors. DC test points are provided through 10-kΩ or 20-kΩ resistors on
all THS3217 nodes. Figure 67 also shows the output network used to emulate a 200-Ω load resistance (RLOAD
)
while presenting a 50-Ω source back to the D2S output pin. The R3 (= 169 Ω) and R4 (= 73.2 Ω) resistors
combine with the 50-Ω network analyzer input impedance to present a 200-Ω load at VO1 (pin 6), The
impedance presented from the input of the network analyzer back to the D2S output (VO1, pin 6) is 50-Ω. The
16.5-dB insertion loss intrinsic to this dc-coupled impedance network is removed from the characterization
curves. The VREF pin was connected to GND for all the tests.
VREF
14
TP_IN+
R5
10 kꢀ
TP_VO1
R7
100 ꢀ
50 ꢀ
J1
Vin+
+IN
2
10 kꢀ
x1
x1
R1
J3
50 ꢀ
R3
169 ꢀ
D2S_OUT
50-ꢀ
Measurement
System
From LMH3401
EVM
+
6
VO1
50 ꢀ
R2
73.2 ꢀ
R4
50 ꢀ
250 ꢀ
500 ꢀ
3
œIN
J2
Vin-
10 kꢀ
R6
TP_IN-
Figure 67. D2S Input and Output Interface Showing 50-Ω Differential Input, 200-Ω RLOAD at VO1
22
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8.2 Frequency Response Measurement
For D2S and full-signal path (D2S + OPS) characterization, the LMH3401, a very wideband, dc-coupled, single-
ended to differential amplifier was used. The LMH3401EVM was used as an interface between a single-ended
source and the differential input required by the D2S, shown in Figure 68. The LMH3401 provides an input
impedance of 50 Ω, and converts a single-ended input to a differential output driving through 50-Ω outputs on
each side to what is a 50-Ω termination at each input of the THS3217 D2S.
Network
Analyzer
GND
Port 1
50 ꢀ
Port 2
50 ꢀ
LMH3401 EVM
THS3217 EVM
IN+
+
_
+
+
œ
œ
IN-
Figure 68. Frequency-Response Measurement: D2S and Full-Path (D2S + OPS) Circuit Configurations
The LMH3401 provides 7-GHz bandwidth with 0.1-dB flatness through 700 MHz. From the single-ended matched
input (using active match through an internal 12.5-Ω resistor), the LMH3401 produces a differential output with
16-dB gain to the internal output pins. Building out to a 50-Ω source by adding external 40.2-Ω resistors on both
differential outputs in series with the internal 10-Ω resistor, results in a net gain of 10 dB to the matched 50-Ω
load on the THS3217EVM.
The maximum output swing test for the D2S stage is 4 VPP (see Figure 15 and Figure 16). With a fixed gain of 2
V/V, the tests in Figure 15 and Figure 16 require a 2-VPP differential input. In order to achieve the 2-VPP
differential swing at the D2S inputs, the LMH3401 internal outputs must drive a 4-VPP differential signal around
the VOCM of the LMH3401. This LMH3401 single-to-differential preamplifier is normally operated with ±2.5-V
supplies, and VOCM set to ground. Under these conditions, the LMH3401 supports ±1.4 V on each internal output
pin; well beyond the maximum required for THS3217 D2S characterization of ±1 V.
The output of the LMH3401EVM connects directly to the Vin+ (J1) and Vin- (J2) SMA connectors on the
THS3217EVM, as shown in Figure 67. The physical spacing of the SMA connectors has been set to line up for a
direct (no cabling) connection between the two different EVMs using SMA barrels. For THS3217 designs that
must be evaluated before any DAC connection, consider using the LMH3401EVM as a gain of 10 dB, single-to-
differential interface to the inputs of the D2S stage. This setup allows single-ended sources to generate
differential output signals through the combined LMH3401EVM to THS3217EVM configuration. The D2S, small-
signal, frequency-response curves over input common-mode voltage (see Figure 13) were generated by
adjusting the LMH3401 voltage supplies and maintaining VOCM at midsupply to preserve input headroom on the
LMH3401. In order to make single-ended, frequency-response measurements, the configuration shown in
Figure 69 was used.
Network
Analyzer
GND
Port 1
50 ꢀ
Port 2
50 ꢀ
THS3217 EVM
+
œ
Figure 69. Frequency-Response Measurement: OPS Inverting and Noninverting, Midscale Buffer, and
VREF Circuit Configurations
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8.3 Harmonic Distortion Measurement
The distortion plots for all stages used a filtered high-frequency function generator to generate a very low-
distortion input signal. The LMH3401 interface was used when testing the D2S and the full-signal path
(D2S+OPS) harmonic distortion performance. Running the filtered signal through the LMH3401, as shown in
Figure 70, provided adequate input signal purity because of the approximately –100-dBc harmonic distortion
performance through 100 MHz. In order to test the harmonic-distortion performance of the OPS and midscale
buffer, the configuration shown in Figure 71 was used.
Function
Generator
LMH3401 EVM
THS3217 EVM
<
>
-
Low Pass Filter
IN+
+
Output
50 ꢀ
_
+
+
œ
œ
IN-
I Input
Q Input
Spectrum
Analyzer
High-Pass Filter
RF
INPUT
Ext Trig
20dB
Attenuator
50 ꢀ
Figure 70. Harmonic-Distortion Measurement: D2S and Full-Path (D2S + OPS) Circuit Configurations
Function
Generator
THS3217 EVM
<
>
-
Low Pass Filter
Output
50 ꢀ
+
œ
I Input
Q Input
Spectrum
Analyzer
High-Pass Filter
RF
INPUT
Ext Trig
20dB
Attenuator
50 ꢀ
Figure 71. Harmonic-Distortion Measurement: OPS Inverting and Noninverting and Midscale Buffer
Circuit Configurations
24
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8.4 Noise Measurement
All the noise measurements were made using a very low-noise, high-gain bandwidth LMH6629 as a low-noise
preamplifier to boost the output noise from the THS3217 before measurement on a spectrum analyzer, as shown
in Figure 72. The 0.69-nV/√Hz input-voltage noise specification of the LMH6629 provides flat gain of 20 V/V
through 100 MHz with its ultrahigh, 6.3-GHz gain bandwidth product. The D2S and OPS noise was measured
with the common-mode voltage at GND.
I Input
Q Input
Ext Trig
Spectrum
Analyzer
RF
INPUT
50 ꢀ
LMH6629
THS3217 EVM
Noise Preamp
+
+
œ
œ
Figure 72. Noise Measurement Using LMH6629 Preamplifier
8.5 Output Impedance Measurement
Output impedance measurement for the three stages under different conditions were performed as a small-signal
measurement calibrated to the device pins using an impedance analyzer. Calibrating the measurement to the
device pins removes the THS3217EVM parasitic resistance, inductance, and capacitance from the measured
data.
8.6 Step-Response Measurement
Generating a clean, fast, differential-input step for time-domain testing presents a considerable challenge. A
multichannel pulse generator with adjustable rise and fall times was used to generate the differential pulse to
drive D2S inputs in Figure 21. A high-speed scope was used to digitize the pulse response.
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8.7 Feedthrough Measurement
In order to test the forward feedthrough performance of the OPS in the disabled state, the circuit shown in
Figure 73 was used. The PATHSEL pin was driven low to select the internal path between the D2S and OPS. A
100-mVPP, swept-frequency, sinusoidal signal was applied at the VREF pin and the output signal was measured
at the OPS output pin (VOUT). The transfer function from VREF to the output of the D2S at VO1 has a gain of 0
dB, as shown in Figure 23. The results shown in Figure 57 account for the 6-dB loss due to the doubly-
terminated OPS output, and therefore report the forward feedthrough between VOUT and VO1 at different OPS
gains. The D2S inputs were grounded through 50-Ω resistors for this test.
Network
Analyzer
GND
Port 1
50 ꢀ
Port 2
50 ꢀ
75 ꢀ
VREF
14
16
15
13
RG
50 kꢀ
12
11
100 ꢀ
1
2
x1
18.5 kꢀ
RF
50 kꢀ
50 ꢀ
49.9 ꢀ
x1
+
VOUT
49.9 ꢀ
49.9 ꢀ
+
250 ꢀ
500 ꢀ
DISABLE = High
3
4
x1
10
18.5 kꢀ
9
PATHSEL = Low
49.9 ꢀ
6
7
8
5
200 ꢀ
Figure 73. Forward-Feedthrough Test Circuit
26
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Feedthrough Measurement (continued)
In order to test the reverse feedthrough performance of the OPS in its disabled state, the circuit shown in
Figure 74 was used. The PATHSEL pin was driven high to select the external path to the OPS noninverting pin,
VIN+. A 100-mVPP, swept-frequency, sinusoidal signal was applied at the VIN+ pin and the output signal was
measured at the D2S output pin (VO1). The results shown in Figure 58 account for the 16.5-dB loss due to the
D2S termination, and the test reports the reverse feedthrough between the VO1 and VIN+ pins. The D2S inputs
were grounded through 50-Ω resistors for this test.
16
15
14
13
162 Ω
50 kꢀ
12
11
100 ꢀ
1
2
x1
18.5 kꢀ
249 Ω
50 kꢀ
50 ꢀ
x1
+
49.9 ꢀ
100 ꢀ
+
250 ꢀ
500 ꢀ
DISABLE = High
3
4
x1
10
18.5 kꢀ
49.9 ꢀ
VIN+
Network
Analyzer
9
PATHSEL = High
49.9 ꢀ
GND
Port 1
50 ꢀ
Port 2
50 ꢀ
6
7
8
5
VO1
169 ꢀ
73.2 ꢀ
Figure 74. Reverse-Feedthrough Test Circuit
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8.8 Midscale Buffer ROUT Versus CLOAD Measurement
For the tests in Figure 53 and Figure 54, the circuit shown in Figure 75 was used. The 150-Ω load circuit
configured as shown, provides a 50-Ω path from the network analyzer back to the output of the buffer. As shown
in Figure 75, place ROUT below the load capacitor to improve the phase margin for the closed-loop buffer output,
while adding 0-Ω dc impedance into the line connected to the VREF pin.
Network
Analyzer
GND
Port 1
50 ꢀ
Port 2
50 ꢀ
+VCC2
16
150Ω
Load
50 kꢀ
VMID_OUT
15
VMID_IN
1
118 ꢀ
x1
CLOAD
88.7 ꢀ
49.9 ꢀ
50 kꢀ
ROUT
5
-VCC2
Figure 75. RS Versus CLOAD Measurement Circuit
28
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9 Detailed Description
9.1 Overview
The THS3217 is a differential-input to single-ended output amplifier system that provides the necessary
functional blocks to convert a differential output signal from a wideband DAC to a dc-coupled, single-ended, high-
power output signal. The THS3217 typically operates using balanced, split supplies. Signal swings through the
device can be adjusted around ground at several points within the device. Single-supply operation is also
supported an ac-coupled signal path. The THS3217 supply voltage ranges from ±4.0 V to ±7.9 V. The two
internal logic gates rely on a logic reference voltage at pin 7 that is usually tied to ground for any combination of
power-supply voltages. The DISABLE control (pin 10) turns the output power stage (OPS) off to reduce power
consumption when not in use.
A differential-to-single-ended stage (D2S) provides a high input impedance for a high-speed DAC (plus any
reconstruction filter between the DAC and THS3217) operating over a common-mode input voltage range from
–1 V to +3.0 V. This range is intended to support either current sourcing or current sinking DACs. The D2S is
internally configured to reject the input common-mode voltage and convert the differential inputs to a single-
ended output at a fixed gain of 2 V/V (6 dB).
An uncommitted, on-chip, wideband, unity-gain buffer is provided (between pins 1 and 15) to drive the VREF pin.
The buffer offers extremely broad bandwidth to achieve very-low output impedance to high frequencies
(Figure 51). The buffer does not provide a high full-power bandwidth because of a relatively low slew rate. The
buffer stage includes a default midsupply bias resistor string of 50-kΩ each to set the default input to midsupply.
This 25-kΩ Thevinin impedance is easily overridden with an external input source, but is intended to provide a
midsupply bias for single-supply operation. The buffer amplifier that drives the VREF pin has two functions:
•
•
Provides an easy-to-interface, dc-correction, servo-loop input
Can be used as an offset injection point for the D2S output
The final OPS provides one of the highest-performance, current-feedback amplifiers available for line-driving
applications. The 950-MHz SSBW stage provides 5000 V/μs of slew-rate, sufficient to drive a 5-VPP output with
500-MHz bandwidth. In addition, the OPS is able to drive a very-high continuous and peak output current
sufficient to drive the most demanding loads at very high speeds. A unique feature added to the OPS is a 2 × 1
input multiplexer at the noninverting input. The PATHSEL control (pin 4) is used to select the appropriate signal
path to the OPS noninverting input. One of the multiplexer select paths passes the internal D2S output directly to
the OPS. The other select path accepts an external input to the OPS at VIN+ (pin 9). This configuration allows
the D2S output, available at VO1 (pin 6), to pass through an external RLC filter and back into the OPS at VIN+
(pin 9).
If the OPS does not require power for certain application configurations, a shutdown feature has been included to
reduce power consumption. For designs that do not use the OPS at all, two internal fixed resistors are included
to define the operating points for the disabled OPS. An approximate 18.5-kΩ resistor to the logic reference (pin
7) from VIN+ (pin 9), and an approximate 18.5-kΩ, fixed, internal feedback resistor are included to hold the OPS
pin voltages in range if no external resistors are used around the OPS. These resistors must be included in the
design calculations for any external network.
Two sets of power supply-pins have been provided for both the positive and negative supplies. Pin 5 (–VCC2)
and pin 16 (+VCC2) power the D2S and midscale buffer stages, while pin 8 (–VCC1) and pin 13 (+VCC1) supply
power to the OPS. The supply rails are connected internally by antiparallel diodes. Externally, connect power first
to the OPS, then connect back on each side with a π-filter (ferrite bead + capacitor) to the input-stage supply
pins (see Figure 90). Do not use mismatched supply voltages on either the positive or negative sides because
the supplies are internally connected through the antiparallel diodes. Imbalanced positive and negative supplies
are acceptable, however.
When the OPS is disabled, the output pin goes to high impedance. However, do not connect two OPS outputs
from different devices together and select them as a wired-or multiplexer. Although the high-impedance output is
disabled, the inverting node is still available through the feedback resistor, and can load the active signal. The
signal path through the inverting node typically degrades the distortion on the desired active signal in a wired-or
multiplexer configuration using CFA amplifiers.
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9.2 Functional Block Diagram
+VCC2
16
+VCC1
13
VREF
14
VMID_OUT
15
50 kꢀ
12 VINœ
100 ꢀ
VMID_IN
1
2
x1
18.5 kꢀ
50 kꢀ
50 ꢀ
+IN
x1
11 VOUT
+
+
250 ꢀ
500 ꢀ
3
4
x1
œIN
10
DISABLE
VIN+
18.5 kꢀ
9
PATHSEL
6
7
8
5
œVCC2
VO1
GND
œVCC1
9.3 Feature Description
9.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2-V/V (Pins 2, 3, 6 and 14)
This buffered-amplifier stage isolates the DAC output nodes from the differential to single-ended conversion.
Presenting two high-impedance inputs allows the DAC to operate in its best configuration independent of
subsequent operations. The two very wideband input buffers hold an approximately constant response shape
over a wide input common-mode operating voltage. Figure 13 shows 6 dB of gain with 0.5-dB flatness through
500 MHz over the intended –1-to +3-V input common-mode range. In this case, the VREF pin is grounded,
forcing the D2S output to be centered on ground for any input common-mode voltage. For the D2S-only tests, a
100-Ω load is used to showcase the performance of this stage directly driving a doubly-terminated cable. The
wide input common-mode range of the D2S satisfies the required compliance voltage over a wide range of DAC
types. Most current sourcing DACs require an average dc compliance voltage on their outputs near ground.
Current sinking DACs require an average dc compliance voltage near their positive supply voltage for the analog
section. The 3-V maximum common-mode range is intended to support DAC supplies up to 3.3 V, where the
average output operating current pulls down from 3.3 V by the termination impedance from the supply. For
instance, a 20-mA tail current DAC must level shift from a 3.3-V bias on the output resistors down to 3 V or
lower. This DAC-to-THS3217 configuration requires at least a 300-mV dc level shift with half the tail current in
each side, implying a 30-Ω load impedance to the supply on each side of the 20-mA reference current.
The overriding limits to the input common-mode operating range are due to the input buffer headroom. Over
temperature, the D2S input headroom specification is 2 V to the negative supply and 1.5 V to the positive supply.
Therefore, operation at a 3-V input common-mode voltage requires at least a 4.5-V positive supply, where 5 V is
a more conservative minimum.
While DAC outputs rarely have any common-mode signal present (unless the reference current is being
modulated), the D2S does a reasonable job of rejecting input common-mode signals over frequency. Figure 17
shows the CMRR to decrease above 10 MHz. For current-sinking DACs coming from a positive supply voltage,
any noise on the positive supply looks like an input common-mode signal. Keeping the noise small at higher
frequencies reduces the possibility of feedthrough to the D2S output due to the decreasing CMRR at higher
frequencies. A current-sinking DAC uses pull-up resistors to the voltage supply to convert the DAC output current
to a voltage. Make sure that the DAC voltage supply has been properly decoupled through a ferrite bead and
capacitor, π-filter network similar to the supply decoupling for the THS3217 shown in Figure 90.
30
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Feature Description (continued)
The D2S provides a differential gain of 6 dB. The gain is reasonably precise using internal resistor matching with
extremely low gain drift over temperature (see Figure 61 and Figure 62). The single-ended D2S output signal can
be placed over a wide range of dc offset levels using the VREF pin. The VREF pin shows a precise gain of 1 V/V
to the D2S output. Grounding VREF places the first stage output centered on ground (with some offset voltage).
For best ac performance through the D2S, anything driving the VREF pin must have a very wide bandwidth with
very low output impedance over frequency while driving a 150-Ω load. The on-chip midscale buffer provides
these features (see Figure 51). When a dc offset (or other small-level ac signal) must be applied to the VREF
pin, buffer the signal through the midscale buffer stage. Maintain the total range of the dc offset plus signal swing
within the available output swing range of the D2S. The headroom to the supplies is a symmetric ±1.65 V (max)
over temperature. Therefore, on the minimum ±4-V supply, the D2S operates over a ±2.35-V output range. At the
maximum ±7.9-V supply, a ±6.25-V output range is supported. At the higher swings, account for available linear
output current, including the current into the internal feedback resistor load of approximately 500-Ω.
Figure 76 shows the internal structure of the D2S functional block. It consists of two internal stages:
1. The first stage consists of two wideband, closed-loop, fixed gain of 1 V/V buffers to isolate the requirements
of the complementary DAC output from the difference operation of the D2S.
2. The second stage is a wideband CFA configured as a difference amplifier, operating in a fixed gain of 2 V/V,
performing the differential to single-ended conversion.
Complementary
Output DAC
10 mA
RF
RG
250 ꢀ
500 ꢀ
3
VIN
2
x1
x1
VO1 = 2VIN
6
25 ꢀ
25 ꢀ
IDIFF
+
R1
50 ꢀ
R2
100 ꢀ
10 mA
14
Optional DC
Source
Figure 76. D2S Operating Example
The CFA design offers the best, full-power bandwidth versus supply current, with moderate noise and dc
precision. Figure 76 shows a typical current-sourcing DAC with a 20-mA total tail current. The tail current is split
equally between the 25-Ω termination resistors to produce a dc common-mode voltage and a differential ac
current signal. This example sets the input common-mode voltage at 0.25 V, and is also the compliance voltage
of the DAC. The 25-Ω termination resistors shown here are typically realized as a 50-Ω matched reconstruction
(or Nyquist) filter between the DAC and the THS3217 buffer inputs for most AWG applications. The DAC signal
is further amplified by 6 dB in the second stage for a net transimpedance gain of 100-Ω to the D2S output at
VO1. This configuration produces a 2-VPP output for the 20-mA reference current assumed in the example of
Figure 76. The input common-mode voltage is cancelled on the two sides of the op amp circuit to give a ground
referenced output. Any voltage applied to the VREF pin has a gain transfer function of 1 V/V to VO1,
independent of the signal path, as long as the source impedance of VREF is very low at dc and over frequency.
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Feature Description (continued)
The IN+ buffer output drives a 150-Ω load with VREF grounded. Any source driving VREF must have the ability
to drive a 150-Ω load with low output impedance across frequency. For differential input signals, the IN– buffer
drives a 150-Ω active load. The active load is realized by a combination of the 250-Ω RG resistor and the inverted
and attenuated signal present at the inverting terminal of the difference amplifier stage. If only IN– is driven (with
IN+ at a dc fixed level), the load is 250 Ω.
The resistor values around the D2S difference amplifier are derived in the following sequence, as shown in
Figure 77:
1. Select the feedback resistor value to set the response shape for the wideband CFA stage. The 500-Ω design
used here was chosen as a compromise between loading and noise constraints.
2. Set the input resistor on the inverting input side to give the desired single-sided gain for that path. Setting
RG= 250-Ω results in a gain of –2 V/V from the buffered signal (–V) to the output of the difference amplifier.
3. Solve the required attenuation to the noninverting input to get a matched gain magnitude for the signal
provided at the buffer output (+V) on the noninverting path. If α = R2 / (R1 + R2), as shown in Figure 77,
then the solution for α is shown in Equation 2:
≈
’
÷
◊
RF
a 1+
= 2
∆
RG
«
(1)
(2)
2
a =
3
R1
=
R1+ R2
RG
RF
250 ꢀ
500 ꢀ
-V
.‡(+V)
VO1
+
R1
+V
R2
Figure 77. D2S Impedance Analysis
4. After solving the attenuation from the buffer output to the amplifier noninverting input, set the impedance (R1
+ R2). It is preferable to have the two first stage buffer outputs drive the same load impedance to match
nonlinearity in their outputs in order to improve even-order harmonic distortion. The load impedance from –V
to RG has an active impedance because of the inverted and attenuated version of the input signal appearing
at the inverting amplifier node from the +V input signal. Assuming a positive input signal into the +V path, an
attenuated version of the signal appears at the amplifier summing junction side of RG, while the inverted
version of the signal appears on the input side of RG.
The impedance seen at node –V in Figure 77 is derived in Equation 3 by solving for the V/I expression across
RG.
RG
250 ꢀ
2
1+
3
Zi =
=
= 150 ꢀ
1+ a
(
)
(3)
For load balancing, (R1 + R2) = 150 Ω while the attenuation is α. More generally, all the terms are now available
to solve for R2, as shown in Equation 4:
2
a
a +1
3
R2 = RG
= 250 ꢀ
= 100 ꢀ
2
3
(
)
1+
(4)
R1 is then simply (Zi- R2) = 50 Ω.
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Feature Description (continued)
This analysis for matched gains and buffer loads can be applied to a more general discrete design using different
target gains and starting RF values. It is clearly useful to have the attenuation and buffer loading accurately
controlled. Therefore, it is very important to control the impedance at the VREF pin to be as low as possible. For
instance, using the midscale buffer to drive the VREF pin only adds 0.21 Ω dc impedance in series with R2. This
low dc output impedance can only be delivered with a closed-loop buffer design. For discrete implementations of
this D2S, consider the BUF602 buffer and LMH6702 wideband CFA amplifier. For even better dc and ac output
impedance in the buffers (and possibly better gain), use a closed-loop, dual, wideband op amp like the OPA2889
for lower frequency applications, or the OPA2822 for higher frequency. These unity gain stable op amps can be
used as buffers offering different performance options along with the LMH6702 wideband CFA over the design
point chosen for the THS3217.
After gain matching is achieved in the single op amp differential stage, the common-mode input voltage is
cancelled to the output, and the VREF input voltage is amplified by 1 V/V to the output. The analysis circuit is
shown in Figure 78, where VREF is shown grounded at the R2 element.
RG
RF
250 ꢀ
500 ꢀ
VCM
VO1
+
R1
50 ꢀ
R2
100 ꢀ
Figure 78. D2S Common-Mode Cancellation
The gain magnitudes are equal on each side of the differential inputs; therefore, the common-mode inputs
achieve the same gain magnitude, but opposite phase, resulting in common-mode signal cancellation. The
inverting path gain is VCM × (RF / RG). The noninverting path gain is VCM × α × (1 + RF / RG). Using Equation 5:
RF
RG
a =
≈
∆
«
’
÷
◊
RF
1+
RG
(5)
the noninverting path gain becomes +VCM × RF / RG, and adding that result to the inverting path signal cancels to
zero. Slight gain mismatches reduce this rejection to the 55-dB typical CMRR, with a 47-dB tested minimum. The
47-dB minimum over the 3-V maximum common mode input range adds another ±13.4-mV worst-case D2S
output offset term to the specified maximum ±35-mV output offset with 0-V input common-mode voltage. The
polarity of the gain mismatch is random.
The VREF pin input voltage (VREF) generates a gain of 1 V/V using the analysis shown in Figure 79
RG
RF
250 ꢀ
500 ꢀ
VO1
+
R1
50 ꢀ
R2
100 ꢀ
VREF
Figure 79. Gain Transfer Function from VREF to VO1
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Feature Description (continued)
The gain from VREF to VO1 is shown in Equation 6:
≈
∆
«
’
÷
◊
RF
R1
VREF
1+
= V
O1
R1+ R2
RG
(6)
Getting both R1 and (R1 + R2) in terms of RG and the target attenuation, α simplifies, as shown in Equation 7:
1- a
R
G 1+ a
R1
=
= 1- a
(
)
1
R1+ R2
(
)
R
G 1+ a
(7)
(8)
Putting Equation 7 back into the gain expression(Equation 6), and expanding out gives:
≈
’
÷
◊
RF
VREF 1- a 1+
= V
O1
(
)
∆
«
RG
Recall that in order to get differential gain balance, α = –(RF / RG). Putting that into Equation 8 reduces the
expression to VO1 = VREF, a gain of 1 V/V. This gain is very precise as shown in the D2S Electrical
Characteristics table, where the tested dc limits are 0.985 V/V to 1.015 V/V.
The D2S output offset and drift are largely determined by the internal elements. The only external consideration
is the dc source impedance at the two buffer inputs. With low source impedance, the D2S output offset is tested
to be within ±35 mV, that becomes a maximum ±17 mV input differential offset specification. Assuming the dc
source impedances are closely matched, the mismatch in the two input bias currents adds another input offset
term for higher source impedances. The input bias offset current is limited in test to be < ±0.40 µA. This error
term does not rise to add more than ±1 mV input differential offset until the dc source impedance exceeds 2.5
kΩ. A high dc source impedance most commonly occurs in an input ac-coupled, single-supply application, where
dc offsets are less critical.
The absolute input bias currents modifies the common-mode input voltage if the dc source resistance is too
large. That term is tested to a limit of ±4 µA on each input. To move the input common mode voltage by ±100
mV, the dc source impedance must exceed 25 kΩ. This added input common-mode voltage is cancelled by the
D2S at the output (VO1, pin6).
The D2S output noise is largely fixed by the internal elements. The D2S shows a differential input voltage noise
of 9 nV/√Hz, and a current noise of 2 pA/√Hz on each input. Higher termination resistors increase this source
noise, as given by Equation 9, where Rt is the dc termination impedance at each buffer input. The D2S has a 1/f
corner at approximately 30 kHz (see Figure 18).
2
2
ei_ diff
=
9nV + 2 4kTR + 2 2pA ìR
t
t
(9)
The total differential input noise is dominated by the differential voltage noise. For instance, evaluating this
expression for Rt = 200 Ω on each input, increases the total differential input noise to 9.4.nV/√Hz, only slightly
greater than the 9 nV/√Hz for the D2S with 0-Ω source Rt on each input. If higher final output SNR is desired,
consider generating as much input swing as the DAC can support, but increase the termination impedance. It is
possible that a lower tail current with higher Rt will yield improved SNR at the D2S input. This differential input
noise appears at the D2S output times a gain of 2 V/V.
eout _ diff = 2ì ei_ diff
(10)
9.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
This optional block can be completely unconnected and not used if the design does not require this feature.
Internal 50-kΩ resistors to the power supplies bias the input of the buffer to the midpoint of the supplies used.
The internal resistors set a midsupply operating point when the buffer is not used, as well as a default midsupply
point at the buffer output to be used in other stages for single-supply, ac-coupled applications.
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Feature Description (continued)
The buffer provides a very wideband, low output-impedance when used to drive the VREF pin (see Figure 51).
To provide this low broadband impedance, the closed-loop midscale (dc) reference buffer offers a very
broadband SSBW, but only a modest large-signal bandwidth (LSBW); see Figure 49. This path is not normally
intended to inject a wideband signal, but can be used for lower-amplitude signals. Driving the buffer output into
the VREF pin allows a wideband small-signal term to be added into the D2S along with the signal from the
differential inputs.
The midscale (or dc) reference buffer injects an offset voltage to the output offset of the D2S when it drives the
VREF pin. The offset has very low drift, but consider the effect of the input bias current times the dc source
impedance at VMID_IN (pin 1). When used as a default midsupply reference for single-supply operation, the
input to this buffer is just the average of the total power supplies though a 25-kΩ source impedance. Add an
external capacitor to filter the supply and the 50-kΩ internal resistors. A 1-µF capacitor on pin 1 adds a 6-Hz pole
to the noise sources. If lower noise at lower frequencies is required, implement a midscale divider with external,
lower-valued resistors in parallel with the internal 50-kΩ values.
If the midscale buffer drive the VREF pin, another noise term is added to Equation 9 and Equation 10. The
midscale buffer 4.4-nV/√Hz voltage noise is amplified by 0 dB, and adds (RMS) a negligible impact to the total
D2S output noise. The biggest impact comes when the internal default 50-kΩ dividers are used. Be sure to
decouple pin 1 with at least a 1-µF capacitor in the application to reduce the noise contribution through this path.
Figure 80 is the simulation circuit where the only change is to add or remove the 1-µF capacitor.
+VCC2
16
50 kꢀ
VMID_IN
15 VMID_OUT
1
x1
1 …F
50 kꢀ
5
-VCC2
Figure 80. Midscale Buffer Noise Model
Figure 81 shows the simulated output noise for the midscale buffer using the internal 50-kΩ divider with and
without a 1-µF capacitor on pin 1.
1000
With 1mF cap.
Without 1mF cap
100
10
1
1
10
100
1k
10k
100k
1M
Frequency (Hz)
D501
Figure 81. Buffer-Output Noise Comparison With and Without the 1-µF Bypass Capacitor on Pin 1
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Feature Description (continued)
In the flat region, the 1-µF capacitor reduces the midscale buffer output spot noise from approximately 55 nV/√Hz
to 4.4 nV/√Hz. If the noise below 100 Hz is unacceptable, either add a low-noise buffer to drive this input, or add
lower-value resistors externally to set up the midsupply bias. Also, consider the noise impact of any reference
voltage source driving the midscale buffer path.
9.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
This wideband current-feedback amplifier (CFA) provides a flexible output driver with several unique features.
The OPS can be left unused if the specific application only uses the D2S alone, or a combination of the D2S with
an off-chip power driver. If left unused, simply tie DISABLE (pin 10) and PATHSEL (pin 4) to the positive supply.
This logic configuration turns the OPS off and opens up the external and internal OPS noninverting input paths.
An internal fixed 18.5-kΩ resistor holds the external input pin at the logic reference voltage on pin 7. Additionally,
the OPS output is connected to the inverting input through another internal 18.5-kΩ resistor when no external
resistors are installed on pins 9, 11, or 12. Disabling the OPS saves approximately 21 mA of supply current from
the nominal total 54 mA with all stages operating on ±6-V supplies.
The noninverting input to the OPS provides two possible paths controlled by the PATHSEL logic control, pin 4.
With the logic reference (pin 7) at ground, floating pin 4 or controlling it to a voltage < 0.7 V connects the input
path directly to the internal D2S output. Tying pin 4 to the positive supply, or controlling it to a logic level > 1.3 V,
connects the input path to the external input at pin 9. The intent for this switched input is to allow an external filter
to be inserted between the D2S output and OPS inputs when needed, and bypass the filter when not.
Alternatively, this switched input also allows a completely different signal path to be inserted at the OPS input,
independent of that available at the internal D2S output.
In situations where the D2S output at pin 6 is switched into another off-chip power driver, the OPS can be
disabled using pin 10. With the logic reference (pin 7) at ground, floating pin 10, or controlling it to a voltage < 0.7
V, enables the OPS. Tying pin 10 to the positive supply, or controlling it to a logic level > 1.3 V, disables the
OPS.
Operation of the wideband, current-feedback OPS requires an external feedback resistor and a gain element.
After configuring, the OPS can amplify the D2S output through either the noninverting path, or be configured as
an inverting amplifier stage using the external OPS input at pin 9 as a dc reference.
One of the first considerations when designing with the OPS is determining the external resistor values as a
function of gain in order to hold the best ac performance. The loop gain (LG) of a CFA is set by the internal
open-loop transimpedance gain from the inverting error current to the output, and the effective feedback
impedance to the inverting input. The nominal internal open-loop transimpedance gain and phase are shown in
Figure 82.
140
120
100
80
45
Gain
Phase
0
-45
-90
-135
-180
-225
60
40
20
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
C502
Figure 82. Simulated OPS ZOL Gain And Phase
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Feature Description (continued)
The feedback transimpedance (ZOPT) can be approximated as shown in Equation 11, where Ri is the open-loop,
high-frequency impedance into the inverting node of the OPS. For a detailed derivation of Equation 11, see
Setting Resistor Values to Optimize Bandwidth section in the OPA695 datasheet (SBOS293).
≈
’
÷
◊
RF
ZOPT ö R + 1+
R
i
∆
F
RG
«
(11)
As the signal gain is varied, hold ZOPT approximately constant to hold the ac response constant over gain.
Holding ZOPT constant is a requirement to solve for RF. An example of the THS3217 OPS RF derivation is shown
in Equation 12:
≈
’
÷
◊
RF
R = 351 ꢀ - 1+
ì 42 ꢀ
∆
F
RG
«
(12)
The calculations are complicated by the internal feedback resistor value of approximately 18.5-kΩ. After the
external RF is approximately set by the constant bandwidth consideration, the RG must be set considering the
other gain error terms. From the noninverting input of a CFA op amp, the total gain to the output includes a loss
through the input buffer stage (described by the CMRR) and the loop gain (LG) loss set by the typical dc open-
loop transimpedance gain and the feedback transimpedance. Extract the buffer gain from the VIN+ input to the
VIN– input from the CMRR using Equation 13. This gain loss only applies to the noninverting mode of operation
and can be neglected in inverting mode operation.
-CMRR
20
≈
’
÷
∆
b = 1-10
= Buffer Gain CFA
∆
«
÷
◊
(13)
The OPS has a typical CMRR of 49 dB (buffer gain, β = 0.9965) with a tested minimum of 47 dB (minimum
buffer gain of 0.9955). The dc LG adds to the gain error. The LG is given by Equation 14 where the typical
design gain of 2.5 V/V value is also shown (the 245 Ω shown for RF is the external 249-Ω feedback resistor in
parallel with the internal 18.5-kΩ feedback resistor).
ZOL
1 Mꢀ
LG =
=
= 2857
R + NGìR
245 ꢀ + 2.5ì 42 ꢀ
F
i
(14)
The closed-loop output impedance with a heavy load also adds a minor gain loss that is neglected here. The
total noninverting gain is then set by Equation 15 (remember to include the internal RF in this analysis. The RF’
shown here is the parallel combination of the internal and external feedback resistors).
≈
’
÷
◊
RF
LG
A+ = bì 1+
ì
∆
v
RG
1+ LG
«
(15)
Using nominal values for each term at the specified RF = 249 Ω and RG = 162 Ω gives the gain calculation in
Equation 16, yielding a nominal gain very close to 2.5 V/V.
245.7
162
2857
≈
’
A+v = 0.9965ì 1+
ì
= 2.507
∆
÷
◊
1+ 2857
«
(16)
Testing the total gain spread with the internal variation in buffer gain, open-loop transimpedance gain, internal
feedback resistor, and ±1% external resistor variation gives a worst-case gain spread of 2.49 V/V to 2.51 V/V.
The gain error is primarily dominated by the external 1% resistors. For the tighter tolerance shown in Table 2,
use 0.1% precision resistors.
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Feature Description (continued)
At very low gains (< 1.5 V/V) parasitic LC effects at the inverting input render a flat frequency response
impossible. Looking then at gains from 1.5 V/V and up, a table of nominally recommended RF and RG values is
shown in Table 2. Do not operate the OPS in noninverting gains of less than 2.5 V/V for large output signals
because the limited slew-rate of the CFA input buffer causes signal degradation. Table 2 accounts for the
nominal gain losses described previously, and uses standardized resistor values to minimize the nominal gain-
error to target gain. The calculation also restricts the solution to a minimum RG = 20 Ω. The gain calculations
include the nominal buffer gain loss, the loop-gain effect, and the nominal internal feedback resistor = 18.5 kΩ.
Table 2. Optimized RF Values for Different OPS Noninverting Signal Gains
CALCULATED GAIN
TARGET GAIN
(V/V)
MEASURED SSBW
(MHz)
BEST RF
BEST RG
GAIN ERROR
(%)
(Ω)
(Ω)
(V/V)
1.505
1.998
2.500
3.008
3.493
4.028
4.495
4.960
5.467
6.043
6.532
6.965
7.553
8.043
8.580
8.971
9.557
9.966
(dB)
1.5
2
1400
—
294
274
249
232
205
182
165
140
121
113
115
121
133
143
154
162
174
187
562
267
162
113
80.6
59
3.551
0.3
–0.1
0
6.013
2.5
3
950
—
7.960
9.566
0.3
3.5
4
—
10.863
12.103
13.055
13.910
14.754
15.624
16.301
16.859
17.563
18.108
18.670
19.057
19.606
19.970
–0.2
0.7
—
4.5
5
—
46.4
34.8
26.7
22.1
20.5
20
–0.1
–0.8
–0.6
0.7
652
—
5.5
6
—
6.5
7
—
0.5
—
–0.5
0.7
7.5
8
—
20
—
20
0.5
8.5
9
—
20
0.9
—
20
–0.3
0.6
9.5
10
—
20
315
20.5
–0.3
The measured bandwidths in Table 2 come from Figure 25 using the resistor values in the table and a 100-Ω
load. Plotting the RF value versus gain gives the curve of Figure 83. The curve shows some ripple due to the
standard value resistors used to minimize the target dc gain error.
350
300
250
200
150
100
50
0
1
2
3
4
5
6
7
8
9
10
Target OPS Gain (V/V)
D503
Figure 83. Suggested External RF Value vs Noninverting Gain for the OPS
38
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Using RF values greater than the recommended values in Table 2 band-limits the response, whereas using less
than the recommended RF values peaks the response. Using the values shown in Table 2 results in an
approximately constant SSBW (see Figure 25. Holding a more constant loop-gain over the external gain setting
also acts to hold a more constant output impedance profile, as shown in Figure 84. The swept-frequency, closed-
loop, output impedance is shown for gains of 2.5 V/V, 5 V/V, and 10 V/V using the RF and RG values of Table 2.
The first two steps do a good job of delivering the same (and very low) output impedance over frequency, while
the gain of 10 V/V shows the expected higher closed-loop output impedance due to the reduced loop-gain and
bandwidth.
10
1
0.1
Gain = 2.5 V/V
Gain = 5 V/V
Gain = 10 V/V
0.01
1M
10M
100M
Frequency (Hz)
D504
Figure 84. OPS Closed-Loop Output Impedance vs Gain Setting
Reducing the RF value with increasing gain also helps minimize output noise versus a fixed RF design. See
Figure 39 for the three noise terms for the OPS. The total output noise calculation is shown in Equation 17:
2
2
2
eo = eni + 4kTR + i R
NG2 + i R
+ 4kTR NG
F
(
)
(
)
(
)
S
bn
S
bi
F
where
•
RS is the source impedance on the noninverting input. If the OPS is driven from the D2S stage directly using
the internal path, RS ≈ 0 Ω.
•
•
NG = (1 + RF / RG) for the design point.
The flat-band noise numbers for the OPS are:
–
–
–
Eni = 3.2 nV/√Hz
Ibn = 2.7 pA/√Hz
Ibi = 30 pA/√Hz
(17)
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Using the values of RF and RG listed in Table 2, a swept gain output- and input-referred noise estimate is
computed, as shown in Table 3. In this sweep, RS = 0 Ω. The input-referred noise (Eni) in Table 2 is at the
noninverting input of the OPS. To refer the noise to the D2S differential inputs, divide the output noise by two if
there is no interstage loss. Dividing the Eni column by 2 V/V shows that the OPS noise contribution is negligible
when referred to the D2S inputs, where the 9-nV/√Hz differential input noise dominates. Operating with higher
feedback resistors in the OPS quickly increases the output noise due to the inverting input current noise term.
Although increasing RF improves phase margin (for example, when driving a capacitive load), be careful to check
the total output noise using Equation 17.
Table 3. Total Input- and Output-Referred Noise of the OPS Versus Gain
TARGET GAIN
(V/V)
BEST RF
BEST RG
EO
(nV/√Hz)
Ein
(nV/√Hz)
(Ω)
(Ω)
1.5
2
294
274
249
232
205
182
165
140
121
113
115
121
133
143
154
162
174
187
562
267
162
113
80.6
59
10.4
11.3
12.3
13.5
14.7
15.9
17.2
18.6
20.0
21.4
22.9
24.4
25.9
27.4
29.0
30.5
32.1
33.6
6.9
5.6
4.9
4.5
4.2
4.0
3.8
3.7
3.6
3.6
3.5
3.5
3.5
3.4
3.4
3.4
3.4
3.4
2.5
3
3.5
4
4.5
5
46.4
34.8
26.7
22.1
20.5
20
5.5
6
6.5
7
7.5
8
20
20
8.5
9
20
20
9.5
10
20
20.5
Operating the OPS as an inverting amplifier is also possible. When driving the OPS directly from the D2S to the
RG resistor, use the values shown in Table 2 for the noninverting mode to achieve good results. Note that the RG
resistor is the load for the D2S stage. Operating with the D2S driving an RG < 80 Ω increases the harmonic
distortion of the D2S. In that case, scaling RF and RG up to reduce the loading may result in better system
performance at the cost of a lower OPS bandwidth. Driving the D2S output at pin 6 into the OPS in an inverting
mode allows for the option to select the external input of the OPS, and drive another signal or dc level into the
noninverting input at pin 9. In order to reduce layout parasitics, consider splitting the RG resistor in two, with the
first half close to pin 6 and the second half close to pin 12. Splitting RG in this manner places the trace
capacitance inside the two resistors keeping both active nodes more stable. Also, open up the ground and power
planes under the trace, if possible.
40
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Using the PS to receive and amplify a signal in the inverting mode with a matched terminating impedance,
requires another resistor to ground (RM) along with RG. This RM resistor is shown in Figure 85 for a 50-Ω
matched input impedance design.
VIN-
12
RG
RF
50-Ω
Source
RM
OPS
Stage
6
11
VOUT
+
From D2S
VIN+
9
Figure 85. Inverting OPS Operation With Matched Input Impedance
Table 4 gives the recommended external resistor values versus gain for the inverting gain mode with input
matching configuration. Table 4 solves for the required RF to simultaneously allow the gain, input impedance (50
Ω), and feedback transimpedance to be controlled to the optimum target values. The table includes the effect of
the internal 18.5-kΩ feedback resistor, and minimizes the RMS error to input impedance target (ZI) and overall
gain.
Table 4. Resistor Values Versus Gain for the Inverting OPS Configuration
TARGET
GAIN
(V/V)
MEASURED
SSBW
CALCULATED GAIN
BEST
BEST
BEST
GAIN ERROR
(%)
ZI ERROR
(%)
ZI (Ω)
RF (Ω) RG (Ω) RM (Ω)
(V/V)
(dB)
(MHz)
1
1.5
2
1000
—
280
255
249
237
226
226
221
226
249
274
301
324
348
374
402
422
449
475
499
274
169
60.4
71.5
1.002
1.506
2.000
2.490
3.013
3.491
4.010
4.525
4.985
5.485
6.026
6.486
6.967
7.487
8.048
8.448
8.989
9.509
9.990
0.022
3.554
0.250
0.376
49.490
50.243
50.254
49.784
50.000
50.019
50.326
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
–1.019
0.486
—
124
84.5
6.019
–0.014
–0.403
0.444
0.508
2.5
3
860
—
93.1
75
107
7.924
–0.433
0.000
150
9.581
3.5
4
—
63.4
54.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
237
10.859
12.064
13.111
13.953
14.784
15.601
16.240
16.861
17.487
18.114
18.536
19.074
19.563
19.991
–0.258
0.259
0.039
—
604
0.651
4.5
5
—
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
0.545
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
760
—
–0.301
–0.264
0.434
5.5
6
—
6.5
7
—
–0.208
–0.472
–0.167
0.600
—
7.5
8
—
—
8.5
9
—
–0.607
–0.123
0.100
—
9.5
10
—
260
–0.100
At higher gains, RM increases to larger values, and the resistor is excluded from the circuit. The resulting input
impedance of the network is resistor RG. From that point, RF simply increases to get higher gains, thereby rapidly
reducing the SSBW. However, below a gain of –5 V/V, the inverting design with the values shown in Table 4
holds a more constant SSBW versus the noninverting mode (see Figure 26).
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9.3.3.1 Output DC Offset and Drift for the OPS
The OPS provides modest dc precision with typical and maximum dc error terms in Table 5. The input offset
voltage applies to either input path with very little difference between the internal and external paths.
Table 5. Typical Offset and Bias Current Values for the OPS
PARAMETER
TYPICAL
MINIMUM
–12
MAXIMUM
UNIT
mV
µA
VIO
Ibn
Ibi
±1
5
12
15
40
–5
±5
–40
µA
Selecting the internal path results in no source resistance for Ibn, so that term drops out. When the external path
is selected, a dc source impedance may be present, so the Ibn term creates another error term, and adds to the
total output offset.
Stepping through an example design for the OPS output dc offset using the external path with a low insertion
loss filter shown in Figure 92, along with its RF and RG values, gives the following results:
•
•
•
RS for the Ibn term = 34 Ω || 249 Ω = 30 Ω. (dc source impedance for the filter design)
RF including the internal 18.5 kΩ resistor = 249 Ω || 18.5 kΩ = 245.7 Ω
Resulting gain with the 130-Ω RG element = 2.89 V/V
Table 6 shows the typical and worst-case output error terms. Note that a positive current out of the noninverting
input gives a positive output offset term, whereas a positive current out of the inverting input gives a negative
output term.
Table 6. Output Offset Voltage Contribution From Various Error Terms at 25°C
ERROR TERM
Ibn × RS × AV
VIO × AV
TYPICAL
0.433
MINIMUM
–0.43
MAXIMUM
1.29
UNIT
mV
±2.89
–34.68
–9.83
34.68
9.83
mV
Ibi × RF
±1.22
mV
Total error
–3.67 to +4.54
–44.94
45.8
mV
The input offset voltage dominates the error terms. The worst-case numbers are calculated by adding the
individual errors algebraically, but is rarely seen in practice. None of the OPS input dc error terms are correlated.
To compute output drift numbers, use the same gains shown in Table 6 with the specified drift numbers.
The OPS PATHSEL control responds extremely quickly with low-switching glitches, as shown in Figure 86. For
this test, the D2S input is set to GND, and the output of the D2S is connected to the external OPS input. The
PATHSEL switch is then toggled at 10 MHz. The results show the offset between the internal and external paths
as well matched.
4
3
0.12
0.08
0.04
0
2
1
0
-0.04
-0.08
-0.12
-0.16
-0.2
-1
-2
-3
-4
PATHSEL In
OPS Out
Time (20 ns/div)
D505
Figure 86. OPS Path-Select Switching Glitch
42
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The OPS includes a disable feature that reduces power consumption from approximately 21 mA to 2.4 mA. The
logic controls are intended to be ground-referenced regardless of the power supplies used. The logic reference
(GND, pin 7) is normally grounded and also provides a connection to the internal 18.5-kΩ resistor on pin 9
(default bias to pin 7). Operating in a single-supply configuration with –VCC at GND and the external OPS input
(pin 9) floated, places pin 9 internally at –VCC = GND. Driving the external OPS input (pin 9) from a source within
the operating range overrides the bias to –VCC. However, if the application requires pin 9 to be floated in a
single-supply operation, consider centering the voltage on pin 9 with an added 18.5-kΩ external resistor to the
+VCC supply.
If the disable feature is not needed, simply float or ground DISABLE (pin 10) to hold the OPS in the enabled
state. Increasing the voltage on the DISABLE pin greater than 1.3 V disables the OPS and reduces the current to
approximately 2.4 mA. If the OPS is unused in the application, it can be disabled by tying pin 10 to +VCC, even
up to the maximum operating supply of 15.8 V in a single-supply design.
Do not move the logic threshold away from those set by the logic ground at pin 7. If a different logic swing level
is required, and pin 7 is biased to a different voltage, be sure the source can sink the typical 280 µA coming out
of pin 7. Also recognize that the 18.5-kΩ bias resistor on the external OPS input (pin 9) is connected to pin 7
voltage internally.
As shown in Figure 56, the OPS enables in approximately 100 ns from the logic threshold at 1.0 V while
disabling to a final value in approximately 500 ns.
9.3.3.2 OPS Harmonic Distortion (HD) Performance
The OPS in the THS3217 provides one of the best HD solutions available through high power levels and
frequencies. Figure 31 and Figure 32 show the swept-frequency HD2 and HD3, where the second harmonic is
clearly the dominant term over the third harmonic. Typical wideband CFA distortion is reported only through 2-
VPP output while Figure 31 and Figure 32 provide sweeps at 5 VPP and 8 VPP into a 100-Ω load. These curves
normally show a 20-dB per decade rise with frequency due to loop-gain roll-off. At the highest 8-VPP swing, the
onset of slew rate limited HD is seen at approximately 40 MHz. The required output signal slew rate at 8 VPP and
40 MHz is 4 VPEAK × 2π × 40 MHz = 1000 V/µs. The output signal requires 1/5 of the available slew rate that will
take the HD2 off the 20-dB per decade rate in the –50-dBc operating region shown. A slight shift in the HD3
slope is also seen around 40 MHz for 8-VPP output in Figure 32.
The distortion performance is extremely robust as a function of RLOAD (see Figure 33 and Figure 34). Normally,
heavier loads degrade the distortion performance, as seen for the HD3 in Figure 34. However, the HD2 actually
improves slightly going from a 200-Ω load to a 100-Ω load.
One of the key advantages offered by the CFA design in the OPS is that the distortion performance holds
approximately constant over gain, as seen in the full-path distortion measurements of Figure 7 and Figure 8.
Here, the D2S provides a fixed gain of 2 V/V driving a 200-Ω interstage load and using the internal path to drive
the OPS at gains from 1.5 V/V to 10 V/V. Holding the loop-gain approximately constant by adjusting the feedback
RF value with gain results in vastly improved performance versus a voltage-feedback-based design.
Testing a 5-VPP output from the OPS with the supplies swept from the minimum ±4 V to ±7.5 V in Figure 35 and
Figure 36 show:
1. The 1.5-V headroom on ±4-V supplies and ±2.5-V output voltage results in degraded performance. At the
lower supplies, target lower output swings for improved linearity performance.
2. The HD2 does not change significantly with supply voltages above ±5 V. The HD3 does improve slightly at
higher supply-voltage settings.
From these plots at ±7.5-V supplies, a 5-VPP output into 100-Ω load shows better than –60-dBc HD2 and HD3
performance through 50 MHz. This exceptional performance is available with the OPS configured as a
standalone amplifier. Combining this performance with the D2S stage (see Figure 3 and Figure 4) degrades the
distortion due to the D2S and OPS harmonics combining in phase, and internal coupling between the stages.
With the D2S and OPS running together at a final 5-VPP output and 50 MHz, the HD2 drops to –50 dBc, and HD3
to –58 dBc on ±6-V supplies. Lower output swings for the combined stages provide much lower distortion. The 2-
VPP output curves on Figure 3 and Figure 4 show –57 dBc for HD2, and a remarkable –76 dBc for HD3 at 50
MHz.
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9.3.3.3 Switch Feedthrough to the OPS
The OPS has two logic control pins, giving four combinations of states; therefore, various feedthrough effects
must be considered. Figure 57 and Figure 58 show the feedthrough of the switches with the OPS disabled. With
the OPS enabled, the signal feedthrough from the deselected input to the OPS output is shown in Figure 87 and
Figure 88 at different closed-loop OPS gains. The results are shown for a 100-mVPP signal at the deselected
input and are not normalized to the gain of the OPS. Adding a low-pass filter between the DAC and the D2S
inputs helps reduce the feedthrough at higher frequencies.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
OPS Gain = 2.5 V/V
OPS Gain =10 V/V
OPS Gain = 2.5 V/V
OPS Gain =10 V/V
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D506
D507
PATHSEL < 0.7 V,
100-mVPP signal to VIN (pin 9)
PATHSEL > 1.3 V,
100-mVPP signal to VREF (pin 14) with D2S inputs grounded
Figure 87. Forward Feedthrough With OPS Enabled,
Internal Path Selected
Figure 88. Forward Feedthrough With OPS Enabled,
External Path Selected
44
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9.3.3.4 Driving Capacitive Loads
The OPS can drive heavy capacitive loads very well as shown in Figure 43 to Figure 48. All high-speed
amplifiers benefit from the addition of an external series resistor to isolate the load capacitor from the feedback
loop. Not having the series isolation resistor often leads to response peaking and possibly oscillation. If
frequency response flatness under capacitive load is the design goal, all CFA type amplifiers benefit by operating
with slightly higher RF values. Targeting a slightly higher feedback transimpedance increases the nominal phase
margin before the capacitive load acts to decrease it. Using a higher RF value has the effect of achieving good
flatness across a range of capacitive loads using lower external series resistor values. Although the suggested
RF and RG values of Table 7 apply when driving a 100-Ω load, if the intended load is capacitive (for example, a
passive filter with a shunt capacitor as the first element, another amplifier, or a Piezo element), use the values
reported in Table 7 as a starting point. The values in Table 7 were used to generate Figure 43 and Figure 44.
The results come from a nominal total feedback transimpedance target of 405 Ω (versus 351 Ω used for
Table 4), and includes the internal 18.5-kΩ resistor in the design. Table 7 finds the least error to target gain in
the selection of standard resistor values, and limits the minimum RG to 20 Ω. The gains calculated here put 18.5-
kΩ in parallel with the reported external standard value RF.
Table 7. Suggested RF and RG Over Gain When Driving a Capacitive Load
CALCULATED GAIN
TARGET GAIN
(V/V)
BEST RF
GAIN ERROR
(%)
BEST RG (Ω)
(Ω)
(V/V)
(dB)
1.5
2
348
332
309
287
267
249
226
205
178
158
137
121
130
140
154
162
174
182
681
324
1.501
2.011
2.491
2.987
3.520
3.992
4.535
4.979
5.505
5.961
6.460
7.004
7.451
7.948
8.457
9.041
9.426
10.034
3.529
0.077
0.575
6.070
2.5
3
205
7.927
–0.361
–0.420
0.565
143
9.506
3.5
4
105
10.930
12.024
13.131
13.943
14.815
15.506
16.204
16.907
17.444
18.005
18.544
19.124
19.486
20.030
82.5
63.4
51.1
39.2
31.6
24.9
20.0
20.0
20.0
20.5
20.0
20.5
20.0
–0.200
0.776
4.5
5
–0.419
0.085
5.5
6
–0.652
–0.621
0.058
6.5
7
7.5
8
–0.652
–0.652
–0.509
0.452
8.5
9
9.5
10
–0.780
0.341
As the capacitive load or amplifier gain increases, lower series resistor values can be used to hold a flat
response (see Figure 43). See Figure 44 for the measured SSBW shapes for various capacitive loads configured
with the suggested series resistor from the output of the OPS and the RF and RG values suggested in Table 7 for
a gain of 2.5 V/V. This measurement includes a 200-Ω shunt resistor in parallel with the capacitive load as a
measurement path.
Figure 45 and Figure 46 demonstrate the OPS harmonic distortion performance when driving a range of
capacitive loads. These show suitable performance for large-signal, piezo-driver applications. If voltage swings
higher than 12 VPP are required, consider driving the OPS output into a step-up transformer. The high peak-
output current for the OPS supports very fast charging edge rates into heavy capacitive loads, as shown in the
step response plots (see Figure 47 and Figure 48). This peak current occurs near the center of the transition time
driving a capacitive load. Therefore, the I × R drop to the capacitive load through the series resistor is at a
maximum at midtransition, and back to zero at the extremes (low dV/dT points).
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9.3.4 Digital Control Lines
The THS3217 provides two logic input lines that provide control over the input path to the OPS and the OPS
power disable feature; both are referenced to GND (pin 7). The control logic defaults to a logic-low state when
the pins are externally floated. Pin 7 must have a dc path to some reference voltage for correct operation. Float
the two logic control lines to enable the OPS and select the internal path connecting the D2S internal output to
the OPS noninverting input. Figure 89 shows a simplified internal schematic for either logic control input pin.
+VCC
50 mA
20 mA
1 kꢀ
Logic
Control
Input
Q1
Q2
17.5 kꢀ
Q3
VCTRL
19 kꢀ
100 ꢀ
D3
D1
D2
PIN 7
Figure 89. Logic Control Internal Schematic
The Q2 branch of the differential pair sets up a switch threshold approximately 1 V greater than the voltage
applied to pin 7 (GND). If the control input is floating or < 0.7 V, the differential-pair tail current diverts to the 100-
Ω detector load, and results in an output voltage (VCTRL, shown in Figure 89) that activates the desired mode.
The floated pin default voltage is the PNP base current into the 19-kΩ resistor. As the control pin voltage rises
above 1.3 V, the differential-pair current is completely diverted away from the 100 Ω side, thus switching states.
This unique design allows the logic control inputs to be connected to a single-supply as high as 15.9 V, in order
to hold the inputs permanently high, while still accepting a low ground-referenced logic swing for single-supply
operation. The NPN transistor (Q3) and two diodes (D1 and D2) act as a clamp to prevent large voltages from
appearing across the differential stage.
When the OPS is disabled, both input paths to the OPS are also opened up regardless of the state of PATHSEL
(pin 4).
9.4 Device Functional Modes
Any combination of the three internal blocks can be used separately, or in various combinations. The following
sections describe the various functional modes of the THS3217.
9.4.1 Full-Signal Path Mode
The full-signal path from the D2S to the OPS is available in various options. Three options are described in the
following subsections.
9.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
The most basic operation is to ground the VREF pin, and use the internal connection from the D2S to the OPS to
provide a differential to single-ended, high-power driver. Figure 90 shows the characterization circuit used for the
combined performance specifications.
46
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Device Functional Modes (continued)
6 V
Ferrite
Bead
16
15
14
13
162 ꢀ
50 kꢀ
12
100 ꢀ
1
x1
18.5 kꢀ
249 ꢀ
50 kꢀ
50 ꢀ
49.9 ꢀ
2
x1
11
+
AV = 5 V/V
To
49.9 ꢀ
49.9 ꢀ
+
Differential
VIN
50-Ω Load
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
9
6
7
8
5
200 ꢀ
Ferrite
Bead
œ6 V
Figure 90. Differential to Single-Ended, Gain of 5-V/V Configuration
This configuration shows the test circuit used to generate Figure 1. Some of the key features in this basic
configuration include:
1. The power supplies are brought into the OPS first, then back to the input stage through a π-filter comprised
of a ferrite bead and local decoupling caps on –VCC2 and +VCC2, pins 5 and 16, respectively (see the
Power Supply Recommendations section for more information).
2. The two logic lines are grounded. This logic configuration (with pin 7 grounded) selects the internal path from
the D2S to OPS, and enables the OPS.
3. The external I/O pins of the midscale buffer are left floating.
4. The VREF pin is grounded, thus setting the D2S output common-mode voltage at VO1 (pin 6) to ground.
5. The D2S external output is loaded with a 200-Ω resistor to ground. Lighter loading on the VO1 pin (versus
the 100 Ω used to characterize the D2S only) results in increased frequency response peaking. Heavier
loading degrades the D2S distortion performance.
6. The external OPS input at pin 9 is left floating. However, it is internally tied to ground by the internal 18.5-kΩ
resistor.
7. The feedback resistor in the OPS is set to the parallel combination of the external 249-Ω resistor and the
internal 18.5-kΩ resistor. This 245.7-Ω total RF with the 162-Ω RG resistor gives a gain of approximately 2.5
V/V (7.98 dB) in the OPS stage
8. The input D2S gives a gain of 2 V/V (6 dB), and along with the 2.5 V/V (7.98 dB) from the OPS, gives an
overall gain of 5 V/V (13.98 dB) with > 700 MHz of SSBW (see Figure 1).
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Device Functional Modes (continued)
9.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
The simplest modification to this starting configuration is using the midscale buffer to drive the VREF pin with
either a dc or ac source into VMID_IN (pin 1), shown in Figure 91.
Ferrite
Bead
6 V
VMID_OUT
16
15
14
13
162 ꢀ
249 ꢀ
50 kꢀ
12
11
100 ꢀ
1
2
x1
+
18.5 kꢀ
VMID_IN
œ
50 kꢀ
50 ꢀ
49.9 ꢀ
x1
+
AV = 5 V/V
49.9 ꢀ
To
50-Ω Load
+
Differential
VIN
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
49.9 ꢀ
9
6
7
8
5
200 ꢀ
Ferrite
Bead
œ6 V
Figure 91. Differential to Single-Ended, Gain of 5-V/V Configuration With VREF Driven by the Midscale
Buffer
The VREF input can be used to offset the output of the D2S that will then be amplified by the OPS. The total dc
offset at the output of the OPS can also be corrected by adjusting the voltage at VMID_IN (pin 1). The on-chip
midscale buffer can be used as a low-impedance source to drive the correction voltage to the VREF pin. A
wideband small-signal source can also be summed into this path with a gain of 1 V/V to the D2S output pin.
Figure 49 shows the midscale buffer to have an extremely flat response through 100 MHz for < 100-mVPPswings,
while 1 VPP can be supported through 80 MHz with a flat response.
From this point on, the diagrams are simplified to not show the power-supply elements. However, the supplies
are required by any application, as described in the Application and Implementation section.
48
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Device Functional Modes (continued)
9.4.1.3 External Connection
In the configuration shown in Figure 92, the bias to PATHSEL (pin 4) is changed in order to select the external
input of the OPS. The external D2S output drives a low insertion loss, third-order Bessel filter. The filter in this
example is designed with a low frequency insertion loss of 1.2 dB and f–3dB = 140 MHz, and results in an
additional insertion loss of 1 dB at 100 MHz. The OPS gain is slightly increased to recover the filter loss, in order
to give an input to output gain of 5 V/V. Using an interstage filter between the D2S and the OPS improves the
step response by reducing the overshoot.
16
15
14
13
130 ꢀ
50 kꢀ
12
11
100 ꢀ
1
2
x1
18.5 kꢀ
249 ꢀ
50 kꢀ
50 ꢀ
49.9 ꢀ
x1
+
AV= 5 V/V
To
50-Ω Load
49.9 ꢀ
49.9 ꢀ
+
Differential
VIN
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
1-dB loss
at 100 MHz
VPATHSEL > 1.3 V
9
249 ꢀ
6
7
8
5
Low Insertion Loss
3rd-Order Bessel Filter
34 ꢀ
33 nH
10 pF
52 pF
Figure 92. External Path Configuration With Interstage Low-Pass Filter
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Device Functional Modes (continued)
9.4.2 Dual-Output Mode
The D2S stage can also be used to directly drive a doubly-terminated line, as shown in Figure 93. In addition, the
OPS amplifies the internal D2S output by 5 V/V. The internal path to the OPS is selected with PATHSEL (pin 4)
at ground, and the OPS gain is increased to 5 V/V. A 2-VPP output at VO1 produces a 10-VPP output at VOUT
(pin 11). This 10-VPP swing requires higher supply operation to provide sufficient headroom in the OPS output
stage in order to preserve signal integrity. A power supply of ±7.5 V provides adequate headroom.
16
15
14
13
34.8 ꢀ
50 kꢀ
12
11
100 ꢀ
1
2
x1
18.5 kꢀ
140 ꢀ
50 kꢀ
50 ꢀ
49.9 ꢀ
AV = 10 V/V
x1
+
To
49.9 ꢀ
49.9 ꢀ
+
Differential
VIN
50-Ω Load
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
9
6
7
8
5
To
50-Ω Load
AV = 2 V/V
49.9 ꢀ
Figure 93. Dual-Output Mode
A simple modification to the circuit in Figure 93 is to disable the OPS, and switch to the external input path by
taking both logic lines (pin 4 and pin 10) high. The D2S output at VO1 is then used either directly or through a
filter to an even higher power driver like the ±15-V THS3091.
50
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Device Functional Modes (continued)
9.4.3 Differential I/O Voltage Mode
Having two amplifiers available also allows a simple differential I/O implementation with independent output
common-mode control, as shown in Figure 94. In this configuration, the D2S provides one side of the differential
output, while simultaneously driving the OPS configured in an inverting gain of –1 V/V to provide the differential
output on the other side. The output at VMID_OUT biases the external noninverting input, VIN+ (pin 9). This
circuit configuration places the differential input to the output filter at a common-mode voltage, VMID_OUT
.
VMID_OUT
VO1
16
15
14
13
274 ꢀ
274 ꢀ
50 kꢀ
12
11
100 ꢀ
1
2
x1
+
18.5 kꢀ
VMID_IN
œ
50 kꢀ
50 ꢀ
x1
+
VOUT
Differential
Input Mixer
Differential
Filter
49.9 ꢀ
+
Differential
VIN
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
49.9 ꢀ
VMID_OUT
9
VPATHSEL > 1.3V
6
7
8
5
VO1
Figure 94. Differential I/O Configuration With Independent Output Common-Mode Voltage Control
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Typical Applications
The five example designs presented show a good, but not comprehensive, range of the possible solutions that
the THS3217 provides. Numerous more configurations are clearly possible to the creative designer.
10.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
6 V
16
6 V
13
15
14
124 ꢀ
50 kꢀ
12
11
OPS AV= 2.84 V/V
100 ꢀ
1
2
x1
18.5 kꢀ
Either 2.5 VPP
or
10 VPP at Load
232 ꢀ
50 kꢀ
50 ꢀ
49.9 ꢀ
VO
x1
+
VOUT= 5 VPP
To
+
Differential
Filter
50-Ω Load
50-MHz, 3rd-order
Bessel filter
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
20 pF
49.9 Ω
150 nH
9
VPATHSEL = 3.3 V
+15V
10 ꢀ
THS3091
AV= 4.4 V/V
+
6
7
8
5
110 pF
200 ꢀ
œ
THS3091
10 ꢀ
-15V
1 kꢀ
œ6 V
œ6 V
100-MHz, 3rd-order Bessel filter
33 nH
294 ꢀ
100 ꢀ
10 pF
52 pF
255 ꢀ
Figure 95. Dual-Channel Design: 5 VPP at THS3217 Output and 20 VPP at THS3091 Output
10.1.1.1.1 Design Requirements
For this design example, use the parameters listed in Table 8 as the input parameters.
Table 8. Dual-Output Design Specifications
DESIGN PARAMETER
High-frequency, THS3217 channel
High-voltage, THS3091 channel
EXAMPLE VALUE
5-VPP, 100-MHz bandwidth
20-VPP, 40-MHz bandwidth
52
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10.1.1.1.2 Detailed Design Procedure
The THS3217 is well suited for high-speed, low-distortion arbitrary waveform generator (AWG) applications
commonly used in laboratory equipment. In this typical application, a high-speed, complementary-current-output
DAC is used to drive the D2S. The OPS of the THS3217 easily drives a 100-MHz, 2.5-VPP signal into a matched
50-Ω load. When a larger output signal is required, consider using the THS3091 as the final driver stage.
A passive RLC filter is commonly used on DAC outputs to reduce the high-frequency content in the DAC steps.
The filtering between the DAC output and the input to the D2S reduces higher-order DAC harmonics from
feeding into the internal OPS path when the external input path is selected. Feedthrough between the internal
and external OPS paths increases with increasing frequency; however, the input filter rolls off the DAC
harmonics before the harmonics couple to VOUT (pin 10) through the deselected OPS signal path. Figure 96
shows an example of a doubly-terminated differential filter from the DAC to the THS3217 D2S inputs at pins 2
and 3.The DAC is modeled as two, fixed, 10-mA currents and a differential, ac-current source. The 10-mA dc
midscale currents set up the average common-mode voltage at the DAC outputs and D2S inputs at 10 mA × 25
Ω = 0.25 VCM. The total voltage swing on the DAC outputs is 0 V to 0.5 V.
Complementary
Output DAC
D2S Stage with input
capacitance included
10 mA
IN+
2
72 nH
15 pF
12 pF
12 pF
49.9 ꢀ
49.9 ꢀ
2.4 pF
2.4 pF
49.9 ꢀ
49.9 ꢀ
IDIFF
72 nH
3
IN-
15 pF
10 mA
Figure 96. 200-MHz Butterworth Filter Between DAC and D2S Inputs
Some of the guidelines to consider in this filter design are:
1. The filter cutoff is adjusted to hit a standard value in the standard high-frequency, chip inductors kits.
2. The required filter output capacitance is reduced from the design value of 14.4 pF to 12 pF to account for the
D2S input capacitance of 2.4 pF, as reported in the D2S Electrical Characteristics table.
3. The capacitor at the DAC output pins must also be reduced by the expected DAC output pin capacitance.
The DAC output capacitance is often specified as 5 pF, but is usually much lower. Contact the DAC
manufacturer for an accurate value.
Figure 97 shows the TINA-simulated filter response for the input-stage filter. The low-frequency 34-dBΩ gain is
due to the 50-Ω differential resistance at the DAC output terminals. At 400 MHz, this filter is down 16 dB from the
50-Ω level; it is also very flat through 100 MHz.
35
30
25
20
15
10
5
0
1M
10M
100M
Frequency (Hz)
1G
D508
Figure 97. Simulated, Differential-Input Filter Response
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In the example design of Figure 95, a 100-MHz, third-order Bessel filter is placed between the D2S output and
the external OPS input. Another 50-MHz, third-order Bessel filter is placed at the input of a very-high, output-
swing THS3091 stage. A double-pole, double-throw (DPDT) relay selects the THS3091 path when the internal
OPS path is selected in the THS3217. Figure 95 shows this design. The key operational considerations in this
design include:
1. When the external OPS path is selected, the 2-VPP maximum D2S output swing experiences a 1.1-dB
insertion loss from the interstage filter between VO1 (pin 6) and VIN+ (pin 9). A standard value inductor is
used and the 255-Ω termination accounts for the internal 18.5-kΩ element. The 10-Ω resistor at pin 9 isolates
the OPS input from the 52-pF filter capacitor. To recover the insertion loss and produce a maximum 5-VPP
output, the OPS gain is set to 2.84 V/V. When the interstage filter path is selected, the two DPDT relays pass
the OPS output on directly from the 49.9-Ω output matching resistor to VO, and the THS3091 can be disabled
to conserve power.
2. To deliver 20 VPP at the VO output, select the THS3091 path. Select the internal OPS path to bypass the
100-MHz filter (1.1-dB insertion loss) in order to give a maximum 5.7-VPP output at VOUT (pin 11). The two
DPDT relays switch position, and the 49.9 Ω at the OPS output becomes part of the 50-MHz, third-order
Bessel filter into the THS3091 stage. This filter has a 2-dB insertion loss requiring a gain of 4.4 V/V in the
THS3091 to deliver 20 VPP from the OPS output.
3. Figure 98 and Figure 99 show the frequency response and harmonic distortion performance of the dual
output-voltage system. The frequency response is normalized to 0 dB to make bandwidth comparisons
easier.
10.1.1.1.3 Application Curves
-20
-30
3
0
5 VPP
20 VPP
-40
-50
-60
-3
-6
-9
-70
-80
HD2 -5 VPP
HD3- 5 VPP
HD2- 20 VPP
HD3- 20 VPP
-90
-100
-110
1M
10M
100M
Frequency (Hz)
1G
1M
10M
Frequency (Hz)
100M
D509
D510
Figure 98. Frequency Response of the 5-VPP and 20-VPP
Channels
Figure 99. Harmonic Distortion Performance of the 5-VPP
and 20-VPP Channels
54
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10.1.1.2 High-Voltage Pulse-Generator
7.5 V
7.5 V
16
15
14
13
113 ꢀ
50 kꢀ
OPS AV= 3 V/V
12
11
100 ꢀ
1
x1
18.5 kꢀ
232 ꢀ
50 kꢀ
5 VPP Max
at Load
50 ꢀ
49.9 ꢀ
0V
1V
1V
0 to 10 mA
2
x1
+
VOUT= 10 VPP
To
50-Ω Load
100 ꢀ
+
250 ꢀ
500 ꢀ
0V
3
4
x1
0 to 10 mA
10
18.5 kꢀ
100 ꢀ
1.6 dB
insertion loss
9
VPATHSEL = 3.3 V
6
7
8
5
10 ꢀ
œ7.5 V
œ7.5 V
55-MHz, 3rd-order Bessel filter
270 nH
100 ꢀ
9.1 pF
47 pF
511 ꢀ
Figure 100. Driving a 10-VPP Pulse Output into a 100-Ω Load With a 55-MHz External Interstage Bessel
Filter
10.1.1.2.1 Design Requirements
To design a high-voltage, high-speed pulse generator with minimum overshoot, use the parameters listed in
Table 8 as the input parameters.
Table 9. Pulse-Generator Specifications
DESIGN PARAMETER
Power supply
EXAMPLE VALUE
±7.5 V
Pulse frequency
10 MHz
Pulse output voltage
10 VPP
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10.1.1.2.2 Detailed Design Procedure
Figure 100 shows an example design using the THS3217 to deliver a 10-VPP maximum voltage from a DAC
input, and includes an example external, third-order, interstage Bessel filter. Some of the salient considerations
for this design include:
1. Reduced DAC output current with increased termination. This example is intended to be used with a current-
sourcing DAC with an output compliance voltage of at least 1 V on a 0.5-V common-mode voltage. The 10-
mA, single-ended, DAC tail current produces a 0-V to 1-V swing on each 100-Ω termination. The resulting 2-
VPP differential DAC signal produces a higher SNR signal at the THS3217 inputs.
2. The midscale buffer is not used. The VREF pin is grounded to set the inputs to a 4-VPP ground-centered
maximum output swing at VO1 (pin 6). The external input to the OPS is selected by setting PATHSEL to 3.3
V (anything over 1.3 V is adequate, or tie this pin to +VCC for fixed, external-path operation).
3. The interstage Bessel filter is –0.3-dB flat through 20 MHz, with only 1.6 dB of insertion loss. The filter is
designed to be low insertion-loss with relatively high resistor values. The filter uses standard inductor values.
The capacitors are also standard-value, and slightly off from the exact filter solution. The final resistor to
ground is designed for 500 Ω, but increased here to a standard 511 Ω externally to account for the internal
18.5-kΩ resistor on the external OPS input pin to GND. To isolate the last 47-pF filter capacitor from the OPS
input stage, a 10-Ω series resistor is added close to the pin 9 input.
4. The filter adds 1.6 dB of insertion loss that is recovered, to achieve a 10-VPP maximum output by designing
the OPS for a gain of 3 V/V. Looking at Table 7, this gain setting requires the 232-Ω external RF and 113-Ω
RG to ground for best operation.
5. For 10-VPP maximum output, using the ±7.5-V supplies shown here gives adequate headroom in the OPS
output stage. The operating maximum supply of 15.8 V requires a 5% tolerance on these ±7.5-V supplies.
6. The Bessel filter gives a very low overshoot full-scale output step-response, as shown in the 10-MHz, ±5-V
square wave of Figure 102. The frequency response of the system is shown in Figure 101.
10.1.1.2.3 Application Curves
16
14
12
10
8
6
4
10 VPP
ê5 V
2
0
-2
-4
-6
6
4
1M
10M
100M
Time (25ns/div)
Frequency (Hz)
D511
D512
Figure 101. Frequency Response of the System With the
Interstage Bessel Filter
Figure 102. Pulse Response of the System With the
Interstage Bessel Filter
56
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10.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
VMID_OUT
VMID_OUT
15 V
15 V
16
15
14
13
200 ꢀ
50 kꢀ
12
11
OPS AV = 3.4 V/V
100 ꢀ
1
2
x1
1 …F
18.5 kꢀ
499 ꢀ
3.3 ꢀ
50 kꢀ
10 nF
50 ꢀ
x1
+
VOUT = 12 VPP
1.62 kꢀ
1.62 kꢀ
49.9 ꢀ
VMID_OUT
49.9 ꢀ
300 pF
+
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
10 nF
(VMID_OUT + 3.5 VPP
)
VPATHSEL=15 V
9
6
7
8
5
10 ꢀ
VO1 = VMID_OUT + 4 VPP
390 nH
105 ꢀ
15-MHz, 2nd-order Chebyshev
filter (0.2 dB ripple)
68 pF
825 ꢀ
1 …F
Figure 103. Single-Supply, Heavy Capacitive-Load Driving
10.1.1.3.1 Design Requirements
The very-high peak output current and slew rate of the THS3217 OPS make it particularly suitable for driving
heavy capacitive loads, such as the piezo elements used in continuous wave (CW) applications that require high-
amplitude, sinusoidal-type excitations. The driver is quickly disabled during the receive time when the output TR
switch is moved to receive mode. Figure 103 shows an example design using the internal midscale buffer to bias
all the stages to midsupply on a single 15-V design. There are many elements to this example that also apply to
any single-supply application. The key points here are:
1. The differential DAC input signal is ac-coupled to the D2S input, and the termination resistors are scaled up
and biased to midsupply using the output of the midscale buffer, VMID_OUT (pin 15). The 10-nF blocking
capacitors before the 1.62 kΩ termination resistors set the high-pass pole at 10 kHz.
2. The internal divider resistors of the midscale buffer are decoupled using a 1-µF capacitor on VMID_IN (pin
1). Use of the capacitor improves both noise and PSRR through the reference buffer stage. In turn, the noise
injected by the bias source is reduced at the various places the buffer output is used.
3. VMID_OUT is also applied to the VREF input (pin 14) to hold the D2S output centered on the single 15-V
supply. There is minimal dc current into VREF (pin 14) because the D2S input buffers operate at the same
common-mode voltage, VMID_OUT
.
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4. The D2S output is dc biased at midsupply and delivers two times the differential swing applied at its inputs.
Assuming 2 VPP at the D2S inputs implies 4 VPP at the D2S output pins. Lower input swings are supported
with the gain in the OPS adjusted to meet the desired output maximum.
5. The filter in Figure 103 is a 0.2-dB ripple, second-order Chebyshev filter at 15 MHz. If the desired maximum
frequency is 12 MHz, for instance, this filter is attenuating the HD2 and HD3 out of the D2S by approximately
3 dB and 5 dB, respectively. Increased attenuation can be provided with higher-order filters, but this simple
filter does a good job of band-limiting the high-frequency noise from the D2S outputs before the noise gets
into the OPS stage.
6. The dc bias voltage at VO1 drives a small dc current into the 18.5-kΩ resistor to ground at the OPS external
input, VIN+ (pin 9). The error voltage due to the bias current will level-shift the dc voltage at the OPS
noninverting input through the 105-Ω filter resistor. This offset will be amplified by the OPS gain since its RG
element is referenced to the VMID output with a dc gain of 3.4 V/V.
7. The logic lines are still referenced to ground in this single-supply application. The external path to the OPS is
selected by connecting PATHSEL (pin 4) to +VCC. DISABLE (pin 10) is grounded in this example in order to
hold the OPS on. If the disable feature is required by the application, drive the OPS using a standard logic
control driver. Note that the midscale buffer output still drives RG and RF to midsupply in this configuration
with the OPS disabled.
8. The RG element can be ac coupled to ground through a capacitor to operate at midsupply. Figure 103 shows
the midscale buffer driving RG, thus eliminating the need for an added capacitor. Using a blocking capacitor
moves the dc gain to 1 V/V. The voltage on the external, noninverting input of the OPS sets the dc operating
point. Use of a blocking capacitor also lightens the load on the midscale buffer output, and eliminates the
bias on RG when the OPS is disabled.
9. Piezo element drivers operate in a relatively low-frequency range; therefore, the OPS RF is scaled up even
further than the values suggested in Table 7. An increased RF allows RG to also be scaled up, thereby
reducing the load on the midscale buffer, and allow a lower series output resistor to be used into the 300-pF
capacitive load.
10. The peak charging current into the capacitive load occurs at the peak dV/dT point. Assuming a 12-MHz
sinusoid at 12 VPP requires a peak output current from the OPS of 6 VPEAK × 2π × 12 MHz × 300 pF = 135
mA. This result matches the rated minimum peak output current of the OPS.
Using a very low series resistor limits the waveform distortion due to the I × R drop at the peak charging point
around the sinusoidal zero crossing. The 135 mA through 3.3 Ω causes a 0.45-V peak drop to the load
capacitance around zero crossing. The voltage drop across the series output resistor increases the apparent
third harmonic distortion at the capacitive load. Figure 45 and Figure 46 show 10-VPP distortion sweeps into
various capacitor loads. The results shown in these figures are for the OPS only because the results set the
harmonic distortion performance in this example.
58
Copyright © 2016, Texas Instruments Incorporated
THS3217
www.ti.com.cn
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
10.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
VMID_OUT
VO1
7.5 V
16
7.5 V
13
15
14
54.9 ꢀ
50 kꢀ
12
11
100 ꢀ
1
2
x1
+
18.5 kꢀ
VMID_IN = ±2 V
221 ꢀ
œ
50 kꢀ
50 ꢀ
x1
VMID_OUT ±4 V
+
AV = œ4 V/V
49.9 ꢀ
49.9 ꢀ
+
1 VPP
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
VMID_OUT
9
VPATHSEL > 1.3V
6
7
8
5
VO1= VMID_OU T ±1 V
œ7.5 V
œ7.5 V
Figure 104. Adding an Output DC Offset Using the Midscale Buffer
10.1.1.4.1 Design Requirements
An easy way to insert a dc offset into the signal channel (without sacrificing any of the DAC dynamic range) is to
apply the desired offset at VMID_IN and use it to bias VREF (pin 14) and VIN+ (pin 9). An example is shown in
Figure 104. This example shows a relatively low maximum differential input of 1 VPP on any compliance voltage
required by the DAC. Other configuration options include:
1. The D2S output is offset using a dc input at VMID_IN (pin 1). Although shown here as ±2 V, the dc offset
expands to ±3.5 V when using ±7.5-V supplies.
2. Connecting VMID_OUT to the VREF input places the D2S output at the dc offset voltage along with a gain of
2 V/V version of the differential input voltage. The stated range of ±2 V, along with the ±0.5 V out of the
upper input buffer, requires a peak output current from VMID_OUT of 2.5 V / 150 Ω = 16.7 mA. This value is
well below the rated minimum linear output current of 40 mA.
3. The dc offset voltage is then applied to the external OPS input. Connecting the circuit in this manner results
in no additional dc gain between the D2S and OPS outputs, while it continues to retain the signal gain of the
OPS configured as an inverting amplifier. The values of RF and RG in this application example are derived
from Table 4. The OPS is setup for a gain of –4 V/V in this example. Using the resistor values from Table 4
results in the widest bandwidth for the OPS; however, the RG = 54.9 Ω resistor presents a heavy load to the
D2S output. In such cases, scaling up the resistors in the OPS helps reduce the loading on the D2S output
at the expense of reduced OPS bandwidth.
4. No filtering is shown in this example; however, introducing filtering in the OPS RG path is certainly possible.
In such cases, the RG element is also the filter termination resistor. Any filtering adds some insertion loss that
can be recovered in the OPS stage.
Copyright © 2016, Texas Instruments Incorporated
59
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
10.1.1.5 Differential I/O Driver With independent Common-Mode Control
VMID_OUT
VO1
16
15
14
13
274 ꢀ
50 kꢀ
12
11
100 ꢀ
1
2
x1
+
18.5 kꢀ
VMID_IN
274 ꢀ
œ
50 kꢀ
50 ꢀ
x1
+
Differential
Input Mixer
Differential
Filter
VOUT = VMID_OUT œ 2VIN
49.9 ꢀ
+
Differential
VIN
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
49.9 ꢀ
9
VMID_OUT
VPATHSEL > 1.3 V
6
7
8
5
VO1= VMID_OUT + 2VIN
Figure 105. Differential I/O Line Driver
10.1.1.5.1 Design Requirements
Certain applications require the differential DAC output voltage to be level-translated from one common-mode
(compliance) level to a differential output at a different common-mode level. The THS3217 performs this function
directly using the very flexible blocks provided internally. Figure 105 shows an example of such an application,
where the differential gain is always 4 V/V. The differential gain is fine-tuned down by setting the insertion loss in
the differential post-filter. The considerations critical to this application include:
1. The input is dc-coupled with the appropriate termination impedance required by the DAC. Use a high-
frequency, antialiasing filter at the input to limit DAC feedthrough in the deselected OPS internal input.
2. The output common-mode control is set with the voltage applied to the VMID buffer input at VMID_IN (pin 1).
The circuit is configured so that the output at VMID_OUT (pin 15) drives both VREF (pin 14), in order to set
the D2S dc output voltage, and VIN+ (pin 9).
3. The D2S output available at VO1 (pin 6) provides one side of the differential-output, and is dc-biased at
VMID_OUT. This VO1 also drives the RG resistor for the OPS in an inverting gain of –1 V/V. The dc bias level at
the RG input and the V+ input of the OPS are the same voltage; therefore, no level shift through the OPS
occurs. The OPS outputs an inverted version of the D2S output signal at the same common-mode voltage
(VMID_OUT). The wideband, differential signal with independent output common-mode voltage control can now
be applied to a differential filter and on to the next stage.
4. Make sure that the differential filter only has differential resistors and capacitors. Termination resistors to
ground level shift the input common-mode voltage, while differential resistors transfers the desired VMID_OUT
directly through the filter.
5. If the desired VMID_OUT + differential signal combined clips in the OPS or D2S stages, offset the supplies to
gain headroom. For instance, if a 5-V output common-mode voltage is required with a 10-VPP differential
signal, the OPS and D2S must deliver 2.5-V to 7.5-V output swings. The D2S has the higher headroom
requirement at 1.55 V (max). Operating the THS3217 with –5 V and +10 V supplies stays within the rated
maximum of 15.8 V total supply range, and provide adequate headroom for the positive offset swing
requirement. Note that the logic lines are still referenced to GND by pin 7. Tying PATHSEL (pin 4) to +VCC
holds this design in the external path mode required.
60
Copyright © 2016, Texas Instruments Incorporated
THS3217
www.ti.com.cn
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
11 Power Supply Recommendations
The THS3217 typically operates on balanced, split supplies. The specifications and characterization plots use ±6
V in most cases. The full operating range for the THS3217 spans ±4 V to ±7.9 V. The input and output stages
have separate supply pins that are isolated internally.
The recommended external supply configuration brings ±VCC into the output stage first, then back to the input
stage connections through a π-filter comprised of ferrite beads and added decoupling capacitors at +VCC2 (pin
16) and –VCC2 (pin 5). Figure 106 shows an example decoupling configuration.
Ferrite Bead
Ferrite Bead
4 ꢁH
4 ꢁH
6 V
2.2 …F
10 nF
220 nF
10 nF
220 nF
16
15
14
13
162 ꢀ
50 kꢀ
12
11
100 ꢀ
1
2
x1
18.5 kꢀ
249 ꢀ
50 kꢀ
50 ꢀ
49.9 ꢀ
x1
+
AV = 5 V/V
To
50-Ω Load
49.9 ꢀ
49.9 ꢀ
+
Differential
VIN
250 ꢀ
500 ꢀ
3
4
x1
10
18.5 kꢀ
9
6
7
8
5
200 ꢀ
Ferrite Bead
Ferrite Bead
4 ꢁH
4 ꢁH
-6 V
2.2 …F
10 nF
220 nF
10 nF
220 nF
Figure 106. Recommended Power-Supply Configuration
Copyright © 2016, Texas Instruments Incorporated
61
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
The ferrite bead acts to break the feedback loop from the output stage load currents back into the D2S and
midscale buffer stages. Operate the two positive supply pins and the two negative supply pins at the same
voltage. Using separate sources on the two pins risks forward-biasing the on-chip parallel diodes connecting the
two supply inputs together. +VCC1 (pin 13) and +VCC2 (pin 16) have two parallel diodes that are normally off if
the voltage at the two pins are equal. The same is true for –VCC1 (pin 8) and –VCC2 (pin 5).
The THS3217 provides considerable flexibility in the supply voltage settings. The overriding consideration is
always satisfying the required headroom to the supplies on all the I/O paths. The logic controls on PATHSEL (pin
4) and DISABLE (pin 10) are intended to operate ground referenced regardless of supplies used. The ground
connection on pin 7 is used to set the reference.
Power savings are certainly possible by operating with only the minimum required supplies for the intended
swings at each of the pins. For instance, consider an example design operating with a current-sinking DAC with
the input common-mode voltage at 3 V, with an output swing at the D2S output of ±1 V. Looking at just the D2S
stage under these conditions, the minimum positive supply is 3 VCM + the maximum input headroom of 1.5 V to
the positive supply, resulting in a minimum 4.5-V supply for this operation. The ±1-V output at VO1 (pin 6) along
with the D2S output headroom sets the minimum negative supply voltage. The maximum 1.65-V headroom gives
a possible minimum negative supply of –2.65 V. However, the minimum operating total of 8 V increases the
negative supply to –3.5 V.
If the ±1-V swing is then amplified by the OPS, the output swing and headroom requirements set the minimum
operating supply. For instance, if the OPS is operating at a gain of 2.5 V/V, the ±2.5-V output requires a
maximum headroom of 1.4 V to either supply. Achieving a 1.4-V headroom requires a minimum balanced supply
of ±3.9 V. However, the input stage overrides the positive side because the required minimum is 4.5 V, while the
negative increases to –3.9 V. This example of absolute minimum supplies saves power. Using a typical 56-mA
quiescent current for all stages, going to the minimum 8.4 V total across the device, uses 470 mW of quiescent
power versus the 672 mW if a simple ±6-V supply is applied. However, ac performance degrades with the lower
headroom. For more power-sensitive applications, consider adjusting the supplies to the minimum required on
each side.
11.1 Thermal Considerations
The internal power for the THS3217 is a combination of its quiescent power and load power. The quiescent
power is simply the total supply voltage times the supply current. This current is trimmed to reduce power
dissipation variation and minimize variations in the ac performance. At a ±7.5-V supply, the maximum supply
current of 57 mA dissipates 855 mW of quiescent power. The worst-case load power occurs if the output is at ½
the single-sided supply voltage driving a dc load. Placing a ±3.75-V dc output into 100 Ω adds another 37.5 mA ×
3.75 V = 140 mW of internal power. This total of approximately 1 W of internal dissipation requires the thermal
pad be connected to a good heat-spreading ground plane to hold the internal junction temperatures below the
rated maximum of 150°C.
The thermal impedance is approximately 45 °C/W with the thermal pad connected. For 1 W of internal power
dissipation there is a 45°C (approximate) rise in the junction temperature from ambient. Designing for the
intended 85°C maximum ambient temperature results in a maximum junction temperature of 130°C.
62
Copyright © 2016, Texas Instruments Incorporated
THS3217
www.ti.com.cn
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
12 Layout
12.1 Layout Guidelines
High-speed amplifier designs require careful attention to board layout in order to achieve the performance
specified in the data sheets. Poor layout techniques can lead to increased parasitics from the board and external
components resulting in suboptimal performance, and also instability in the form of oscillations. The THS3217
evaluation module (EVM) serves as a good reference for proper, high-speed layout methodology. The EVM
includes numerous extra elements needed for lab characterization, and also additional features that are useful in
certain applications. These additional components can be eliminated on the end system if not required by the
application. General suggestions for the design and layout of high-speed, signal-path solutions include:
1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O
pins should be opened on all of the ground and power planes around those pins. On other areas of the board
continuous ground and power planes are preferred for signal routing with matched impedance traces for
longer runs.
2. Use good, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power pins.
Higher value capacitors (2.2 µF) are required, but may be placed further from the device power pins and
shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that
offer a much higher self-resonance frequency over standard capacitors. Avoid narrow power and ground
traces to minimize inductance between the pins and the decoupling capacitors. Follow the power-supply
guidelines recommended in the Power Supply Recommendations section.
3. Careful selection and placement of external components preserve the high-frequency performance of the
THS3217. Use low-reactance type resistors. Surface-mount resistors work best, and allow a tighter overall
layout. Keep the printed circuit board (PCB) trace length as short as possible. Never use wire-bound type
resistors in a high-frequency application. The output pin and inverting input pins are the most sensitive to
parasitic capacitance; therefore, always position the feedback and series output resistors, if any, as close as
possible to the inverting input pins and output pins. Place other network components, such as input
termination resistors, close to the gain-setting resistors.
4. When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces. On differential lines, like those on the D2S inputs, match the routing in order to
minimize common-mode noise effects and improve HD2 performance.
5. The input summing junction of the OPS is very sensitive to parasitic capacitance. Connect the RG element
into the summing junction with minimal trace length to the device pin side of the resistor. The other side of
RG can have more trace length if needed to the source or to ground. For best results, do not socket a high-
speed part like the THS3217. The additional lead length and pin-to-pin capacitance introduced by the socket
can create an extremely troublesome parasitic network that can make it almost impossible to achieve a
smooth, stable frequency response. Best results are obtained by soldering the THS3217 directly onto the
board.
Copyright © 2016, Texas Instruments Incorporated
63
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
12.2 Layout Example
RF and RG close to device pins to
minimize stray capacitance
Place bypass caps. close to
PWR pins
Remove GND and PWR
planes under D2S inputs to
minimize capacitance
50Ω Output resistor close to
pin to minimize parasitic
capacitance
Figure 107. Layout Example
64
版权 © 2016, Texas Instruments Incorporated
THS3217
www.ti.com.cn
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
13 器件和文档支持
13.1 器件支持
13.1.1 开发支持
13.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
13.2 文档支持
13.2.1 相关文档
相关文档如下：
•
•
•
•
•
《THS3217EVM 用户指南》，SBOU161
《电压反馈运放与电流反馈运放》，SLVA051
《电流反馈放大器的分析与补偿》，SLOA021
《电流反馈放大器：审阅、稳定性分析以及 应用》，SBOA081
《电流反馈放大器的稳定性处理》，SBOA095
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
版权 © 2016, Texas Instruments Incorporated
65
THS3217
ZHCSEP3B –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
13.4 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
66
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS3217IRGVR
THS3217IRGVT
ACTIVE
VQFN
VQFN
RGV
16
16
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
THS3217
IRGV
ACTIVE
RGV
NIPDAU
THS3217
IRGV
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS3217IRGVR
THS3217IRGVT
VQFN
VQFN
RGV
RGV
16
16
2500
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS3217IRGVR
THS3217IRGVT
VQFN
VQFN
RGV
RGV
16
16
2500
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGV 16
4 x 4, 0.65 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224748/A
www.ti.com
PACKAGE OUTLINE
RGV0016A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.15
3.85
A
B
PIN 1 INDEX AREA
4.15
3.85
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
2.16 0.1
2X 1.95
SYMM
(0.2) TYP
5
8
(0.37) TYP
EXPOSED
THERMAL PAD
9
4
SYMM
2X 1.95
17
2.16 0.1
12X 0.65
1
12
PIN 1 ID
0.38
16X
0.23
13
16
0.1
C A B
0.65
0.45
16X
0.05
4219037/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGV0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.16)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.75)
12
1
16X (0.305)
12X (0.65)
17
SYMM
(0.83)
(3.65)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(0.83)
(3.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219037/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGV0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.58) TYP
13
16
16X (0.75)
1
12
16X (0.305)
(0.58) TYP
(3.65)
17
SYMM
12X (0.65)
4X (0.96)
4
9
(R0.05) TYP
8
5
4X (0.96)
SYMM
(3.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219037/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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