THS3491IRGTR [TI]
900-MHz high-power-output current-feedback amplifier | RGT | 16 | -40 to 85;型号: | THS3491IRGTR |
厂家: | TEXAS INSTRUMENTS |
描述: | 900-MHz high-power-output current-feedback amplifier | RGT | 16 | -40 to 85 |
文件: | 总53页 (文件大小:3653K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
THS3491
ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
THS3491 900MHz、500mA 高功率输出电流反馈放大器
1 特性
3 说明
• 带宽:
THS3491 电流反馈放大器 (CFA) 可以为在从直流到大
于 100MHz 值(负载为 100Ω)的高输出功率水平实
现最低失真的应用提供更出色的性能。尽管该电流反馈
设计的额定增益为 5V/V,但它能够在宽增益范围内保
持几乎恒定的带宽和失真。
– 900MHz(VO = 2VPP,AV = 5V/V)
– 320MHz(VO = 10VPP,AV = 5V/V)
• 压摆率:8000V/µs (VO = 20VPP
• 输入电压噪声:1.7nV/√Hz
)
• 双极电源电压范围:±7V 至±16V
• 单电源电压范围:14 V 至32 V
• 输出摆幅:28VPP(±16V 电源,100Ω负载)
• 线性输出电流:±420 mA(典型值)
• 16.8mA 修整后的电源电流(低温度系数)
• HD2 和HD3:小于–75dBc(50MHz,VO =
10VPP,100Ω负载)
8000V/µs 的压摆率能够以低失真和 100MHz 的频率为
严苛的负载提供 10VPP 的输出。900MHz、小信号带
宽能够以 10V 阶跃以及小于 1.3ns 的上升和下降时间
提供小于 1.5% 的低过冲。大于 500mA 的峰值输出电
流驱动值能够以快速的信号驱动高电容负载。
通过使用 VQFN-16 (RGT) 封装,新设计能实现超低失
真,而 8 引脚 HSOIC (DDA) 封装(具有 PowerPAD
• 上升和下降时间:1.3ns(10V 阶跃)
• 过冲:1.5%(10V 阶跃,AV = 5V/V)
• 电流限制和热关断保护
™
)可升级现有的 THS3091 或 THS3095 设计。与传
统的 THS3091 或 THS3095 选项相比,THS3491 的
更低输出余量能够在相同的±15V 电源下提供更大的输
出摆幅。
• 关断特性
2 应用
封装信息(1)(2)
• 高电压任意波形发生器
封装尺寸(标称值)
器件型号
THS3491
封装
• 用于LCD 测试仪的信号发生器
• 用于LCR 表的输出驱动器
• 功率FET 驱动器
RGT(VQFN,16) 3.00mm × 3.00mm
DDA(HSOIC,8) 4.89mm × 3.90mm
• 高容性负载压电元件驱动器
• VDSL 线路驱动器
• 以引脚兼容的方式对THS3095 (DDA) 进行升级
器件信息
芯片尺寸(标称值)
器件型号
THS3491
封装
1.02 mm × 1.06 mm
裸片
(1) 如需了解所有可用封装,请参阅数据表末尾的封装选项附录。
(2) 请参阅器件比较表
+VS
œVS
0
HD2
HD3
VOUT = 10 VPP
-10
15 V
œ15 V
143 ꢀ
576 ꢀ
-20
-30
-40
-50
+VS
œ
High power gain of
5 V/V output driver
with load sharing
40.2 ꢀ
+
THS3491
THS3217
Output
50-Ω
Load
-60
-70
œVS
49.9 ꢀ
30 ꢀ
Passive
Filter
143 ꢀ
576 ꢀ
-80
13 VPP maximum
available at
matched 50-Ω
load
250 ꢀ
+VS
-90
œ
40.2 ꢀ
-100
0.1
+
1
10
Frequency (MHz)
100 200
THS3491
D071
œVS
谐波失真与频率间的关系
典型的任意波形发生器输出驱动电路
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBOS875
THS3491
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
Table of Contents
9.2 Functional Block Diagram.........................................24
9.3 Feature Description...................................................25
9.4 Device Functional Modes..........................................27
10 Application and Implementation................................30
10.1 Application Information........................................... 30
10.2 Typical Application.................................................. 32
10.3 Power Supply Recommendations...........................34
10.4 Layout..................................................................... 35
11 Device and Documentation Support..........................40
11.1 Documentation Support.......................................... 40
11.2 接收文档更新通知................................................... 40
11.3 支持资源..................................................................40
11.4 Trademarks............................................................. 40
11.5 静电放电警告...........................................................40
11.6 术语表..................................................................... 40
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Bare Die Information....................................................... 6
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................7
8.5 Electrical Characteristics: VS = ±15 V......................... 8
8.6 Electrical Characteristics: VS = ±7.5 V...................... 11
8.7 Typical Characteristics: ±15 V...................................13
8.8 Typical Characteristics: ±7.5 V..................................20
9 Detailed Description......................................................24
9.1 Overview...................................................................24
Information.................................................................... 40
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision B (July 2018) to Revision C (February 2023)
Page
• 向数据表添加了裸片封装详细信息......................................................................................................................1
• Removed bipolar-supply operating range and single-supply operating range specifications from Electrical
Characteristics: VS = ±15 V ............................................................................................................................... 8
• Added new test level A2 that is clarifies what is tested for die sales..................................................................8
Changes from Revision A (March 2018) to Revision B (July 2018)
Page
• 将典型的任意波形发生器输出驱动电路中的电阻值从49.9Ω更改为40.2Ω.....................................................1
• 将典型的任意波形发生器输出驱动电路中的电阻值从24.9Ω更改为30Ω........................................................1
• Changed TA = 25°C to TA ≅ 25°C in Electrical Characteristics: ±15 V condition statement............................... 8
• Changed 100% tested at 25°C to 100% tested at ≅ 25°C in the footnote of Electrical Characteristics: ±15 V ...
8
• Added DDA package only in Test Conditions column for "VOS" specification.....................................................8
• Added new VOS specifiction line for RGT package.............................................................................................8
• Added min/max values to RFB_TRACE specification ............................................................................................8
• Changed units from: pF || kΩ to: kΩ || pF and changed typical spec accordingly.............................................. 8
• Added min/max values to TJ_SENSE 25℃value specification............................................................................. 8
• Changed TJ_SENSE temperature coefficient specification's typical value from 3 mV/℃to 3.2 mV/℃................ 8
• Added min/max values to TJ_SENSE input impedance specification....................................................................8
• Changed "TA = 25°C" to "TA ≅ 25°C" in Electrical Characteristics: ±7.5 V condition statement....................... 11
• Changed "100% tested at 25°C" to "100% tested at ≅ 25°C" in the footnote of Electrical Characteristics: ±7.5
V .......................................................................................................................................................................11
• Added "DDA package only" in Test Conditions column for "VOS" specification ............................................... 11
• Added new VOS specifiction line for RGT package...........................................................................................11
• Changed units from "pF || kΩ" to "kΩ || pF" and changed typical values accordingly ......................................11
• Added min/max values to "TJ_SENSE 25℃value" specification.........................................................................11
• Added min/max values to "TJ_SENSE input impedance" specification................................................................11
• Changed "TA = 25°C" to "TA ≅ 25°C" in Typical Characteristics: ±15 V condition statement............................13
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• Changed ZOL low frequency value from 160 dB to 138 dB in Open-Loop Transimpedance Gain and Phase vs
Frequency ........................................................................................................................................................13
• Changed Overdrive Recovery Time grid lines and added gain information..................................................... 13
• Added TJ_SENSE Voltage vs Ambient Temperature ..........................................................................................13
• Changed "TA = 25°C" to "TA ≅ 25°C" in Typical Characteristics: ±7.5 V condition statement...........................20
• Changed Overdrive Recovery Time grid lines and added gain information..................................................... 20
• Corrected polarity of negative supply capacitor in Wideband Noninverting Gain Configuration (5 V/V) ......... 27
• Corrected negative supply capacitor polarity in Wideband Inverting Gain Configuration (5 V/V) ....................28
• Added "RISO" to "1 Ω" in Driving a Large Capacitive Load Using an Output Series Isolation Resistor ...........30
• Added 1-kΩresistor to Driving a Large Capacitive Load Using an Output Series Isolation Resistor .............30
• Changed supply values from ±15 V to ±7.5 V in Video Distribution Amplifier Application ...............................31
• Changed RS2 values from 100 Ωto 40.2 Ωin Load-Sharing Driver Application ............................................32
• Added 30-Ωresistor to Load-Sharing Driver Application ................................................................................32
• Added text to Design Requirements and Detailed Design Procedure sections ...............................................33
• Added Application Curves section ...................................................................................................................34
Changes from Revision * (August 2017) to Revision A (March 2018)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Device Comparison Table
HD2/3,
LINEAR
OUTPUT
CURRENT
(mA)
INPUT NOISE
Vn
(nV/√Hz)
SSBW,
AV = 5
(MHz)
MAXIMUM ICC
AT 25°C
SUPPLY, VS
10 VPP AT 50 MHz, SLEW RATE
DEVICE
(V)
G = 5 V/V
(dBc)
(V/µs)
(mA)
THS3491
THS3095
THS3001
THS3061
±15
±15
±15
±15
900
190
350
260
17.3
9.5
9
1.7
1.6
1.6
2.6
7100(1)
1200(2)
1400(3)
1060(4)
±420
±250
±120
±140
–76/–75
–40/–42
N/A
8.3
N/A
(1) Slew rate from FPBW of 320 MHz, 10 VPP
(2) Slew rate from FPBW of 135 MHz, 4 VPP
(3) Slew rate from FPBW of 32 MHz, 20 VPP
(4) Slew rate from FPBW of 120 MHz, 4 VPP
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6 Pin Configuration and Functions
PD
16
NC
15
+VS
14
+VS
13
REF
VINœ
VIN+
œVS
1
2
3
4
8
7
6
5
PD
1
2
3
4
12
11
10
9
NC
FB
NC
+VS
VOUT
VOUT
VOUT
NC
œ
+
NC
VINœ
VIN+
NC - no internal connection
图6-1. DDA Package, 8-Pin HSOIC With PowerPAD
5
6
7
8
GND TJ_SENSE œVS
œVS
(Top View)
NC - no internal connection
图6-2. RGT Package, 16-Pin VQFN With Exposed
Thermal Pad (Top View)
表6-1. Pin Functions
PIN (1)
HSOIC
—
TYPE (2)
DESCRIPTION
NAME
FB
VQFN
1
5
O
Input side feedback pin
GND
GND
Ground, PD logic reference on the VQFN-16 (RGT) package
—
No connect (there is no internal connection). Recommended connection to
a heat spreading plane, typically GND.
NC
5
8
1
2, 9, 12, 15
—
Amplifier power down: low = amplifier disabled, high (default) = amplifier
enabled
PD
16
I
I
PD logic reference on the SOIC-8 (DDA) package. Typically connected to
GND.
REF
—
TJ _SENSE
VIN–
VIN+
6
3
O
I
Voltage proportional to die temperature
Inverting input
—
2
3
4
I
Noninverting input
VOUT
–VS
6
10, 11
7, 8
13, 14
O
P
P
Amplifier output
4
Negative power supply
Positive power supply
+VS
7
Thermal pad. Electrically isolated from the device. Recommended
connection to a heat spreading plane, typically GND.
Thermal pad
—
(1) Both packages include a backside thermal pad. The thermal pad can be connected to a heat spreading plane that can be at any
voltage because the device die is electrically isolated from this metal plate. The thermal pad can also be unused (not connected to any
heat spreading plane or voltage) giving higher thermal impedance.
(2) GND = ground, I = input, O = output, P = power
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7 Bare Die Information
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE POTENTIAL
BOND PAD METALLIZATION BOND PAD DIMENSIONS
Wafer backside is electrically
connected to -VS
Silicon with backgrind
Al
76.0 µm × 76.0 µm
15 mils (381 μm)
55.31
19
18
17
16 15
14
1
2
3
13
12
11
10
4
5
6
7
8
9
0
0
1.57
Bond Pad Coordinates in Microns
NAME
FB
PAD NUMBER
X MIN
26.9
26.9
26.9
180
Y MIN
X MAX
103
Y MAX
963
1
2
887
VIN-
VIN+
REF
DNC
TJ_SENSE
-VS
549
103
625
3
211
103
287
4
23.7
23.7
23.7
23.7
23.7
23.7
292
256
99.7
99.7
99.7
99.7
99.7
99.7
368
5
431
507
6
601
677
7
760
836
-VS
8
862
938
-VS
9
993
1069
1298
1298
1298
1298
1069
938
-VS
10
11
12
13
14
15
16
17
18
19
1222
1222
1222
1222
993
VOUT
VOUT
+VS
459
535
639
715
806
882
+VS
1074
1074
1074
1074
1074
1074
1150
1150
1150
1150
1150
1150
+VS
862
+VS
760
836
DNC
PD
601
677
431
507
REF
180
256
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
33
UNIT
V
Supply voltage, (+VS) –(–VS)
Supply voltage turnon, turnoff maximum dV/dT (2)
1
V/µs
Voltage
Input/output voltage range
(+VS) + 0.5
±0.5
±10
(–VS) –0.5
V
Differential input voltage
Continuous input current (3)
Current
mA
Continuous output current (3)
±100
150
Maximum
(4)
Junction temperature, TJ
Continuous operation, long-term reliability
125
Temperature
°C
(5)
Storage temperature, Tstg
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Stay below this dV/dT supply turnon and turnoff edge rate to make sure that the edge-triggered ESD absorption device across the
supply pins remains open. Exceeding this supply edge rate may transiently show a short circuit across the supplies.
(3) Long-term continuous current for electro-migration limits.
(4) Thermal shutdown at approximately 160°C junction temperature and recovery at approximately 145°C.
(5) See the MSL or reflow rating information provided with the material or see https://www.ti.com for the latest information.
8.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±7
NOM
±15
30
MAX
±16
32
UNIT
V
Dual-supply
(+VS) –(–
VS)
Supply voltage
Single-supply
14
TA
Operating free-air temperature
85
°C
–40
8.4 Thermal Information
THS3491
THERMAL METRIC(1)
DDA (HSOIC)
8 PINS
44.5
RGT (VQFN)
8 PINS
49.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
66.8
55.4
19.2
23.1
6.4
1.8
ψJT
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
19.5
23.2
ψJB
RθJC(bot)
7.5
7.8
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package ThermalMetrics application
report.
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8.5 Electrical Characteristics: VS = ±15 V
at +VS = +15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V, and RGT
package: RF = 576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
Test
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX UNIT
Level(1)
SSBW
LSBW
Small-signal bandwidth
Large-signal bandwidth
Bandwidth for 0.2-dB flatness
Slew rate (20% –80%)
Overshoot and undershoot
Rise and fall time
VO = 2 VPP, < 0.5-dB peaking
VO = 10 VPP, < 1-dB peaking
VO = 2 VPP
900
320
MHz
MHz
MHz
V/µs
C
C
C
C
C
C
C
350
SR
VO = 20 VPP
8000
1.5%
1.3
VO = 10-V step (input tr/tf = 1.0 ns)
VO = 10-V step (input tr/tf = 1.0 ns)
VO = 10-V step (input tr/tf = 1.0 ns)
f = 20 MHz, VO = 10 VPP
f = 50 MHz, VO = 10 VPP
f = 70 MHz, VO = 10 VPP
f = 100 MHz, VO = 10 VPP
f = 20 MHz, VO = 20 VPP
f = 50 MHz, VO = 20 VPP
f = 70 MHz, VO = 20 VPP
f = 100 MHz, VO = 20 VPP
f = 20 MHz, VO = 10 VPP
f = 50 MHz, VO = 10 VPP
f = 70 MHz, VO = 10 VPP
f = 100 MHz, VO = 10 VPP
f = 20 MHz, VO = 20 VPP
f = 50 MHz, VO = 20 VPP
f = 70 MHz, VO = 20 VPP
f = 100 MHz, VO = 20 VPP
tr/tf
ts
ns
ns
Settling time to 0.1%
7
–78
–76
–68
–60
–75
–65
–61
–51
–81
–75
–61
–51
–64
–55
–48
–47
HD2
Second-order harmonic distortion
dBc
C
HD3
Third-order harmonic distortion
dBc
dBc
C
C
2nd-order two-tone intermodulation f = 20 MHz, VO = 5 VPP per tone,
distortion 100-kHz tone spacing
IMD2
–79
3rd-order two-tone intermodulation f = 20 MHz, VO = 5 VPP per tone,
IMD3
en
dBc
C
C
C
–68
1.7
distortion
100-kHz tone spacing
Input-referred voltage noise
f ≥100 kHz
nV/√Hz
pA/√Hz
Noninverting, input-referred current
noise
inp
15
f ≥100 kHz
Inverting, input-referred current
noise
inn
20
1
C
C
f ≥100 kHz
pA/√Hz
ZOUT
Closed-loop output impedance
f = 50 MHz
Ω
DC PERFORMANCE
ZOL
Open-loop transimpedance gain
5
–2
8
1
A1
A1
A1
B
VO = ±10 V, RLOAD = 500 Ω
DDA package only
MΩ
mV
2
VOS
Input offset voltage
RGT package & DIE sales
–40°C ≤TJ ≤+125°C
1
2.5
mV
–2.5
Input offset voltage drift(2)
3
µV/°C
µA
IB+
Noninverting input bias current(3)
7
A1
–7
–2
Noninverting input bias current
drift(2)
nA/°C
µA
B
–40°C ≤TJ ≤+125°C
–8
–7
IB-
Inverting input bias current(3)
20
A1
–20
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8.5 Electrical Characteristics: VS = ±15 V (continued)
at +VS = +15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V, and RGT
package: RF = 576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
Test
PARAMETER
TEST CONDITIONS
–40°C ≤TJ ≤+125°C
MIN
TYP
–116
1.5
MAX UNIT
Level(1)
Inverting input bias current drift(2)
nA/°C
B
Internal trace resistance to
feedback pin
RFB_TRACE
RGT only, pins 10 and 11 to pin 1
f = DC
1.1
69
1.9
A2
A1
Ω
CMRR
INPUT
HRIN
Common-mode rejection ratio
75
dB
Headroom to either supply
Noninverting input impedance
Inverting input impedance
CMRR > 60 dB
4.1
4.3
18
V
kΩ|| pF
Ω
A2
C
ZIN+
Closed-loop measurement
Open-loop measurement
50 || 1.2
8
ZIN-
15
B
OUTPUT
HROUT
Headroom to either supply
Maximum current output
1.2
1.5
1.7
V
A1
A2
RLOAD = 24 Ω, VO = ±12.67 V,
magnitude, both polarities
IoutMAX
480
520
550
mA
RLOAD = 24 Ω, VO = ±9.4 V,
ZOL > 1 MΩ, source and sink
IoutLINEAR
Linear output current
380
500
550
420
540
mA
mA
A2
B
Peak output current in transition
(transition peak at zero-crossing
VO = 0 V, RO < 0.5 Ω, magnitude,
both polarities
IoutPEAK
IOUT
)
VS = ±9 V, VO = ±6 V, magnitude,
both polarities
ISC
Output short-circuit current
DC output impedance
620
mA
B
C
ZOUT
Closed-loop (±50 mA)
0.17
Ω
POWER SUPPLY
VS = ±15 V, No load
VS = ±16 V, No load
VS = ±7 V, No load
16.1
16.2
15.2
16.7
16.8
15.8
17.3
17.4
16.3
mA
mA
mA
A1
A2
A1
IQ
Quiescent current
VS = ±15 V, TJ = –40°C to +125°C,
No load
IQ TC
5
82
80
µA/°C
dB
B
PSRR+
PSRR–
Positive power supply rejection ratio
78
77
A1
A1
+VS ± 1.5 V, –VS
+VS, –VS ± 1.5 V
Negative power supply rejection
ratio
dB
POWER DOWN
REFRANGE REF pin voltage range
IREF_BIAS
GND +Vs –5
Do NOT float the REF pin.
V
A2
A2
–Vs
V
REF = 0 V, PD = REF + 3 V,
positive out of the pin.
REF pin bias current
35
46
52
µA
VIL
VIH
Disable voltage threshold
Enable voltage threshold
REF = 0 V, guaranteed off below
REF = 0 V, guaranteed on above
0.8
V
V
A1
A1
1.5
17
PD = REF = GND,
positive out of the pin.
PD LOW_BIAS PD pin low input bias current
PD HIGH_BIAS PD pin high input bias current
21
0
25
1
µA
µA
A2
A2
PD = REF + 3 V, REF = GND,
positive out of the pin.
–1
IQ_OFF_+VS
IQ_OFF_–VS
tON
+Vs disabled supply current
–Vs disabled supply current
Turnon time delay
650
600
780
723
50
880
820
µA
µA
ns
µs
A1
A2
C
DC output to 90% of final value
DC output to 10% of final value
tOFF
Turnoff time delay
4
C
JUNCTION-TEMPERATURE SENSE, TJ_SENSE (QFN-16 ONLY, PIN 6)
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.5 Electrical Characteristics: VS = ±15 V (continued)
at +VS = +15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V, and RGT
package: RF = 576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
Test
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Level(1)
Device disabled (22°C to 32°C ATE
ambient temperature)
TJ_ SENSE 25°C value
0.915
1.06
1.15
V
A2
TJ_ SENSE temperature coefficient
TJ_ SENSE input impedance
TJ = 0°C to 125°C
3.2
35
mV/°C
B
Internally connected to REF pin
32.4
38
A2
kΩ
(1) Test levels (all values set by characterization and simulation): (A1) 100% tested at ≈25°C for all devices, overtemperature limits by
characterization and simulation; (A2) 100% tested at ≈25°C for packaged devices, not tested in production for die sales (B) Not
tested in production, limits set by characterization and simulation; (C) Typical value only for information;
(2) Input offset voltage drift and input bias current drift are average values calculated by taking data at the end points, computing the
difference, and dividing by the temperature range.
(3) Current is considered positive out of the pin.
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.6 Electrical Characteristics: VS = ±7.5 V
at +VS = +7.5 V, –VS = –7.5 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V, and RGT
package: RF = 576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
Test
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX UNIT
Level(1)
SSBW
LSBW
SR
Small-signal bandwidth
VO = 2 VPP, < 0.5-dB peaking
VO = 5 VPP, < 1-dB peaking
VO = 10 VPP
800
550
MHz
MHz
V/µs
dBc
C
C
C
C
C
C
Large-signal bandwidth
Slew rate (20%-80%)
6000
–83
–78
1.7
HD2
HD3
en
Second-order harmonic distortion
Third-order harmonic distortion
Input-referred voltage noise
f = 20 MHz, VO = 5 VPP
f = 20 MHz, VO = 5 VPP
dBc
f ≥100 kHz
f ≥100 kHz
nV/√Hz
pA/√Hz
Noninverting, input-referred current
noise
inp
15
C
Inverting, input-referred current
noise
inn
20
1
C
C
f ≥= 100 kHz
pA/√Hz
ZOUT
Closed-loop output impedance
f = 50 MHz
Ω
DC PERFORMANCE
ZOL
Open-loop transimpedance gain
6
–2
14
1
A1
A1
A1
B
VO = ±2.5 V, RLOAD = 500 Ω
DDA package limits
MΩ
2
mV
mV
VOS
Input offset voltage
RGT package & die sales limits
–40°C ≤TJ ≤+125°C
1
2.5
–2.5
Input offset-voltage drift(2)
3
µV/°C
µA
IB+
Noninverting input bias current(3)
-2
7
A1
–7
Noninverting input bias current
drift(2)
nA/°C
B
–40°C ≤TJ ≤+125°C
–40°C ≤TJ ≤+125°C
–10
IB–
Inverting input bias current(3)
19
µA
A1
B
–19
–6
Inverting input bias current drift(2)
nA/°C
–112
INPUT
ZIN+
Noninverting input impedance
Inverting input impedance
Headroom to either supply
Closed-loop measurement
Open-loop measurement
CMRR > 60 dB
35 || 1.2
C
C
B
kΩ|| pF
ZIN–
15
Ω
HRIN
4.1
4.3
1.7
V
OUTPUT
HROUT
Headroom to either supply
Linear output current
1.2
1.5
V
A1
A2
RLOAD = 24 Ω, VO = ±5 V,
ZOL > 1 MΩ, source and sink
IoutLINEAR
200
230
mA
POWER SUPPLY
IQ
Quiescent current
No load
15.2
15.8
16.4
mA
A1
POWER DOWN
REFRANGE
IREF_BIAS
REF pin voltage range
Do NOT float the REF pin.
V
B
–Vs GND +Vs –5 V
REF = 0 V, PD = REF + 3 V,
positive out of the pin
REF pin bias current
35
37
52
µA
A2
VIL
VIH
Disable voltage threshold
Enable voltage threshold
REF = 0 V, guaranteed off below
REF = 0 V, guaranteed on above
0.8
V
V
A1
A1
1.5
17
PD = REF = GND,
positive out of the pin.
PD LOW_BIAS PD pin low input bias current
PD HIGH_BIAS PD pin high input bias current
21
0
25
1
µA
µA
A2
A2
PD = REF + 3 V, REF = GND,
positive out of the pin.
–1
IQ_OFF_+VS
IQ_OFF_–VS
+Vs disabled supply current
600
550
700
642
850
770
µA
µA
A1
A2
–Vs disabled supply current
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.6 Electrical Characteristics: VS = ±7.5 V (continued)
at +VS = +7.5 V, –VS = –7.5 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V, and RGT
package: RF = 576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
Test
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Level(1)
JUNCTION-TEMPERATURE SENSE, TJ_SENSE (QFN-16 ONLY, PIN 6)
Device disabled (22°C to 32°C ATE
ambient temperature)
TJ_ SENSE 25°C value
0.915
32.4
1.06
1.15
38
V
A2
TJ_SENSE temperature coefficient
TJ_SENSE input impedance
TJ = 0°C to 125°C
3.2
35
mV/°C
B
B
Internally connected to REF pin
kΩ
(1) Test levels (all values set by characterization and simulation): (A1) 100% tested at ≅ 25°C for all devices, overtemperature limits by
characterization and simulation; (A2) 100% tested at ≅ 25°C for packaged devices, not tested in production for die sales (B) Not tested
in production, limits set by characterization and simulation; (C) Typical value only for information;
(2) Input offset voltage drift and input bias current drift are average values calculated by taking data at the end points, computing the
difference, and dividing by the temperature range.
(3) Current is considered positive out of the pin.
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.7 Typical Characteristics: ±15 V
at +VS = 15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V. RGT package : RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
3
3
0
0
-3
-3
-6
-6
-9
-9
G = 2 V/V, RF = 976
G = 5 V/V, RF = 576
G = 10 V/V, RF = 499
W
W
W
W
G = 2 V/V, RF = 2100
W
G = 5 V/V, RF = 798
G = 10 V/V, RF = 704
G = 20 V/V, RF = 564
W
-12
-15
-12
-15
W
W
G = 20 V/V, RF = 383
1
10
100
Frequency (MHz)
1000
4000
1
10
100
Frequency (MHz)
1000
4000
D001
D006
VO = 2 VPP
RGT package
VO = 2 VPP
DDA package
图8-1. Noninverting Small-Signal Frequency Response
图8-2. Noninverting Small-Signal Frequency Response
3
18
0
-3
15
12
9
-6
-9
6
VO = 2 VPP
VO = 5 VPP
-12
G = -2 V/V, RF = 604
G = -5 V/V, RF = 576
G = -10 V/V, RF = 549
W
W
VO = 10 VPP
VO = 20 VPP
VO = 26 VPP
3
0
-15
-18
W
10
100
Frequency (MHz)
1000
4000
1
10
100
Frequency (MHz)
1000
4000
D018
D002
VO = 2 VPP
RGT package; see 节9.4.4 section for more details
图8-4. Frequency Response vs Output Swing
图8-3. Inverting Small-Signal Frequency Response
18
18
15
12
9
15
12
9
6
3
0
6
RS = 20-W, CL = 10 pF
RS = 15-W, CL = 22 pF
RS = 10-W, CL = 47 pF
RS = 7.5-W, CL = 100 pF
T = -40èC
T = 25èC
T = 85èC
T = 105èC
-3
-6
-9
3
0
10
100
Frequency (MHz)
1000
4000
10
100
Frequency (MHz)
1000
4000
D016
D017
VO = 2 VPP
RGT package
RGT package; see 图10-1 for setup information
图8-5. Frequency Response vs CLOAD
图8-6. Frequency Response vs Temperature
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.7 Typical Characteristics: ±15 V (continued)
at +VS = 15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V. RGT package : RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
VO = 2 VPP
VO = 10 VPP
VO = 20 VPP
VO = 2 VPP
VO = 10 VPP
VO = 20 VPP
0.1
1
10
Frequency (MHz)
100 200
0.1
1
10
Frequency (MHz)
100 200
D065
D066
DDA package
DDA package
图8-7. HD2 vs Frequency
图8-8. HD3 vs Frequency
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
G = 5 V/V
G = -5 V/V
G = 2 V/V
G = 5 V/V
G = -5 V/V
G = 2 V/V
-40
-50
-60
-70
-80
-90
-100
-110
-120
0.1
1
10
Frequency (MHz)
100
500
0.1
1
10
Frequency (MHz)
100
500
D007
D008
VO = 2 VPP
RGT package
VO = 2 VPP
RGT package
图8-9. HD2 vs Frequency
图8-10. HD3 vs Frequency
-20
-30
-40
-50
-60
-70
-80
-90
-20
-30
G = 5 V/V, VO = 10 VPP
G = 5 V/V, VO = 10 VPP
G = -5 V/V, VO = 10 VPP
G = 5 V/V, VO = 20 VPP
G = -5 V/V, VO = 20 VPP
G = -5 V/V, VO = 10 VPP
G = 5 V/V, VO = 20 VPP
G = -5 V/V, VO = 20 VPP
-40
-50
-60
-70
-80
-90
-100
-110
0.1
1
10
Frequency (MHz)
100 200
0.1
1
10
Frequency (MHz)
100 200
D009
D010
图8-11. HD2 vs Frequency Across Output Swing
图8-12. HD3 vs Frequency Across Output Swing
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8.7 Typical Characteristics: ±15 V (continued)
at +VS = 15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V. RGT package : RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
0
-10
0
-10
f = 10 MHz, RL = 100 W
f = 100 MHz, RL = 100 W
f = 10 MHz, RL = 1 kW
f = 100 MHz, RL = 1 kW
f = 10 MHz, RL = 100 W
f = 100 MHz, RL = 100 W
f = 10 MHz, RL = 1 kW
f = 100 MHz, RL = 1 kW
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Voltage Swing (VPP
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Voltage Swing (VPP
)
)
D011
D012
图8-13. HD2 vs Output Swing
图8-14. HD3 vs Output Swing
-30
-40
-50
-60
-70
-80
-90
-100
-30
-40
T = -40èC
T = -40èC
T = 25èC
T = 85èC
T = 105èC
T = 25èC
T = 85èC
T = 105èC
-50
-60
-70
-80
-90
-100
-110
-120
0.1
1
10
Frequency (MHz)
100
500
0.1
1
10
Frequency (MHz)
100
500
D013
D014
VO = 2 VPP
VO = 2 VPP
图8-15. HD2 vs Frequency Across Temperature
图8-16. HD3 vs Frequency Across Temperature
-10
-30
HD2
HD3
-20
-30
-40
-50
-40
-60
-50
-70
-60
-80
-70
-90
-80
-100
-110
-120
-90
IMD2
IMD3
-100
-110
0.1
1
10
Frequency (MHz)
100
500
1
10
Frequency (MHz)
100
500
D015
D038
VO = 2 VPP
VO = 5 VPP per tone
±100-kHz frequency spacing
RLoad = 1 kΩ
图8-18. Intermodulation Distortion vs Frequency
图8-17. Harmonic Distortion vs Frequency
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.7 Typical Characteristics: ±15 V (continued)
at +VS = 15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V. RGT package : RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f = 20 MHz
f = 50 MHz
f = 100 MHz
f = 20 MHz
f = 50 MHz
f = 100 MHz
2
4
6
Output Voltage Swing per tone (VPP
8
10
)
12
2
4
6
Output Voltage Swing per tone (VPP)
8
10
12
D061
D062
±100-kHz frequency spacing
±100-kHz frequency spacing
图8-19. IMD2 vs Output Voltage Swing
图8-20. IMD3 vs Output Voltage Swing
1000
1000
140
0
Vn
Inp
Inm
ZOL (dBW)
Phase (deg)
130
120
110
100
90
-15
-30
-45
100
10
1
100
10
1
-60
-75
80
-90
70
-105
-120
-135
-150
60
50
40
100
1k
10k
100k 1M
Frequency (Hz)
10M
100M
1G
100
1000
10000 100000
Frequency (Hz)
1000000
1E+7
D072
D003
图8-21. Spot Input Noise vs Frequency
No load
图8-22. Open-Loop Transimpedance Gain and Phase vs
Frequency
6
5
12
VIN
VOUT
VIN
VOUT
10
8
4
3
6
4
2
1
2
0
0
-1
-2
-3
-4
-5
-6
-2
-4
-6
-8
-10
-12
Time (4 nsec/div)
Time (4 nsec/div)
D005
D004
VO = 10 VPP
VO = 20 VPP
图8-23. G = 5 V/V Pulse Response
图8-24. G = 5 V/V Pulse Response
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.7 Typical Characteristics: ±15 V (continued)
at +VS = 15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V. RGT package : RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
6
5
12
10
8
VIN
VOUT
VIN
VOUT
4
3
6
2
4
1
2
0
0
-1
-2
-3
-4
-5
-6
-2
-4
-6
-8
-10
-12
Time (4 nsec/div)
Time (4 nsec/div)
D032
D033
VO = 10 VPP
VO = 20 VPP
图8-25. G = –5 V/V Pulse Response
图8-26. G = –5 V/V Pulse Response
500
100
16
4.8
VOUT (AV = +5)
VIN x 5 gain
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
4.2
3.6
3
2.4
1.8
1.2
0.6
0
-0.6
-1.2
-1.8
-2.4
-3
-3.6
-4.2
-4.8
10
1
0.1
0.05
10
100
Frequency (MHz)
1000
Time (100 nsec/div)
D019
D021
图8-27. Output Impedance vs Frequency
图8-28. Overdrive Recovery Time
-10
-20
-30
-40
-50
-60
-70
17.6
17.2
16.8
16.4
16
15.6
15.2
14.8
14.4
14
TA = -40èC
TA = 25èC
TA = 85èC
G = 5 V/V
G = -5 V/V
12 14 16 18 20 22 24 26 28 30 32 34
Single-supply Voltage VS (V)
0.1
1
10
100
Frequency (MHz)
D041
D031
图8-30. Quiescent Current vs Supply Voltage
VIN = 2 VPP
图8-29. Shutdown Feedthrough vs Frequency
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ZHCSHX6C –AUGUST 2017 –REVISED FEBRUARY 2023
8.7 Typical Characteristics: ±15 V (continued)
at +VS = 15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V. RGT package : RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
15
12
9
4500
4000
3500
3000
2500
2000
1500
1000
500
30-V Supply
15-V Supply
6
Source, TA = -40èC
Source, TA = 25èC
Source, TA = 85èC
Sink, TA = -40èC
Sink, TA = 25èC
3
0
-3
-6
-9
-12
-15
Sink, TA = 85èC
0
0
50 100 150 200 250 300 350 400 450 500 550 600
IOUT (mA)
D043
D045
Input Offset Voltage (mV)
A. Measured with devices soldered on TI EVM. Devices not
turned off at any read points but load applied for a few
milliseconds to measure VOUT and then removed.
图8-31. Output Voltage Swing vs Output Current
7100 units at each supply
图8-32. Input Offset Voltage Distribution
5000
4000
3750
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
30-V Supply
15-V Supply
30-V Supply
15-V Supply
4500
4000
3500
3000
2500
2000
1500
1000
500
500
250
0
0
-20 -16 -12 -8
-4
0
4
8
12 16 20
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
Inverting IB (mA)
Non-inverting IB (mA)
D046
D047
7100 units at each supply
7100 units at each supply
图8-34. Noninverting IB Distribution
图8-33. Inverting IB Distribution
2
1.8
1.6
1.4
1.2
1
15
12.5
10
7.5
5
2.5
0
-2.5
-5
0.8
0.6
0.4
0.2
0
-7.5
-10
-12.5
-15
-17.5
-20
-40 -25 -10
5
20 35 50 65 80 95 110 125
TA Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TA Temperature (èC)
D048
D050
Flash tested to keep TJ as close to TA as possible
Flash tested to keep TJ as close to TA as possible
图8-35. Input Offset Voltage Over Temperature
图8-36. Inverting IB Over Temperature
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8.7 Typical Characteristics: ±15 V (continued)
at +VS = 15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V. RGT package : RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
-0.5
-1
65
60
55
50
45
40
35
30
25
20
15
10
5
30-V Supply
15-V Supply
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TA Temperature (èC)
-10 -8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (mV/èC)
D051
D052
Flash tested to keep TJ as close to TA as possible
90 units at each supply
图8-37. Noninverting IB Over Temperature
图8-38. Input Offset Voltage Drift Histogram
45
40
35
30
25
20
15
10
5
36
33
30
27
24
21
18
15
12
9
30-V Supply
15-V Supply
30-V Supply
15-V Supply
6
3
0
0
-165 -150 -135 -120 -105 -90 -75 -60 -45 -30 -15
-Ib Drift (nA/èC)
0
-40 -35 -30 -25 -20 -15 -10 -5
+Ib Drift (nA/èC)
0
5
10 15
D053
D054
90 units at each supply
90 units at each supply
图8-40. Noninverting IB Drift Histogram
图8-39. Inverting IB Drift Histogram
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
0.75
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature TA (èC)
D075
Device in shutdown mode to minimize self-heating, RGT package
图8-41. TJ_SENSE Voltage vs Ambient Temperature
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8.8 Typical Characteristics: ±7.5 V
at +VS = 7.5 V, –VS = –7.5 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V RGT package: RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
3
0
3
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-12
-15
-18
G = 2, RF = 976-W
G = 5, RF = 576-W
G = 10, RF = 499-W
G = 20, RF = 383-W
G = -2 V/V, RF = 832
G = -5 V/V, RF = 749
G = -10 V/V, RF = 719
W
W
W
10
100
Frequency (MHz)
1000
4000
10
100
Frequency (MHz)
1000
4000
D023
D068
VO = 2 VPP
VO = 2 VPP
图8-42. Noninverting Small-Signal Frequency Response
图8-43. Inverting Small-Signal Frequency Response
-20
-20
G = 5 V/V
G = -5 V/V
G = 2 V/V
G = 5 V/V
G = -5 V/V
G = 2 V/V
-30
-30
-40
-50
-60
-70
-80
-90
-100
-40
-50
-60
-70
-80
-90
-100
-110
-120
0.1
1
10
Frequency (MHz)
100
500
0.1
1
10
Frequency (MHz)
100
500
D024
D025
VO = 2 VPP
VO = 2 VPP
图8-44. HD2 vs Frequency
图8-45. HD3 vs Frequency
-20
-30
-40
-50
-60
-70
-80
-90
-20
-30
VO = 5 VPP
VO = 10 VPP
VO = 5 VPP
VO = 10 VPP
-40
-50
-60
-70
-80
-90
-100
-110
0.1
1
10
Frequency (MHz)
100 200
0.1
1
10
Frequency (MHz)
100 200
D026
D027
图8-46. HD2 vs Frequency Across Output Swing
图8-47. HD3 vs Frequency Across Output Swing
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8.8 Typical Characteristics: ±7.5 V (continued)
at +VS = 7.5 V, –VS = –7.5 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V RGT package: RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
0
-10
0
-10
f = 10 MHz, RL = 100 W
f = 100 MHz, RL = 100 W
f = 10 MHz, RL = 1 kW
f = 100 MHz, RL = 1 kW
f = 10 MHz, RL = 100 W
f = 100 MHz, RL = 100 W
f = 10 MHz, RL = 1 kW
f = 100 MHz, RL = 1 kW
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
1
2
3
4
Output Voltage Swing (VPP
5
6
7
8
9
10 11 12
0
1
2
3
4
Output Voltage Swing (VPP)
5
6
7
8
9
10 11 12
)
D028
D029
图8-48. HD2 vs Output Swing
图8-49. HD3 vs Output Swing
-30
-40
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
HD2
HD3
IMD2
IMD3
-50
-60
-70
-80
-90
-100
-110
-120
0.1
1
10
Frequency (MHz)
100
500
1
10
Frequency (MHz)
100
500
D030
D039
VO = 2.5 VPP per tone
±100-kHz frequency spacing
VO = 2 VPP
图8-50. Harmonic Distortion vs Frequency
RLOAD = 1 kΩ
图8-51. Intermodulation Distortion vs Frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
f = 20 MHz
f = 50 MHz
f = 100 MHz
f = 20 MHz
f = 50 MHz
f = 100 MHz
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
1
2
Output Voltage Swing per tone (VPP
3
4
5
)
6
0
1
2
Output Voltage Swing per tone (VPP
3
4
5
)
6
D063
D064
±100-kHz frequency spacing
±100-kHz frequency spacing
图8-52. IMD2 vs Output Voltage Swing
图8-53. IMD3 vs Output Voltage Swing
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8.8 Typical Characteristics: ±7.5 V (continued)
at +VS = 7.5 V, –VS = –7.5 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V RGT package: RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
3
2.5
2
6
5
VIN
VOUT
VIN
VOUT
4
1.5
1
3
2
0.5
0
1
0
-0.5
-1
-1
-2
-3
-4
-5
-6
-1.5
-2
-2.5
-3
Time (4 nsec/div)
Time (4 nsec/div)
D034
D035
VO = 5 VPP
VO = 10 VPP
图8-54. G = 5 V/V Pulse Response
图8-55. G = 5 V/V Pulse Response
3
2.5
2
6
5
VIN
VOUT
VIN
VOUT
4
1.5
1
3
2
0.5
0
1
0
-0.5
-1
-1
-2
-3
-4
-5
-6
-1.5
-2
-2.5
-3
Time (4 nsec/div)
Time (4 nsec/div)
D036
D037
VO = 5 VPP
VO = 10 VPP
图8-56. G = –5 V/V Pulse Response
图8-57. G = –5 V/V Pulse Response
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8.8 Typical Characteristics: ±7.5 V (continued)
at +VS = 7.5 V, –VS = –7.5 V, TA ≅ 25°C, RLOAD = 100 Ωto midsupply, noninverting gain (G) = 5 V/V RGT package: RF =
576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω(unless otherwise noted)
8
7
6
5
4
3
2
1
0
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
7
6
VOUT (AV = +5)
VIN x 5 gain
5
4
3
Source, TA = -40èC
Source, TA = 25èC
Source, TA = 85èC
Sink, TA = -40èC
Sink, TA = 25èC
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-0.3
-0.6
-0.9
-1.2
-1.5
-1.8
-2.1
-2.4
-1
-2
-3
-4
-5
-6
-7
Sink, TA = 85èC
0
50 100 150 200 250 300 350 400 450 500 550 600
IOUT (mA)
Time (100 nsec/div)
D022
D044
图8-58. Overdrive Recovery Time
Measured with devices soldered on TI EVM. Devices not
turned off at any read points but load applied for a few msec
to measure VOUT and then removed.
图8-59. Output Voltage Swing vs Output Current
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TA Temperature (èC)
D049
Flash tested to keep TJ as close to TA as possible
图8-60. Input Offset Voltage Over Temperature
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9 Detailed Description
9.1 Overview
The THS3491 is a high-voltage, low-distortion, high-speed, current-feedback amplifier designed to operate over
a wide supply range of ±7 V to ±16 V for applications requiring large, linear output swings such as arbitrary
waveform generators.
The THS3491 features a power-down pin that puts the amplifier in low power standby mode and lowers the
quiescent current from 16.7 mA to 750 µA.
The RGT package also features a feedback pin (pin 1). Internally on the die this pin is connected to the
amplifier's output. This feedback pin arrangement minimizes the PCB trace lengths in the feedback path for the
connection from the feedback resistor to the inverting input and output pins. This in turn minimizes the board
parasitics in the feedback path, thus allowing to maximize bandwidth with minimal peaking.
9.2 Functional Block Diagram
VSIG
VIN+
+
VREF
(1 + RF/RG)VSIG
.(s)
VO
VREF
THS3491
ZINœ
VINœ
ZOL(s)×Ierr
œ
Ierr
RF
AV = VO/VIN+ = 1 + (RF/RG)
RG
VREF
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9.3 Feature Description
9.3.1 Power-Down (PD) Pin
The THS3491 features a power-down ( PD) pin that lowers the quiescent current from 16.7 mA down to 750 µA,
which is designed to reduce system power.
The power-down pin of the amplifier defaults to 2 V below the positive supply voltage in the absence of an
externally applied voltage, which places the amplifier in the power-on mode of operation. To turn off the amplifier
in an effort to conserve power, the power-down pin can be pulled low. The PD pin threshold voltages are
specified with respect to the REF pin voltage. The threshold voltages for power on and power down are relative
to the REF pin and are shown in the 节 8.5 and 节 8.6 tables. Above the enable threshold voltage, the device is
on. Below the disable threshold voltage, the device is off. The behavior is not specified between these threshold
voltages.
This power-down functionality helps the amplifier consume less power in power-down mode. Power-down mode
is not intended to provide a high-impedance output. The power-down functionality is not intended for use as a tri-
state bus driver. In power-down mode, the impedance looking back into the output of the amplifier is dominated
by the feedback and gain-setting resistors, but the output impedance of the device varies depending on the
voltage applied to the outputs.
As with most current-feedback amplifiers, the internal architecture places limitations on the system in power-
down mode. The most common limitation is that the amplifier turns on if there is a ±1 V or greater difference
between the two input nodes (VIN+ and VIN–) of the amplifier. If this difference exceeds ±1 V, the amplifier
creates an output voltage equal to approximately [(VIN+ –VIN–) –0.7 V] × gain. Conversely if a voltage is
applied to the output while in power-down mode, the VIN– node voltage is equal to VO(applied) × RG / (RF + RG).
For low-gain configurations and a large applied voltage at the output, the amplifier may turn on because of the
aforementioned behavior.
The time delays associated with turning the device on and off are specified as the time it takes for the amplifier
to reach 10% or 90% of the final output voltage. The time delays are in nanoseconds during power on and
microseconds during power off because the amplifier moves out of linear operating mode for power-off
conditions.
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9.3.2 Power-Down Reference (REF) Pin
In addition to the power-down pin, the DDA package features a reference pin (REF) that allows control over the
enable or disable power-down voltage levels applied to the PD pin. This reference pin is explicitly pinned out on
the DDA package as the REF pin. However, on the RGT package, the reference pin refers to pin 5 (GND), which
must be connected to GND. In most split-supply applications, the reference pin is connected to ground. In either
case, be aware of voltage-level thresholds that apply to the power-down pin. 表 9-1 provides examples and
shows the relationship between the reference voltage and the power-down thresholds. In 表 9-1, the threshold
levels are derived by the conditions that follow:
• PD ≤REF + 0.8 V (Disable)
• PD ≥REF + 1.5 V (Enable)
where the usable range at the REF pin is:
• VS–≤VREF ≤(VS+ –5 V)
表9-1. Example Power-Down Threshold Voltage Levels
SUPPLY
VOLTAGE (V)
REFERENCE PIN
VOLTAGE (V)
ENABLE
LEVEL (V)
DISABLE
LEVEL (V)
±15, ±7, 30
0
2
1.5
3.5
0.8
2.8
±15
±15
±7
–2
1
–0.5
2.5
–1.2
1.8
±7
0.5
–1
15
7
–0.2
15.8
7.8
30
16.5
8.5
14
The recommended operating mode is to tie the REF pin to ground for single and split-supply operations, which
sets the enable and disable thresholds to 1.5 V and 0.8 V, respectively.
The REF pin must be tied to a valid potential within the recommended operating range of (–VS ≤V(REF) ≤+VS
– 5 V). Although the PD pin can be floated, TI does not recommend floating the PD pin in case stray signals
couple into the pin and cause unintended turnon or turnoff device behavior. However, if the PD pin is left
unterminated, the PD pin floats to 2 V below the positive rail and the device remains enabled. As a result, the
THS3491 DDA package is a drop-in replacement for the THS3091 DDA pinout if the REF pin (pin 1) is tied to a
valid potential. If balanced, split supplies are used (±VS) and the REF and PD pins are grounded, the device is
disabled.
9.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
The RGT package includes an internal, junction-temperature sense pin (TJ_SENSE). This pin is a temperature-
dependent current source from the positive supply into one side of the internal resistor, where the other side of
the internal resistor is connected to pin 5 (GND), the PD logic reference pin on the die. For simplicity, and to
keep the TJ_SENSE output ground referenced, tie pin 5 to ground (internally, the PD logic reference pin). If pin 5 is
tied to a voltage in the same range as the REF pin voltage for the DDA package, the output of the TJ_SENSE
voltage and input threshold voltages of the PD pin are level shifted.
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9.4 Device Functional Modes
9.4.1 Wideband Noninverting Operation
The THS3491 is a 900-MHz current-feedback operational amplifier that is designed to operate from a power
supply of ±7 V to ±16 V.
图9-1 shows the THS3491 in a noninverting gain configuration of 5 V/V which is used to generate the majority of
the performance curves. Most of the curves are characterized using signal sources with a 50-Ω source
impedance and measurement equipment presenting a 50-Ωload impedance.
15 V
+
0.1 …F
6.8 …F
RG
RF
143 ꢀ
576 ꢀ
49.9 ꢀ
œ
50-Ω Source
VI
+
THS3491
50-Ω Load
6.8 …F
RT
49.9 ꢀ
0.1 …F
+
œ15 V
图9-1. Wideband Noninverting Gain Configuration (5 V/V)
Current-feedback amplifiers are highly dependent on the RF feedback resistor for maximum performance and
stability. 表 9-2 provides the optimal resistor values for RF and RG at different gains to achieve maximum
bandwidth with minimal peaking in the frequency response. Use lower RF values for higher bandwidth. Note that
this can cause additional peaking and a reduction in phase margin. Conversely, increasing RF decreases the
bandwidth but phase margin increases and stability improves. To gain further insight on the feedback and
stability analysis of current-feedback amplifiers like the THS3491, see the Current-feedback Amplifiers section of
TI Precision Labs.
表9-2. Recommended Resistor Values for Minimum Peaking and Optimal Frequency Response
With RLOAD = 100 Ω
RGT PACKAGE
DDA PACKAGE
GAIN (V/V)
RG (Ω)
976
RF (Ω)
976
RG (Ω)
2.1k
RF (Ω)
2.1k
798
2
5
143
576
200
10
20
54.9
20
499
78.7
29.4
704
383
564
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9.4.2 Wideband, Inverting Operation
图 9-2 shows the THS3491 in a typical inverting gain configuration where the input and output impedances and
signal gain from 图9-1 are retained in an inverting circuit configuration.
15 V
+
0.1 …F
6.8 …F
RG
RF
50-Ω Source
115 ꢀ
576 ꢀ
VI
RT
88.7 ꢀ
49.9 ꢀ
œ
+
THS3491
50-Ω Load
6.8 …F
49.9 ꢀ
0.1 …F
+
œ15 V
图9-2. Wideband Inverting Gain Configuration (5 V/V)
9.4.3 Single-Supply Operation
The THS3491 operates from a single-supply voltage ranging from 14 V to 32 V. When operating from a single
power supply, biasing the input and output at midsupply allows for the maximum output voltage swing. 图 9-3
shows circuits that display noninverting (a) and inverting (b) amplifiers that are configured for single-supply
operation.
a) Noninverting Gain Configuration
+VS
+VS
2
+
0.1 …F
6.8 …F
RG
RF
143 ꢀ
576 ꢀ
49.9 ꢀ
œ
50-Ω Source
+
VI
THS3491
50-Ω Load
RT
49.9 ꢀ
+VS
2
+VS
b) Inverting Gain Configuration
+
0.1 …F
6.8 …F
RG
RF
50-Ω Source
115 ꢀ
576 ꢀ
VI
RT
49.9 ꢀ
œ
88.7 ꢀ
+
+VS
2
THS3491
50-Ω Load
49.9 ꢀ
+VS
2
图9-3. DC-Coupled, Single-Supply Operation
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9.4.4 Maximum Recommended Output Voltage
The THS3491 is designed to produce better than 40 dB SFDR while driving a 100-MHz, 20-Vpp signal into a 100-
Ω load. To accomplish this, the geometries of certain signal path transistors must be limited. As a result of this
limitation, some internal devices begin to saturate when large signal levels are input at frequencies greater than
100 MHz. When these devices saturate, the loop opens and the amplifier is no longer in linear operation. This
appears as a gain step-up in the frequency response curve. To avoid this phenomenon, applications must
comply with the recommended linear operating region shown in 图 9-4. 图 9-4 shows the maximum output
voltage vs frequency that is permitted to keep the amplifier in linear operation.
30
VS = ê 15V
VS = ê 7.5V
25
20
15
10
5
0
1
10
100
Frequency (MHz)
1000
D020
图9-4. Maximum Recommended Output Voltage vs Frequency
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
10.1.1 Driving Capacitive Loads
Applications such as power JFET and MOSFET (power FET) drivers are highly capacitive and cause stability
problems for high-speed amplifiers.
图10-1 and 图10-2 show recommended methods for driving capacitive loads. The basic idea is to use a resistor
or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier
feedback path. The output impedance of the amplifier in conjunction with CLOAD introduces a pole in the open-
loop transimpedance gain response and if the pole is at a frequency lower than the non-dominant pole of the
amplifier, then this results in a reduced loop gain and a reduced phase margin. The isolation resistor introduces
a zero in the response, which counteracts the effect of the pole. The location of the zero is dependent on the
values of RISO and CLOAD. 图 8-5 shows examples of the recommended RISO values to achieve flat frequency
response while driving certain capacitive loads. See Effect of Parasitic Capacitance in Op Amp Circuits for a
detailed analysis of selecting isolation resistor values while driving capacitive loads.
143 ꢀ
576 ꢀ
+VS
œ
RISO
1 ꢀ
+
VI
THS3491
RLOAD
CLOAD
49.9 ꢀ
1 kꢀ
1 …F
œVS
图10-1. Driving a Large Capacitive Load Using an Output Series Isolation Resistor
Placing a small series resistor (RISO) between the output of the amplifier and the capacitive load as 图 10-1
shows is a simple way to isolate the load capacitance.
图 10-2 shows two amplifiers in parallel to double the output drive current in order to drive larger capacitive
loads. This technique is used when more output current is required to charge and discharge the load faster, such
as driving large FET transistors.
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143 ꢀ
24.9 ꢀ
143 ꢀ
576 ꢀ
+VS
œ
2.49 ꢀ
+
THS3491
œVS
576 ꢀ
1 nF
VS
+VS
œ
2.49 ꢀ
24.9 ꢀ
+
THS3491
œVS
图10-2. Driving a Large Capacitive Load Using Two Parallel Amplifier Channels
图 10-3 shows a push-pull FET driver circuit commonly used in ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
+VS
+VS
THS3491
+
œ
2.49 ꢀ
œVS
576 ꢀ
286 ꢀ
576 ꢀ
+VS
œ
2.49 ꢀ
+
THS3491
œVS
œVS
图10-3. Power FET Drive Circuit
10.1.2 Video Distribution
The wide bandwidth, high slew rate, and high output drive current of the THS3491 meets the demands for video
distribution by delivering video signals down multiple cables. For high signal quality with minimal degradation of
performance, use a 0.1-dB gain flatness that is at least seven times the pass-band frequency to minimize group
delay variations from the amplifier. A high slew rate minimizes distortion of the video signal and supports
component video and RGB video signals that require fast transition and settling times for high signal quality.
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7.5 V
976 ꢀ
976 ꢀ
75-Ω Transmission Line
75 ꢀ
VO(1)
œ
+
VI
THS3491
75 ꢀ
n
75 ꢀ
Lines
75 ꢀ
VO(n)
œ7.5 V
75 ꢀ
图10-4. Video Distribution Amplifier Application
10.2 Typical Application
The fundamental concept of load sharing is to drive a load using two or more of the same operational amplifier.
Each amplifier is driven by the same source. 图10-5 shows two THS3491 amplifiers sharing the same load. This
concept effectively reduces the current load of each amplifier by 1/N, where N is the number of amplifiers.
a) Single THS3491 Amplifier Driving a Transmission Line
RG1
143 ꢀ
RF1
576 ꢀ
15 V
50-Ω Transmission Line
(TL1)
RS3
50 ꢀ
RSOURCE
50 ꢀ
VOUT
-
+
U3
THS3491
RLOAD
50 ꢀ
+
RT3
50 ꢀ
œ15 V
VIN
b) Two THS3491 Amplifiers Driving a Transmission Line
RG1
143 ꢀ
RF1
576 ꢀ
15 V
RS2
40.2 ꢀ
-
+
U1
THS3491
RT1
100 ꢀ
œ15 V
RT
30 ꢀ
50-Ω Transmission Line (TL2)
RSOURCE
50 ꢀ
VOUT
RG2
143 ꢀ
RF2
576 ꢀ
RLOAD
50 ꢀ
+
15 V
VIN
RS2
40.2 ꢀ
œ
+
U2
THS3491
RT2
100 ꢀ
œ15 V
图10-5. Load-Sharing Driver Application
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10.2.1 Design Requirements
Use two THS3491 amplifiers in a parallel load-sharing circuit to improve distortion performance.
表10-1. Design Parameters
DESIGN PARAMETER
VO (At amplifier output)
RLOAD
VALUE
20 VPP
100 Ω
Gain flatness at 100 MHz
Less than 0.5 dB
10.2.2 Detailed Design Procedure
In addition to providing higher output current drive to the load, the load-sharing configuration provides improved
distortion performance. In many cases, an operational amplifier shows greater distortion performance as the load
current decreases (that is, for higher resistive loads) until the feedback resistor dominates the current load. In a
load-sharing configuration of N amplifiers in parallel, the equivalent current load that each amplifier drives is 1/N
times the total load current. For example, in a two amplifier load- sharing configuration with matching resistance
(see 图 10-5) driving a resistive load (RLOAD), the total series resistance (RTOT_SERIES) at the output of the
amplifiers is 2 x RLOAD and each amplifier drives 2 x RLOAD. The total series resistance in the two-amplifier
configuration shown in 图 10-5 is the parallel combination of RS2 resistors in series with RT resistor (RTOT_SERIES
= RS2 || RS2 + RT). Such configuration of resistors at the output allows for fault detection if the load is shorted to
GND and can be used for filtering the signal going to the load.
图 10-5 shows two circuits: one of a single THS3491 amplifier driving a double-terminated, 50-Ω cable and one
of two THS3491 amplifiers in a load-sharing configuration. In the load-sharing configuration, the two 40.2-Ω
series output resistors act in parallel and in conjunction with the 30-Ω terminating resistor provide 50-Ω back-
matching to the 50-Ωcable.
图 10-6 shows the normalized frequency response for the two-amplifier load-sharing configuration. The total
load, RTOT_LOAD, for the configuration is the sum of RTOT_SERIES and RLOAD which is 100 Ω for the two-amplifier
configuration in 图10-5. 图10-7 shows the distortion performance of the two-amplifier configuration.
Benefit of the multiple amplifier's in load-sharing configuration becomes even more evident when the total load
increases. 图 10-8 and 图 10-9 show the HD2 and HD3 performance, respectively, in two, three, and four
amplifier configurations when the RTOT_LOAD = 20 Ω. HD2 improves by almost 13 dB and 24 dB, respectively in
the three and four amplifier configuration from the two-amplifier configuration, and HD3 shows an improvement
of almost 15 and 19 dB in the three and four amplifier configurations, respectively.
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10.2.3 Application Curves
3
2
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
0
-1
-2
-3
-4
-5
-6
HD2
HD3
1
10
Frequency (MHz)
100
10
100
Frequency (MHz)
D081
D081
VO (amplifier output) = 20 VPP
VO (amplifier output) = 20 VPP
RTOT_LOAD = 100 Ω
RTOT_LOAD = 100 Ω
图10-7. Distortion Of Two-Amplifier Configuration
图10-6. Frequency Response Of Two-Amplifier
Configuration in 图10-5 (Gain = 5 V/V, Measured At
in 图10-5 (Gain = 5 V/V, Measured At VOUT
)
VOUT
)
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-30
2 x THS3491
3 x THS3491
4 x THS3491
2 x THS3491
3 x THS3491
4 x THS3491
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
1
10
Frequency (MHz)
1
10
Frequency (MHz)
D083
D084
VO (amplifier output) = 20 VPP
RTOT_LOAD = 20 Ω
VO (amplifier output) = 20 VPP
RTOT_LOAD = 20 Ω
图10-8. HD2 For Amplifier Load-Sharing
图10-9. HD2 For Amplifier Load-Sharing
Configuration (Gain = 5 V/V)
Configuration (Gain = 5 V/V)
10.3 Power Supply Recommendations
The THS3491 operates from a single supply or with dual supplies if the input common-mode voltage range
(CMIR) has the required headroom (4.3 V) to either supply rail. Supplies must be decoupled with low inductance
(often ceramic) capacitors to ground less than 0.5 inches from the device pins. TI recommends using ground
planes, and as in most high-speed devices, removing ground planes close to device sensitive pins such as input
pins is advisable. An optional supply decoupling capacitor across the two power supplies (for split-supply
operation) improves second harmonic distortion performance.
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10.4 Layout
10.4.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the THS3491 requires careful attention
to board layout parasitic and external component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O
pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and power
planes must be unbroken elsewhere on the board.
• Minimize the distance (< 0.25 of an inch [6.35 mm] from the power supply pins to high-frequency 0.1-μF and
100-pF decoupling capacitors. At the device pins, the ground and power plane layout must not be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power supply connections must always be decoupled with these
capacitors Use larger tantalum decoupling capacitors (with a value of 6.8 µF or more) that are effective at
lower frequencies on the main supply pins. These can be placed further from the device and can be shared
among several devices in the same area of the printed circuit board (PCB).
• Careful selection and placement of external components preserve the high-frequency performance of the
THS3491. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter
overall layout. Keep leads and PCB trace length as short as possible. Never use wire-bound type resistors in
a high-frequency application. Because the output pin and inverting input pins are the most sensitive to
parasitic capacitance, always position the feedback and series output resistors, if any, as close to the
inverting input pins and output pins as possible, respectively. Place other network components such as input
termination resistors close to the gain setting resistors. Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values create significant time constants constraints? that can
degrade performance. Good axial metal film or surface-mount resistors feature approximately 0.2 pF
capacitance in shunt with the resistor. For resistor values greater than 2 kΩ, this parasitic capacitance adds a
pole or a zero that can effect circuit operation. Keep resistor values as low as possible and consistent with
load-driving considerations.
• Make connections to other wideband devices on the board with short direct traces or through onboard
transmission lines. For short connections, consider the trace and the input to the next device as a lumped
capacitive load. Use relatively wide traces of 0.05 inch to 0.1 inch (1.3 mm to 2.54 mm), preferably with open
ground and power planes around the traces. Estimate the total capacitive load and determine if isolation
resistors on the outputs are required. Low parasitic capacitive loads ( less than 4 pF) may not require series
resistance because the THS3491 is nominally compensated to operate with a 2-pF parasitic load. Higher
parasitic capacitive loads without a series resistance are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required and the 6-dB signal loss intrinsic to a twice-terminated
transmission line is acceptable, implement a matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques).
• A 50-Ωenvironment is not required onboard, and a higher impedance environment improves distortion as
shown in the distortion versus load plots; see 图8-7 and 图8-8. With a characteristic board trace impedance
based on board material and trace dimensions, a matching series resistor into the trace from the output of the
THS3491 is used. A terminating shunt resistor at the input of the destination device is also used. The
terminating impedance is the parallel combination of the shunt resistor and the input impedance of the
destination device. This total effective impedance must be set to match the trace impedance.
If the 6-dB attenuation of a twice-terminated transmission line is unacceptable, a long trace can be series
terminated at the source end only. Treat the trace as a capacitive load in this case. This termination does not
preserve signal integrity as well as a twice-terminated line. If the input impedance of the destination device is
low, there is some signal attenuation because of the voltage divider formed by the series output into the
terminating impedance.
• Do not socket a high-speed device like the THS3491. The socket introduces additional lead lengths and pin-
to-pin capacitance, which can create a troublesome parasitic network. This can make it achieving a smooth,
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stable frequency response impossible. Obtain better results by soldering the THS3491 devices directly onto
the board.
10.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
The THS3491 is available in a thermally-enhanced PowerPAD integrated circuit package. These packages are
constructed using a downset leadframe on which the die is mounted, as shown in the (a) and (b) sections of 图
10-10. This arrangement results in the lead frame that is exposed as a thermal pad on the underside of the
package, a shown in 图 10-10(c). Because this thermal pad directly contacts the die, achieve efficient thermal
performance by providing a good thermal path away from the thermal pad. Devices such as the THS3491 have
no electrical connection between the PowerPAD and the die.
The PowerPAD integrated circuit package allows for assembly and thermal management in one manufacturing
operation. During the surface-mount solder operation (when the leads are soldered), the thermal pad can be
soldered to a copper area underneath the package. By using thermal paths within this copper area, heat is
conducted away from the package into a ground plane or other heat-dissipating device.
The PowerPAD integrated circuit package represents a breakthrough in combining the small area and ease of
assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
图10-10. Views of Thermally Enhanced Package
Although there are many ways to properly heat sink the PowerPAD integrated circuit package, see 节 10.4.1.1.1
for the recommended approach.
10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
The DDA package top-side etch and via pattern is shown in 图10-11.
0.300
(7,62)
0.100
(2,54)
0.026
(0,66)
0.035
(0,89)
0.010
(0,254)
0.030
(0,732)
0.176
(4,47)
0.060
(1,52)
0.140
(3,56)
0.050
(1,27)
0.060
(1,52)
0.035
(0,89)
0.080
(2,03)
0.010
(0.254)
vias
All Units in inches (millimeters)
图10-11. DDA PowerPAD™ Integrated Circuit Package PCB Etch and Via Pattern
1. Use etch for the leads and the thermal pad.
2. Place 13 vias in the thermal pad area. These vias must be 0.01 inch (0.254 mm) in diameter. Keep the vias
small so that solder wicking through the vias is not a problem during reflow.
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3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area, and help
dissipate the heat generated by the THS3491 device. These additional vias may be larger than the 0.01-inch
(0.254 mm) diameter vias directly under the thermal pad because they are not in the area that requires
soldering. As a result, wicking is not a problem.
4. Connect all vias to the internal ground plane. The PowerPAD integrated circuit package is electrically
isolated from the silicon and all leads. Connecting the PowerPAD integrated circuit package to any potential
voltage such as –VS is acceptable because there is no electrical connection to the silicon.
5. When connecting these vias to the ground plane, do not use the typical web or spoke through connection
methodology. Web and spoke connections have a high thermal resistance that slows the heat transfer during
soldering . Avoiding these connection methods makes the soldering of vias that have plane connections
easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the vias under the THS3491 PowerPAD integrated circuit package must connect to the internal
ground plane with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask must leave the pins of the package and the thermal pad area with the 13 vias
exposed.
7. Apply solder paste to the exposed thermal pad area and all of the device pins.
8. With these preparatory steps in place, the device is placed in position and run through the solder reflow
operation as any standard surface-mount component. This results in a device that is properly installed.
10.4.1.1.2 Power Dissipation and Thermal Considerations
The THS3491 includes automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if
the junction temperature exceeds approximately 160°C. When the junction temperature decreases to
approximately 145°C, the amplifier turns on again. However, for maximum performance and reliability, make sure
that the design does not exceed a junction temperature of 125°C. Between 125°C and 150°C, damage does not
occur, but the performance of the amplifier begins to degrade and long-term reliability suffers. The package and
the PCB dictate the thermal characteristics of the device. Maximum power dissipation for a particular package is
calculated using the following formula.
Tmax - TA
PDmax
=
qJA
(1)
where
• PDmax is the maximum power dissipation in the amplifier (W).
• Tmax is the absolute maximum junction temperature (°C).
• TA is the ambient temperature (°C).
• θJA = θJC + θCA
• θJC is the thermal coefficient from the silicon junctions to the case (°C/W).
• θCA is the thermal coefficient from the case to ambient air (°C/W).
The thermal coefficient for the PowerPAD integrated circuit packages are substantially improved over the
traditional SOIC package. The data for the PowerPAD packages assume a board layout that follows the
PowerPAD package layout guidelines referenced above and detailed in PowerPAD™ Thermally Enhanced
Package. Maximum power dissipation levels are shown in Comparison of θJA for Various Packages. If the
PowerPAD integrated circuit package is not soldered to the PCB, the thermal impedance increases substantially
and may cause serious heat and performance issues. Take care to always solder the PowerPAD integrated
circuit package to the PCB for optimum performance.
When determining whether or not the device satisfies the maximum power dissipation requirement, make sure to
consider not only quiescent power dissipation, but dynamic power dissipation. Often times, this dissipation is
difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation
provides visibility into a possible problem.
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10.4.2 Layout Example
THS3491RGT thermal pad
directly on top of blind vias
Rout pad closer to
the device output
Blind Vias to GND to help with
heat dissipation out of the board
Power Connection with Vias
to the internal power plane
图10-12. RGT Package Layout Example
GND trace cut-out underneath the device inputs
and output from PCB second layer to the fourth
layer in-order to reduce PCB parasitic capacitance
图10-13. Ground Trace Cutout Beneath the Device Inputs and Output
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Heat Sink attach on the
bottom layer directly
underneath the device
Blind Vias to GND to help with
heat dissipation of the board
图10-14. Heat Sink Attachment to Bottom Layer
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, PowerPAD™ Made Easy
• Texas Instruments, PowerPAD™ Thermally Enhanced Package
• Texas Instruments, Voltage Feedback vs Current Feedback Op Amps
• Texas Instruments, Current Feedback Amplifier Analysis and Compensation
• Texas Instruments, Current Feedback Amplifiers: Review, Stability Analysis, and Applications
• Texas Instruments, Effect of Parasitic Capacitance in Op Amp Circuits
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS3491IDDAR
THS3491IDDAT
THS3491IRGTR
THS3491IRGTT
THS3491YR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
RGT
RGT
Y
8
8
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
HS3491
Samples
Samples
Samples
Samples
Samples
NIPDAUAG
NIPDAU
NIPDAU
Call TI
HS3491
HS3491
HS3491
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
16
16
0
DIESALE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS3491IDDAR
THS3491IDDAT
SO
PowerPAD
DDA
DDA
8
8
2500
250
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
SO
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
PowerPAD
THS3491IRGTR
THS3491IRGTT
VQFN
VQFN
RGT
RGT
16
16
2500
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS3491IDDAR
THS3491IDDAT
THS3491IRGTR
THS3491IRGTT
SO PowerPAD
SO PowerPAD
VQFN
DDA
DDA
RGT
RGT
8
8
2500
250
366.0
366.0
346.0
210.0
364.0
364.0
346.0
185.0
50.0
50.0
33.0
35.0
16
16
2500
250
VQFN
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016P
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
B
A
PIN 1 INDEX AREA
3.15
2.85
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.66 0.1
(0.1) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(45 X 0.35)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4228232/A 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016P
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.66)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228232/A 11/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016P
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.51)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
84% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4228232/A 11/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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