THS3201MDGNEP(1) [TI]
1.8-GHz LOW-DISTORTION CURRENT-FEEDBACK AMPLIFIER; 1.8 - GHz的低失真电流反馈放大器
| 型号： | THS3201MDGNEP(1) |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.8-GHz LOW-DISTORTION CURRENT-FEEDBACK AMPLIFIER |
| 文件： | 总32页 (文件大小：882K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DGK-8
DGN-8
THS3201-EP
DBV-5
D-8
www.ti.com ..................................................................................................................................................... SGLS283B–APRIL 2005–REVISED JANUARY 2009
1.8-GHz LOW-DISTORTION CURRENT-FEEDBACK AMPLIFIER
1
FEATURES
DESCRIPTION
2
•
Unity Gain Bandwidth: 1.8 GHz
•
High Slew Rate: 6700 V/µs (G = 2 V/V,
RL = 100 Ω, 5-V Step)
The THS3201 is
a
wide-band, high-speed
current-feedback amplifier, designed to operate over
a wide supply range of ±3.3 V to ±7.5 V for today's
high-performance applications.
•
•
•
IMD3: –78 dBc at 20 MHz: (G = 10 V/V,
RL = 100 Ω, 2-VPP Envelope)
The wide supply range, combined with low distortion
and high slew rate, makes the THS3201 ideally
suited for arbitrary waveform driver applications. The
Noise Figure: 11 dB (G = 10 V/V, RG = 28 Ω,
RF = 255 Ω)
Input Referred Noise (f > 10 MHz)
distortion
performance
also
enables
driving
–
–
–
Voltage Noise: 1.65 nV/√Hz
high-resolution and high-sampling rate ADCs.
Noninverting Current Noise: 13.4 pA/√Hz
Inverting Current Noise: 20 pA/√Hz
High-voltage operation capabilties make the
THS3201 especially suitable for many test,
measurement, and ATE
applications
where
•
•
Output Drive: 100 mA
lower-voltage devices do not offer enough voltage
swing capabilty. Output rise and fall times are nearly
independent of step size (to first-order appoximation),
making the THS3201 ideal for buffering small to large
step pulses with excellent linearity in high dynamic
systems.
Power-Supply Voltage Range: ±3.3 V to ±7.5 V
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
The THS3201 is offered in 8-pin SOIC and 8-pin
MSOP with PowerPAD™ packages.
RELATED DEVICES AND DESCRIPTIONS
THS3202
THS3001
±7.5-V 2-GHz Dual Low-Distortion CFB Amplifier
±15-V 420-MHz Low-Distortion CFB Amplifier
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
THS3061/2 ±15-V 300-MHz Low-Distortion CFB Amplifier
THS3122
THS4271
±15-V Dual CFB Amplifier With 350-mA Drive
±7.5-V 1.4-GHz Low-Distortion VFB Amplifier
APPLICATIONS
•
High-Resolution, High-Sampling-Rate
Analog-to-Digital Converter Drivers
•
High-Resolution, High-Sampling-Rate
Digital-to-Analog Converter Output Buffers
•
•
Test and Measurement
ATE
(1) Additional temperature ranges are available - contact factory
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2009, Texas Instruments Incorporated
THS3201-EP
SGLS283B–APRIL 2005–REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
NONINVERTING SMALL SIGNAL
Low-Noise, Low-Distortion, Wideband Application Circuit
FREQUENCY RESPONSE
8
+7.5 V
50 Ω Source
7
50 Ω
R
= 768 Ω
F
6
5
+
49.9 Ω
THS3201
_
V
I
49.9 Ω
4
3
2
1
0
50 Ω
-7.5 V
Gain = 2.
R
L
= 100 Ω,
= 0.2 V .
PP
= ±7.5 V
V
V
O
S
768 Ω
768 Ω
100 k
1 M
10 M
100 M
1 G
10 G
:
NOTE Power supply decoupling capacitors not shown
f - Frequency - Hz
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VS
VI
Supply voltage
16.5 V
Input voltage
±VS
175 mA
±3 V
IO
Output current
VID
Differential input voltage
Continuous power dissipation
Maximum junction temperature(2)
Maximum junction temperature, continuous operation, long-term reliability(3)
Storage temperature range
Lead temperature 1,6 mm (1/16 in) from case for 10 s
Human body model
See Dissipation Ratings Table
TJ
150°C
125°C
TJ
Tstg
–65°C to 150°C
300°C
3000 V
ESD ratings
Charged device model
1500 V
Machines model
100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The absolute maximum ratings under any condition are limited by the constraints of the silicon process. Stresses above these ratings
may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(3) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See Figure 1 for additional information on thermal derating.
2
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Product Folder Link(s): THS3201-EP
THS3201-EP
www.ti.com ..................................................................................................................................................... SGLS283B–APRIL 2005–REVISED JANUARY 2009
1G
100M
80°C, 74M Hrs
10M
100°C, 5.9M Hrs
1M
120°C, 490K Hrs
100K
140°C, 58K Hrs
10K
80
90
100
110
120
130
140
150
T − Junction Temperature − °C
J
Figure 1. EME-G600 Estimated Wirebond Life
DISSIPATION RATINGS
(1)
0JC
0JA
PACKAGE
(°C/W)
(°C/W)
D (8)
DGN (8)(2)
38.3
4.7
97.5
58.4
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) The THS3201 may incorporate a thermal pad on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature;
which could permanently damage the device. See Texas Instruments technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
RECOMMENDED OPERATING CONDITIONS
MIN
±3.3
6.6
MAX
±7.5
15
UNIT
V
Dual supply
Supply voltage
Single supply
TA
Operating free air temperature
–55
125
°C
PACKAGE/ORDERING INFORMATION
PART NUMBER
THS3201MDEP(1)
THS3201MDREP(1)
THS3201MDGNEP(1)
THS3201MDGNREP
PACKAGE TYPE
PACKAGE MARKING
TRANSPORT MEDIA, QUANTITY
Rails, 75
SOIC-8
—
Tape and reel, 2500
Rails, 80
MSOP-8-PP
BLM
Tape and reel, 2500
(1) Product Preview
Copyright © 2005–2009, Texas Instruments Incorporated
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SGLS283B–APRIL 2005–REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
PIN ASSIGNMENTS
D OR DGN PACKAGE
(TOP VIEW)
NC
NC
1
2
3
4
8
7
6
5
V
V
V
V
IN−
IN+
S+
OUT−
V
S−
NC
NC − No internal connection
A. If a PowerPAD package is used, the thermal pad is electrically isolated from the active circuitry.
4
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Product Folder Link(s): THS3201-EP
THS3201-EP
www.ti.com ..................................................................................................................................................... SGLS283B–APRIL 2005–REVISED JANUARY 2009
ELECTRICAL CHARACTERISTICS
VS = ±7.5 V: Rf = 1 kΩ, RL = 100 Ω, G = +2 (unless otherwise noted)
OVER
TEMPERATURE
TYP
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
UNIT
–55°C to
25°C
25°C
125°C
AC Performance
G = +1, RF = 1.2 kΩ
1.8
850
565
520
380
880
GHz
MHz
G = +2, RF = 768 Ω
Small-signal bandwidth, –3 dB
(VO = 200 mVPP
Typ
)
G = +5, RF = 619 Ω
G = +10, RF = 487 Ω
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
G = +2, VO = 200 mVpp, RF = 768 Ω
G = +2, VO = 2 Vpp, RF = 715 Ω
MHz
MHz
Typ
Typ
G = +2, VO = 5-V step, RF = 768 Ω,
Rise/fall
5400/4000
9800/6700
0.7/0.9
Slew rate (25% to 75% level)
V/µs
Typ
G = +2, VO = 10-V step, RF = 768 Ω,
Rise/fall
G = +2, VO = 4-V step, RF = 768 Ω,
Rise/fall
Rise and fall time
ns
ns
Typ
Typ
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
Second-order harmonic
Third-order harmonic
20
60
G = –2, VO = 2-V step
G = +5, f = 10 MHz, VO = 2 Vpp, RL = 100 Ω
–64
–73
dBc
Typ
Third-order intermodulation
distortion (IMD3)
G = +10, fc = 20 MHz, Δf = 1 MHz,
VO(envelope) = 2 Vpp
–78
11
dBc
dB
Typ
Typ
G = +10, fc = 100 MHz, RF = 255 Ω,
RG = 28
Noise figure
Input voltage noise
f > 10 MHz
1.65
13.4
nV/√Hz
pA/√Hz
pA/√Hz
Typ
Typ
Typ
Input current noise (noninverting)
Input current noise (inverting)
f > 10 MHz
20
NTSC
PAL
0.008
0.004
0.007
0.011
G = +2, RL = 150 Ω,
RF = 768 Ω
Differential gain
%
°
Typ
Typ
NTSC
PAL
G = +2, RL = 150 Ω,
RF = 768 Ω
Differential phase
DC Performance
Open-loop transimpedance gain
Input offset voltage
VO = ±4 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
300
200
±4
100
±6
kΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
±0.7
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
±13
±90
±400
±60
±400
µV/°C
µA
±13
±14
±65
±40
nA/°C
µA
nA/°C
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ELECTRICAL CHARACTERISTICS (continued)
VS = ±7.5 V: Rf = 1 kΩ, RL = 100 Ω, G = +2 (unless otherwise noted)
OVER
TEMPERATURE
TYP
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
UNIT
–55°C to
25°C
25°C
125°C
Input
Common-mode input range
Common-mode rejection ratio
Inverting input impedance, Zin
RL = 1 kΩ
±5.1
71
±5
58
±5
53
V
dB
Ω
Min
Min
Typ
VCM = ±3.75 V
Open loop
16
Noninverting
Inverting
780
11
kΩ
Ω
Input resistance
Typ
Typ
Input capacitance
Noninverting
1
pF
Output
RL = 1 kΩ
±6
±5.9
±5.7
105
85
±5.7
±5.35
100
Voltage output swing
V
Min
RL = 100 Ω
RL = 20 Ω
±5.8
115
100
0.01
Current output, sourcing
Current output, sinking
mA
mA
Ω
Min
Min
Typ
RL = 20 Ω
80
Closed-loop output impedance
Power Supply
G = +1, f = 1 MHz
Minimum operating voltage
Maximum operating voltage
Maximum quiescent current
Absolute minimum
Absolute maximum
Output open
±3.3
±7.5
18
±3.3
±7.5
22
V
V
Min
Max
Max
Min
Min
14
69
65
mA
dB
dB
Power-supply rejection (+PSRR) VS+ = 7 V to 8 V, RL = 1 kΩ
Power-supply rejection (–PSRR) VS– = –7 V to –8 V, RL = 1 kΩ
60
56
58
55
6
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ELECTRICAL CHARACTERISTICS
VS = ±5 V: Rf = 1 kΩ, RL = 100 Ω , G = +2 (unless otherwise noted)
OVER
TEMPERATURE
TYP
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
UNIT
–55°C to
25°C
25°C
125°C
AC Performance
G = +1, RF= 1.2 kΩ
1.3
725
540
480
170
900
GHz
MHz
G = +2, RF = 715 Ω
Small-signal bandwidth, –3 dB
(VO = 200 mVPP
Typ
)
G = +5, RF = 576 Ω
G = +10, RF = 464 Ω
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
G = +2, VO = 200 mVpp, RF = 715 Ω
G = +2, VO = 2 Vpp, RF = 715 Ω
MHz
MHz
Typ
Typ
G = +2, VO = 5-V step, RF = 715 Ω,
Rise/Fall
Slew rate (25% to 75% level)
Rise and fall time
5200/4000
0.7/0.9
V/µs
Typ
Typ
G = +2, VO = 4-V step, RF = 715 Ω,
Rise/Fall
ns
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
20
60
G = –2, VO = 2-V step
ns
Typ
G = +5, f = 10 MHz,
RL = 100 Ω
Second-order harmonic
Third-order harmonic
–69
–75
–81
11
dBc
dBc
dBc
dB
Typ
Typ
Typ
Typ
VO = 2 Vpp
G = +5, f = 10 MHz,
RL = 100 Ω
VO = 2 Vpp
Third-order intermodulation
distortion (IMD3)
G = +10, fc = 20 MHz, Δf = 1 MHz,
VO(envelope) = 2 Vpp
G = +10, fc = 100 MHz, RF = 255 Ω,
RG = 28
Noise figure
Input voltage noise
f > 10 MHz
1.65
13.4
20
nV/√Hz
pA/√Hz
pA/√Hz
Typ
Typ
Typ
Input current noise (noninverting)
Input current noise (inverting)
f > 10 MHz
NTSC
PAL
0.006
0.004
0.03
0.04
G = +2, RL = 150 Ω,
RF = 768 Ω
Differential gain
%
°
Typ
Typ
NTSC
PAL
G = +2, RL = 150 Ω,
RF = 768 Ω
Differential phase
DC Performance
Open-loop transimpedance gain
Input offset voltage
VO = ±2 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
VCM = 0 V, RL = 1 kΩ
300
200
±3
100
±5.5
±13
kΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
±0.7
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
µV/°C
µA
±13
±14
±65
±40
±90
±400
±60
nA/°C
µA
±400
nA/°C
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ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V: Rf = 1 kΩ, RL = 100 Ω , G = +2 (unless otherwise noted)
OVER
TEMPERATURE
TYP
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
UNIT
–55°C to
25°C
25°C
125°C
Input
Common-mode input range
Common-mode rejection ratio
Inverting input impedance, Zin
RL = 1 kΩ
±2.6
71
±2.5
56
±2.5
50
V
dB
Ω
Min
Min
Typ
VCM = ±2.5 V
Open loop, RL = 1 kΩ
Noninverting
Inverting
17.5
780
11
kΩ
Ω
Input resistance
Typ
Typ
Input capacitance
Noninverting
1
pF
Output
RL = 1 kΩ
±3.65
±3.45
115
±3.5
±3.33
105
±3.4
±3.2
90
Voltage output swing
V
Min
RL = 100 Ω
RL = 20 Ω
Current output, sourcing
Current output, sinking
mA
mA
Ω
Min
Min
Typ
RL = 20 Ω
100
80
75
Closed-loop output impedance
Power Supply
G = +1, f = 1 MHz
0.01
Minimum operating voltage
Maximum operating voltage
Maximum quiescent current
Absolute minimum
Absolute maximum
±3.3
±7.5
16.8
60
±3.3
±7.5
20.5
56
V
V
Min
Max
Max
Min
Min
14
69
65
mA
dB
dB
Power-supply rejection (+PSRR) VS+ = 4.5 V to 5.5 V, RL = 1 kΩ
Power-supply rejection (–PSRR) VS– = –4.5 V to –5.5 V, RL = 1 kΩ
58
55
8
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TYPICAL CHARACTERISTICS
Table of Graphs (VS = ±7.5 V)
FIGURE NO.
Noninverting small-signal frequency response
Inverting small-signal frequency response
Inverting large-signal frequency response
0.1-dB gain flatness frequency response
Capacitive load frequency response
Recommended switching resistance
2nd harmonic distortion
2, 3
4
5, 6
7
8
vs Capacitive load
vs Frequency
9
10
11
12
13
14
15
16
17
18
19, 20
21
22
23
24
25
26
27, 28
29
30
31
32
33
34
35
36
37
3rd harmonic distortion
vs Frequency
2nd-order harmonic distortion, G = 2
3rd-order harmonic distortion, G = 2
2nd-order harmonic distortion, G = 5
3rd-order harmonic distortion, G = 5
2nd-order harmonic distortion, G = 10
3rd-order harmonic distortion, G = 10
3rd-order intermodulation distortion (IMD3)
S-Parameter
vs Output voltage
vs Output voltage
vs Output voltage
vs Output voltage
vs Output voltage
vs Output voltage
vs Frequency
vs Frequency
Input voltage and current noise
Noise figure
vs Frequency
vs Frequency
Transimpedance
vs Frequency
Input offset voltage
vs Case temperature
vs Case temperature
vs Output voltage
Input bias and offset current
Slew rate
Settling time
Quiescent current
vs Supply voltage
vs Load resistance
vs Frequency
Output voltage
Rejection ratio
Noninverting small-signal transient response
Inverting large-signal transient response
Overdrive recovery time
Differential gain
vs Number of loads
vs Number of loads
vs Frequency
Differential phase
Closed-loop output impedance
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Table of Graphs (VS = ±5 V)
Figure No.
Noninverting small-signal frequency response
Inverting small-signal frequency response
0.1-dB gain flatness frequency response
2nd-order harmonic distortion
38
39
40
vs Frequency
41
3rd-order harmonic distortion
vs Frequency
42
2nd-order harmonic distortion, G = 2
3rd-order harmonic distortion, G = 2
2nd-order harmonic distortion, G = 5
3rd-order harmonic distortion, G = 5
2nd-order harmonic distortion, G = 10
3rd-order harmonic distortion, G = 10
3rd-order intermodulation distortion (IMD3)
S-Parameter
vs Output voltage
vs Output voltage
vs Output voltage
vs Output voltage
vs Output voltage
vs Output voltage
vs Frequency
43
44
45
46
47
48
49
vs Frequency
50, 51
52
Slew rate
vs Output voltage
Noninverting small-signal transient response
Inverting large-signal transient response
Overdrive recovery time
53
54
55
10
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VS = ±7.5 V Graphs
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
24
22
20
18
16
14
12
10
24
22
8
7
6
5
R
F
= 619 Ω
G = 10, R = 487 Ω
G = -10, R = 499 Ω
F
F
R
F
= 768 Ω
20
18
G = 5, R = 619 Ω
F
16
14
12
10
8
G = -5, R = 549 Ω
F
R
F
= 1 kΩ
R
V
V
= 100 Ω,
R
V
V
= 100 Ω,
L
L
= 0.2 V
= ±7.5 V
.
= 0.2 V
.
O
S
PP
O
S
PP
4
3
2
1
0
= ±7.5 V
8
6
4
2
G = 2, R = 768 Ω
F
6
G = -2, R = 576 Ω
F
Gain = 2.
4
R
L
= 100 Ω,
G =1, R = 1.2 kΩ
2
0
-2
-4
F
V
V
= 0.2 V
= ±7.5 V
.
O
S
PP
0
-2
G = -1, R = 619 Ω
F
-4
100 k 1 M
10 M
100 M
1 G
10 G
100 k 1 M
10 M
100 M
1 G
10 G
100 k 1 M
10 M
100 M
1 G
10 G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 2.
Figure 3.
Figure 4.
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
16
14
12
10
16
14
12
10
8
6.4
6.3
6.2
Gain = 2,
G =-5, R = 576 Ω
F
R
R
V
V
= 768 Ω,
= 100 Ω,
F
L
G =-5, R = 549 Ω
F
= 0.2 V
= ±7.5 V
,
O
S
PP
R
L
= 100 Ω,
6.1
6
V
V
= 2 V .
PP
= ±7.5 V
O
S
6
4
2
8
6
4
G = 2, R = 715 Ω
F
5.9
5.8
5.7
5.6
G = -1, R = 576 Ω
F
0
-2
-4
R
L
= 100 Ω,
V
V
= 2 V .
PP
= ±7.5 V
O
S
2
0
100 k 1 M
10 M
100 M
1 G
10 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 5.
Figure 6.
Figure 7.
RECOMMENDED SWITCHING
RESISTANCE
2nd HARMONIC DISTORTION
CAPACITIVE LOAD
vs
vs
FREQUENCY RESPONSE
CAPACITIVE LOAD
FREQUENCY
16
14
12
10
8
60
-40
-50
R
= 30 Ω, C = 22 pF
L
G = 10
R
(ISO)
Gain = 5,
= 499 W, R = 54ꢀ9 W
G
R
R
= 619 Ω
= 100 Ω,
= ±7.5 V
F
F
L
R
C
= 20 Ω,
= 50 pF
(ISO)
50
40
30
20
L
G = 5
R
V
S
= 619 W,
F
-60
-70
Gain = 5
R
= 154 W
G
R
R
= 619 Ω
= 100 Ω
=± 7.5 V
F
L
V
6
S
Vs = 7ꢀ5V
= 2V
V
4
R
= 15 Ω,
out
PP
R = 100 W
L
-80
(ISO)
R
ISO
_
+
C
L
= 100 pF
2
C
L
G = 2
R
10
0
-90
R
= 20 Ω,
(ISO)
= 768 W, R = 768 W
0
F
G
C
L
= 47 pF
-2
-100
0
100
200
300
400
500
10
100
1
10
100
f - Frequency - MHz
C
L
- Capacitive Load - pF
f - Frequency - MHz
Figure 8.
Figure 9.
Figure 10.
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VS = ±7.5 V Graphs (continued)
2nd HARMONIC DISTORTION
3rd HARMONIC DISTORTION
3rd HARMONIC DISTORTION
G = 2
vs
G = 2
vs
vs
FREQUENCY
OUTPUT VOLTAGE
OUTPUT VOLTAGE
-30
-40
-30
-40
-60
-65
-70
-75
Vs = 7ꢀ5V
G = 2
Vs = 7ꢀ5V
G = 2
G = 2
R
R
= 768 W, R = 768 W
R
= 768 W, R = 768 W
F
G
F
L
G
= 768 W, R = 768 W
F
G
64MHz
32MHz
R
= 100 W
-50
-50
R
= 100 W
L
32MHz
64MHz
-60
-60
Vs = 7ꢀ5V
= 2V
V
-80
-85
-90
-70
-70
out
PP
R
= 100 W
L
-80
-80
G = 5
R
1MHz
= 619 W, R = 154 W
1MHz
-90
-90
F
G
2MHz
4MHz
8MHz
16MHz
4MHz
4
8MHz
3
G = 10
R
-100
-110
-100
-110
-95
16MHz
2
2MHz
5
= 499 W, R = 54ꢀ9 W
F
G
-100
0
1
4
5
6
0
1
2
3
6
1
10
100
V
- Output Voltage - V
V
- Output Voltage - V
f - Frequency - MHz
PP
PP
out
out
Figure 11.
Figure 12.
Figure 13.
2nd HARMONIC DISTORTION
3rd HARMONIC DISTORTION
2nd ORDER HARMONIC DISTORTION
G = 5
vs
G = 5
vs
G = 10
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
-30
-40
-30
-40
-30
Vs = 7.5V, G = 10
32MHz
Vs = 7ꢀ5V
G = 5
Vs = 7ꢀ5V
G = 5
R
R
= 499 W, R = 54.9 W
F
G
64MHz
-40
-50
32MHz
32MHz
= 100 W
R
= 619 W, R = 154 W
R
= 649 W, R = 154 W
L
F
L
G
F
L
G
64MHz
64MHz
R
= 100 W
R
= 100 W
-50
-50
-60
-60
-60
-70
-70
-70
-80
-80
-80
1MHz
1MHz
-90
-90
-90
4MHz
2MHz
1MHz
4MHz
2MHz
8MHz
16MHz
8MHz
3
-100
-110
-100
-110
8MHz
-100
-110
16MHz
2
4MHz
2MHz
16MHz
0
1
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
- Output Voltage - V
V
- Output Voltage - V
V
out
- Output Voltage - V
PP
PP
PP
out
out
Figure 14.
Figure 15.
Figure 16.
3rd ORDER HARMONIC DISTORTION
3rd ORDER INTERMODULATION
G = 10
vs
DISTORTION
vs
S-PARAMETER
vs
FREQUENCY
OUTPUT VOLTAGE
FREQUENCY
-30
0
-40
-50
-60
-70
V
=± 7.5 V
S
Vs = 7.5V
G = 10
Vs = 7ꢀ5V
= 2V
Gain = +10
C = 0 pF
32MHz
-40
-50
V
out
PP
G10
= 499 W, R = 54ꢀ9 W
R
= 499 W, R = 54.9 W
G
= 100 W
F
L
R
= 100W
R
-20
-40
S11
L
F
G
64MHz
R
-60
S22
S12
-70
-60
-80
-80
R
R
F
G
-80
G2
R
C
= 768 W, R = 768 W
-90
F
G
-
1MHz
+
50 Ω
50 Ω
-90
G5
R
-100
-110
8MHz
50 Ω
Source
= 619 W, R = 154 W
50 Ω
4MHz
F
G
2MHz
5
16MHz
-100
-100
1 M
10 M
100 M
1 G
10 G
0
1
2
3
4
6
10 20 30 40 50 60 70 80 90 100
f - Frequency - Hz
V
- Output Voltage - V
f - Frequency - MHz
PP
out
Figure 17.
Figure 18.
Figure 19.
12
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VS = ±7.5 V Graphs (continued)
INPUT VOLTAGE AND
S-PARAMETER
vs
FREQUENCY
CURRENT NOISE
vs
FREQUENCY
50
45
40
0
4
V
=± 7.5 V
S
V
T
A
= ±7.5 V and ±5 V
= 25°C
S
Gain = +10
C = 3.3 pF
3.5
-20
3
V
n
2.5
1.5
S22
S11
35
30
-40
-60
S12
Inverting
Noise Current
25
20
0.5
0
R
R
G
F
C
-
-80
Noninverting
Current Noise
+
50 Ω
50 Ω
15
10
50 Ω
Source
50 Ω
-100
1 M
10 M
100 M
1 G
10 G
100 k
1 G
10
1 M
10 M
100 M
f - Frequency - Hz
f - Frequency - Hz
Figure 20.
Figure 21.
NOISE FIGURE
vs
FREQUENCY
TRANSIMPEDANCE
vs
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
FREQUENCY
14
13
12
11
10
9
120
100
80
60
40
20
0
3
2.5
2
V
=± 5 and ±7.5V
S
V
= ±7.5 V
S
1.5
1
V
= ±5 V
S
Gain = +10
_
+
10 Ω
R
R
= 28 Ω
G
F
8
= 255 Ω
= ±7.5 V & ±5 V
V
I
0.5
0
O
V
S
+
_
Gain W +
7
IB
6
0
50 100 150 200 250 300 350 400
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
100 k
1 M
10 M
100 M
f - Frequency - MHz
f - Frequency - Hz
T
C
- Case Temperature - °C
Figure 22.
Figure 23.
Figure 24.
INPUT BIAS AND OFFSET CURRENT
SLEW RATE
vs
OUTPUT VOLTAGE
vs
CASE TEMPERATURE
SETTLING TIME
7
1.5
1
10000
9000
8000
17
16
V
=± 7.5 V
S
Rising Edge
6
5
4
SR+
I
-
IB
15
14
7000
6000
0.5
Gain = -2
R
L
R
F
= 100 Ω
= 576 Ω
SR-
I
+
IB
0
-0.5
-1
5000
4000
3000
2000
f= 1 MHz
= ±7.5 V
3
2
13
12
V
S
Falling Edge
I
OS
1
0
11
10
1000
0
-1.5
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
0
2
4
6
8
10
1
2
3
4
5
6
7
8
9
t - Time - ns
T
C
- Case Temperature - °C
V
- Output Voltage - Vstep
out
Figure 25.
Figure 26.
Figure 27.
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VS = ±7.5 V Graphs (continued)
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
SETTLING TIME
3
20
18
16
14
7
6
5
4
3
2
1
0
2.5
T
= 85°C
A
Rising Edge
2
1.5
T
A
= 25°C
1
Gain = -2
12
10
8
0.5
V
T
= ±7.5 V
= -40 to 85°C
R
L
R
F
= 100 Ω
= 576 Ω
T
A
= -40°C
S
0
-0.5
-1
A
-1
f= 1 MHz
-2
-3
-4
-5
-6
-7
V
= ±7.5 V
S
6
-1.5
4
-2
-2.5
-3
Falling Edge
2
0
0
2.5
5
7.5
10
12.5
10
100
1000
2
2.5
3
3.5
4
4.5
5
5.5
6 6.5 7 7.5
t - Time - ns
R
L
- Load Resistance - Ω
V
- Supply Voltage - ±V
S
Figure 28.
Figure 29.
Figure 30.
REJECTION RATIO
vs
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
FREQUENCY
80
0.3
0.2
0.1
6
5
4
3
2
1
0
V
= ±7.5 V
S
Output
Gain = -5
70
60
50
40
30
20
R
R
= 100 Ω
549 Ω
L
F =
V
= ±7.5 V
S
CMRR
Input
Input
0
Gain = 2
= 100 Ω
715 Ω
PSRR+
-1
R
R
L
-0.1
-2
-3
-4
-5
-6
F =
V
= ±7.5 V
S
-0.2
-0.3
Output
10
0
100 k
1 M
10 M
100 M
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
f - Frequency - Hz
t - Time - µs
t - Time - µs
Figure 31.
Figure 32.
Figure 33.
DIFFERENTIAL GAIN
vs
OVERDRIVE RECOVERY TIME
NUMBER OF LOADS
10
8
5
0.030
0.025
0.020
0.015
0.010
G = 2,
Gain = 2
4
R
F
= 768 Ω,
= ±7.5 V
R
V
= 768 Ω
= ±7.5 V
F
S
3
6
V
S
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
4
2
1
2
PAL
0
0
-2
-4
-1
-2
NTSC
-6
-8
-3
-4
-5
0.005
0
-10
0
0.2
0.4
0.6
0.8
1
0
1
2
3
4
5
6
7
8
t - Time - µs
Number of Loads - 150 Ω
Figure 34.
Figure 35.
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VS = ±7.5 V Graphs (continued)
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
0.040
0.035
0.030
0.025
0.020
0.015
0.010
1000
Gain = 2
Gain = 2
R
V
= 768 kΩ
= ±7.5 V
F
S
R
F
R
L
= 715 Ω
= 100 Ω
= ±7.5 V
100
10
°
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
V
S
PAL
1
0.1
NTSC
0.01
0.005
0
0.001
0
1
2
3
4
5
6
7
8
100 k
1 M
10 M
1 M
1 G
Number of Loads - 150 Ω
f - Frequency - Hz
Figure 36.
Figure 37.
VS = ±5 V Graphs
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
24
22
20
24
6.4
6.3
6.2
Gain = 2,
22
20
18
16
14
12
G = 10, R = 464 Ω
G = -10, R = 499 Ω
F
F
R
R
V
V
= 715 Ω,
= 100 Ω,
F
L
18
16
= 0.2 V ,
PP
= ±5 V
O
S
G = 5, R = 576 Ω
F
G = -5, R = 549 Ω
F
14
12
10
6.1
6
R
L
= 100 Ω,
R
V
V
= 100 Ω,
L
V
V
= 0.2 V .
PP
= ±5 V
O
S
= 0.2 V .
PP
= ±5 V
O
S
10
8
8
6
4
2
G = 2, R = 715 Ω
F
5.9
5.8
5.7
5.6
6
G = -2, R = 576 Ω
4
2
F
G =1, R = 1.2 kΩ
F
0
-2
0
G =-1, R = 576 Ω
F
-2
-4
-4
100 k 1 M
10 M
100 M
1 G
10 G
100 k 1 M
10 M
100 M
1 G
10 G
100 k 1 M
10 M
100 M
1 G
10 G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 38.
Figure 39.
Figure 40.
2nd ORDER HARMONIC DISTORTION
2nd HARMONIC DISTORTION
3rd ORDER HARMONIC DISTORTION
G = 2
vs
vs
vs
OUTPUT VOLTAGE
-30
FREQUENCY
FREQUENCY
-40
-50
-60
G = 10
R
Vs = 5V
G = 2
-40
64MHz
= 464 W, R = 51.1 W
G
F
-65
-70
-75
G = 2
= 715 W, R = 715 W
RF = 715 W, RG = 715 W
= 100 W
L
R
G = 5
R
F
G
R
-50
-60
= 576 W,
F
-60
-70
R
= 143 W
G
32MHz
Vs = 5V
= 2V
V
-80
-85
-90
-70
out
PP
1MHz
2MHz
R
= 100 W
L
Vs = 5V
= 2V
-80
-80
V
G = 5
= 576 W, R = 143 W
out
PP
R
-90
R
= 100 W
F
G
L
4MHz
-90
8MHz
3
G = 10
R
-100
-110
G = 2
R
-95
16MHz
2
= 464 W, R = 51.1 W
= 715 W, R = 715 W
F
G
F
G
-100
-100
0
1
4
5
6
1
10
100
1
10
100
V
- Output Voltage - V
f - Frequency - MHz
PP
out
f - Frequency - MHz
Figure 41.
Figure 42.
Figure 43.
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VS = ±5 V Graphs (continued)
3rd ORDER HARMONIC
DISTORTION, G = 2
vs
2nd ORDER HARMONIC
DISTORTION, G = 5
vs
3rd ORDER HARMONIC
DISTORTION, G = 5
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
-30
-40
-30
-40
-30
-40
Vs = 5V
G = 5
64MHz
64MHz
Vs = 5V
G = 2
Vs = 5V
G = 5
64MHz
R
= 576 W, R = 143 W
R
= 715 W, R = 715 W
R
= 576 W, R = 143 W
F
L
G
F
L
G
F
L
G
R
= 100 W
-50
-50
-50
R
= 100 W
R
= 100 W
32MHz
32MHz
-60
-60
-60
32MHz
-70
-70
-70
1MHz
1MHz
1MHz
2MHz
-80
-80
-80
2MHz
2MHz
4MHz
4MHz
-90
-90
-90
4MHz
8MHz
8MHz
8MHz
16MHz
-100
-110
-100
-110
-100
-110
16MHz
2
16MHz
2
0
1
3
4
5
6
0
1
2
3
4
5
6
0
1
3
4
5
6
V
- Output Voltage - V
V
- Output Voltage - V
V
- Output Voltage - V
PP
PP
PP
out
out
out
Figure 44.
Figure 45.
Figure 46.
2nd ORDER HARMONIC
DISTORTION, G = 10
vs
3rd ORDER HARMONIC
DISTORTION, G = 10
vs
3rd ORDER INTERMODULATION
DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
FREQUENCY
-30
-40
-30
-40
-50
-55
-60
-65
-70
-75
-80
-85
Vs = 5V, G = 10
32MHz
64MHz
Vs = 5V
G = 10
Vs = 5V
64MHz
R
= 464 W, R = 51.1 W
V
= 2V
F
L
G
out
PP
G2
R
F
R
= 464 W, R = 51.1 W
R
= 100 W
F
L
G
R
= 100W
= 715 W, R = 715 W
G
L
-50
-50
R
= 100 W
-60
-60
32MHz
-70
-70
1MHz
1MHz
2MHz
G10
R
-80
-80
= 464 W,
F
2MHz
R
= 51.1 W
G
4MHz
-90
-90
G5
R
F
4MHz
-90
-95
8MHz
8MHz
= 576 W,
= 143 W
16MHz
-100
-110
-100
-110
R
G
16MHz
2
-100
0
1
2
3
4
5
6
0
1
3
4
5
6
10 20 30 40 50 60 70 80 90 100
V
- Output Voltage - V
V
- Output Voltage - V
f - Frequency - MHz
PP
PP
out
out
Figure 47.
Figure 48.
Figure 49.
S-PARAMETER
vs
S-PARAMETER
vs
SLEW RATE
vs
FREQUENCY
FREQUENCY
OUTPUT VOLTAGE
0
0
6000
5000
4000
3000
V
=± 5 V
V
=± 5 V
S
Gain = +10
C = 3.3 pF
S
Gain = +10
C = 0 pF
-20
-20
-40
SR+
SR-
-40
-60
S22
S11
S22
S11
S12
S12
-60
-80
R
G
R
F
R
G
R
F
2000
1000
0
C
C
-
-
-80
+
+
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
Source
50 Ω
Source
50 Ω
50 Ω
-100
-100
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
10 G
1
2
3
4
5
f - Frequency - Hz
f - Frequency - Hz
V
- Output Voltage - Vstep
out
Figure 50.
Figure 51.
Figure 52.
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VS = ±5 V Graphs (continued)
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
OVERDRIVE RECOVERY TIME
0.3
0.2
0.1
3
2.5
2
6
4
2
0
3
G = 2,
Output
Input
Gain = -5
R
V
= 715 Ω,
= ±5 V
F
S
2
1
R
R
V
= 100 Ω
L
1.5
1
549 Ω
F =
= ±5 V
S
0.5
Input
0
0
0
-0.5
Gain = 2
-2
-0.1
-1
-1
-2
-3
R
R
= 100 Ω
L
715 Ω
-1.5
F =
V
= ±5 V
S
-4
-6
-0.2
-0.3
-2
-2.5
-3
Output
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.2
0.4
0.6
0.8
1
t - Time - µs
t - Time -µs
t - Time - µs
Figure 53.
Figure 54.
Figure 55.
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APPLICATION INFORMATION
Table 1. Recommended Resistor Values for
Optimum Frequency Response
Wideband Noninverting Operation
The THS3201 is
a unity gain stable 1.8-GHz
THS3201 RF for AC When Rload = 100 Ω
current-feedback operational amplifier, designed to
operate from a ±3.3-V to ±7.5-V power supply.
Gain
(V/V)
Supply Voltage
(V)
RG
(Ω)
RF
(Ω)
Figure 56 shows the THS3201 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves are
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment
presenting a 50-Ω load impedance. The 49.9-Ω shunt
resistor at the VI terminal in Figure 56 matches the
source impedance of the test generator.
±7.5
—
—
1.2 k
1.2 k
768
715
619
576
487
464
619
576
576
549
499
1
2
±5
±7.5
768
715
154.9
143
54.9
51.1
619
576
287
110
49.9
±5
±7.5
5
±5
±7.5
10
–1
7.5 V
±5
+V
S
±7.5
+
±5
100 pF
0.1 µF 6.8 µF
50 Ω Source
49.9 Ω
–2
–5
±7.5 and ±5
±7.5 and ±5
±7.5 and ±5
+
V
I
49.9 Ω
–10
THS3201
_
50 Ω
R
F
Wideband Inverting Gain Operation
768 Ω
768 Ω
R
G
Figure 57 shows the THS3201 is a typical inverting
gain configuration, where the input and output
impedances and signal gain from Figure 56 are
retained in an inverting circuit configuration.
0.1 µF 6.8 µF
+
100 pF
-V
S
-7.5 V
7.5 V
+V
S
Figure 56. Wideband Noninverting Gain
Configuration
+
100 pF
0.1 µF
49.9 Ω
6.8 µF
Unlike voltage-feedback amplifiers, current-feedback
amplifiers are highly dependent on the feedback
resistor RF for maximum performance and stability.
Table 1 shows the optimal gain setting resistors RF
and RG at different gains to give maximum bandwidth
with minimal peaking in the frequency response.
Higher bandwidths can be achieved, at the expense
of added peaking in the frequency response, by using
even lower values for RF. Conversely, increasing RF
decreases the bandwidth, but stability is improved.
+
THS3201
_
50 Ω
50 Ω Source
R
G
R
F
V
I
287 Ω
576 Ω
R
M
0.1 µF
6.8 µF
60.4 Ω
+
100 pF
-V
S
-7.5 V
Figure 57. Wideband Inverting Gain Configuration
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Single Supply Operation
768 Ω
768 Ω
±7.5 V
The THS3201 has the capability to operate from a
single-supply voltage ranging from 6.6 V to 15 V.
When operating from a single power supply, care
must be taken to ensure the input signal and amplifier
is biased appropriately to allow for the maximum
output voltage swing. The circuits shown in Figure 58
demonstrate methods to configure an amplifier in a
manner conducive for single-supply operation
75-Ω Transmission Line
V
O(1)
75 Ω
-
+
THS3201
V
I
±7.5 V
75 Ω
n Lines
75 Ω
V
O(n)
75 Ω
+V
S
75 Ω
50 Ω Source
+
49.9 Ω
Figure 59. Video Distribution Amplifier
Application
V
I
THS3201
_
R
T
49.9 Ω
50 Ω
+V
2
S
R
F
ADC Driver Application
768 Ω
The THS3201 can be used as a high-performance
ADC driver in applications such as radio receiver IF
stages and test and measurement devices. All
high-performance ADCs have differential inputs. The
R
768 Ω
G
+V
2
S
THS3201 can be used in conjunction with
a
R
F
transformer as a drive amplifier in these applications.
Figure 60 and Figure 61 show two different
approaches.
576 Ω
V
S
50 Ω Source
R
G
_
49.9 Ω
In Figure 60, a transformer is used after the amplifier
to convert the signal to differential. The advantage of
this approach is fewer components are required.
ROUT and RT are required for impedance matching
the transformer.
V
I
287 Ω
T
THS3201
+
60.4 Ω
R
50 Ω
+V
+V
2
S
S
2
V
Figure 58. DC-Coupled Single-Supply Operation
S+
0.1 µF
Video HDTV Drivers
R
G
R
F
The exceptional bandwidth and slew rate of the
THS3201 matches the demands for professional
video and HDTV. Most commercial HDTV standards
require a video passband of 30 MHz. To ensure high
signal quality with minimal degradation of
performance, a 0.1-dB gain flatness should be at
least 7x the passband frequency to minimize group
delay variations requiring 210-MHz 0.1-dB frequency
flatness from the amplifier. High slew rates ensure
there is minimal distortion of the video signal.
Component video and RGB video signals require fast
transition times and fast settling times to keep high
signal quality. The THS8135, for example, is a
240-MSPS video DAC and has a transition time
R
1:n
OUT
24.9 Ω
THS3201
V
IN
R
T
47pF
ADC
CM
24.9 Ω
V
S-
47pF
0.1 µF
0.1 µF
Figure 60. Differential ADC Driver Circuit 1
In Figure 61, a transformer is used before two
amplifiers to convert the signal to differential. The two
amplifiers then amplify the differential signal. The
advantage to this approach is each amplifier is
required to drive one half the voltage as before. RT is
used to impedance match the transformer.
approaching
4 ns. The THS3201 is a perfect
candidate for interfacing the output of such
high-performance video components.
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1
fP +
V
S+
2pRC
Placing this pole at about 10x the highest frequency
of interest ensures it has no impact on the signal.
Since the resistor is typically a small value, it is bad
practice to place the pole at (or near) frequencies of
interest. At the pole frequency, the amplifiers see a
load with a magnitude of:
0.1 µF
R
G
R
F
24.9 Ω
THS3201
V
1:n
IN
47pF
Ǹ
2 xR
ADC
CM
R
T
24.9 Ω
If R is only 10 Ω, the amplifier is heavily loaded
above the pole frequency, and generates excessive
distortion.
R
G
THS3201
47pF
R
F
DAC Driver Application
0.1 µF
V
S-
The THS3201 can be used as a high-performance
DAC output driver in applications such as radio
0.1 µF
transmitter
stages,
and
arbitrary
waveform
generators. All high-performance DACs have
differential current outputs. Two THS3201s can be
Figure 61. Differential ADC Driver Circuit 2
used as
applications as shown in Figure 62.
a differential drive amplifier in these
It is almost universally recommended to use a
resistor and capacitor between the operational
amplifier output and the ADC input as shown in
Figure 60 and Figure 61.
RPU on the DAC output is used to convert the output
current to voltage. The 24.9-Ω resistor and 47-pF
capacitor between each DAC output and the
operational amplifier input is used to reduce the
images generated at multiples of the sampling rate.
The values shown form a pole a 136 MHz. ROUT sets
the output impedance of each amplifier.
This resistor-capacitor (RC) combination has multiple
functions:
•
•
•
The capacitor is a local charge reservoir for ADC.
The resistor isolates the amplifier from the ADC.
In conjunction, they form a low-pass noise filter.
V
S+
During the sampling phase, current is required to
charge the ADC input sampling capacitors. By placing
external capacitors directly at the input pins, most of
the current is drawn from them. They are seen as a
low-impedance source. They can be thought of as
serving much the same purpose as a power-supply
bypass capacitor - to supply transient current - with
the amplifier then providing the bulk charge.
0.1 µF
AV
DD
R
G
R
F
R
PU
R
OUT
THS3201
24.9 Ω
V
V
OUT1
IOUT1
DAC
IOUT2
47pF
24.9 Ω
R
OUT
Typically, a low-value capacitor in the range of 10 pF
to 100 pF provides the required transient charge
reservoir.
THS3201
OUT2
47pF
R
PU
R
G
R
F
The capacitance and the switching action of the ADC
AV
DD
is one of the worst loading scenarios that
a
V
S-
high-speed amplifier encounters. The resistor
provides a simple means of isolating the associated
phase shift from the feedback network and
maintaining the phase margin of the amplifier.
0.1 µF
Figure 62. Differential DAC Driver Circuit
Typically, a low-value resistor in the range of 10 Ω to
100 Ω provides the required isolation. Together, the
R and C form a real pole in the s-plane located at the
frequency:
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Printed-Circuit Board Layout Techniques for
Optimal Performance
resistors, excessively high resistor values can
create significant time constants that can degrade
performance.
Good
axial
metal-film
or
Achieving optimum performance with high-frequency
amplifier-like devices in the THS3201 requires careful
attention to board layout parasitic and external
component types.
surface-mount resistors have approximately
0.2 pF in shunt with the resistor. For resistor
values >2 kΩ, this parasitic capacitance can add a
pole and/or a zero that can effect circuit operation.
Keep resistor values as low as possible,
consistent with load driving considerations.
Recommendations that optimize performance include:
•
Minimize parasitic capacitance to any power or
ground plane for the negative input and ouput pins
by voiding the area directly below these pins and
connecting traces and the feedback path.
Parasitic capacitance on the output and negative
input pins can cause instability. To reduce
unwanted capacitance, a window around the
signal I/O pins should be opened in all of the
ground and power planes around those pins and
the feedback path. Otherwise, ground and power
planes should be unbroken elsewhere on the
board.
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils) should
be used, preferably with ground and power planes
opened up around them. Estimate the total
capacitive load and determine if isolation resistors
on the outputs are necessary. Low parasitic
capacitive loads (<4 pF) may not need an RS
since the THS3201 is nominally compensated to
operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded
phase margin). If a long trace is required and the
6-dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for these techniques).
A 50-Ω environment is not necessary onboard
and, in fact, a higher-impedance environment
improves distortion as shown in the distortion
versus load plots. With a characteristic board
trace impedance based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS3201 is used,
as well as a terminating shunt resistor at the input
of the destination device.
•
Minimize the distance (<0.25 in) from the
power-supply pins to high frequency 0.1-µF and
100-pF decoupling capacitors. At the device pins,
the ground and power-plane layout should not be
in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power-supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board. The primary goal is to
•
minimize
the
impedance
seen
in
the
differential-current return paths. For driving
differential loads with the THS3201, adding a
capacitor between the power-supply pins
improves
2nd
order
harmonic
distortion
•
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device; this
total effective impedance should be set to match
the trace impedance. If the 6-dB attenuation of a
performance. This also minimizes the current loop
formed by the differential drive.
•
Careful selection and placement of external
components preserve the high frequency
performance of the THS3201. Resistors should be
a low-reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Again,
keep their leads and PC board trace length as
short as possible. Never use wirebound-type
resistors in a high-frequency application. Since the
output pin and inverting input pins are the most
sensitive to parasitic capacitance, always position
the feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed close
doubly-terminated
unacceptable,
transmission
long trace
line
can
is
be
a
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high-speed part such as the THS3201
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network, which can make it almost
•
to the gain-setting resistors. Even with
low-parasitic capacitance shunting the external
a
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impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
0.205
THS3201 parts directly onto the board.
0.060
0.017
PowerPAD Design Considerations
Pin 1
0.013
The THS3201 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which
the die is mounted [see Figure 63(a) and
Figure 63(b)]. This arrangement results in the lead
frame being exposed as a thermal pad on the
underside of the package [see Figure 63(c)]. Because
this thermal pad has direct thermal contact with the
die, excellent thermal performance can be achieved
by providing a good thermal path away from the
thermal pad.
0.030
0.075
0.025 0.094
0.035
0.040
0.010
vias
Top View
Figure 64. DGN PowerPAD PCB Etch and Via
Pattern
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
PowerPAD PCB Layout Considerations
1. Prepare the PCB with a top-side etch pattern as
shown in Figure 64. There should be etch for the
leads as well as etch for the thermal pad.
package into either
heat-dissipating device.
a ground plane or other
2. Place five holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal-pad
area. This helps dissipate the heat generated by
the THS3201 IC. These additional vias may be
larger than the 10-mil diameter vias directly under
the thermal-pad. They can be larger because
they are not in the thermal pad area to be
soldered so that wicking is not a problem.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
4. Connect all holes to the internal ground plane.
Figure 63. Views of Thermally Enhanced Package
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer.
Therefore, the holes under the THS3201
Although there are many ways to properly heat sink
the PowerPAD package, the following steps define
the recommended approach.
PowerPAD
connection to the internal ground plane with a
complete connection around the entire
circumference of the plated-through hole.
package
should
make
their
6. The top-side solder mask should leave the
terminals of the package and the thermal-pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal-pad area. This prevents solder from
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being pulled away from the thermal-pad area
during the reflow process.
the effect of not soldering the PowerPAD to a PCB.
The thermal impedance increases substantially,
which may cause serious heat and performance
issues. Be sure to always solder the PowerPAD to
the PCB for optimum performance.
7. Apply solder paste to the exposed thermal-pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
4.0
T
J
= 125°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
θ
= 58.4°C/W
JA
θ
= 98°C/W
JA
Power Dissipation and Thermal
Considerations
To maintain maximum output capabilities, the
THS3201 does not incorporate automatic thermal
shutoff protection. The designer must take care to
ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure
may result if the absolute maximum junction
temperature of 150°C is exceeded. For the best
θ
= 158°C/W
JA
-40 -20
0
20
40
60
80 100
T
A
- Free-Air Temperature - °C
Results are With No Air Flow and PCB Size = 3”x3”
performance, design for
a
maximum junction
θ
θ
θ
= 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
= 98°C/W for 8-Pin SOIC High Test PCB (D)
= 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
JA
JA
JA
temperature of 125°C. Between 125°C and 150°C,
damage does not occur, but the performance of the
amplifier begins to degrade.
Figure 65. Maximum Power Dissipation vs
Ambient Temperature
The thermal characteristics of the device are dictated
by the package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
When determining whether or not the device satisfies
the maximum power-dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
Tmax * TA
qJA
PDmax
+
where:
P
is the maximum power dissipation in the
Dmax
amplifier (W).
T
max
is the absolute maximum junction
temperature (°C).
T is the ambient temperature (°C).
A
Design Tools
θ
θ
= θ + θ
JC CA
is the thermal coefficient from the silicon
JA
JC
Evaluation Fixture, Spice Models, and
Applications Support
junctions to the case (°C/W).
θ
is the thermal coefficient from the case to
CA
ambient air (°C/W).
TI is committed to providing its customers with the
highest quality of applications support. To support this
goal, an evaluation board has been developed for the
THS3201 operational amplifier. The board is easy to
use, allowing for straightforward evaluation of the
device. The evaluation board can be ordered through
the TI web site, www.ti.com, or through your local TI
sales representative. The schematic diagram, board
layers, and bill of materials of the evaluation boards
are in Figure 66 through Figure 70.
For systems where heat dissipation is more critical,
the THS3201 is offered in an 8-pin MSOP with
PowerPAD and the THS3201 is available in the
SOIC-8 PowerPAD package offering even better
thermal performance. The thermal coefficient for the
PowerPAD packages are substantially improved over
the traditional SOIC. Maximum power dissipation
levels are listed in the Dissipation Ratings table.. The
data for the PowerPAD packages assume a board
layout that follows the PowerPAD layout guidelines
referenced above and detailed in the PowerPAD
application report SLMA002. Figure 65 also shows
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PD
J9*
C8*
R5
768 Ω
Vs+
7
2
8
U1
6
R3
J1
Vin
_
+
R6
-
J4
3
768 Ω
R2
49.9 Ω
Vout
0 Ω
R7
4
1
Not Populated
Vs -
J8*
D Ref
J2
Vin+
C7*
R4
49.9 Ω
*Does Not Apply to the THS3201
J6
GND TP1
J5
VS+
FB2
J7
VS-
VS-
VS+
FB1
+
C1
+
C2
C6
0.1 µF
C5
C3
0.1 µF
C4
100 pF
22 µF
100 pF
22 µF
Figure 66. THS3201 EVM Circuit Configuration
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Figure 67. THS3201 EVM Board Layout
(Top Layer)
Figure 69. THS3201 EVM Board Layout
(Third Layer, Power)
Figure 68. THS3201 EVM Board Layout
(Second Layer, Ground)
Figure 70. THS3201 EVM Board Layout
(Bottom Layer)
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Table 2. Bill of Materials(1)
THS3201DGN EVM
PCB
QUANTITY
ITEM
DESCRIPTION
Bead, ferrite, 3 A, 80 Ω
SMD SIZE
REF DES
MANUFACTURER PART NUMBER
1
2
1206
D
FB1, FB2
C1, C2
C4, C5
C3, C6
R7
2
2
2
2
1
1
2
2
1
1
1
2
3
(Steward) HI1206N800R-00
(AVX) TAJD226K025R
Cap, 22 F, tanatalum, 25 V, 10%
Cap, 100 pF, ceramic, 5%, 150 V
Cap, 0.1 F, ceramic, X7R, 50 V
Open
3
AQ12
0805
0805
0805
0805
1206
1206
1206
(AVX) AQ12EM101JAJME
(AVX) 08055C104KAT2A
4
6
7
Resistor, 49.9 Ω, 1/8 W, 1%
Resistor, 768 Ω, 1/8 W, 1%
Open
R6
(Phycomp) 9C08052A49R9FKHFT
(Phycomp) 9C08052A7680FKHFT
9
R3, R5
C7, C8
R2
10
11
12
13
14
Resistor, 0 Ω, 1/4 W, 1%
Resistor, 49.9 Ω, 1/4 W, 1%
Test point, black
(KOA) RK73Z2BLTD
R4
(Phycomp) 9C12063A49R9FKRFT
(Keystone) 5001
TP1
Open
J8, J9
J5, J6, J7
Jack, Banana Receptance, 0.25” dia.
hole
(HH Smith) 101
15
16
17
18
19
20
Connector, edge, SMA PCB jack
Standoff, 4-40 hex, 0.625” length
Screw, Phillips, 4-40, .250”
IC, THS3201
J1, J2, J4
3
4
4
1
1
(Johnson) 142-0701-801
(Keystone) 1804
SHR-0440-016-SN
U1
(Texas Instruments) THS3201DGN
(Texas Instruments) Edge # 6447972 Rev.A
Board, printed circuit
(1) The components shown in the BOM were used in test by TI.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF-amplifier circuits,
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the THS4500 family of devices is available
through the TI web site (www.ti.com). The Product
Information Center (PIC) is available for design
assistance and detailed product information. These
models do a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. They are not intended to model
the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package
types in their small-signal ac performance. Detailed
information about what is and is not modeled is
contained in the model file itself.
Additional Reference Material
•
•
•
•
•
•
PowerPAD™ Made Easy, application brief
(SLMA004)
PowerPAD™
Thermally-Enhanced
Package,
technical brief (SLMA002)
Voltage Feedback vs Current Feedback Amplifiers
(SLVA051)
Current Feedback Analysis and Compensation
(SLOA021)
Current Feedback Amplifiers: Review, Stability,
and Application (SBOA081)
Effect of Parasitic Capacitance in Op Amp Circuits
(SLOA013)
26
Submit Documentation Feedback
Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3201-EP
PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
THS3201MDGNREP
V62/05609-01YE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
8
8
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-1-260C-UNLIM
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS3201-EP :
Catalog: THS3201
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2012
Catalog - TI's standard catalog product
•
Addendum-Page 2
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