TAS3208PZPR [TI]
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE; 具有模拟接口的数字音频处理器
| 型号： | TAS3208PZPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE |
| 文件： | 总9页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A–JANUARY 2007–REVISED FEBRUARY 2007
FEATURES
–
–
–
–
135-MHz Operation
•
Audio Input/Output
48-Bit Data Path With 76-Bit Accumulator
Hardware Single Cycle Multiplier (28 × 48)
–
–
–
Three Synchronous Serial Audio Inputs
(Six Channels)
Two Memory Loads and One Memory Store
Per Cycle
Two Synchronous Serial Audio Outputs
(Four Channels)
–
Usable 768 Data RAM Words (48 Bit),
Usable 1K Coefficient RAM (28 Bit)
Input and Output Data Formats: 16-, 20-, or
24-Bit Data Left, Right, and I2S
–
–
Usable 2.5K Program RAM
–
–
–
SPDIF Transmitter
360 mS @ 48KHz, 17280 Words 24-Bit
Delay Memory for Video Sync
64 × Fs Bit Clock Rate
512 × Fs XTAL Input for Master-Mode
•
System Control Processor
Clock Rates
–
–
Embedded 8051 WARP Microprocessor
–
–
256 × Fs MCLKIN for Slave-Mode Clock
Rates
Programmable Using Standard 8051 C
Compilers
Ten Multiplexed Stereo Analog Inputs
Selectable Into One Stereo ADC and Three
Stereo Line Outputs
–
–
16K Words of Program RAM (8 Bit)
Programmable Using Standard 8051 C
Compilers
–
High-Quality 93 dB DNR (Typical) ADC
Channel Performance (Two Channels)
–
–
–
2048 Words of Data RAM (8 Bit)
256 Words of Internal RAM (8 Bit)
Programmable Functionality
–
A Single Ended Analog Stereo Line
Driver Output With 1 of 11 Selectable
Inputs, 10-kΩ, 100-pF Drive Capability
(Typical Output Level: 1-V RMS)
•
General Features
–
–
Easy to Use Control Interface
I2C Serial Control Master and Slave
–
Three Stereo Audio DACs
Interface
–
High-Quality 96-dB DNR (Typical) DAC
Channel Performance (Six Channels)
–
Control Interface Operational Without
External MCLK Input
–
Stereo Headphone Amplifier – 24 mW
Power Output Into 16 Ω, 100 pF
–
–
–
Single 3.3-V Power Supply
Integrated Regulators
100-Pin TQFP Package
•
Audio Digital Signal Processor
Programmable Functionality
–
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A–JANUARY 2007–REVISED FEBRUARY 2007
TQFP PACKAGE
(TOP VIEW)
DVSS1
/VREG_EN
STEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
V1P5_REF
BG_REF
BIAS_REF
AVSS_ADC /REF
AVDD_ADC
LINEIN10R
LINEIN10L
Test
Test
GPIO4
GPIO3
MCLKOUT
LRCLKOUT
SCLKOUT
SDOUT1
AVSS_LI
LINEIN9R
LINEIN9L
AVDD_LI
LINEIN8R
LINEIN8L
AVSS_LI
LINEIN7R
LINEIN7L
AVDD_LI
LINEIN6R
LINEIN6L
AVSS_LI
LINEIN5R
LINEIN5L
SDOUT 2 / SPDIFOUT
DVDD2
VR_DIG1
DVSS2
SPDIF_IN
Test
Test
Test
Test
SDIN3
SDIN2
SDIN1
LRCLKIN
SCLKIN
53
52
51
AVDD_LI
LINEIN4R
LINEIN4L
DESCRIPTION/ORDERING INFORMATION
The TAS3208 is an audio SOC designed for digital TV Audio Systems and Mini/Micro Component applications.
TAS3208 has a programmable audio DSP that preserves high-quality audio by using a 48-bit data path, 28-bit
filter coefficients, and a single-cycle 28 times 48-bit multiplier. The programmability feature allows users to
customize features in the DSP RAM.
The TAS3208 is composed of seven functional blocks.
•
•
•
•
•
•
Clock and Serial Data Interface
Analog Input and Output
8051 WARP Controller, Serial Control Interface and Device Control
Audio DSP – Digital Audio Processing
Power Supply
Internal References
ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TBD
TQFP – YZP
TBD
TAS3208YZPR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
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TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A–JANUARY 2007–REVISED FEBRUARY 2007
BLOCK DIAGRAM
10 pf
512 Fs
10 pf
OSC
AVSS AVSS
TBD
MCLKIN
MCLKOUT
Clock
Control
SCLKIN
SCLKOUT
LRCLKIN
SCLKI
LRCLKI
SDIN
1
2
3
SDOUT
1
SAP
IN
Audio
SAP
OUT
2
SDIN
SDIN
LRCLKOUT
processing
MUTEZ
Control
SPDIF OUT
/
SDOUT
2
3:1
MUX
SDA
1
SPDIF
SPDIF IN
SCL 1
SDA
SCL
CS
2
I 2
C
8051
2
DAC
Mod
47 uF
16 Ohm
HP OUT L / R
2
GPIO 1-4
HP AMP
10
K ohm
2
10 ch stereo
Analog line Input
2
2
DACOUT 2L/ R
DACOUT 1 L/ R
10 ch stereo
Analog
Inputs
6 CH
DAC
33 K
Apply to all Line and
DAC outputs
A -MUX
10 : 1
2 CH
ADC
2.8V
2
RMS
1V
RMS
0.8 uF
A- MUX
11:1
2.2uF
2
LINEOUT 1L/R
10 ch stereo
10 K ohm
Line outputs
DAC outputs
1V
RMS
RMS
(
(
MAX
MAX
)
0.9 V
)
3
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TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A–JANUARY 2007–REVISED FEBRUARY 2007
TYPICAL APPLICATIONS
The TAS3208 may be used with an external Asynchronous Sample Rate Converter (ASRC) to
accommodate asynchronous serial inputs at different sampling rates. An example of this is shown in the
block diagram of Figure 2.2.
10
pf
512
Fs
pf
OSC
AVSS
AVSSTBD
10
MCLKIN
MCLKOUT
SCLKOUT
Clock
SCLKIN
Control
LRCLKIN
External
ASRC
SCLKI
SDIN 1A
SDIN 2B
MUX
SDI
1
LRCLKI
SDIN
1
2
3
SDO
SDO
SDO
1
2
3
SDOUT
1
SAP
IN
Audio
SAP
OUT
SDIN 3B
SDIN 4B
2
SDIN
SDIN
SDI
SDI
2
3
LRCLKOUT
processing
SCLKA
LRCLKA
SCLKO
LRCLKO
MCLKO
SCLKI
LRCLKI
MCLKI
MCLKA
SCLKB
MUTEZ
MUX
Control
SPDIF OUT
/
LRCLKB
MCLKB
SDOUT 2
3: 1
MUX
SDA
1
SPDIF
SPDIF IN
SCL 1
I 2
C
SDA
SCL
CS
2
8051
2
DAC
Mod
HP OUT L
/ R
2
GPIO 1-4
HP AMP
2
2
DACOUT 2 L/R
DACOUT 1 L/R
10 ch stereo
Analog
Inputs
2
6CH
DAC
A
-MUX
10 :1
2 CH
ADC
2
A- MUX
11:1
2
LINEOUT 1 L/R
10 ch stereo
Figure 1. TAS3208 and interface to external ASRC
4
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TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A–JANUARY 2007–REVISED FEBRUARY 2007
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX UNIT
DVDD Supply voltage range
3.8
3.8
V
V
AVDD
Supply voltage range
Input voltage range
3.3-V TTL
VDDS + 0.5
AVDDS + 0.5
AVDD + 0.5(2)
VDDS + 0.5
AVDDS + 0.5
DVDD + 0.5(3)
AVDD + 0.5(4)
±20
VI
3.3-V analog
V
1.8-V LVCMOS
3.3-V TTL
3.3-V analog
Voltage range applied to any output in the high-impedance
or power-off state
VO
V
1.8-V LVCMOS
1.8-V LVCMOS
VI < 0 or VI > DVDD
VO < 0 or VO > DVDD
IIK
Input clamp current
mA
mA
°C
IOK
Tstg
Output clamp current
±20
Storage temperature range
–65
150
Lead temperature 1,6 mm (1/16 in) from case for 10 s
260
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AVDD is an internal 1.8-V supply derived from a regulator in the CXD9890Q chip. Pin XTALI is the only CXD9890Q input that is
referenced to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI.
(3) DVDD is an internal 1.8-V supply derived from regulators in the CXD9890Q chip. DVDD is routed to– DVDD_BYPASS_CAP – to provide
access to external filter capacitors, but should not be used to source power to external devices.
(4) Pin XTALO is the only CXD9890Q output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed
is for reference; only a crystal should be connected to XTALO. AVDD is also routed to – AVDD_BYPASS_CAP – to provide access to
external filter capacitors, but should not be used to source power to external devices.
RECOMMENDED OPERATING CONDITIONS
MIN
3.0
NOM
3.3
MAX UNIT
DVDD Digital supply voltage
3.6
3.6
V
V
AVDD
Analog supply voltage
3.3-V analog
3.0
3.3
3.3-V TTL
2.0
VIH
High-level input voltage
V
V
1.8-V LVCMOS (XTL_IN)
3.3-V TTL
1.26
1.95
0.8
VIL
Low-level input voltage
1.8-V LVCMOS (XTL_IN)
0.54
70
TA
TJ
Operating ambient air temperature (ensuring Parametric)
Operating junction temperature
–20
–20
25
°C
°C
105
5
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TAS3208
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
www.ti.com
SLES201A–JANUARY 2007–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
3.3-V TTL
IOH = –4 mA
IOH = –0.55 mA
IOL = 4 mA
2.4
High-level output
voltage
VOH
V
1.8-V LVCMOS
(XTL_OUT)
1.44
3.3-V TTL
0.5
Low-level output
voltage
VOL
V
1.8-V LVCMOS
(XTL_OUT)
IOL = 0.75 mA
0.396
High-impedance
output current
IOZ
3.3-V TTL
±20
µA
µA
1.8-V LVCMOS
(XTL_IN)
VI = VIL
VI = VIL
VI = VIH
VI = VIH
±1
±1
Low-level input
current
(1)
IIL
3.3-V TTL
1.8-V LVCMOS
(XTL_IN)
±1
High-level input
current
(2)
IIH
µA
3.3-V TTL
±1
Digital supply
current
DSP clock = 135-MHz LRCLKIN/LRCLKOUT = 48 KHz,
XTALI = 24.288 MHz
IDVDD
IAVDD
IDVDD
IAVDD
200
mA
mA
mA
mA
Analog supply
current
DSP clock = 135-MHz LRCLKIN/LRCLKOUT = 48 KHz,
XTALI = 24.288 MHz
28
0.1
5
Digital supply
current
RESET = Low
RESET = Low
Analog supply
current
(1) Value given is for those input pins that connect to an internal pull-up resistor as well as an input buffer. For inputs that have a pull-down
resistor or no resistor, IIL is ± 1 µa.
(2) Value given is for those input pins that connect to an internal pull-down resistor as well as an input buffer. For inputs that have a pull-up
resistor or no resistor, IIH is ± 1 µa.
6
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2007
PACKAGING INFORMATION
Orderable Device
TAS3208PZP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PZP
100
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS3208PZPR
HTQFP
PZP
100
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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