TAS3218_1_技术文档

TAS3218

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DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE

1

FEATURES

•

Audio Digital Signal Processor

2

•

Audio Input/Output

–

Programmable Functionality

135-MHz Operation

–

3 Synchronous Serial Audio Inputs

(6 Channels)

48-Bit Data Path With 76-Bit Accumulator

2 Synchronous Serial Audio Outputs

(4 Channels)

Two Memory Loads and One Memory Store

Per Cycle

Input and Output Data Formats: 16-, 20-, or

24-Bit Data Left, Right ,and I²S

–

Usable 768 Data RAM Words (48-Bit),

Usable 1K Coefficient RAM (28-Bit)

–

SPDIF Transmitter

–

Usable 2.5K Program RAM

64 Fs Bit Clock Rate

360 ms at 48 kHz, 17408 Words 24-Bit Delay

Memory for Video Sync

512 Fs XTAL Input for Master Mode Clock

Rates

•

System Control Processor

–

256 Fs MCLKIN for Slave Mode Clock Rates

–

Embedded 8051 WARP Microprocessor

10 Multiplexed Stereo Analog Inputs

Selectable into 1 Stereo ADC and 3 Stereo

Line Outputs

Programmable Using Standard 8051 C

Compilers

–

16K Words of Program RAM (8-Bit)

2048 Words of Data RAM (8-Bit)

256 Words of Internal RAM (8-Bit)

Programmable Functionality

–

High Quality DNR: 93 dB (Typical) ADC

Channel Performance (2 Channels)

3 Single-Ended Analog Stereo Line Driver

Outputs With 1 of 11 Selectable Input, 10 k

•

General Features

100-pF Drive Capability (Typical Output

Level: 1 Vrms)

–

Easy-to-Use Control Interface

I²C Serial Control Master and Slave

Interface

–

3 Stereo Audio DACs

High-Quality DNR: 97 dB (Typical) DAC

Channel Performance (6 Channels)

–

Control Interface Operational Without

External MCLK Input

–

Stereo Headphone Amplifier 24 mW Power

Output into 16 , 100 pF

–

Single 3.3-V Power Supply

Integrated Regulators

100-Pin TQFP (PZP) Package

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TAS3218

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The TAS3218 is available in a 100-pin TQFP (PZP) package.

PZP PACKAGE

(TOP VIEW)

V1P5_REF

BG_REF

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DVSS1

VREG_EN

STEST

1

2

3

BIAS_REF

AVSS_ADC/REF

AVDD_ADC

LINEIN10R

LINEIN10L

AVSS_LI

4

TEST

5

TEST

6

GPIO4

7

GPIO3

8

MCLKOUT

LRCLKOUT

SCLKOUT

SDOUT1

SDOUT2/SPDIFOUT

DVDD2

9

LINEIN9R

LINEIN9L

AVDD_LI

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

LINEIN8R

LINEIN8L

AVSS_LI

VR_DIG1

DVSS2

LINEIN7R

LINEIN7L

AVDD_LI

SPDIF_IN

TEST

LINEIN6R

LINEIN6L

AVSS_LI

TEST

SDIN3

LINEIN5R

LINEIN5L

AVDD_LI

SDIN2

SDIN1

LRCLKIN

SCLKIN

LINEIN4R

LINEIN4L

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

TAS3218IPZP

TAS3218IPZPR

TAS3218PZP

TAS3218PZPR

–40°C to 85°C

TAS3218IPZP

TAS3218PZP

TQFP–PZP

Tape and reel

–20°C to 70°C

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

2

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TERMINAL FUNCTIONS

TERMINAL

I/O

TERMINATION⁽¹⁾DESCRIPTION

NO.

1

NAME

DVSS1

P

Digital ground

2

VREG_EN

STEST

DI

Voltage regulator enable

3

Pulldown

Test pin to reconfigure pins

4, 5,

17, 18,

19, 20

TEST

6

7

GPIO4

GPIO3

DIO

DO

Pulldown

General purpose input/output 4

General purpose input/output 3

Master clock output

8

MCLKOUT

LRCLKOUT

SCLKOUT

SDOUT1

9

Left/right (frame) clock output

Serial audio data clock output

Serial digital audio data output 1

10

11

SDOUT2/

SPDIF_OUT

12

13

DO

P

Serial digital audio data out 2 or S/PDIF out

3.3-V digital power

DVDD2

Pin out of internal regulator. A 4.7-F low ESR capacitor should be

connected between this pin and digital ground. This terminal must not be

used to power external devices.

14

VR_DIG1

P

15

16

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

DVSS2

SPDIF_IN

SDIN3

P

DI

Digital ground

S/PDIF input

DI

Serial digital audio data input 3

Serial digital audio data input 2

Serial digital audio data input 1

Left/right (frame) clock input

Serial audio data clock input

Master clock input

SDIN2

DI

SDIN1

DI

LRCLKIN

SCLKIN

MCLKIN

DVSS3

DVDD3

I2C_SDA2

I2C_SCL2

I2C_SDA1

I2C_SCL1

CS

DI

P

Digital ground

P

3.3-V digital power master

I²C serial data master

I²C serial clock slave

I²C serial data slave

I²C serial clock

DIO

DI

Chip select

GPIO1

DIO

DI

General purpose input/output 1

General purpose input/output 2

Mute device

GPIO2

MUTE

Pullup

RESET

DVSS4

DVDD4

DVSS5

DI

Reset

P

Digital ground

P

3.3-V digital power

P

3.3-V digital power

Pin out of internal regulator. A 4.7-F low ESR capacitor should be

connected between this pin and digital ground. This terminal must not be

used to power external devices.

41

VR_DIG2

P

42

43

AVSS_ESD

LINEIN1L

P

Analog ESD ground

AI

Left-channel analog input 1

(1) All pullups are 20-A weak pullups, and all pulldowns are 20-A weak pulldowns (166 k) . The pullups and pulldowns are included to

ensure proper input logic levels if the terminals are left unconnected (pullups at logic 1 input; pull-downs at logic 0 input). Devices that

drive inputs with pullups must be able to sink 20 A while maintaining a logic 0 drive level. Devices that drive inputs with pull-downs must

be able to source 20 A while maintaining a logic 1 drive level.

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TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

TERMINATION⁽¹⁾DESCRIPTION

Right-channel analog input 1

NO.

NAME

44

LINEIN1R

AI

P

45, 53,

59, 65

AVDD_LI

3.3-V analog power

46

47

LINEIN2L

LINEIN2R

AI

Left-channel analog input 2

Right-channel analog input 2

48, 56,

62, 68

AVSS_LI

P

Analog ground

49

50

51

52

54

55

57

58

60

61

63

64

66

67

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

LINEIN3L

LINEIN3R

AI

Left-channel analog input 3

Right-channel analog input 3

Left-channel analog input 4

LINEIN4L

AI

LINEIN4R

AI

Right-channel analog input 4

Left-channel analog input 5

LINEIN5L

AI

LINEIN5R

AI

Right-channel analog input 5

Left-channel analog input 6

LINEIN6L

AI

LINEIN6R

AI

Right-channel analog input 6

Left-channel analog input 7

LINEIN7L

AI

LINEIN7R

AI

Right-channel analog input 7

Left-channel analog input 8

LINEIN8L

AI

LINEIN8R

AI

Right-channel analog input 8

Left-channel analog input 9

LINEIN9L

AI

LINEIN9R

AI

Right-channel analog input 9

Left-channel analog input 10

Right-channel analog input 10

3.3-V analog power

LINEIN10L

LINEIN10R

AVDD_ADC

AVSS_ADC/REF

BIAS_REF

BG_REF

AI

P

Analog ground

AO

P

Pin should be tied to analog ground with 22-k 1%

Band gap output. Must be tied to ground with 1-F low ESR capacitor.

Common mode output. Must be tied to ground with 1-F low ESR capacitor.

3.3-V analog power

V1P5_REF

AVDD_REF

LINEOUT3L

LINEOUT3R

LINEOUT2L

LINEOUT2R

AVSS_LO

LINEOUT1L

LINEOUT1R

DACOUT1L

DACOUT1R

DACOUT2L

DACOUT2R

AVSS_DAC

AVDD_DAC

AVDD_HP

HPOUTL

AO

P

Analog line output #3 left channel

Analog line output #3 right channel

Analog line output #2 left channel

Analog line output #2 right channel

Analog ground

AO

P

Left-channel analog output 1

Right-channel analog output 1

Left-channel digital-to-analog converter output 1

Right-channel digital-to-analog converter output 1

Left-channel digital-to-analog converter output 2

Right-channel digital-to-analog converter output 2

Analog ground

P

3.3-V analog power

P

3.3-V analog power

AO

P

Left-channel headphone output

Analog ground

AVSS_HP

HPOUTR

AO

P

Right-channel headphone output

3.3-V analog power

AVDD_HP

4

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TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

TERMINATION⁽¹⁾DESCRIPTION

NO.

95

NAME

AVSS_ESD

XTAL_IN

P

Analog ground

96

DI

External crystal input

97

XTAL_OUT

DO

External crystal output

Pin out of internal regulator. A 4.7-F low ESR capacitor should be

connected between this pin and digital ground. This terminal must not be

used to power external devices.

98

VR_ANA

P

99

AVDD_OSC

DVDD1

P

3.3-V analog power

3.3-V digital power

100

DESCRIPTION

TAS3218 is an audio system-on-a-chip (SOC) designed for digital television audio systems and mini/micro

component applications. TAS3218 has a programmable audio DSP that preserves high-quality audio by using a

48-bit data path, 28-bit filter coefficients, and a single cycle 28 x 48-bit multiplier. The programmability feature

allows users to customize features in the DSP RAM.

The TAS3218 is composed of seven functional blocks.

•

Clock and serial data interface

Analog input and output

M8051 WARP controller, serial control interface, and device control

Audio DSP digital audio processing

Power supply

Internal references

Figure 1 shows the functional structure of the TAS3218.

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TAS3218

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TBD

10 pf

512 Fs 512Fs

OSC

AVSS

TBD

AVSS

10 pf

MCLKIN

MCLKOUT

SCLKOUT

Clock

Control

SCLKIN

LRCLKIN

SCLKI

LRCLKI

SDIN

1

2

3

SDOUT

1

SAP

IN

Audio

processing

SAP

OUT

2

SDIN

LRCLKOUT

MUTEZ

Control

SPDIF OUT

/

SDOUT

2

3:1

MUX

SDA 1

SCL 1

SDA 2

SCL 2

CS

SPDIF

SPDIF IN

I ²

C

8051

DAC

Mod

47 uF

220

16 Ohm

HP OUT L / R

2

GPIO 1-4

HP AMP

10 K ohm

2

DACOUT 2L/ R

DACOUT 1 L/ R

10 ch stereo

Analog

Inputs

Analog line Input

2

6CH

DAC

33K

1V

A -MUX

10:1

2CH

ADC

A-MUX

11:1

2.8V

RMS

2

LINEOUT 1L/R

LINEOUT 2L/R

LINEOUT 3L/R

Apply to all Line and

DAC outputs

RMS

0.8uF

2.2uF

A-MUX

10:1

10K ohm

10 ch stereo

A-MUX

10:1

Line outputs

DAC outputs

1V

RMS( MAX

)

0.9V

)

Figure 1. Block Diagram

6

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TBD

10pf

512 Fs 512Fs

OSC

AVSS

TBD

10pf

MCLKIN

MCLKOUT

SCLKOUT

Clock

Control

SCLKIN

LRCLKIN

External

ASRC

SCLKI

SDIN1A

SDIN2B

MUX

SDI1

LRCLKI

SDIN 1

SDO 1

SDOUT 1

SAP

IN

Audio

processing

SAP

OUT

SDIN3B

SDIN4B

SDIN 2

SDIN 3

2

SDO 2

SDO 3

SDI2

SDI3

LRCLKOUT

SCLKA

LRCLKA

MCLKA

SCLKO

SCLKI

LRCLKI

MCLKI

LRCLKO

MCLKO

MUTEZ

Control

MUX

SCLKB

LRCLKB

MCLKB

SPDIF OUT

/

SDOUT 2

3:1

MUX

SDA1

SCL1

SDA2

SCL 2

CS

SPDIF

SPDIF IN

I ²

C

8051

DAC

Mod

HP OUT L / R

2

GPIO 1-4

HP AMP

2

DACOUT 2L/R

DACOUT 1L/R

10 ch stereo

Analog

Inputs

6CH

2

A -MUX

10:1

2CH

DAC

2

ADC

A- MUX

11:1

2

LINEOUT 1L/R

10 ch stereo

Figure 2. Interface to External ASRC

Clocks

The TAS3218 can be configured as either the clock master or clock slave depending on the settings in the clock

configuration register. By default, the TAS3218 is configured as the clock master. Figure 3 shows the block

diagram of the TAS3218 clocks

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SDA SCL

I2C Sampling Clock

(N = 0)

DIV by 2^N

Digital Signal Processor

(DSP)

I2C Module

DIV by

(M+1)

N[2:0]

DIV by 10

DSP_CLK

(135MHz)

I2C Master SCL

M[2:0]

2816Fs

DPLL

(11x)

Clock

(M = 8)

DIV BY

8051uC & Control

4

MICRO_CLK

(33MHz)

SPDIF _CONTROL_REG_IN[ ]

CMS

Parallel Data from DSP SPDIF _L[23:0]

Parallel Data from DSP SPDIF _R[23:0]

spdif_tx_out

SPDIF

Transmitter

256Fs

DIV BY

MCLKIN

DIV BY

2

0

1

2

512Fs

SPDIF_CLK

(Audio Output Select - Control Bits [1:0]

128Fs

DIV BY

4

from SPDIF Control Register

: 0x16)

OSC

OUTMUX [1:0]

64Fs

Fs

DIV BY

8

CMS (Clock Master /Slave Selection )

SPDIF_MUTE

(Mute Control Register : 0x09)

DIV BY

512

01

MCLKIN

0

1

MCLKOUT

SCLKOUT

00

1*

0

SPDIF_OUT/

256Fs

SDOUT2

1

0

CMS

0

SPDIF _IN

SCLKIN

64Fs

1

Data from DSP Ch 1[23:0]

Data from DSP Ch 2[23:0]

Data from DSP Ch 3[23:0]

Data from DSP Ch 4[23:0]

SAPOUT_MUTE [1:0]

CMS

SDOUT 1

SAP OUT

LRCLKIN

0

1

(Transmitter )

sdout2

Fs

OW[1:0] (SAP Output Word Size

OM[1:0] (SAP Output Mode )

)

LRCLKOUT

(Recreation /

Normalization )

IM[1:0]

ON (Output Normalization

Enable)

LRCLKOUT

Data to DSP Ch 1[23:0]

SDIN 1

SDIN 2

SDIN 3

Data to DSP Ch 2[23:0]

Data to DSP Ch 3[23:0]

Data to DSP Ch 4[23:0]

Data to DSP Ch 5[23:0]

Data to DSP Ch 6[23:0]

SAP IN

(Receiver )

IM[1:0]

(SAP Input Mode )

IW[1:0]

(SAP Input Word Size )

Figure 3. Clocking System

Digital Audio Interface

The TAS3218 has three digital inputs that accept discrete I²S, discrete left-justified, and discrete right-justified

PCM data.

The TAS3218 has two digital outputs that provide discrete I²S, discrete left-justified, and discrete right-justified

PCM data.The second digital output can also be configured to provide S/PDIF encoded PCM data.

The TAS3218 has a SPDIF input which is capable of routing an S/PDIF encoded signal through the device. This

input is not processed by the digital audio processor (DAP) The clocking system for the device is illustrated in

Figure 4.

8

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I²C Sub Address x 00

31 25 24

23 21 18 16

15 13 11

9

7

5

3

1

0

S Slave Addr Ack Sub Addr Ack Res Res CMS Ack Res Res Res ON Ack Res OW Res IW Ack Res OM Res IM Ack

IM[1] IM[0] INPUT SAP MODE

0

1

0

1

0

Left-justified

CMS CLOCK MASTER SELECT

Right-justified

I²S

0

1

Clock slave mode

Master mode

1

Reserved

OM[1] OM[0] OUTPUT SAP MODE

ON SAP OUTPUT NORMALIZATION

0

1

0

1

0

Left-justified

0

1

Normalization disable

Normalization enable

Right-justified

I²S

1

Reserved

IW[1] IW[0] INPUT SAP WORD SIZE

0

1

0

1

0

16-bit

20-bit

24-bit

1

Reserved

OW[1] OW[0] OUTPUT SAP WORD SIZE

0

1

0

1

0

16-bit

20-bit

24-bit

1

Reserved

I²C Sub Address x 01

31

23

15

7

6

2

0

S Slave Addr Ack Sub Addr Ack Res Ack Res Ack Res Ack Res

M

N

Ack

Figure 4. Clocking System I²C Mapping

Clock Master Operation

When configured as the device clock master, an external crystal is used as a reference to an internal oscillator.

In this mode of operation, all internal clocks are generated by the oscillator.

•

LRCLKOUT is fixed at 48 kHz (Fs)

SCLKOUT is fixed at 64 Fs

MCLKOUT is fixed 256 Fs

Clock Slave Operation

When configured as the device clock Slave, the DAP, MCU, and I²C interface are derived from the external

crystal, however the digital audio clocks are supplied externally.

Internal analog clocks for the analog to digital converter (ADC) and digital to analog converter (DAC) are derived

from the MCLKIN input. As a result, analog performance will depend on the quality of MCLKIN.

Degradation in analog performance is to be expected depending on the quality of MCLKIN.

The TAS3218 device does not include any internal clock error or click/pop detection/management. The muting of

the outputs at updating of sample rate dependent coefficients must be initiated by the host system controller.

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MCLKOUT, SCLKOUT, and LRCLKOUT are passed through from the clock inputs MCLKIN, SCLKIN, and

LCLKIN.

•

MCLKIN 256 Fs is supplied externally

SCLKIN 64 Fs is supplied externally

LRCLKIN Fs is supplied externally

NOTE:

In slave mode all incoming serial audio data must be synchronous to an incoming

LRCLKIN of 32, 44.1 or 48 kHz. The TAS3218 does not support the use of an

external (i.e., 24 MHz) clock input through into XTALI

Digital Audio Data Formats

Serial data is input on pins SDIN1-3 on the TAS3218, allowing up to 6 channels of digital audio input. The

TAS3218 supports 16-, 20-, or 24-bit data in left, right, or I²S serial data format. By default, all TAS3218 serial

digital inputs are configured in the 24-bit I²S format. The serial data input format is configurable via the

SAP/Clock Settings Register.

Serial data is output on pins SDOUT1-2, allowing up to 4 channels of digital audio output. By default, the SDOUT

data format is 24-bit, I²S format at the same data rate as the input. The SDOUT1-2 output uses the SCLKOUT

and LRCLKOUT signals to provide synchronization. SDOUT2 is multiplexed with an SPDIF output.

NOTE:

To avoid audio artifacts, I²C commands to reconfigure the serial audio port (SAP)

should not be issued as standalone commands, rather should be accompanied by

mute and unmute commands.

The TAS3218 uses the SCLK as a reference for both input and output samples. The negative edge of SCLK is

used to output a new data bit, where as the positive edge of SCLK is used to sample incoming serial data.

Discrete I²S Timing

I²S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. The LRCLK is LOW for the left channel and HIGH for the right channel. A bit clock running at 64

Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to

the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The

TAS3218 will mask unused trailing data bit positions.

2-Channel I²S (Philips Format) Stereo Input

32 clks

LRCLK (note reversed phase)

SCLK

Left Channel

Right Channel

MSB

LSB MSB

LSB

24-Bit Mode

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

5

1

8

4

0

7

3

6

2

5

1

4

0

3

2

1

0

23 22 21 20 19 18

16 15 14 13 12 11 10

9

5

1

8

4

0

7

3

6

2

5

1

4

0

3

2

1

0

17

20-Bit Mode

19 18

16 15 14 13 12 11 10

9

5

8

7

3

6

19 18

9

5

8

4

7

3

6

2

17

16 15 14 13 12 11 10

16-Bit Mode

15 14 13 12 11 10

9

8

7

6

4

2

15 14 13 12 11 10

9

8

7

6

A. All data are presented in 2's complement form with MSB first.

Figure 5. SAP I²S Format 64 Fs Format

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Discrete Left-Justified

Left-justified (LJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and

when it is for the right channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit

clock running at 64 Fs is used to clock in the data. The first bit of data appears on the data lines at the same

time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3218

will mask unused trailing data bit positions.

2-Channel Left-Justified Stereo Input

32 clks

Right Channel

LRCLK

SCLK

Left Channel

MSB

LSB MSB

LSB

24-Bit Mode

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

5

1

8

4

0

7

3

6

2

5

1

4

0

3

2

1

0

23 22 21 20 19 18

16 15 14 13 12 11 10

9

5

1

8

4

0

7

3

6

2

5

1

4

0

3

2

1

0

17

20-Bit Mode

19 18 17 16 15 14 13 12 11 10

9

5

8

7

3

6

19 18

16 15 14 13 12 11 10

9

5

8

4

7

3

6

2

17

16-Bit Mode

15 14 13 12 11 10

9

8

7

6

4

2

15 14 13 12 11 10

9

8

7

6

A. All data are presented in 2's complement form with MSB first.

Figure 6. SAP Left-Justified 64 Fs Format

Discrete Right-Justified

Right Justified (RJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and

when it is for the right channel. The L/RCLK is HIGH for the left channel and LOW for the right channel. A bit

clock running at 64 Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods

(for 24-bit data) after L/RCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before

L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3218 will

mask unused leading data bit positions.

2-Channel Right-Justified (Sony Format) Stereo Input

32 clks

Right Channel

LRCLK

SCLK

Left Channel

MSB

LSB MSB

LSB

24-Bit Mode

23 22 21 20 19 18 17 16 15 14 13 12 11 10

19 18 17 16 15 14 13 12 11 10

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

23 22 21 20 19 18

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

17

20-Bit Mode

16-Bit Mode

19 18

16 15 14 13 12 11 10

15 14 13 12 11 10

A. All data are presented in 2's complement form with MSB first.

Figure 7. SAP Right-Justified 64 Fs Format

SAP Input and Output Normalization

The TAS3218 supports SAP input and SAP output normalization. This supports simultaneous output to

left-justified and I²S devices.

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NOTE:

The normalization function is only available in Slave mode.

I²S, Left, or

Right Justified

I²S, Left, or

Right Justified

MCLKIN

SCLKIN

LRCLKIN

SDIN

MCLKOUT

SCLKOUT

LRCLKOUT

SDOUT

External

Data Source

TAS3208

DAC

Figure 8. SAP Output Normal Configuration (No Normalization)

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DAC 1

(Left Justified)

I²S

External

TAS3218

Data Source

DAC 2

(I²S)

I²S LRCLK

SCLK

I²S SDIN

MSB

Left Channel

Right Channel

Left-Justified LRCLK

Left-Justified SDOUT MSB

Left Channel

MSB

Right Channel

Figure 9. SAP Output Configuration (I²S to Left Normalization ON)

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Left-Justified

LRCLK

SCLK

Left-Justified

SDIN

MSB

Left Channel

MSB

Right Channel

I²S LRCLK

I²S SDOUT

MSB

Left Channel

MSB

Right Channel

MSB

Left Channel

Figure 10. SAP Output Configuration (I²S to Left Normalization OFF)

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DAC1

(I2S)

Left Justified

External

Data

Source

TAS3208

DAC2

(Left Jusitified)

Left Justified

LRCLK

Left Justified

LRCLK

SCLK

Left Justified

SDIN

MSB

Left Channel

Right Channel

I2S LRCLK

I2S SDOUT

MSB

Left Channel

Right Channel

Left Channel

Figure 11. SAP Output Configuration (Left to I²S Normalization ON)

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I2 S LRCLK

SCLK

MSB

I2 S SDIN

Left Channel

Right Channel

Left Justified LRCLK

MSB

Left Justified SDOUT

MSB

Left Channel

Right Channel

Figure 12. SAP Output Configuration (Left to I²S Normalization OFF)

SPDIF Encoder

The SPDIF encoder is a digital audio transmitter designed for use in consumer audio applications. Transmit data

rates up to 48 kHz are supported. The SPDIF encoder complies with the IEC-60958 interface standard.

The SPDIF encoder creates a multiplexed bit stream, containing audio, status, and user data. The multiplexed

data format is shown in Figure 14. The data is then bi-phase mark-encoded and output.

The hardware architecture of the S/PDIF Encoder can is shown in Figure 13.

SDOUT2

Serial Audio Port

Transmitter

SCLKIN

Channel Mute

Control

Serial Audio

Port

(Receiver)

LRCLKIN

SDIN

SDOUT2/

SPDIF

SPDIF Encoder

Control Signals

DAP

Analog

Interface

ANALOGIN

SPDIF_IN

SPDIF Control

Register

“0”

Output

Selector

Figure 13. SPDIF Encoder Hardware Architecture

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Start of Channel Status Block

Frame 191

Frame 0

Frame 1

X

Channel A

Channel B

Z

Channel A

Y

Channel B

X

Channel A

Y

Channel B

One Sub-Frame

Audio Data

Bits:⁰

3 4

7 8

27 28 29 30 31

Preamble Aux Data LSB

MSB V U C P

Validity Data

User Data

Channel Status Data

Parity Bit

Figure 14. SPDIF Frame Format

SPDIF Encoder Operation

The SPDIF encoder performs the multiplexing of audio, channel status, user, and validity flag. It also performs

bi-phase mark encoding of the multiplexed data stream. Audio data for both left and right channels from the DAP

are latched at the rising edge of the internal LRCLK, which marks the beginning of next sample cycle. The SPDIF

encoder then multiplexes these samples with internally generated preambles, channel status, user data, validity

flag, and parity. The channel status and validity flag are generated based on the settings in the SPDIF control

registers while the user data is fixed to all zero. The bi-phase mark encoded signal is then output starting at the

next rising edge of the internal LRCLK. The generated SPDIF stream is fixed to consumer mode linear audio

PCM format.

While the RESET input is low, the transmitter output, SPDIF_OUT, is forced to logic low level. Upon setting

RESET high, the SPDIF encoder will remain inactive until the module reset is removed by writing 0 to the RST

bit of the control register. Then this module will wait for synchronization with the internal frame clock and starts

encoding audio data. It is recommended to set all other SPDIF control register bits before releasing the module

reset.

Transmitter Control Register

Table 1 shows the M8051 SFR register map for the S/PDIF module control.

Table 1. M8051 SFR Register Map

ADDR

xx00

xx01

xx10

xx11

7

6

5

4

3

2

1

0

RST

CP

EMP

L

CATEGORY

L

ESFR

VL

SRCNUM

SR

VR

CLKAC

WORDLEN

Figure 15. I²C Register to EFSR and Hardware Connection Map

Specification Coverage

The TAS3218 is covered by the following specificaiotns:

•

IEC60956-1: Second Edition, 2004-03

IEC60956-3: Second Edition, 2003-01

IEC958-2: First Edition, 1994-07

Specifcation coverage details can be found in Table 3.

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Table 3. Specification Coverage for TAS3218⁽¹⁾

SPECIFICATION

SECTION

Interface Format (4)

SUPPORTED

REMARKS

Auto frame formatting

Yes

IEC60958-1

Channel Status (5)

First 2 bits fixed to 00. (consumer, linear PCM)

Mode 1 (software info delivery using

b32191 of channel stat) (4.2.2.14.2.2.3)

IEC958-2

No

Bits 28191 are fixed to all zero.

Channel Status General (5.1)

Yes

First channel status bit fixed to 0.

b01:

b2:

Fixed (00)

Register settable

Fixed (00)

Channel Status Application (5.2.1) –

Byte0 (control)

Yes

b35:

b67:

Category code is register settable, with default value

Yes, with restriction 0101010L (Digital Sound Processor), but user data is

fixed to all zero.

Channel Status Application (5.2.2) –

Byte1 (category)

b1619:

b2023:

b2427:

b2829:

Register settable

Channel Status Application (5.2.2)

Byte2 (source and channel number)

Yes

H/W auto set (1 for left, 2 for right channel)

Register settable (32,44.1,48 kHz only)

Register settable

Channel Status Application (5.2.2)

Byte3 (sampling freq and clock accuracy)

Yes, with restriction

IEC60958-3

H/W auto set according to register setting

24-bit original output sample is truncated

to the specified word length.

Channel Status Application (5.2.2)

Byte4 (word length, original sampling

rate, Byte0, b1, 6, 7 = 0)

b3235 :

b3639 :

Yes, partially

Fixed to all zero (not indicated)

Specifying categories other than 0101010L (Digital

Category Code Groups (5.3.2)

User Data (6)

Yes, with restriction Sound Processor), especially those require non-zero

user data is not recommended.

All zero

Clock accuracy indication is register settable.

Timing accuracy (7.2.1)

Yes

No

Expected to set level I (50 ppm) for master mode

(XTAL source) or level II (1000 ppm) for slave mode.

Standard output buffer. Needs external SPDIF driver

(ex.: optical driver)

Line driver characteristics (7.3.2)

(1) Other sections of the specification not mentioned here are either considered irrelevant or covered elsewhere. IEC60958-4 is specific for

professional applications and thus, irrelevant.

Analog Audio Interface

The TAS3218 is has 10 analog stereo inputs that are multiplexed to one analog to digital converter (ADC).

Additionally, the TAS3218 has one line output that can source any of the 10 analog stereo inputs.

The TAS3218 has three stereo digital to analog converters (DAC). The outputs of of DAC3 are designed to be

used as a 24 mW headphone amplifier or line driver. The other two DAC outputs are configured as stereo line

drivers.

Both the ADC and DAC blocks can be placed in power down when not used.

Figure 16 shows a block diagram of the Analog interface.

Stereo Analog to Digital Converter

The TAS3218 has a analog 10:1 input multiplexer and a 11:1 output multiplexer. These can accept analog stereo

inputs up to 1 Vrms. The outputs of the multiplexers are the stereo ADC and the line output.

The ADC supports a sampling rate of 48 kHz as a Clock Master Mode. In Clock Slave Mode, 32, 44.1, and 48

kHz sampling frequencies are supported, based upon the master clock frequency.

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Stereo Digital to Analog Converters

The TAS3218 has three stereo digital to analog converters (DACs). Each DAC can operate a maximum of 48

kHz. The DACs provide a 48 kHz sampling frequency in master mode. In slave mode 32, 44.1, and 48 kHz are

supported, based upon the master clock frequency. Two of the DACs are configured for providing line outputs.

One of the stereo DACs has the capability to drive either a line out or to be used as a headphone (HP) amplifier.

The stereo headphone amplifier is designed to drive up to 24 mW per channel into a headphone speaker load of

16 Ω. The headphone output is a single ended configuration using series 16-Ω resistors and AC-coupling

capacitors.

The TAS3218 includes three multiplexed stereo line driver outputs. The input to each of these line drives can be

selected to use one of the ten stereo analog input channels. Additionally, line driver output 1 can output the

contents of the stereo DAC. Each line driver is capable of driving up to a 10 kΩ load.

NOTE:

To avoid audio aritifacts when using the line driver outputs, I²C commands to

reconfigure the lineout multiplexers should not be issued alone, rather should be

accompanied by a mute/unmute sequence to all analog audio channels of the

TAS3218.

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Line Amp

–1

MUX 10:1

–1

Amp

ADC

LINE IN 10 ch

(Stereo)

1 V

(single-ended)

RMS

D2S Line Amp

MUX 11:1

+

–1

Amp

DAC 1

LINEOUT 1 L/R

(Stereo)

–1

–

MUX 10:1

V

REF

–1

Amp

LINEOUT 2/3 L/R

(Stereo)

DACOUT 1 L/R

(Stereo)

D2S Line Amp

–1

–

DACOUT 2 L/R

(Stereo)

DAC 2

+

D2S HP Amp

–1

–

DAC 3

HPOUT L/R

(Stereo)

+

Register Map for MUTE Control

0x09

Pin Name

BIT

MUTE Block

Pin Name

BIT

MUTE Block

LINEOUT1

13

12

MUX1

DACOUT1

7

6

4

2

DAC 1

Pin Name

BIT

MUTE Block

Pin Name

BIT

MUTE Block

15

13

14

MUX2

DACOUT2

5

DAC 2

LINEOUT2

Pin Name

BIT

MUTE Block

Pin Name

BIT

MUTE Block

LINEOUT3

17

MUX3

HPOUT

3

DAC 3

DESCRIPTION

0

*

0

1

0

HW Mute control

Force MUTE OFF

Force MUTE ON

1

Figure 16. Analog Input/Output

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Embedded M8051 WARP Microcontroller

The embedded M8051 WARP microcontroller provides the overall control for the TAS3218 device. This control

includes device initialization, memory loading, I²C transactions, control pin operations, and participation in most

processing tasks requiring multi-frame processing cycles.

The microcontroller has its own data RAM for storing intermediate values and queuing I²C commands, a fixed

boot program ROM and a programmable program RAM. The microprocessors boot program cannot be altered.

The microcontroller has specialized hardware for a master and slave interface operation, Volume Updates, and a

programmable interval timer interrupt.

M8051 Addressing Modes

The 256 bytes of Internal Data Memory address space is accessible using indirect addressing instructions

(including stack operations). However, only the lower 128 bytes are accessible using direct addressing. The

upper 128 bytes of direct address Data Memory space are used to access ESFRs.

Register Banks

There are four directly addressable register banks, only one of which may be selected at one time. The register

banks occupy Internal Data Memory addresses from 00 hex to 1F hex.

Bit Addressing

The 16 bytes of Internal Data Memory that occupy addresses from 20 hex to 2F hex are bit-addressable. SFRs

that have addresses of the form 1XXXX000 binary are also bit-addressable.

Scratchpad

Internal data memory occupying direct addresses from 30 hex to 7F hex can be used as scratch pad registers or

for the stack.

External Data Memory

External Data RAM occupies a 64K address space. This space contains the External Special Function Data

Registers ESFRs. The ESFRs permit access and control of the hardware features and internal interfaces of the

TAS3218 Digital Signal Processor.

M8051 Boot-Up Sequence

Figure 17 shows the boot-up sequence. M8051 MCU ROM code follows this sequence after device reset

release. After Micro completes boot up application code (RAM code), the microcontroller switches the program

counter from ROM to RAM code by pc_source(esfr - 0xFD).

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Any State

Reset

State

RESET = True

RESET = False

Start-up Oscillator

Initialize

DPLL

PLL Locked and Stable

DAP -> Idle

uP -> Initialization

I2C BUS -> HIGH

uP Flushs

Internal RAM

RAM Flushed

uP Flushs

RAM Flushed

External RAM

uP -> Cmd to

Flush Delay

Memory

Delay Memory Flush command issued

uP initialize

its variables

Variables initialized

uP Sets default

H/W configuration

Default Values

Loaded

uP Flushs

uP Instruction

RAM

RAM Flushed

uP Flushs DAP

Instruction RAM

RAM Flushed

uP Flushs

DAP Coef/Data

RAM

RAM Flushed

Setup

I2C Master I /F

Enable I2C

Master mode

EEPROM

Load Process

Disable I2C

Master mode

3 Reads tried

OR

SCL, SDA = LOW for 1ms detected

GPIO1 = Low

Load default

DAP Program

and coefficient

Check GPIO 1

Successful Load

GPIO1 = High

Loaded

Zero length data

header has been read

Setup

I2C Slave I/F

Enable DAP

Processing start

GPIO1

output Low

Successful Load

Zero length data header

has been received

Test command

received

Switch ROM to RAM

I2C Slave

download process

Test Processing

Routine

Main IDLE loop

IDLE uP

Slave download

command received

Start App uP Code

Figure 17. Boot-Up Sequence

Detailed information about the boot-up sequence is described in Table 4.

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Table 4. Process Description

PROCESS STATE

DSP idle

ESFR

DESCRIPTION

uP initialization

I²C bus high

uP Flush Internal RAM

uP Flush External RAM

Clear micro internal RAM (256 byte)

Clear micro external RAM (2048 byte)

uP command to Flush Delay

Memory

clr_dly_ram (0xc0 bit(3))

1

uP initialize variables

Initialize variables

mute0_t

0

mute1_t

0

Default mutez control

mute2_t

0

reset_dac_mod

reset_adc_sinc

clock_control1

clock_delay_control2

clock_delay_sel

i2s_word_byte

i2c_mode_byte

sap_en

0xff

0x03

0x0a

0x05

0x80

0x22

1

uP set default H/W configuration

IW/OW: 24 bit

IM/OM: I²S

uP Flush uP Instruction RAM

uP Flush DSP Instruction RAM

mem_sel

0x02

0x01

Clear uP Instruction RAM (16384Byte)

Clear DSP Instruction RAM (3328W)

mem_sel

Clear DSP lower coefficient RAM (1024 W) and data

(48 bit) RAM (768 W)

uP flush DSP lower coef/data RAM mem_sel

0x00

Enable I²C master I/F

EEPROM load

Setup I²C master I/F mode (enable interrupt 10)

Disable I²C master mode and

enable slave I/F

i2c_ms_ctl

0

1

Switch control MUX to slave I²C port

Switch ROM to RAM

pc_source

host_dsp

If (gpio_in_3_0 == 1) {

Host_dsp = 1; /* keep DSP turned off */

} else {

Host_dsp = 0; /* turn on DSP */

}

Load default DSP

Program and coefficient

0

GPIO1 output low

Enable GPIO output mode, and output low.

Control Pins

RESET

RESET is an asynchronous control signal that restores all TAS3218 components to the default configuration.

When a reset occurs, the Digital Audio Processor (DAP) is put into an idle state and the M8051 MCU starts

initialization. A reset can be initiated by inputting logic 0 on the reset pin . A reset will also be issued at power up

sequencing by the internal 1.8V regulator power sub-system.

NOTE:

There is a 1.3-s de-glitch filter on the RESET pin.

During a power up sequencing process, RESET should be held low until the DVDD and AVDD power inputs

have reached a voltage of 3.0 V.

As long as the RESET pin is held a logic 0 the device is in the reset state. During this reset state, all I²C and

Serial Data bus operations are ignored. The I²C interface SCL and SDA lines goes HIGH and remain in that state

until device initialization has completed.

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Power-Up Sequence

The rising edge of the RESET pin begins the initialization of housekeeping functions by clearing memory and

setting the default register values. After housekeeping initialization is complete, the TAS3218 enables the master

I²C interface. The TAS3218 then uses the master I²C interface to determine if an external memory device is

present.

External Memory Device Present

Using the master I²C interface, the TAS3218 will automatically test to see if an external memory device is at

address 1010xxx. The value xxx can be chip selects, other information, or dont care depending on the EEPROM

selected.

If an external memory device is present and it contains the correct header information along with one or more

blocks of program/memory data, the TAS3218 will automatically download the M8051 MCU program RAM,

coefficient and/or data RAM from the external EEPROM. This download is considered complete when an end of

program header is read by the TAS3218.

The memory block structure of the external memory device is available in Master I2C Load RAM Block Formats.

At this point, the TAS3218 will disable the master I²C interface, enable the slave I²C interface, and start normal

operation. After a successful download, the M8051 MCU program counter will be reset and the downloaded

M8051 MCU and DSP application firmware will control execution.

External Memory Device Not Present

If no external EEPROM is present or if an error occurred during the external memory device read, the TAS3218

will disable the master I²C interface, enable the slave I²C interface. The default slave configuration will then be

loaded from the ROM into the M8051 MCU and DSP. In this default configuration, the TAS3218 will stream audio

from input to output if the GPIO1 pin pulled LOW.

NOTE:

The master and slave interfaces do not operate simultaneously, thus when one

interface is enabled, the other is disabled.

I²C Chip Select

The CS pin on the TAS3218 allows up to two TAS3218 devices to be addressed by the I²C bus via an external

host controller without the need for external logic. Table 5 and Table 6 list the I²C address for each I²C interface.

Table 5.

I²C Slave Addressing

SLAVE ADDRESS

0x68/69

CS

0

0x6A/6B

1

Table 6.

I²C Master Addressing

SLAVE ADDRESS

0xA0/A1

CS

0

0xA2/A3

1

GPIO Pins

The TAS3218 has two level-sensitive GPIO pins, GPIO1 and GPIO2, that are firmware programmable. Upon

power up or following a RESET, the GPIO1 pin becomes an input, and has a special function as described in

GPIO1 Pin Function.

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GPIO1 Pin Function

•

After RESET or powerup initialization, if no EEPROM is present, a memory error occurs, or SDA and SCL are

pulled LOW for 1 ms, then TAS3218 will disable the master I²C interface and enable the slave I²C interface

initialization, to load the slave default configuration.

–

When GPIO1 has been pulled HIGH through a 1020-k resistor the TAS3218 will then initialize in the

default configuration with the serial data outputs not active. Once the TAS3218 has completed its default

initialization procedure, with the status register updated and the I²C slave interface enabled, then the

GPIO1 pin will become an output and will be driven LOW. Following the High to Low transition of the

GPIO1 pin, the system controller can access the TAS3218 through the I²C interface and read the status

register to determine the load status.

If a memory read error occurs the TAS3218 will report the error in the status register.

–

When GPIO1 has been pulled LOW through a 1020-k resistor to permit a simple functional device test, the

GPIO1 pin can be pulled low using external logic and a 1020-k resistor. In this case, once the TAS3218

has completed its default test initialization procedure, with the status register updated and the I²C slave

interface enabled, then the TAS3218 will stream audio from the input SDIN1 to outputs SDOUT1 and

SDOUT2.

At this point the GPIO1 pin will become an output and will be driven LOW. If the external logic is no longer

driving the GPIO1 pin low after the load has completed (100 ms following a RESET if no EEPROM is

present), then the state of the GPIO1 pin can be observed. At this point the system controller can access

the TAS3218 through the I²C interface and read the status register to determine the load status.

NOTE:

If the GPIO1 pin state is not observed, the only indication that the device has

completed its initialization procedure is that the TAS3218 will stream audio and the

I²C slave interface has been enabled.

NOTE:

Some I²C masters will hang when they receive a NAC during an I²C transaction.

•

Once the TAS3218 has been programmed either through a successful boot load or via slave I²C download,

the operation of GPIO1 can be programmed to be an input or an output.

General Purpose I/O Ports (GPIOs)

In I²C slave mode, the GPIO ports can be used as true general-purpose ports. Each port can be individually

programmed, via the I²C bus, to be either an input or an output port. The default assignment for all GPIO ports,

in I²C slave mode, is an input port.

When a given GPIO port is programmed as an output port, by setting the appropriate bit in the bit field GPIODIR

of subaddress 0x0C to logic 1, the logic level output is set by the logic level programmed into the appropriate bit

in bit field GPIO IN OUT. The I²C bus then controls the logic output level for those GPIO ports assigned as

output ports. When a given GPIO port is programmed as an input port by setting the appropriate bit in bit field

GPIODIR to logic 0, the logic input level into the GPIO port is written to the appropriate bit in bit field GPIO IN

OUT. The I²C bus can then be used to read bit field GPIO IN OUT to determine the logic levels at the input GPIO

ports. Whether a given bit in the bit field GPIO IN OUT is a bit to be read via the I²C bus or a bit to be written to

via the I²C bus is strictly determined by the corresponding bit setting in bit field GPIODIR.

In the I²C slave mode, the GPIO input ports are read every GPIOMICROCOUNT Micro Clocks, as was the case

in the I²C master mode. However, parameter GPIO_samp_int does not have a role in the I²C slave mode. If a

GPIO port is assigned as an output port, a logic 0 bit value is supplied by the TAS3218 for this GPIO port in

response to a read transaction at subaddress 0x0C.

If the GPIO ports are left in their power turn on default state, they are input ports with a weak pull-up on the input

to VDSS.

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Watchdog Timer

There is a hardware watchdog timer in the TAS3218 that can be programmed in the customer application code

to monitor the microprocessor activity. If the watchdog timer expires it will generate a reset to the 8051

microprocessor. GPIOMICROCOUNT, in subaddress 0x0C, is used in order to trigger GPIO input/output and the

monitoring to the DSP diagnostic count. Because of this, the value selected for GPIOMICROCOUNT must be

chosen to provide a good tradeoff of between micro overheard and adequate execution frequency of these

processes. The default value for this counter is 0x5820 which corresponds to a period of 1.25 ms.

Figure 18 shows the GPIO register, the GPOI interface, and a typical user application code implementation of the

watchdog timer reset.

I²C Sub Address x 0C

31

30

27

25

24 23

15

GPIOMICROCOUNT

LS BYTE

7

0

GPIOMICROCOUNT

MS BYTE

GPIO IN/OUT GPIO DIR

0

GPIO_samp_int

See Note A

S

Slave Addr Ack Sub Addr Ack WDE Res

Ack

1

0

8051 uControl

Data_IN_OUT

“0” (default state) enables

watchdog timer

Down Counter

LD

MICRO_CLK

Reset

MICRO_CLK

Watchdog Timer

Decode 2^16

8051 uC Firmware

Decode 2^16

Reset

Data Path

Switch

ENB

GPIO1

Q

D

Sampling

Logic

ENB

GPIO1

Q

D

A. Determines how many consecutive Logic 0 samples (where each sample is spaced by GPIOMICROCOUNT

Micro_clks) are required to read a Logic 0 on a GPIO input port

Figure 18. GPIO Ports

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I²C Control Interface

General I²C Transactions

The M8051 microprocessor receives and distributes I²C data to the I²C bus controllers, and participates in most

I²C processing tasks requiring multi-frame processing cycles. The master and slave interfaces do not operate

simultaneously.

The I²C communication protocol for the I²C slave mode is shown in Figure 19.

Start

(by master)

Read or Write

(by master)

Stop

(by master)

Slave Address

(By master)

Data Byte

(by transmitter)

Data Byte

(by transmitter)

S

0

1

0

1

S

(See Note A)

Acknowledge

(by TAS3208)

Acknowledge

(by receiver)

Acknowledge

(by receiver)

I2C_SDA

I2C_SCL

MSB

MSB–1 MSB–2

LSB

Start Condition

I2C_SDA ↓ while I2C_SCL = 1

Stop Condition

I2C_SDA ↑ while I2C_SCL = 1

A. Bits CS1 and CS0 in the TAS3218 slave address are compared to the logic levels on pins CS0 and CS1 for address

verification. This provides the ability to address up to four TAS3218 chips on the same I²C bus.

Figure 19. I²C Slave Mode Communication Protocol

The I²C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially one bit at a time. The address and data be transferred in byte

(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop

conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.

Normal data bit transitions must occur within the low time of the clock period. The master generate the 7-bit slave

address and the read/write (R/W) bit to open communication with another device and then wait for an

acknowledge condition. The slave holds SDA LOW during acknowledge clock period to indicate an

acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is

addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals

via a bi-directional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and

SCL signals to set the HIGH level for the bus.

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus.

A read transaction requires that the master device first issue a write transaction to give the TAS3218 the sub

address to be used in the read transaction that follows. This sub address assignment write transaction is then

followed by the read transaction. For write transactions, the sub address is supplied in the first byte of data

written, and this byte is followed by the data to be written. For write transactions, the sub address must always

be included in the data written. There cannot be a separate write transaction to supply the sub address, as was

required for read transactions. If a subaddress assignment only write transaction is followed by a second write

transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is

interpreted by the TAS3218 as another sub address replacing the one previously written.

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Multiple Byte Write

A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes

are transmitted by the master device to slave as shown in Figure 20. After receiving each data byte, the

TAS3218 will respond with an acknowledge bit.

Start

Condition

Stop

Condition

Acknowledge

A0 Ack D7

Acknowledge

D0 Ack D7

Acknowledge

D0 Ack D7

Acknowledge

A6

A5

A1 A0 R/W Ack A7

A6

A1

D0 Ack

SS

I²C Device Address and Read/ Write Bit

First Data Byte

Other Data Bytes

Last Data Byte

Sub Address

Figure 20. Multiple Byte Write Transfer

Multiple Byte Read

A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes

are transmitted by the TAS3218 to the master device as shown in Figure 21. Except for the last data byte, the

master device will respond with an acknowledge bit after receiving each data byte.

Repeat Start

Condition

Stop

Condition

Start

Condition

Not

Acknowledge

A6

A0 R/W Ack

A7 SS A0 Ack

A6

D7 SS D0 Ack D7 SS D0 Ack D7 SS D0 Ack

SS A0

R/W Ack

SS

I²C Device Address

and Read/Write Bit

I²C Device Address

and Read/Write Bit

First Data Byte

Other Data Bytes

Last Data Byte

Sub Address

Figure 21. Multiple Byte Read Transfer

Random I²C Transactions

Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. For random

I²C read commands, the TAS3218 responds with data, a byte at a time, starting at the sub address assigned, as

long as the master device continues to respond with acknowledges. If a given sub address does not use all 32

bits, the unused bits are read as logic 0. I²C write commands, however, are treated in accordance with the data

assignment for that address space. If a write command is received for a biquad sub address, for example, the

TAS3218 expects to see five 32-bit words. If fewer than five data words have been received when a stop

command (or another start command) is received, the data received is discarded.

Sequential I²C Transactions

The TAS3218 supports sequential I²C addressing. For write transactions, if a sub address is issued followed by

data for that sub address and the fifteen sub addresses that follow, a sequential I²C write transaction has taken

place, and the data for all 16 sub addresses is successfully received by the TAS3218. For I²C sequential write

transactions, the sub address then serves as the start address and the amount of data subsequently transmitted,

before a stop or start is transmitted, determines how many sub addresses are written to. As was true for random

addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data

is written to the last sub address, the data for the last sub address is discarded. However, all other data written is

accepted; just the incomplete data is discarded.

Sequential read transactions do not have restrictions on outputting only complete sub address data sets.

If the master does not issue enough data received acknowledges to receive all the data for a given sub address,

the master device simply does not receive all the data.

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If the master device issues more data received acknowledges than required to receive the data for a given sub

address, the master device simply receives complete or partial sets of data, depending on how many data

received acknowledges are issued from the sub address(es) that follow. I²C read transactions, both sequential

and random, can impose wait states.

For the standard I²C mode (SCL = 100 kHz), worst-case wait state times for an 8-MHz microprocessor clock is

on the order of 2 s. Nominal wait state times for the same 8-MHz microprocessor clock is on the order of 1 s. For

the fast I²C mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock, worst-case wait state times can

extend up to 10.5 s in duration. Nominal wait state times for this same case lie in a range from 2 s to 4.6 s.

Increasing the microprocessor clock frequency lowers the wait state times and for the standard I²C mode, a

higher microprocessor clock can totally eliminate the presence of wait states.

For example, increasing the microprocessor clock to 16 MHz results in no wait states. For the fast I²C mode,

higher microprocessor clocks shortens the wait state times encountered, but does not totally eliminate their

presence.

I²C Master Mode Operation

I²C master mode operation is enabled following a reset or power on reset.

The TAS3218 uses the master mode to download from EEPROM the memory contents for the following.

•

Micro program memory

Micro extended memory

DSP program memory

DSP coefficient memory

DSP data memory

The TAS3218, when operating as an I²C master, can execute a complete download of any internal memory or

any section of any internal memory without requiring any wait states.

When the TAS3218 operates as an I²C master, it generates a repeated start without an intervening stop

command while downloading program and memory DATA from an external EEPROM. When a repeated start is

sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to quickly transfer large blocks

of data.

Repeat Start

Condition

Stop

Condition

Start

Condition

Not

Acknowledge

A6

A0 R/W Ack

A7 SS A0 Ack

A6

D7 SS D0 Ack D7 SS D0 Ack D7 SS D0 Ack

SS A0

R/W Ack

SS

I²C Device Address

and Read/Write Bit

I²C Device Address

and Read/Write Bit

First Data Byte

Other Data Bytes

Last Data Byte

Sub Address

Figure 22. Multiple Byte Read Transfer

The TAS3218 will query the bus for an I²C EEPROM at an address 1010xxx. The value xxx can be chip selects,

other information, or dont cares depending on the EEPROM selected.

The first act of the TAS3218 as master will be to transmit a start condition along with the device address of the

I²C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the address

byte, and the TAS3218 send a sub address byte, which the EEPROM will acknowledge. Most EEPROMs have at

least 2-byte addresses and will acknowledge as many as are appropriate. At this point, the EEPROM sends a

last acknowledge and becomes a slave transmitter. The TAS3218 acknowledges each byte repeatedly to

continue reading each data byte that is stored in memory.

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The memory load information starts with reading the header and data information that starts at sub-address 0 of

the EEPROM. This information must be stored in a sequential memory addresses with no intervening gaps. The

Data block is contiguous blocks of data that immediately follow the headers locations. The TAS3218 memory

data can be stored and loaded in (almost) any order. Additionally this addressing scheme permits portions of the

TAS3218 internal memories to be loaded.

I2C EEPROM Memory Map

Block Header 1

Data Block 1

Block Header 2

Data Block 2

…

Block Header N

Data Block N

Figure 23. EEPROM Address Map

The TAS3218 will sequentially read EEPROM memory and load its internal memory unless it does not find a

valid memory header block, is not able to read the next memory location because the end of memory was

reached, detects a check sum error, or reads a end of program header block. When it encounters a valid header

or read error, the TAS3218 will attempt to read the header or memory location three times before it determines

that it has an error. If the TAS3218 encounters a Check Sum error it will attempt to re-read the entire block of

memory two more times before it determines that it has an error.

NOTE:

Once the micro program memory has been loaded, it can not be reloaded until the

TAS3218 has been RESET.

If an error is encountered TAS3218 terminates its memory load operation, loads the default configuration for both

the M8051 MCU and DSP from the embedded ROM, and disables further master I²C bus operations.

If an end of program data block is read, the TAS3218 has completed the initial program load.

The I²C master mode utilizes the starting and ending I²C check sums to verify a proper EEPROM download. The

first 16-bit data word received from the EEPROM is the I²C check sum at sub address 0x00, is stored and

compared against the 16-bit data word received for last subaddress, the ending I²C check sum and the check

sum that is computed during the download. These three values must be equal. If the read and computed values

do not match, the TAS3218 sets the memory read error bits in the Status register and repeats the download from

the EEPROM two more times. If the comparison check again fails the third time, the TAS3218 sets the micro

program to the default value.

NOTE:

When acting as an I²C master, the data rate transfer is fixed at 375 kHz.

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I²C Slave Mode Operation

The I²C slave mode is the mode that is used to change configuration parameters during operation and perform

program and coefficient downloads from a master device. The latter can be used to replace the I²C master mode

EEPROM download.

The TAS3218 uses the slave mode to load the memory contents for the:

•

Micro program memory

Micro extended memory

DSP program memory

DSP coefficient memory

DSP data memory

Update coefficient and other control values

Read status flags

The TAS3218 support both random and sequential I²C transactions. The TAS3218 I²C slave address is

011010X, where the first 6 bits are the TAS3218 device address and the final 1 bit is set by the TAS3218 internal

microprocessor at power-up. The internal microprocessor derives the last bit from an external pin (pin CS) which

is pulled up or down to create two unique addresses for control of multiple-TAS3218 part applications. The

pulldown resistance of CS creates a default 00 address when no connection is made to the pin.

The TAS3218 I²C block does respond to the broadcast address (00h).

NOTE:

When acting as an I²C slave, data rate transfer is determined by the master device on

the bus. However, the setting of I²C parameter N at sub-address 0x01 does play a

role in setting the maximum possible data transfer rate. In the I²C slave mode, bit

rates other than (and including) the I²C-specific 100 Kbps and 400 Kbps bit rates can

be obtained, but N must always be set so that the over-sample clock into the I²C

master and slave controllers is at least a factor of 20 higher in frequency than SCL.

N = 0 is a special case. When N = 0, a mode is enabled that detects I²C frames and enables the TAS3218 I²C

interface to reset and continue operation after receiving an invalid I²C frame.

Table 7.

I²C Slave Addresses

SLAVE ADDRESS

0x68/69

CS

0

0x6A/6B

1

Table 8.

I²C Master Addresses

SLAVE ADDRESS

0xA0/A1

CS

0

0xA2/A3

1

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Digital Signal Processor (DSP) Arithmetic Unit

Overview

The arithmetic processor is a fixed-point computational engine consisting of an arithmetic unit and data and

coefficient memory blocks. The primary features are:

•

Two pipe parallel processing architecture

–

48-bit datapath with 76-bit accumulator

Hardware single cycle multiplier (28 48)

Three 48-bit general purpose data registers

One 28 bit coefficient register

48-bit adder

28-bit adder

Shift right, shift left

Bi-modal clip

Log2/Alog2

Magnitude truncation

•

Read/read/write single-cycle memory access

Data input is 48-bit 2s complement multiplexed in from SAP immediately following FSYNC pulse

Data output is four 32-bit 2s complement busses

Separate control for writing to delay memory

Separate coefficient memory (28-bit) and data memory (48-bit)

Linear Feedback Shift Register (LFSR) in the instruction register doubles as a random number generator in

normal operating mode

•

Coefficient RAM, Data RAM, LFSR seed, Program counter, and memory pointers are all mapped into the

same memory space for convenient addressing by the micro

Memory interface block contains four pointers, two for data memory and two for coefficient memory

Data Format

Figure 24 shows the data word structure of the arithmetic unit. Eight bits of overhead or guard bits are provided

at the upper end of the 48-bit word, and 16 bits of computational precision or noise bits are provided at the lower

end of the 48-bit word. The incoming digital audio words are all positioned with the most significant bit abutting

the 8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as

signed data samples.

The arithmetic engine is a 48-bit (25.23 format) processor consisting of a general-purpose 76-bit arithmetic logic

unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks)

always involve 48-bit words and 28-bit coefficients (usually I²C programmable coefficients). If a group of products

are to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a DSP-like

multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain

precision in the intermediate computational stages.

To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations, intermediate

overflows are permitted, and it is assumed that subsequent terms in the computation flow will correct the

overflow condition.

The memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM, and a fixed

program ROM. Only the coefficient RAM, assessable via the I²C bus, is available to the user.

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47

S

Overhead/Guard Bits

S

40

39

S

16-bit

18-bit

audio

32

31

20-bit

audio

24-bit

audio

24

23

22

21

32-bit

audio

20

19

16

15

8

7

Precision/Noise Bits

0

Figure 24. Arithmetic Unit Data Word Structure

8-Bit ALU Operation

(without saturation)

10110111 (–73)

+ 11001101 (–51)

10000100 (–124)

–73

–51

+

–124

–45

+ 11010011 (–45)

01010111

(57)

(59)

–169

59

Rollover

+ 00111011

10010010 (–110)

–110

Figure 25. DSP ALU Operation with Intermediate Overflow

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DAP Data Path Data Representation

D23 D22 ------------ D1 D0

Input 24-Bit Data

0 ... 0

D23 D22 ------------ D1 D0

39 ------------------16

0 ... 0

15–0

8-Bit Headroom

and 16-Bit Noise

47–40

Coefficient

Representation

27–23

22 --------------- 0

Scaling

Data (24-Bits)

Headroom

70–63

8

Fractional Noise

Multiplier

Output

30–0

31

75–71

5

62–39

12

38–31

8

12

48-Bit Clipping

POS48 =

NEG48 =

0x7F_F FFF_FFFF

0x80_0 000_0000

_FF

_00

32-Bit Clipping

POS40 =

NEG40 =

0xXX_ 7FFF_FFFF

0xXX_ 8000_0000

_XX

28-Bit Clipping

POS20 =

NEG20 =

0xXXXXX_ 7FFF_FFF

0xXXXXX_ 8000_000

Figure 26. DSP Data Path Data Representation

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28

24

DATA RAM

1024 ^X24

Micro

Mem

IF

24

28

48

28

DATA RAM

768 ^X48

COEF RAM

1.2 K ^X24

28

VOL (5 LSBs)

VOL

48

DI (3 LSBs)

28

28 48

48

28 48

48

LFS

2

48

MD

48

28

MC

48

L

B

48

28

Barrel Shift

NEG, ABS, or

THRU

LOG, ALOG,

NEG, ABS, or

THRU

DLYO

Multiply

76

ACC

76

MR

48

BR

LR

Legend

“ZERO”

76

48

76

48

Register

24

28

32

48

Operand A

Operand B

24-bit data

28-bit data

32-bit data

48-bit data

76-bit data

ADD

76

CLIP

48

76

Delay RAM

DLYI

Output Register File (DO8–DO8)

32

To Output SAP

Figure 27. DSP Data Path Architecture

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DO0

DO1

DO2

DO3

DO4

DO5

DO6

DO7

DO8

Inside core

Outside core

Audio_out8

Audio_out2 Audio_out3

Audio_out5 Audio_out6 Audio_out7

DAC

(TDM)

Audio_out1

SDOUT1(L)

Audio_out4

SDOUT2(R)

Micro Data

Ext_mem

(2^ndGen)

SPDIF(L)

SPDIF(R)

SDOUT1(R)

SDOUT2(L)

Figure 28. DSP Output Register Configuration

DSP

MICRO

Coef RAM

(1K x 28)

48 -bit

Datapath

28x 48-bit Multiplier

76-bit Accumulator

Data RAM

Internal

(768 x 48 )

Data RAM

(256 x 8)

Memory

Interface

DSP

Program RAM

(3.25 K x 55 )

External

Data RAM

(2K x 8)

Controller

8-bit MCU

(8051 )

Program RAM

(16 K x 8)

Delay

Memory

Control

(

17408 x 24 )

A. Memory size K = 1024

Figure 29. DSP, MCU, and Memory Interfaces

Delay Memory

The Delay Memory Interface (DMIF) is the interface block between the DSP core and the delay memory. The

DMIF blocks primary purpose is to keep track of twenty four sets of delay memory pointers that are initially set up

by the micro controller through an I²C command(s). Eight of the pointers are used to write/retrieve 48-bit data

(full-precision intermediate) and the other sixteen for 24-bit data (post quantized). Thus to support 48-bit word

reverb delay, two RAM locations must be used.

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The key features of the felay memory are

•

17408 24 delay memory locations

Twenty four separately addressable pointers

Programmable start/stop address on each pointer

Pointers capable of accessing 24-bit or 48-bit words

Single port access (one pointer access per access cycle)

Access cycle < 4 DSP clocks

Self clearing INIT pin used to clear all memory to zero

Fully synchronous

DP1DP15: sixteen 24-bit pointers

RP1RP8: eight 48-bit (full precision) pointers

Since all of the pointers are contiguous, it is only necessary to write the address END point. For example, if DP1

is to be a three-sample delay, the register DP1 should be set to 0x003. If RP1 is to be a 3 sample delay, the

register RP1 should be set to the value of DP15 + 6. All of the DP1-16 and RP1-8registers must be set to a

minimum of a one sample delay (one or two words).

DP1 Start address is defined as 000x0

DP2 Start address is equal to DP1 end address + 1 ...

RP1 Start address is equal to DP16 end address + 1 ...

RP8 Start address is equal to RP7 end address + 2

Since the start/stop address for each pointer is programmable anywhere in the delay RAMs address space, the

delay for any one channel can be anywhere in the delay RAM. There is, however, no address space collision

avoidance logic to separate the pointers. The user (or micro) must take care to avoid overlapping the address

spacing of each pointer.

Pointer register address endpoint registers DP1-DP16 and RP 1-RP8 are typically written only during the

initialization (fast load) mode of the device. Writing to these registers while the TAS3218 DSP core is accessing

the pointers may cause the pointers to cross the address space of another pointer.

To write to the delay RAM, the TAS3218 DSP core controller must present the data to be written on the

PT_DATA bus (LS bit always in bit zero of the bus), select the pointer to be accessed by driving the PT_SEL

pins, and assert the PT_WZ pin for a minimum of four clocks. The pointer will not increment until a write has

been performed and the PT_WZ pin has been de-asserted.

To perform a read, the PT_OUT bus may be read four clocks after PT_SEL is driven.

DSP Instruction Word

TAS3218 has a 55-bit instruction word. Each instruction has five independent operations, which can load two

operands from data memory and coefficient memory, store the result into data or coefficient memory and perform

two parallel arithmetic operations.

55-BIT INSTRUCTION

ALU First Stage

P1OP

ALU Second Stage

P2OP

Data Memory Load

Coefficient Memory Load

Memory Store

Ext

0

MOP3

13–10

MOP2

AD2

AD3

9–0

MOP1

AD1

54

53–49

48–42

41–37

36–27

26–24

23–14

Figure 30. Instruction Word

The TAS3218 instruction set is a superset of the TAS3218 instruction set, extending the DSP processing

capabilities for improved efficiency of FIR operations as well as extending the addressable memory space. The

Ext instruction bit (bit 54) has been added to extend the internal memory address space by 1 bit, increasing the

memory space from 1K to 2K words.

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The superset instruction word maintains backward compatibility with the 54-bit instruction word of the TAS3218

device, since the 54 bit instruction word required dummy storage of 2 bits in the EEPROM.

TAS3208 instruction word

DUM

54-BIT INSTRUCTION

Data Memory Load

ALU First Stage

ALU Second Stage

Coefficient Memory Load

Memory Store

P1OP

5

P2OP

4

MOP1

5

AD1

10

MOP2

3

AD2

10

MOP3

4

AD3

10

2

54–55

53–49

48–42

41–37

36–27

26–24

23–14

13–10

9–0

Contains two dummy bits in every instruction word of the EEPROM.

All TAS3208 tool compilers always ZERO to these dummy bits in the compile EEPROM image.

Figure 31. Instruction Word

As shown in Figure 32 the extension bit designates an offset of 1K to all three addresses in the instruction word.

However, it should be noted that both data and coefficient memory addresses above the 1K boundary are

reserved for housekeeping processing tasks. Any attempt to write to these addresses may corrupt the audio

output.

New “Ext”-ended field

54-BIT INSTRUCTION

ALU First Stage

P1OP

ALU Second Stage

P2OP

Data Memory Load

Coefficient Memory Load

Memory Store

Ext

0

MOP1

AD1

MOP2

AD2

MOP3

AD3

54

53–49

48–42

41–37

36–27

26–24

23–14

13–10

9–0

Extension bit designates offset of 1K to these

address references for LD/ST operations

Figure 32. Instruction Word Extension Field

DSP Instruction Set

Please see the TAS3xxx Programmers Guide for detailed information regarding programming of this device.

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

MIN

0.5

MAX

3.8

UNIT

V

DVDD

AVDD

Supply voltage range

3.8

V

3.3-V TTL

VDDS + 0.5

AVDDS + 0.5

AVDD⁽²⁾+ 0.5

VDDS + 0.5

AVDDS + 0.5

DVDD⁽³⁾+ 0.5

AVDD⁽⁴⁾+ 0.5

20

V_I

Input voltage range

3.3-V Analog

1.8-V LVCMOS

3.3-V TTL

V

3.3-V Analog

V_O

Output voltage range

1.8-V LVCMOS

I_IK

Input clamp current

(V_I< 0 or V_I> DVDD)

(V_O< 0 or V_O> DVDD)

mA

C

I_OK

T_stg

Output clamp current

Storage temperature range

20

65

150

Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds

260

C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) AVDD is an internal 1.8-V supply derived from a regulator in the TAS3218 chip. Pin XTALI is the only TAS3218 input that is referenced

to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI.

(3) DVDD is an internal 1.8-V supply derived from regulators in the TAS3218 chip. DVDD is routed to DVDD_BYPASS_CAP to provide

access to external filter capacitors, but should not be used to source power to external devices.

(4) Pin XTALO is the only TAS3218 output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed is

for reference; only a crystal should be connected to XTALO. AVDD is also routed to AVDD_BYPASS_CAP to provide access to external

filter capacitors, but should not be used to source power to external devices.

PACKAGE DISSIPATION RATINGS⁽¹⁾⁽²⁾

PACKAGE

T_A25C POWER RATING

DERATING FACTOR ABOVE T_A= 25C

T_A= 70C POWER RATING

TQFP PZP

2.78 W

28.7C/W

1.22 W

(1) High-K Board, 105C junction

(2) Refer to PowerPAD™ Thermally Enhanced Package Application Report (literature number SLMA002).

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Digital supply voltage

MEASUREMENT

MIN

NOM

3.3

MAX UNIT

DVDD

AVDD

3

3.6

V

Analog supply voltage

3.3-V Analog

3.3

3.3-V TTL

2

V_IH

V_IL

High-level input voltage

V

1.8-V LVCMOS (XTL_IN)

3.3-V TTL

1.26

1.95

0.8

Low-level input voltage

1.8-V LVCMOS (XTL_IN)

0.54

Operating ambient air temperature range

(guarantying parametric)

T_A

T_J

20

25

70

C

Operating junction temperature range

105

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AUDIO SPECIFICATIONS CHANNEL, INPUT TO OUTPUT

T_A=25C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, Clock source from XTALI, AES17 filter, second order 30 kHz

low pass filter (unless otherwise noted)

PARAMETER

CONDITIONS

MIN

87

TYP

92

MAX UNIT

A-in ADC DSP DAC Lineout

A-in MUX Lineout

A: WTD

A-WTD

Overall dynamic

range

dB

95

98

AUDIO SPECIFICATIONS DIGITAL FILTERS

T_A=25C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, Clock source from XTALI, AES17 filter, second order 30 kHz

low pass filter (unless otherwise noted)

PARAMETER

ADC Decimation Filter, Fs = 48 kHz

MIN

TYP

MAX

UNIT

Filter gain from 0 to 0.39 Fs

Filter gain at 0.4125 Fs

Filter gain at 0.45 Fs

Filter gain at 0.5 Fs

Filter gain from 0.55 Fs to 64 Fs

Filter group delay

0.1

0.25

3

dB

s

17.5

75

17/Fs

DAC Interpolation Filter, Fs = 48 kHz

Pass band

20

0.45 Fs

Hz

dB

Hz

kHz

dB

s

Pass band ripple

0.06

Transition band

0.45 Fs

0.5501 Fs

7.455 Fs

Stop band

0.5501 Fs

Stop band attenuation

Filter group delay

65

21/Fs

42

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ELECTRICAL SPECIFICATIONS ANALOG SECTIONS⁽¹⁾

T_A=25C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, Clock source from XTALI, AES17 filter, second order 30-kHz

low-pass filter (unless otherwise noted)

PARAMETER

Stereo MUX Input/ADC Channel

Full scale input voltage (0 dB)

Input common mode voltage

DNR

TEST CONDITIONS

1-kHz sine wave input

MIN

TYP

MAX UNIT

1

1.5

93

80

57

90

1.15 Vrms

over recommended operating conditions

60-dB full-scale input applied at Line inputs, A-weighted

1-kHz, 4-dB full-scale input

1.43

90

1.57

V

dBA

dB

k

THD + N

75

PSRR

1 kHz, 100 mVpp on AVDD

51

Channel separation

Input resistance

1 kHz

80

14.6 18.33

10

22

Input capacitance

DAC Channel/DAC Output

Full scale output voltage (0 dB)

Gain error

pF

1-kHz sine wave input, load = 10 k, 10 pF

0.81

10

0.9

Vrms

%

10

Output common mode

DNR

over recommended operating conditions

60-dB full-scale input applied at Line inputs, A-weighted

1-dBFS input, 0 dB gain

1.43

95

1.5

97

90

56

1.57

V

dBA

dB

pF

k

THD + N

80

PSRR

1 kHz, 100 mVpp on AVDD, V_GNDpowered down

50

Load capacitance

Load resistance

10

81

Channel separation

84

dB

1-kHz sine wave input, Load = 16 , external series resistance

DAC Channel/ Headphone Output

= 16 ,

coupling capacitance = 47 F

Full scale output voltage (0 dB)

DNR

0.72

80

0.9

90

60

54

24

Vrms

dBA

dB

60-dB full-scale input applied at Line inputs, A-weighted

0-dBFS input, 0-dB gain

THD + N

50

PSRR

1 kHz, 100 mVpp on AVDD , V_GNDpowered down

48

dB

Maximum output power⁽²⁾

Load capacitance

Load resistance

Channel separation

mW

pF

100

16

70

80

dB

(1) When the TAS3218 is operated in slave mode, the internal analog clocks for ADC and DAC are derived from external MCLKIN input. In

this case, the analog performance will depend on MCLKIN quality (i.e., jitter, phase noise, etc.).

(2) 16- series resistor required in L and R headphone outputs for short-circuit protection.

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ELECTRICAL SPECIFICATIONS ANALOG SECTIONS (continued)

T_A=25C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, Clock source from XTALI, AES17 filter, second order 30-kHz

low-pass filter (unless otherwise noted)

PARAMETER

DAC Channel/Headphone Output

Full scale output voltage (0 dB)

DNR

TEST CONDITIONS

MIN

TYP

MAX UNIT

1-kHz sine wave input, load = 10 k, 10 pF

0.81

80

0.9

90

82

54

80

Vrms

dBA

dB

60-dB full-scale input applied at Line inputs, A-weighted

0-dBFS input, 0 dB gain

THD + N

70

PSRR

1 kHz, 100 mVpp on AVDD, V_GNDpowered down

48

dB

Channel separation

Analog Mux in Bypass Mode

Mux switching noise

Full scale input voltage (0 dB)

Input common mode voltage

Load capacitance

70

dB

1-kHz sine wave input, load = 10 k, 10 pF

LINEIN inputs floating

20

1.43

10

20

mV

1

1.15 Vrms

1.5

1.57

20

V

pF

k

Load resistance

Between Lch and Rch

Between each line input

80

1

dB

Channel separation

Full scale output voltage (0 dB)

0.9

1.1 Vrms

44

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ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

3.3-V TTL

1.8-V LVCMOS (XTL_OUT) I_OH= 0.55 mA

3.3-V TTL I_OL= 4 mA

TEST CONDITIONS

MIN TYP

2.4

MAX UNIT

I_OH= 4 mA

V_OH

High-level output voltage,

Low-level output voltage

V

1.44

0.5

V

V_OL

I_OZ

I_IL

1.8-V LVCMOS (XTL_OUT) I_OL= 0.75 mA

0.396

High-impedance output

current,

3.3-V TTL

20

A

1.8-V LVCMOS (XTL_IN)

V_I= V_IL

1

Low-level input current⁽¹⁾

High-level input current⁽²⁾

3.3-V TTL

1.8-V LVCMOS (XTL_IN)

V_I= V_IH

I_IH

A

3.3-V TTL

DSP clock = 135 MHz,

LRCLKIN/LRCLKOUT = 48

KHz,

XTALI = 24.288 MHz

I_DVDD

Digital supply current

Analog supply current

200

28

mA

DSP clock = 135 MHz,

LRCLKIN/LRCLKOUT = 48

KHz,

I_AVDD

mA

XTALI = 24.288 MHz

I_DVDD

I_AVDD

Digital supply current

Analog supply current

RESET = LOW

0.1

5

mA

(1) Value given is for those input pins that connect to an internal pullup resistor as well as an input buffer. For inputs that have a pulldown

resistor or no resistor, I_ILis 1 A.

(2) Value given is for those input pins that connect to an internal pulldown resistor as well as an input buffer. For inputs that have a pullup

resistor or no resistor, I_IHis 1 A.

MASTER CLOCK SIGNALS

over recommended operating conditions, see Figure 33

PARAMETER

MIN

TYP

MAX

UNIT

24.576

(512 Fs)

(1)

f_XTALI

XTALI frequency (1/ t_cyc1

)

MHz

t_cyc1

XTALI cycle time⁽²⁾

1/(512 Fs)

256 Fs

ns

MHz

ns

f_MCLKIN

MCLKIN frequency (1/ t_cyc2

MCLKIN pulse duration⁽³⁾

)

tw_MCLKIN

f_MCLKOUT

tr_MCLKOUT

tf_MCLKOUT

tw_MCLKOUT

0.4 t_cyc2

0.6 t_cyc2

MCLKOUT frequency(1/ t_cyc3

)

256 Fs

MHz

ns

MCLKOUT rise time

C_L= 30 pF

10

MCLKOUT fall time

MCLKOUT pulse duration⁽⁴⁾

ns

0.4 t_cyc3

0.6 t_cyc3

ns

XTALI master clock

source

MCLKOUT jitter

Delay time,

80

ps

td_MIMO

MCLKIN rising edge to MCLKOUT rising MCLKOUT = MCLKIN

edge

17

ns

(5)

(1) Frequency tolerance is 100 ppm (or better) at 25C.

(2) t_cyc1= 1/ fX_TALI

(3) t_cyc2= 1/ f_MCLKIN

(4) t_cyc3= 1/ f_MCLKOUT

(5) When MCLKOUT is derived from MCLKIN, MCLKOUT jitter = MCLKIN jitter. MCLKOUT has the same duty cycle as MCLKIN when

MCLKOUT = MCLKIN.

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RESET TIMING WITH RESPECT TO DVDD POWER GOOD

See Figure 34

PARAMETER

MIN

TYP

MAX

UNIT

t_pgw(L)

Minimum pulse duration, RESET low following DVDD = 3.3 V

100

ms

RESET TIMING

control signal parameters over recommended operating conditions (unless otherwise noted), see Figure 35

PARAMETER

MIN

TYP

UNIT

s

tr_DMSTATETime to outputs inactive

tw_RESETPulse duration, RESET active

tr_EMSTATETime to enable I²C

100

200

ns

<50

ms

SERIAL AUDIO PORT SLAVE MODE SIGNALS

over recommended operating conditions (unless otherwise noted), see Figure 36

PARAMETER

TEST CONDITIONS

MIN

32

TYP

MAX

48

UNIT

kHz

ns

f_LRCLK

Frequency, LRCLKIN (FS)

tw_SCLKINPulse duration, SCLKIN high⁽¹⁾

0.4 t_cyc

0.6 t_cyc

f_SCLKIN

t_cyc

Frequency, SCLKIN

Cycle time, SCLKIN⁽¹⁾

64 Fs

MHz

ns

1/64 Fs

16

Propagation delay, SCLKIN falling edge to

SDOUT

t_pd1

ns

t_su1

t_h1

t_su2

t_h2

Setup time, LRCLK to SCLKIN rising edge

Hold time, LRCLK from SCLKIN rising edge

Setup time, SDIN to SCLKIN rising edge

Hold time, SDIN from SCLKIN rising edge

10

5

ns

10

5

Propagation delay, SCLKIN falling edge to

SCLKOUT falling edge

t_pd2

SCLKOUT = SCLKIN

15

ns

(1) t_cyc= 1/ f_SCLKIN

SERIAL AUDIO PORT MASTER MODE SIGNALS

over recommended operating conditions (unless otherwise noted), see Figure 37

PARAMETER

Frequency LRCLKOUT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

ns

f_LRCLK

tr_LRCLK

tf_LRCLK

48

Rise time, LRCLKOUT

Fall time, LRCLKOUT

C_L= 30 pF

12

C_L= 30 pF

ns

f_SCLKOUTFrequency, SCLKOUT⁽¹⁾

tr_SCLKOUTRise time, SCLKOUT

tf_SCLKOUTFall time, SCLKOUT

64 Fs

MHz

ns

C_L= 30 pF

12

ns

Propagation delay, SCLKOUT falling edge to

LRCLKOUT edge

t_pd1

t_pd2

5

ns

Propagation delay, SCLKOUT falling edge to

SDOUT12

t_su

t_h

Setup time, SDIN to SCLKOUT rising edge

Hold time, SDIN from SCLKOUT rising edge

25

30

ns

(1) Typical duty cycle is 50/50.

46

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SPDIF INTERFACE SIGNALS TIMING CHARACTERISTICS

PARAMETER

Encoded data sampling rate

SPDIF signal bitrate

Unit interval

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

MHz

ns

Fs

32

48

R_spdif

UI

128 Fs

1/R_spdif

T_LO/T_HI

V_OH

V_OL

Low/high periods

1 UI

2.4

3 UI

0.5

ns

High-level output voltage

Low-level output voltage

3.3-V TTL, I_OH= 4 mA

3.3-V TTL, I_OL= 4 mA

V

I²C INTERFACE AND I/O CHARACTERISTICS OF THE SDA AND SCL BUS LINES FOR

STANDARD- AND FAST-MODE I²C BUS DEVICES

See Figure 38

PARAMETER

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

f_SCL

SCL clock frequency

0

100

0

400⁽¹⁾

kHz

s

Hold time (repeated) START condition. After this period,

the first clock pulse is generated.

t_HD;STA

4

0.6

t_LOW

tHI_GH

t_su;STA

t_su;DAT

t_r

LOW period of the SCL clock

4.7

4

1.3

0.6

s

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data set-up time

4.7

250

0.6

100⁽²⁾

s

ns

s

(3)

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

1000

300

20 + 0.1 C_b

300

(3)

t_f

20 + 0.1 C_b

t_su;STO

t_BUF

C_b

4

0.6

1.3

Bus free time between a STOP and START condition

Capacitive load for each bus line

4.7

s

400

pF

Noise margin at the LOW level for each connected device

(including hysteresis)

V_nL

0.1 V_DD

0.2 V_DD

0.1 V_DD

V

Noise margin at the HIGH level for each connected device

(including hysteresis)

V_nH

V_hys

t_SP

0.2 V_DD

0.05 V_DD

0

V

Hysteresis of Schmitt trigger inputs

Pulse width of spikes which must be suppressed by the

input filter

50

ns

Input current each I/O pin with an input voltage between

0.1 V_DDand 0.9 V_DDmax

I_i

10

10⁽⁴⁾

10

A

C_i

t_of

Capacitance for each I/O pin

pF

ns

Output fall time from V_IHmin to V_ILmax with a bus

capacitance from 10 pF to 400 pF

250⁽⁵⁾

7 + 0.1 C_b

250⁽⁵⁾

(3)

(1) In Master mode the maximum I²C clock rate is 375 kHz.

(2) A Fast-mode I²C bus device can be used in a Standard-mode I²C bus system, but the requirement t_SU;DAT250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line.

(3) C_b= total capacitance of one bus line in pF.

(4) I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if V_DDis switched off.

(5) The maximum t_ffor the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This

allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the

maximum specified tf.

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PARAMETER MEASUREMENT INFORMATION

Waveforms

XTALI

t

cyc1

tw

MCLKI

t

cyc2

td

MI–MO

tr

tf

tw

MCLKO

MCLKOUT

t

cyc3

Figure 33. Master Clock Signals Timing Waveforms

t

pgw(L)

RESET

DVD

3.3 V

Figure 34. Reset Timing During Power-On

RESET

tw

RESET

Start of

Boot Sequence

Outputs

Inactive

tr

= ~100 µs

tr

DMSTATE

EMSTATE

Figure 35. Reset Timing

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PARAMETER MEASUREMENT INFORMATION (continued)

tw

SCLKIN

t

cyc

SCLKIN

t

h1

t

su1

LRCLKIN

(input)

tf

tr

LRCLK, LRCLK

t

pd1

SDOUT1

SDOUT2

t

h2

t

su2

SDIN1

SDIN2

t

pd2

SCLKOUT

Figure 36. Serial Audio Port Slave Mode Timing Waveforms

tf

SCLKOUT

tr

SCLKOUT

t

pd1, SC

LRCLKOUT

tf

tr

LRCLK, LRCLK

t

pd2

SDOUT1

SDOUT2

t

h

t

su

SDIN1

SDIN2

SDIN3

Figure 37. Serial Audio Port Master Mode Timing Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

SDA

t

HD;STA

t

r

SU;DAT

f

t

BUF

SP

t

LOW

t

r

t

f

SCL

t

SU;STO

HD;DAT

SU;STA

t

HIGH

t

HD;STA

S

P

S

Sr

Figure 38. I²C SCL and SDA Timing Waveforms

Master I²C Load RAM Block Formats

This section describes the format of the data that is stored in an external memory device and downloaded to the

TAS3218 via the master I²C bus.

Master I²C Memory Block Header

Table 9. 1 Memory Block Header

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

NOTES

Checksum most significant byte (MSB)

Checksum least significant bye (LSB)

Header ID byte 1 = 0x00

0

2 byte

Checksum of byte 2 through N + 12

2

4

2 byte

Must be 0x001F

Header ID byte 2 = 0x1F

0x00: micro program RAM or

termination header

0x01: micro external data RAM

0x02: DSP program RAM

0x03 : DSP coefficient RAM

0x04: DSP data RAM

Memory to be loaded

1 byte

0x050x0F: reserved

5

6

0x00

1 byte

2 byte

Unused

Start memory address MSB

Start memory address LSB

Total number of byte transferred MSB

If this is a termination header, this

value is 0000

Header size (12) + data byte + last

checksum byte. If this is a termination

header, this value is 0000

8

2 byte

Total number of byte transferred LSB

10

11

0x00

1 byte

Unused

50

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Master I²C Download Memory Block Structure

Table 10. 1 M8051 MCU Program RAM and External Data RAM Block Structure

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

VALUE

NOTES

Checksum MSB

Checksum of byte 2

through N + 12

0

2 byte

Checksum LSB

Header ID byte 1

Header ID byte 2

0x00

0x1F

2

2 byte

Must be 0x001F

0x00 or

0x01

Micro program RAM or

micro external data RAM

4

5

Memory to be loaded

1 byte

0x00

Unused

Start memory address MSB

Start memory address LSB

Total number of byte transferred MSB

Total number of byte transferred LSB

0x00

If this is a termination

header, this value is 0000

6

8

2 byte

Header (12) + data (N) +

checksum (4)

10

11

1 byte

0x00

Unused

0x00

Data byte 1 (LSB)

Data byte 2

12

16

4 byte

14 microprocessor byte

58 microprocessor byte

Data byte 3

Data byte 4 (MSB)

Data byte 5 (LSB)

Data byte 6

Data byte 7

Data byte 8 (MSB)

0x00

Repeated checksum byte

2 through N +11

N + 12

4 byte

Checksum MSB

Checksum LSB

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Table 11. DSP Program RAM Block Structure

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

VALUE

NOTES

Checksum MSB

Checksum LSB

Header ID byte 1

Header ID byte 2

0

2 byte

Checksum of byte 2 through N + 12

0x00

0x1F

2

2 byte

Must be 0x001F

Micro program RAM or micro external

data RAM

4

5

Memory to be loaded

0x00

1 byte

0x02

0x00

Unused

Start memory address

MSB

If this is a termination header, this

value is 0000

6

8

2 byte

Start memory address

LSB

Total number of byte

transferred MSB

Header (12) + data (N) + checksum (4)

Total number of byte

transferred LSB

10

11

0x00

1 byte

0x00

Unused

0x00

Unused

Program byte 1 (LSB)

Program byte 2

Program byte 3

Program byte 4

Program byte 5

Program byte 6

Program byte 7 (MSB)

Program byte 8 (LSB)

Program byte 9

Program byte 10

Program byte 11

Program byte 12

Program byte 13

Program byte 14 (MSB)

Program word 1 D7D0

D15D8

D23D16

12

7 byte

D31D24

D39D32

D47D40

D55D48

19

7 byte

Program word 2

0x00

Repeated checksum byte 2

through N +11

N + 12

0x00

7 byte

0x00

Checksum MSB

Checksum LSB

52

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Table 12. DSP Coefficient RAM Block Structure

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

VALUE

NOTES

Checksum MSB

Checksum LSB

Header ID byte 1

Header ID byte 2

0

2 byte

Checksum of byte 2 through N + 12

0x00

0x1F

2

2 byte

Must be 0x001F

Micro program RAM or micro external

data RAM

4

5

Memory to be loaded

0x00

1 byte

0x03

0x00

Unused

Start memory address

MSB

If this is a termination header, this

value is 0000

6

8

2 byte

Start memory address

LSB

Total number of byte

transferred MSB

Header (12) + data (N) + checksum (4)

Total number of byte

transferred LSB

10

11

0x00

1 byte

0x00

Unused

0x00

Unused

Data byte 1 (LSB)

Data byte 2

Coefficient word 1 D7D0

D15D8

12

16

4 byte

Data byte 3

D23D16

Data byte 4 (MSB)

Data byte 5 (LSB)

Data byte 6

D31D24

Coefficient word 2

Data byte 7

Data byte 8 (MSB)

0x00

Repeated checksum byte 2 through N

+11

N + 12

4 byte

Checksum MSB

Checksum LSB

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Table 13. DSP Data RAM Block Structure

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

VALUE

NOTES

Checksum MSB

Checksum LSB

Header ID byte 1

Header ID byte 2

0

2 byte

Checksum of byte 2 through N + 12

0x00

0x1F

2

2 byte

Must be 0x001F

Micro program RAM or micro external

data RAM

4

5

Memory to be loaded

0x00

1 byte

0x04

0x00

Unused

Start memory address

MSB

If this is a termination header, this

value is 0000

6

8

2 byte

Start memory address

LSB

Total number of byte

transferred MSB

Header (12) + data (N) + checksum (4)

Total number of byte

transferred LSB

10

11

0x00

1 byte

0x00

Unused

0x00

Unused

Data byte 1 (LSB)

Data byte 2

Data word 1 D7D0

D15D8

Data byte 3

D23D16

12

18

6 byte

Data byte 4 (MSB)

Data byte 5

D31D24

D39D32

Data byte 6 (MSB)

Data byte 7 (LSB)

Data byte 8

D47D40

Data byte 9

Data word 2

Data byte 10

Data byte 11

Data byte 12 (MSB)

0x00

Repeated checksum byte 2 through N

+11

N + 12

Checksum MSB

Checksum LSB

Slave I²C Load RAM Block Formats

The slave I²C bus permits the system controller to load the TAS3218 memories as an alternative to using the

master download from an external memory device via the I²C master bus. The transfer is performed by writing to

two I²C registers (0x04 and 0x05). The first register holds the header information, and the second register holds

eight bytes of data. Figure 39 shows the I²C slave download flow.

I²C slave download register format are described in Table 14 to Table 18. The I²C slave download process is

terminated when a termination header with zero length byte count field is received.

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Enable I²C Slave Mode

receive mem_load_ctrl (0x04)

IDLE

Initialize Header

Information

Clear Invalid Memory

Select Status

Invalid

> 0

Num_byte?

0 (= termination

header)

Mem_select

Valid

YES

Status Error?

Status I = error

NO

pc_source = 1

PCON = 0x01

Check num_byte

NG

Num_byte OK?

OK

RAM Switch

receive

mem_load_ctrl

(0x04)

Halt DSP

host_dsp = 1

Load Data

receive

mem_load_data

(0x05)

Load Received Data

to Specified Memory

Calculate Checksum

NO

End Checksum?

YES

Check Checksum

YES

Checksum Error?

NO

Clear Error Status

Figure 39. I²C Slave Download Flow

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Table 14. M8051 Microcontroller Program RAM

and External Data RAM Block Structure⁽¹⁾

CALC

CHECK

SUM

TOTAL

NUM

BYTE

REG

BYTE

DATA BLOCK FORMAT

NOTE

1

2

Checksum MSB

Checksum LSB

Memory to be loaded 0x00 or

0x01

3

4

5

6

0x00

Control

register

0x04

Start memory address MSB

Start memory address LSB

Total number of byte transferred

MSB

7

8

Total number of byte transferred

LSB

1

2

3

4

5

6

7

8

Datum 1 D7D0

Datum 2 D7D0

Datum 3 D7D0

Datum 4D7D0

Datum 5 D7D0

Datum 6 D7D0

Datum 7 D7D0

Datum 8 D7D0

Data

Register

0x05

1

2

3

4

5

6

7

8

Datum 9 D7D0

Datum 10 D7D0

Datum 11D7D0

Datum 12 D7D0

Datum 13 D7D0

Datum 14 D7D0

Datum 15 D7D0

Datum 16 D7D0

Data

Register

0x05

1

2

3

4

5

6

7

8

Datum N-3 D7D0

Datum N-2 D7D0

Datum N-1 D7D0

Datum N D7D0

0x00

If the last data register datum

is less than 6 byte, zero data

should be filled.

Data

Register

0x05

Should be zero

0x00

Checksum MSB

Checksum LSB

End checksum is always

located here

(1) Shades cells indicate the values included in the checksum/total number of bytes calculation.

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Table 15. DSP Program RAM Block Structure⁽¹⁾

CALC

CHECK

SUM

TOTAL

NUM

BYTE

REG

BYTE

DATA BLOCK FORMAT

NOTE

1

2

3

4

5

6

Checksum MSB

Checksum LSB

Memory to be loaded 0x02

0x00

Control

register

0x04

Start memory address MSB

Start memory address LSB

Total number of byte transferred

MSB

7

8

Total number of byte transferred

LSB

1

2

3

4

5

6

7

8

0x00

D55D48

D47D40

D39D32

D31D24

D23D16

D15D8

D7D0

Data

Register

0x05

Program word 1

1

2

3

4

5

6

7

8

0x00

D55D48

D47D40

D39D32

D31D24

D23D16

D15D8

D7D0

Data

Register

0x05

Program word 2

1

2

3

4

5

6

7

8

0x00

Should be zero

Data

Register

0x05

0x00

Checksum MSB

Checksum LSB

End checksum is always

located here

(1) Shades cells indicate the values included in the checksum/total number of bytes calculation.

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Table 16. DSP Coefficient RAM Block Structure⁽¹⁾

CALC

CHECK

SUM

TOTAL

NUM

BYTE

REG

BYTE

DATA BLOCK FORMAT

NOTE

1

2

3

4

5

6

Checksum MSB

Checksum LSB

Memory to be loaded 0x03

0x00

Control

register

0x04

Start memory address MSB

Start memory address LSB

Total number of byte transferred

MSB

7

8

Total number of byte transferred

LSB

1

2

3

4

5

6

7

8

D31D24

D23D16

D15D8

D7D0

Coefficient word 1

Coefficient word 2

Data

Register

0x05

D31D24

D23D16

D15D8

D7D0

1

2

3

4

5

6

7

8

D31D24

D23D16

D15D8

D7D0

Coefficient word 3

Coefficient word 4

Data

Register

0x05

D31D24

D23D16

D15D8

D7D0

1

2

3

4

5

6

7

8

D31D24

D23D16

D15D8

Coefficient word N or zero

Should be zero

Data

Register

0x05

D7D0

0x00

Checksum MSB

Checksum LSB

End checksum is always

located here

(1) Shades cells indicate the values included in the checksum/total number of bytes calculation.

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Table 17. DSP Data Block Structure⁽¹⁾

CALC

CHECK

SUM

TOTAL

NUM

BYTE

REG

BYTE

DATA BLOCK FORMAT

NOTE

1

2

3

4

5

6

Checksum MSB

Checksum LSB

Memory to be loaded 0x04

0x00

Control

register

0x04

Start memory address MSB

Start memory address LSB

Total number of byte transferred

MSB

7

8

Total number of byte transferred

LSB

1

2

3

4

5

6

7

8

0x00

Coefficient word 1

Coefficient word 2

D47D40

D39D32

D31D24

D23D16

D15D8

D7D0

Data

Register

0x05

1

2

3

4

5

6

7

8

0x00

Coefficient word 3

Coefficient word 4

D47D40

D39D32

D31D24

D23D16

D15D8

D7D0

Data

Register

0x05

1

2

3

4

5

6

7

8

0x00

Should be zero

Data

Register

0x05

0x00

Checksum MSB

Checksum LSB

End checksum is always

located here

(1) Shades cells indicate the values included in the checksum/total number of bytes calculation.

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Table 18. Termination Header Block Structure⁽¹⁾

CALC

CHECK

SUM

TOTAL

NUM

BYTE

REG

BYTE

DATA BLOCK FORMAT

NOTE

1

2

3

4

5

6

Checksum MSB

00

Checksum LSB

Memory to be loaded

0x00

Control

register

0x04

Start memory address MSB

Start memory address LSB

Total number of byte transferred

MSB

7

8

00

Total number of byte transferred

LSB

(1) Shades cells indicate the values included in the checksum/total number of bytes calculation.

I²C Register Map

The I²C register map for ROM advanced code is described in Table 19.

Table 19. I²C Register Map⁽¹⁾

SUB

ADDRESS

REGISTER

BYTES

CONTENTS

DEFAULT VALUE

0x00

SAP/Clock Setting

I²C M and N

4

See SAP/Clock Setting

0x01

u(31:24), u(23:16), u(15:8), u(7)M(6:3)N(2:0)

0x00, 0x00, 0x00, 0x00

0x02

0x03

0x04

Status Register

Reserved

8

4

8

See Status Register

u(31:24), u(23:16), u(15:8), u(7:0)

0x00, 0x00, 0x00, 0x00

See Load Memory Control and Data

Register

0x00, 0x00, 0x00, 0x00

I²C RAM Load Control

See Load Memory Control and Data

Register

0x00, 0x00, 0x00, 0x00

I²C RAM Load Data

PEEK/POKE Control

PEEK/POKE Data

0x05

0x06

0x07

8

4

8

See PEEK and POKE

0x00, 0x00, 0x00, 0x00

0x08

0x09

0x0a

0x0b

0x0c

0x0d

0x0e

0x0f

Silicon Version

Mute Control

Reserved

4

ver(31:24), ver(23:16), ver(15:8), ver(7:0)

See Mute Control

0x00, 0x00, 0x00, 0x02

0x00, 0x00, 0x00, 0x00

u(31:24), u(23:16), u(15:8), u(7:0)

See GPIO Control

Reserved

GPIO Control

Reserved

u(31:24), u(23:16), u(15:8), u(7:0)

See Powerdown Control

Reserved

0x10

0x11

0x12

0x13

0x14

0x15

Powerdown Control

Reserved

u(31:24), u(23:16), u(15:8), u(7:0)

See A-MUX Control

A-MUX Control

Reserved

u(31:24), u(23:16), u(15:8), u(7:0)

Reserved

(1) Shades cells indicate common to basic and advanced modes. Unshaded cells indicate advanced mode only.

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Table 19. I²C Register Map (continued)

SUB

ADDRESS

REGISTER

BYTES

CONTENTS

DEFAULT VALUE

0x16

SPDIF Control

Reserved

4

See SPDIF Control

0x00, 0x00, 0x00, 0x00

0x17

u(31:24), u(23:16), u(15:8), u(7:0)

0x18

0x19

0x1a

0x1b

0x00, 0x00, 0x00, 0x01

0x47, 0xae, 0x00, 0x00

0x1c

Reserved

8

u(31:24), u(23:16), u(15:8), u(7:0)

0x1d

0x1e

0x1f

DC Dither

DSP Program Start Address

Reserved

Unused

4

See DC Dither

0x00, 0x00, 0x00, 0x01

0x00, 0x00, 0x00, 0x00

See DSP Program Start Address

u(31:24), u(23:16), u(15:8), u(7:0)

4

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2a

0x2b

0x2c

0x2d

0x2e

0x2f

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

Unused

4

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3a

0x3b

0x3c

0x3d

0xfe

Unused

4

Unused

4

Unused

16

Unused

0xff

Unused

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SAP/Clock Setting (0x00)

The SAP/Clock Setting register is used to configure the device as a Clock Master/Slave as well as specify the

desired format of the digital audio ports. This register is four bytes in length.

Table 20. SAP/Clock Setting

BIT

31

30

29

28

27

26

25

24

DESCRIPTION

Unused

0

CM/S

Clock master/slave select

23

22

14

21

13

20

12

19

11

18

10

17

9

16

Unused

ON

SAP output normalization

15

8

0

Unused

OW1 OW0

Digital audio output word size

Unused

0

IW1

IW0

Digital audio input word size

BIT

7

6

5

4

3

2

1

0

Unused

OM1 OM0

Digital audio output format

Unused

0

IM1

IM0

Digital audio input format

Table 21. Clock Master/Slave Select⁽¹⁾

CLOCK MASTER/SLAVE SELECT

CMS

Master

1

Slave

0

(1) Default values are shown in italics.

Table 22. Digital Audio Port Normalization⁽¹⁾

DIGITAL AUDIO PORT NORMALIZATION

ON

1

Enable

Disable

0

(1) Default values are shown in italics.

Bits 98 (IW1 and IW0) define the data word size for the input SAP. Bits 1312 (OW1 and OW0) define the data

word size for the output SAP.

Table 23. Audio Data Word Size⁽¹⁾

DIGITAL AUDIO I/O WORD SIZE

IW1/OW1

IW0/OW0

16 bit

20 bit

24 bit

0

1

0

1

0

1

(1) Default values are shown in italics.

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Table 24. Audio Data Format⁽¹⁾

DIGITAL AUDIO I/O FORMAT

IM1/OM1

IM0/OM0

Left-justified

Right-justified

I²S

0

1

0

1

0

1

(1) Default values are shown in italics.

Status Register (0x02)

Status register provide memory load information. When a memory load error for a particular memory occurs, the

memory load error bit for that memory is set to 1. When a memory load is successful for a particular memory the

memory load error bit for that memory is set to 0. Host needs to check this load status after memory load. Host

can clear all load error status by writing 0 to bits D40D32 of this register.

Table 25. SAP/Clock Setting

BIT

63

0

62

0

61

0

60

0

59

0

58

0

57

0

56

0

DESCRIPTION

Reserved

55

0

54

0

53

0

52

0

51

0

50

0

49

0

48

Reserved

Unsused

47

0

46

0

45

0

44

0

43

0

42

0

41

0

BIT 40

39

x

38

x

37

x

36

x

35

x

34

x

33

x

32

1

x

Micro program memory load error

Micro external memory load error

DAP program memory load error

DAP coefficient memory load error

DAP data memory load error

x

1

x

1

x

1

x

1

x

1

x

DAP upper data memory load error

DAP upper coefficient memory load

error

x

1

x

1

x

Invalid memory select

End of load header error

No EEPROM

1

0

No error

BIT

31

0

30

0

29

0

28

0

27

0

26

0

25

0

24

Reserved

BIT

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

8

15

0

14

13

12

11

10

9

7

6

5

4

3

2

1

0

Reserved

Analog busy flag

Reserved

ABSY

0

Reserved

0

Reserved

0

Reserved

BUSE

I²C bus error

0

Reserved

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Bits 4032 define the memory load error status on EEPROM download and slave download.

Table 26. Analog Busy⁽¹⁾

ANALOG BUSY FLAG

Analog is busy

ABSY

1

Analog not busy

0

(1) Default values are shown in italics.

Analog control sequence takes time (maximum around 500 ms for headphone power up). This busy flag indicate

whether analog control sequence is running or not.

Table 27. I²C Bus Error⁽¹⁾

I²C BUS ERROR

BUSE

Bus error

1

No bus error

0

(1) Default values are shown in italics.

If I²C bus error occurs, this flag will be set. Only host uC can clear this flag by writing 0 to this bit. I²C bus error

status is read from ESFR (0xC5, bit 6), and is cleared by ESFR (0xC7, bit 6).

Load Memory Control and Data Register (0x04 and 0x05)

The I²C Memory Load port permits the system controller to load the TAS3218 memories as an alternative to

having the TAS3218 load its memory from an external EEPROM.

The transfer is performed by writing to two I²C registers. The first register is a eight byte register than holds the

check sum, the memory to be written, the starting address, the number of data bytes to be transferred. The

second register holds eight bytes of data.

The memory load operation starts with the first register being set. Then the data is written into the second

register using the format shown. After the last data byte is written into the second register, an additional two

bytes are written which constrain the two byte checksum. At that point, the transfer is complete and status of the

operation is reported in the status register.

NOTE:

Once the micro program memory has been loaded, further updates to this memory

are inhibited until the device is RESET.

When the first I²C slave down load register is written by the system controller the TAS3218 will update the status

register by setting a error bit to indicate an error for the memory type that is being loaded. This error bit is reset

when the operation complete and a valid checksum has been received.

For example when the Micro program memory is being loaded, the TAS3218 will set a Micro program memory

error indication in the status register at the start of the sequence. When the last byte of the micro program

memory and checksum is received, the TAS3218 will clear the micro program memory error indication. This

enables the TAS3218 to preserve any error status indications that occur as a result of incomplete transfers of

data/ checksum error during a series of data and program memory load operations.

The checksum is always contained in the last two bytes of the data block.

The I²C slave download is terminated when a termination header with a zero length byte count filed is received.

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Table 28. Load Memory Control Register (0x04)

BYTE

DATA BLOCK FORMAT

Checksum code

SIZE

NOTES

12

2 bytes

Checksum of bytes 2 through N+8, If this is

a termination header, this value is 00 00.

3

Memory to be loaded

1 byte

0: Micro Program memory

1: Micro External Data memory

2: DSP Program memory

3: DSP Coefficient memory

4: DSP Data Memory

515: Reserved

4

Unused

1 byte

Reserved

67

Starting TAS3218

Memory address

2 bytes

If this is a termination header, this value is

00 00

78

Number of data bytes to be transferred

2 bytes

If this is a termination header, this value is

00 00

Table 29. Load Memory Data Register (0x05)

BYTE

8-BIT DATA

Datum 1 D7D0

24-BIT DATA

28-BIT DATA

XXXX D27D24

48-BIT DATA

55-BIT DATA

1

2

3

4

5

6

7

8

Datum 2 D7D0

Datum 3 D7D0

Datum 4 D7D0

Datum 5 D7D0

Datum 6 D7D0

Datum 7 D7D0

Datum 8 D7D0

D23D16

D15D8

X D54D48

D15D8

D7D0

D47D40

D39D32

D31D24

D23D16

D15D8

D7D0

D39D32

D31D24

D23D16

D15D8

D7D0

XXXX D27D24

D23D16

D15D8

D23D16

D15D8

D7D0

PEEK and POKE (0x06 and 0x07)

Registers 0x06 (Table 30) and 0x07 (Table 31) allow the user to access the internal resources of TAS3218.

Figure 40 shows the I²C transaction for PEEK and POKE register.

Table 30. Memory Select and Address (0x06)

BIT

31

0

30

0

29

0

28

0

27

0

26

0

25

0

24

0

DESCRIPTION

Unused

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

1

DSP coefficient memory load error

DSP data memory load error

DSP delay memory

0

1

0

1

0

1

0

M8051 internal data memory

M8051 external data memory

Extended special function registers

M8051 program memory

0

1

0

1

0

1

0

1

0

1

0

DSP program memory

BIT

15

0

14

0

13

0

12

0

11

0

10

0

9

8

0

Memory address MSB

Memory address LSB

7

6

5

4

3

2

1

0

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Table 31. Data Register (0x07)

BIT

63

D63 D62 D61

55 54 53

D55 D54 D53

47 46 45

D47 D46 D45

39 38 37

D39 D38 D37

31 30 29

D31 D30 D29

23 22 21

D23 D22 D21

15 14 13

D15 D14 D13

62

61

60

D60

52

59

D59 D58 D57

51 50 49

D51 D50 D49

43 42 41

D43 D42 D41

35 34 33

D35 D34 D33

27 26 25

D27 D26 D25

19 18 17

D19 D18 D17

58

57

56

D56

48

DESCRIPTION

Data to be read or written

D52

44

D48

40

Data to be read or written

D44

36

D40

32

D36

28

D32

24

D28

20

D24

16

D20

12

D16

8

11

10

9

D9

1

D12

4

D11 D10

D8

0

7

6

5

3

2

D7

D6

D5

D4

D3

D2

D1

D0

Memory Select and Address

Sub address

(0x06)

Slave address

+ W

ACK

S

00000000

memory section

address (MS Byte)

address (LS Byte)

P

Peek (Read)

Sub address

(0x07)

Slave address

+ W

ACK

ACK P

S

Slave address

+ W

ACK

NAK

D55–D48

D23–D16

D47–D40

D15–D8

D63–D56

D31–D24

D39–D32

D7–D0

P

Poke (Write)

Sub address

(0x07)

Slave address

+ W

ACK

NAK

ACK

D55–D48

D23–D16

D47–D40

D15–D8

S

D63–D56

D31–D24

D39–D32

D7–D0

P

Figure 40. I²C Transaction for PEEK and POKE

66

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Mute Control

Table 32. Mute Control

BI

T

31

0

30

0

29

0

28

0

27

0

26

0

25

0

24

0

DESCRIPTION

Unused

BI

T

23

0

22

0

21

0

20

0

19

0

18

0

17

16

Unused

AMX3 AMX3

AMUX03 (LINEOUT3)

BI

T

15

14

13

12

11

10

9

8

AMX2 AMX2

Analog MUX out (LINEOUT2)

Analog MUX out (LINEOUT1)

SDOUT2/SPDIFOUT

SDOUT1

AMX1 AMX0

SD2

SD1

BI

T

7

6

5

4

3

2

1

0

DAC1 DAC1

DAC1 (DACOUT1)

DAC2 (DACOUT2)

DAC3 (HPOUT)

DIT (BiPhase)

DAC2 DAC2

DAC3 DAC3

DIT

Table 33. MUTE⁽¹⁾

MUTE

MUTE[1]

MUTE[0]

HW Mute Control

Force mute off

Force mute on

0

x

1

0

1

0

(1) Default values are shown in italics.

GPIO Control (0x0c)

Table 34. GPIO Control (0x0c)

BIT

31

30

29

28

27

26

25

24

DESCRIPTION

Watchdog timer

WDE

0

Unused

IO2

GPIO2 input/output value

GPIO1 input/output value

GPIO2 direction

IO1

DIR2

DIR1

GPIO1 direction

BIT

23

x

22

x

21

x

20

x

19

x

18

x

17

x

16

x

GPIOMICROCOUNT MSB

GPIOMICROCOUNT LSB

GPIO_Sampling_Interval

15

x

14

x

13

x

12

x

11

x

10

x

9

8

x

7

6

5

4

3

2

1

0

y

GPIOMICROCOUNT sets the number of micro clock cycles for Timer 0 interrupt. In Timer 0 interrupt service

routine, watchdog timer is reset if it is enabled. The default value for this counter is 0x5820 which correspond to

a period 1.25 ms.

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Table 35.

Watchdog Timer Enable⁽¹⁾

WATCHDOG TIMER

Enable

WDE

0

Disable

1

(1) Default values are shown in italics.

Table 36. GPIO Direction⁽¹⁾

GPIOx DIRECTION

Output

DIRx

0

1

Input

(1) Default values are shown in italics.

Powerdown Control (0x10)

Table 37. Powerdown Control

BIT 31

30

0

29

0

28

0

27

0

26

0

25

0

24

0

DESCRIPTION

0

BIT 23

0

Unused

22

0

21

0

20

0

19

0

18

0

17

0

16

0

Unused

BIT 15

0

14

0

13

0

12

0

11

0

10

0

9

8

0

BIT

7

6

5

4

3

2

1

0

DIT

DIT reset

DAC3

DAC3 (HPOUT)

DAC2

DAC2 (DACOUT2)

DAC1 (DACOUT1)

AMUX + AAF + ADC

AMUX3 + Line Amp 3

AMUX2 + Line Amp 2

AMUX1 + LineAmp1

DAC1

ADC

AMX3

AMX2

AMX1

Table 38. Powerdown⁽¹⁾

POWERDOWN

PD

Powerdown and disable

0

Powerup and enable

1

(1) Default values are shown in italics.

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A-MUX Control (0x12)

Table 39. A-MUX Control (0x12)

BIT

31

x

0

23

x

0

15

x

30

x

0

22

x

0

14

x

29

x

0

21

x

0

13

x

28

x

0

20

x

0

12

x

27

1

0

19

1

0

11

1

0

26

1

0

1

0

18

1

0

1

0

10

1

0

1

25

1

0

1

0

1

0

1

0

17

1

0

1

0

1

0

1

0

9

1

0

1

0

1

0

24

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8

1

0

1

0

1

0

1

0

1

0

1

DESCRIPTION

Reserved

DAC

Analog MUX line 10 select

Analog MUX line 9 select

Analog MUX line 8 select

Analog MUX line 7 select

Analog MUX line 6 select

Analog MUX line 5 select

Analog MUX line 4 select

Analog MUX line 3 select

Analog MUX line 2 select

Analog MUX line 1 select

MUTE

Reserved

AMUX2 IN 10

AMUX2 IN 9

AMUX2 IN 8

AMUX2 IN 7

AMUX2 IN 6

AMUX2 IN 5

AMUX2 IN 4

AMUX2 IN 3

AMUX2 IN 2

AMUX2 IN 1

MUTE

Reserved

AMUX3 IN 10

AMUX3 IN 9

AMUX3 IN 8

AMUX3 IN 7

AMUX3 IN 6

AMUX3 IN 5

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Table 39. A-MUX Control (0x12) (continued)

BIT

31

x

0

7

x

0

30

x

0

6

x

0

29

x

0

5

x

0

28

x

0

4

x

0

27

0

3

1

0

26

1

0

2

1

0

1

0

25

0

1

0

1

0

1

0

1

0

1

0

24

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

DESCRIPTION

AMUX3 IN 4

AMUX3 IN 3

AMUX3 IN 2

AMUX3 IN 1

MUTE

BIT

Reserved

DAC

Analog MUX line 10 select

Analog MUX line 9 select

Analog MUX line 8 select

Analog MUX line 7 select

Analog MUX line 6 select

Analog MUX line 5 select

Analog MUX line 4 select

Analog MUX line 3 select

Analog MUX line 2 select

Analog MUX line 1 select

MUTE

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SPDIF Control (0x16)

Table 40. PDIF Control (0x16)

BIT 31

30

29

28

27

26

25

24

DESCRIPTION

Copyright flag

CP

EMP

Pre-emphasis flag

CLKAC CLKAC

Clock accuracy

b28

b29

20

0

WL3

WL2

WL1

WL0

Sample word length

BIT 23

SR

22

SR

b25

21

19

18

17

16

Sampling rate

b24

0

VL

Left-channel validity flag

Right-channel validity flag

VR

SRC# SRC# SRC# SRC#

Source channel number

b19

11

b18

10

b17

9

b16

BIT 15

Cat

14

Cat

b9

13

12

8

Cat

b10

Cat

b11

Cat

b12

Cat

b13

Cat

b14

Category code

b8

0

L

0

Generation status

BIT

7

6

5

4

3

2

1

0

Unused

MUX1 MUX0

SPDIF MUX

Table 41. Copyright Flag⁽¹⁾

COPYRIGHT FLAG

CP

Copy prohibited

0

Copy permitted

1

(1) Default values are shown in italics.

Table 42. Pre-Emphasis Flag⁽¹⁾

PRE-EMPHASIS FLAG

No pre-emphasis

EMP

0

50/15 s pre-emphasis

1

(1) Default values are shown in italics.

Table 43. Sample Word Length

SAMPLE WORD LENGTH

WLx

24-bit sample word length

0

Table 44. Sampling Rate

SAMPLING RATE

b24

b25

48 kHz

0

1

Table 45. Validity Flag⁽¹⁾

VALIDITY FLAG

Valid

Vx

0

Not valid

1

(1) Default values are shown in italics.

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Table 46. Channel Source Number

CHANNEL SOURCE NUMBER

b19

b18

b17

b16

Channel 2

0

1

0

Table 47. Category Code

CATEGORY CODE

b8

b9

b10

b11

b12

b13

b14

Digital sound processor

0

1

0

1

0

1

0

Table 48. Generation Status

GENERATION STATUS

Vx

0

Gen 1 or higher

Original

1

Table 49. SDOUT/SPDIF MUX⁽¹⁾

SDOUT/SPDIF MUX

SDOUT2

MUX1

MUX2

0

1

0

SPDIF Tx

1

SPDIF In

(1) Default values are shown in italics.

DC Dither (0x1d)

Table 50. DC Dither (0x1d)

BIT

31

0

30

0

29

0

28

0

27

0

26

0

25

0

24

0

DESCRIPTION

Unused

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

Unused

15

0

14

0

13

0

12

0

11

0

10

0

9

8

0

7

6

5

4

3

2

1

0

Unused

ON

DC dither enable

Table 51.

DC Dither Enable⁽¹⁾

DC DITHER ENABLE

Disable

ON

0

Enable

1

(1) Default values are shown in italics.

DSP Program Start Address (0x1e)

The DSP instruction execution loops each Fs cycle. At the beginning of the Fs cycle, the DSP instruction pointer

is set to the starting address specified in the 12 LSBs. The maximum address is the end address of DSP

instruction address 3327.

Table 52. DSP Program Start Address (0x1e)

BIT

31

0

30

0

29

0

28

0

27

0

26

0

25

0

24

0

DESCRIPTION

Unused

23

22

21

20

19

18

17

16

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Table 52. DSP Program Start Address (0x1e) (continued)

BIT

31

0

30

0

29

0

28

0

27

0

26

0

25

0

24

0

DESCRIPTION

Unused

15

0

14

0

13

0

12

0

11

x

10

x

9

8

x

Starting address MSB

Starting address LSB

7

6

5

4

3

2

1

0

x

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APPLICATION INFORMATION

DAC

1

R

L

1

2

1

2

22uF

2

10K

1

22uF

2

10K

DAC

2

R

L

1

2

22uF

2

10K

1

Headphone

L

22uF

10K

Line Out

3

R

L

1

2

10K

2

1

47uF

1

2

1

2

R

22uF

2

10K

1

2

10K

147uF

1

22uF

2

10K

Line Out

2

1

R

L

2

1

2

10pF

24.576MHz

AVDD_DAC

22uF

2

10K

1

10pF

R

L

AVDD_HP

2

1

22uF

2

10K

1

AVDD_LI

AVDD_HP

22uF

2

10K

1

AVDD_LI

DVDD1

AVDD_LI

22uF

10K

AVDD_REF

AVDD_ADC

AVDD_REF

AVDD_DAC

AVDD

4.7uF

10uF

0.1 uF

1

2

75

1

2

1uF

DVSS1

V1P5_REF

BG_REF

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1uF

24k

/VREG_EN

RESERVED

MCLKOUT

LRCLKOUT

SCLKOUT

SDOUT1

3

BIAS_REF

4

AVSS_ADC/REF

AVDD_ADC

LINEIN10R

LINEIN10L

AVSS_LI

AVDD

5

AVDD_ADC

33K

2

4.7uF

2

6

1

Line In 10

R

AVDD_HP

7

2

1

2

L

33K

4.7uF

8

MCLK_OUT

L/RCLK_OUT

SCLK_OUT

33K

2

4.7uF

2

4.7uF

0.1 uF

9

1

Line In

9

R

LINEIN9R

LINEIN9L

AVDD_LI

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

2

L

33K

4.7uF

AVDD_LI

SDOUT1

33K

2

4.7uF

2

1

AVDD

Line In

8

R

L

SDOUT2/SPDIFOUT

SDOUT2/SPDIF_OUT

DVDD2

LINEIN8R

LINEIN8L

AVSS_LI

U1

2

DVDD2

AVDD_HP

33K

4.7uF

TAS3218PZP

VR_DIG1

DVSS2

33K

2

4.7uF

2

1

Line In

7

R

L

LINEIN7R

LINEIN7L

AVDD_LI

2

4.7uF

0.1 uF

SPDIF

SPDIF_IN

RESERVED

SDIN3

33K

4.7uF

AVDD_LI

33K

2

4.7uF

2

1

Line In

6

R

L

LINEIN6R

LINEIN6L

AVSS_LI

4.7uF

2

33K

4.7uF

33K

2

4.7uF

2

1

SDIN3

SDIN2

Line In

5

R

L

LINEIN5R

LINEIN5L

AVDD_LI

2

SDIN2

33K

4.7uF

AVDD_LI

SDIN1

33K

2

4.7uF

2

1

L/RCLK_IN

SCLK_IN

Line In

4

R

L

LRCLKIN

SCLKIN

LINEIN4R

LINEIN4L

2

33K

4.7uF

MCLK_IN

DVDD3

33K

2

4.7uF

2

1

MASTER_SDA

MASTER_SCL

SLAVE_SDA

SLAVE_SCL

Chip_Select

GPIO1

Line In

3

2

1

R

L

DVDD4

4.7uF

AVDD_LI

33K

2

4.7uF

2

Line In

33K

2

4.7uF

2

R

L

33K

2

4.7uF

2

33K

2

4.7uF

2

GPIO2

R

L

33K

2

4.7uF

2

nMUTE

nRESET

DVDD

DVDD3

DVDD4

DVDD1

DVDD2

4.7uF

0.1 uF

4.7uF

0.1 uF

4.7uF

0.1 uF

4.7uF

0.1 uF

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PACKAGE OPTION ADDENDUM

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18-Sep-2008

PACKAGING INFORMATION

Orderable Device

TAS3218IPZP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTQFP

PZP

100

90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TAS3218IPZPR

TAS3218PZPR

HTQFP

PZP

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TAS3218_1
厂家：	TEXAS INSTRUMENTS
描述：	DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE 具有模拟接口的数字音频处理器
文件：	总79页 (文件大小：1305K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TAS3218_1 [TI]

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