TAS3308PZTR [TI]
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE; 具有模拟接口的数字音频处理器
| 型号： | TAS3308PZTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE |
| 文件： | 总11页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS3308
DIGITAL AUDIO PROCESSOR
WITH ANALOG INTERFACE
www.ti.com
SLES215A–FEBRUARY 2008–REVISED MARCH 2008
1
FEATURES
2
•
Audio Input/Output
•
Audio Digital Signal Processor
–
–
–
–
Up to Three Synchronous Serial Audio
Inputs (6 Channels)
–
–
–
–
–
Programmable Functionality
135-MHz Operation
Up to Two Synchronous Serial Audio
Outputs (4 Channels)
Left, RIght and I2S Input Data Formats: 16-,
20-, or 24-Bit Data
Left, Right and I2S Output Data Formats:
16-, 20-, or 24-Bit Data
48-Bit Datapath With 76-Bit Accumulator
Hardware Single Cycle Multiplier (28 × 48)
Two Memory Loads and One Memory Store
Per Cycle
–
–
–
Usable 1K Words Data RAM (48 Bit) and
Usable 1K Coefficient RAM (28 Bit)
–
–
64 × Fs Bit Clock Rate
3.25K Words Instruction Program RAM
(2.8K Words Available)
24.576-MHz XTAL Input for Master Clock
Modes and Clock Auto Detection
360 mS at 48 KHz, 17,408 Words 24-Bit
Delay Memory
–
–
–
Slave Mode 256, 384, or 512 × Fs MCLKIN
With Automatic Clock Rate Detection
•
PWM Features
Slave Mode 32-, 44.1-, and 48-kHz Fs With
Auto Sample Rate Detection
–
–
Proven PurePath Digital™ Technology
Fourth-Order Chaotic Noise Shaper With
Non-Linear Correction
Master Mode – 48-kHz Fs 10 Multiplexed
Stereo Analog Inputs Selectable Into One
Stereo ADC. ADC Maximum Input Level: 1
Vrms SE
–
–
High-Quality DNR 105 dBA (Typical) PWM
Performance
Click and Pop Minimizing at Power
Up/Down Using TI Patented Technology
–
–
Three Stereo Differential PWM Outputs
High-Quality DNR 100-dBA (Typical) ADC
Channel Performance (2 Channels) With
Master Mode Clock
•
General Features
–
–
Easy-to-Use Control Interface
I2C Serial Control Master and Slave
Interface
–
–
High-Quality DNR 105-dBA (Typical) PWM
Channel Performance (6 Channels)
–
Control Interface Operational Without
External MCLK Input
One Single-Ended Analog Stereo Line
Driver Output With 1 of 10 Selectable
Inputs, 10-kΩ, 100=pF Drive Capability
(Maximum Output Level: 1 Vrms)
–
–
–
–
–
Single 3.3-V Power Supply
Integrated Regulators
100-Pin TQFP Package
M8051 Device Controller
–
Line-Out Supports Left/Right, Left/Left, and
Right/Right Combinations
Auto Clock and Serial Data Rate Detection
and Automatic Device Configuration
Without Audible Artifacts
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PurePath Digital is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TAS3308
DIGITAL AUDIO PROCESSOR
WITH ANALOG INTERFACE
www.ti.com
SLES215A–FEBRUARY 2008–REVISED MARCH 2008
PZT PACKAGE
(TOP VIEW)
DVDD_PWM2
PWM2_RD
PWM2_RI
PWM3_LD
PWM3_LI
DVSS_PWM3
DVDD_PWM3
PWM3_RD
PWM3_RI
VALID/SYNC
DVDD2
1
2
3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AVDD_LO
AVDD_REF
V1P5_REF
BG_REF
4
5
BIAS_REF
LINEIN10R
LINEIN10L
AVSS_LI3
LINEIN9R
LINEIN9L
AVDD_LI3
LINEIN8R
LINEIN8L
AVDD_ADC
LINEIN7R
LINEIN7L
AVSS_ADC/REF
LINEIN6R
LINEIN6L
AVSS_LI2
LINEIN5R
LINEIN5L
AVDD_LI2
LINEIN4R
LINEIN4L
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DVSS2
VREG_EN
RSVD
MCLKOUT
LRCLKOUT
SCLKOUT
SDOUT1
SDOUT2/SPDIF_OUT
SPDIF_IN
SDIN3
SDIN2
SDIN1
LRCLKIN
SCLKIN
DESCRIPTION/ORDERING INFORMATION
TAS3308 is an audio system-on-a-chip (SOC) designed for digital TV audio systems and mini/micro component
applications. It includes analog and digital audio interface. For analog input and output the TAS3308 has ten
multiplexed stereo inputs with one stereo ADC and three stereo PWM outputs. For digital input and output the
TAS3308 has three I2S inputs and two I2S outputs. One I2S output can also be configured to be S/PDIF encoded
PCM data.
TAS3308 has a programmable audio DSP that preserves high-quality audio by using a 48-bit data path, 28-bit
filter coefficients, and a single cycle 28 × 48-bit multiplier. The programmability feature allows users to customize
features in the DSP RAM.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TAS3308PZT
TOP-SIDE MARKING
Tray
0°C to 70°C
TQFP – PZT
Tape and reel
TAS3308PZTR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
2
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS3308
TAS3308
DIGITAL AUDIO PROCESSOR
WITH ANALOG INTERFACE
www.ti.com
SLES215A–FEBRUARY 2008–REVISED MARCH 2008
The TAS3308 comprises nine functional blocks.
•
•
•
•
•
•
•
•
•
Analog input/MUX/stereo ADC
Three stereo PWM output for speaker/headphone/stereo
Line driver outputs
Clock, digital PLL, analog PLL, serial data interface, and auto-detect system
Serial control interface/device control
Audio DSP – digital audio processing
8051 device controller
Power supply
Internal references
BLOCK DIAGRAM
MCLK
I2C
PWMCLK,
ADCCLK
APLL
RESET
POWER
Auto-
Detect
REFERENCE
8051 Device
Micro-Controller
XTAL
OSC
%2
DPLL
DIGCLK
SDIN1–3,
LRCLKI,
SCLKI
Input Serial
Audio Port
1–3
LRCLKO, SCLKO,
MCLKO
Output Serial
Audio Port
1024 W
DATA RAM
1024 W
COEF RAM
SDOUT1
360 MS
DELAY RAM
SPDIF
SPDOUT/SDOUT2
SPDIN
Digital
Audio Processor
VALID
10 STEREO
ANALOG IN
Stereo
ADC
Sync
Decimation
PWM
1–3
Decimation
FW
PWM1L(I+D),R(I+D)
Interpolation
PWM2L(I+D),R(I+D)
PWM3L(I+D),R(I+D)
LINEOUT1(L+R)
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): TAS3308
TAS3308
DIGITAL AUDIO PROCESSOR
WITH ANALOG INTERFACE
www.ti.com
SLES215A–FEBRUARY 2008–REVISED MARCH 2008
APPLICATION INFORMATION
3.3V
DVDD1
TAS3308
0.1 u
10
p (TBD)
DVSS1
MCLK_IN
SCLK_IN
LRCLK_IN
XTAL_OUT
3.3V
1M
DVDD2
24.576M
XTAL_IN
0.1 u
10p (TBD)
DVSS2
SDIN_1
SDIN_2
SDIN_3
GPIO_1
GPIO_2
VR_ANA2
3.3V
3.3V
AVDD_PLL
AVSS_PLL
DVDD3
220
0.1u
220
4.7u
0.01u
0.1 u
0.01u
DVSS3
0.1u
0.1u
3.3V
PLL_FLTM
PLL_FLTP
MUTE
RSVD
DVDD4
0.1 u
DVSS4
RESET
I2C_SCL1
I2C_SDA1I
I2C_SCL2
I2C_SDA2
CS
VREG_EN
3.3V
VR_ANA1
AVSS_SOC
VR_ANA2
AVDD_LI1
4. 7u
0.1u
AVSS_LI1
4.7 u
AVSS_PLL
VR_DIG1
DVSS1
3.3V
AVDD_LI2
4.7 u
MCLKOUT
SCLKOUT
LRCLKOUT
SDOUT1
0.1u
VR_DIG2
AVSS_LI2
4.7 u
DVSS_DPLL
3.3V
VR_DIG3
DVSS4
4.7 u
AVDD_LI3
SPDIFOUT/SDOUT2
SPDIFIN
0.1u
47K
AVSS_LI3
LINEIN1L
LINEIN2L
LINEIN3L
LINEIN4L
LINEIN5L
LINEIN6L
LINEIN7L
LINEIN8L
LINEIN9L
LINEIN10L
47K
47K
47K
47K
47K
47K
47K
47K
47K
3.3V
PWM1LI
PWM1LD
PWM1RI
PWM1RD
AVDD_OSC
AVSS_OSC
LPF
LPF
0.1u
3.3V
3.3V
AVDD_REF
0.1u
0.1u
PWM2LI
PWM2LD
PWM2RI
PWM2RD
LPF
LPF
AVDD_LO
AVSS_LO
3.3V
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
AVDD_ADC
LINEIN1R
LINEIN2R
LINEIN3R
LINEIN4R
LINEIN5R
LINEIN6R
LINEIN7R
LINEIN8R
LINEIN9R
LINEIN10R
PWM3RD
PWM3LI
PWM3LD
PWM3RI
0.1u
LPF
LPF
AVSS_ADC/REF
22
10u
22
DVDD_PWM1
VALID/SYNC
2. 2u
2. 2u
47
DVSS_PWM1
DVDD_PWM2
DVSS_PWM2
DVDD_PWM3
DVSS_PWM3
LINEOUT1L
LINEOUT1R
V1P5_REF
47
10u
1u
10k
10k
22
VREG_EN
STEST
BIAS_REF
BG_REF
24
K
<5%
10u
1u
Figure 1. Peripheral Connections
4
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS3308
TAS3308
DIGITAL AUDIO PROCESSOR
WITH ANALOG INTERFACE
www.ti.com
SLES215A–FEBRUARY 2008–REVISED MARCH 2008
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
3.8
UNIT
DVDD
AVDD
Supply voltage range
Input voltage range
3.8
V
DVDD_PWM
3.8
3.3 V TTL
VDDS + 0.5
VDDS + 0.5
AVDDS + 0.5
3.3 V LVCMOS
3.3 V analog
1.8 V LVCMOS
3.3 V TTL
VI
V
V
–0.5 AVDD(2) + 0.5
VO
–0.5
–0.5
–0.5
VDDS + 0.5
VDDS + 0.5
AVDDS + 0.5
3.3 V LVCMOS
3.3 V analog
Output voltage range
–0.5 DVDD(3) + 0.5
–0.5 AVDD(4) + 0.5
1.8 V LVCMOS
IIK
Input clamp current
VI < 0 or VI > DVDD
VO < 0 or VO > DVDD
±20
±20
mA
mA
°C
IOK
Tstg
Output clamp current
Storage temperature range
–65
150
260
Lead temperature 1.6 mm (1/16) inch from case for 10 seconds
°C
(1) Stresses beyond those listed under “absolute ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operation conditions” is
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) AVDD is an internal 1.8-V supply derived from a regulator in the TAS3308 chip. Pin XTALI is the only TAS3308 input that is referenced
to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI.
(3) DVDD is an internal 1.8-V supply derived from regulators in the TAS3308 chip. DVDD is routed to DVDD_BYPASS_CAP to provide
access to external filter capacitors, but should not be used to source power to external devices.
(4) Pin XTALO is the only TAS3308 output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed is
for reference; only a crystal should be connected to XTALO. AVDD is also routed to AVDD_BYPASS_CAP to provide access to external
filter capacitors, but should not be used to source power to external devices.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Digital supply voltage
Analog supply voltage
MEASUREMENTS
MIN NOM
MAX UNIT
DVDD
AVDD
3
3.3
3.3
3.3
3.6
3.6
3.6
V
V
V
3.3 V analog
3
DVDD_PWM PWM supply voltage
3.3 V PWM
3
2
3.3 V TTL
VIH
High-level input voltage
Low-level input voltage
3.3 V LVCMOS (I2C)
1.8 V LVCMOS (XTL_IN)
3.3 V TTL
3.3 V LVCMOS (I2C)
1.8 V LVCMOS (XTL_IN)
(specifying parametrics)
(specifying functions)
0.7 × VDDS
1.26
V
0.8
0.3 × VDDS
0.54
VIL
TA
0
V
0
25
25
70
Operating ambient air temperature
range
°C
–20
70
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): TAS3308
TAS3308
DIGITAL AUDIO PROCESSOR
WITH ANALOG INTERFACE
www.ti.com
SLES215A–FEBRUARY 2008–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MEASUREMENT
3.3 V TTL
3.3 V LVCMOS (I2C)
TEST CONDITIONS
IOH = –4 mA
MIN
2.4
MAX UNITS
V
V
IOH = –0.10 mA
VDDS – 0.2
VOH
High-level output voltage
1.8 V LVCMOS
(XTL_OUT)
IOH = –0.6 mA
1.197
V
3.3 V TTL
3.3 V LVCMOS (I2C)
IOL = 4 mA
0.5
0.2
V
V
IOL = 0.10 mA
VOL
Low-level output voltage
1.8 V LVCMOS
(XTL_OUT)
IOL = 1.8 mA
0.585
V
3.3 V TTL
3.3 V LVCMOS (I2C)
±20
±20
±1
µA
µA
µA
µA
High-impedance output
current
IOZ
Driver only, driver disable
VI = VIL
3.3 V TTL
3.3 V LVCMOS (I2C)
VI = VIL, Receiver only
±1
(1)
IIL
Low-level input current
High-level input current
1.8 V LVCMOS
(XTL_IN)
VI = VIL
VI = VIH
±1
±1
µA
µA
1.8 V LVCMOS
(XTL_IN)
3.3 V LVCMOS (I2C)
(2)
IIH
VI = VIH, Receiver only
VI = VIH
±1
±1
µA
µA
3.3 V TTL
DSP clock = 135 MHz
IDVDD
Digital supply current
Analog supply current
LRCLKIN/LRCLKOUT = 48 KHz,
XTALI = 24.576 MHz
160
40
mA
mA
DSP clock = 135 MHz
LRCLKIN/LRCLKOUT = 48 KHz,
XTALI = 24.576 MHz
IAVDD
IDVDD
IAVDD
Digital supply current
Analog supply current
RESET = LOW
RESET = LOW
100
10
mA
mA
(1) Value given is for those input pins that connect to an internal pullup resistor as well as an input buffer. For inputs that have a pulldown
resistor or no resistor, IIL is ±1 µa.
(2) Value given is for those input pins that connect to an internal pulldown resistor as well as an input buffer. For inputs that have a pullup
resistor or no resistor, IIH is ±1 µa.
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Product Folder Link(s): TAS3308
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2008
PACKAGING INFORMATION
Orderable Device
TAS3308PZT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PZT
100
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS3308PZTR
TQFP
PZT
100
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TAS3308PZTR
TQFP
PZT
100
1000
330.0
24.4
17.0
17.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PZT 100
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
TAS3308PZTR
1000
Pack Materials-Page 2
MECHANICAL DATA
MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996
PZT (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
50
51
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
0,25
15,80
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
1,20 MAX
0,08
4073179/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
TAS333J100P1A
Tantalum Capacitor, Polarized, Tantalum (dry/solid), 100V, 5% +Tol, 5% -Tol, 0.033uF, Through Hole Mount, AXIAL LEADED
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