SN75LBC172ADWG4 [TI]

Quad RS-485 Differential Line Drivers 20-SOIC 0 to 70;


型号：	SN75LBC172ADWG4
厂家：	TEXAS INSTRUMENTS
描述：	Quad RS-485 Differential Line Drivers 20-SOIC 0 to 70 驱动信息通信管理光电二极管接口集成电路驱动器
文件：	总22页 (文件大小：978K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

Designed for TIA/EIA-485, TIA/EIA-422,

and ISO 8482 Applications

Driver Positive- and Negative-Current

Limiting

†

Signaling Rates up to 30 Mbps

Power-Up and Power-Down Glitch-Free for

Live Insertion Applications

Propagation Delay Times <11 ns

Thermal Shutdown Protection

Low Standby Power Consumption

1.5 mA Max

Industry Standard Pin-Out, Compatible

With SN75172, AM26LS31, DS96172,

LTC486, and MAX3045

Output ESD Protection 12 kV

description

The SN65LBC172A and SN75LBC172A are quadruple differential line drivers with 3-state outputs, designed

for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications.

logic diagram (positive logic)

16-DW PACKAGE

N PACKAGE

(TOP VIEW)

GND

11 3Z

10 3Y

GND

20-DW PACKAGE

(TOP VIEW)

logic diagram (positive logic)

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments.

†

The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

description (continued)

These devices are optimized for balanced multipoint bus transmission at signalling rates up to 30 million bits

per second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate

rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise

coupling to the environment.

Each driver features current limiting and thermal-shutdown circuitry making it suitable for high-speed mulitpoint

data transmission applications in noisy environments. These devices are designed using LinBiCMOSt,

facilitating low power consumption and robustness.

The G and G inputs provide driver enable control using either positive or negative logic. When disabled or

powered off, the driver outputs present a high-impedance to the bus for reduced system loading.

The SN75LBC172A is characterized for operation over the temperature range of 0°C to 70°C. The

SN65LBC172A is characterized over the temperature range from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

16-PIN PLASTIC

SMALL OUTLINE

(JEDEC MS-013)

20-PIN PLASTIC

SMALL OUTLINE

(JEDEC MS-013)

16-PIN PLASTIC

THROUGH-HOLE

(JEDEC MS-001)

†

SN75LBC172A16DW

SN65LBC172A16DW

SN75LBC172ADW

Marked as 75LBC172A

SN65LBC172ADW

SN75LBC172AN

0°C to 70°C

SN65LBC172AN

−40°C to 85°C

Marked as 65LBC172A

†

Add R suffix for taped and reeled version.

FUNCTION TABLE

(EACH DRIVER)

INPUT

ENABLES

OUTPUTS

OPEN

H = high level, L = low level, X = irrelevant,

Z = high impedance (off)

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

equivalent input and output schematic diagrams

Y or Z Output

A, G, or G Input

16 V

20 V

100 kΩ

1 kΩ

Input

Output

16 V

9 V

17 V

†

absolute maximum ratings

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

Output voltage range, V , at any bus (steady state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V

Output voltage range, V , at any bus (transient pulse through 100 Ω, see Figure 8) . . . . . . . . . . . −30 V to 30 V

Input voltage range, V , at any A, G, or G terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

Electrostatic discharge: Human body model (see Note 2)

Y, Z, and GND . . . . . . . . . . . . . . . . . . . . . 12 kV

All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV

Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to GND.

2. Tested in accordance with JEDEC standard 22, Test Method A114−A.

3. Tested in accordance with JEDEC standard 22, Test Method C101.

DISSIPATION RATING TABLE

‡

JEDEC

BOARD

MODEL

≤ 25°C

DERATING FACTOR

= 70°C

T = 85°C

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

Low K

High K

Low K

High K

Low K

1200 mW

2240 mW

1483 mW

2753 mW

1150 mW

9.6 mW/°C

17.9 mW/°C

11.86 mW/°C

22 mW/°C

769 mW

1434 mW

949 mW

1762 mW

736 mW

625 mW

1165 mW

771 mW

1432 mW

598 mW

16-PIN DW

20-PIN DW

16-PIN N

9.2 mW/°C

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

recommended operating conditions

MIN NOM

MAX

5.25

UNIT

Supply voltage, V

4.75

−7

Voltage at any bus terminal

High-level input voltage, V

Y, Z

0.8

A, G, G

Low-level input voltage, V

Output current

−60

SN75LBC172A

SN65LBC172A

Operating free-air temperature, T

°C

−40

electrical characteristics over recommended operating conditions

†

PARAMETER

Input clamp voltage

TEST CONDITIONS

MIN TYP

MAX

UNIT

I = −18 mA

−1.5 −0.77

Open-circuit output voltage

Y or Z, No load

2.5

No load (open circuit)

Steady-state differential output voltage

V

OD(SS)



= 54 Ω, see Figure 1

1.6

‡

magnitude

With common-mode loading, see Figure 2

Change in steady-state differential output

voltage between logic states

∆V

OD(SS)

See Figure 1

−0.1

0.1

2.8

Steady-state common-mode output

voltage

See Figure 3

2.4

OC(SS)

Change in steady-state common-mode

output voltage between logic states

∆V

OC(SS)

See Figure 3

A, G, G

−0.02

−50

0.02

Input current

µA

V = 0 V

Short-circuit output current

−200

200

µA

V = V

I CC

= −7 V to 12 V,

TEST

See Figure 7

High-impedance-state output current

Output current with power off

G at 0 V, G at V

−50

−10

= 0 V

O(OFF)

All drivers enabled

All drivers disabled

V = 0 V or V

CC,

Supply current

No load

1.5

†

‡

All typical values are at V

The minimum V

of lower output signal into account in determining the maximum signal transmission distance.

= 5 V and 25°C.

may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

5.5

TYP

MAX

UNIT

Propagation delay time, low-to-high level output

Propagation delay time, high-to-low level output

Differential output voltage rise time

PLH

PHL

7.5

0.6

= 54 Ω, C = 50 pF,

see Figure 4

Differential output voltage fall time

Pulse skew |t

– t

sk(p)

sk(o)

PLH PHL

†

Output skew

Part-to-part skew

‡

sk(pp)

PZH

PHZ

PZL

Propagation delay time, high-impedance-to-high-level output

Propagation delay time, high-level-output-to-high impedance

Propagation delay time, high-impedance-to-low-level output

Propagation delay time, low-level-output-to-high impedance

See Figure 5

See Figure 6

PLZ

†

‡

Output skew (t

Part-to-part skew (t

) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.

sk(o)

) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when

sk(pp)

both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test

circuits.

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

PARAMETER MEASUREMENT INFORMATION

54 Ω

GND

Figure 1. Test Circuit, V

Without Common-Mode Loading

375 Ω

TEST

= −7 V to 12 V

Input

60 Ω

375 Ω

TEST

Figure 2. Test Circuit, V

With Common-Mode Loading

27 Ω

Signal

Generator

‡

= 50 pF

50 Ω

†

PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω

‡

Includes probe and jig capacitance

Figure 3. V

Test Circuit

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

‡

C = 50 pF

= 54 Ω

Signal

Generator

50 Ω

†

‡

PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω

Includes probe and jig capacitance

3 V

1.5 V

0 V

Input

PHL

PLH

≈ 1.5 V

90%

0 V

10%

Output

≈ −1.5 V

Figure 4. Output Switching Test Circuit and Waveforms

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

PARAMETER MEASUREMENT INFORMATION

Output

0 V or 3 V w

‡

= 50 pF

= 110 Ω

Input

Signal

Generator

50 Ω

†

3 V

†

‡

PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω

Includes probe and jig capacitance

3-V if testing Y output, 0 V if testing Z output

3 V

1.5 V

0 V

Input

0.5 V

PZH

2.3 V

0 V

Output

PHZ

Figure 5. Enable Timing Test Circuit and Waveforms, t

and t

PHZ

PZH

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

PARAMETER MEASUREMENT INFORMATION

5 V

= 110 Ω

Output

0 V or 3 V w

‡

= 50 pF

Input

Signal

Generator

50 Ω

†

3 V

†

‡

PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω

Includes probe and jig capacitance

3-V if testing Y output, 0 V if testing Z output

3 V

1.5 V

0 V

Input

PZL

PLZ

5 V

Output

2.3 V

0.5 V

Figure 6. Enable Timing Test Circuit and Waveforms, t

and t

PLZ

PZL

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

TEST

Voltage Source

= −7 V to 12 V

TEST

Slew Rate ≤ 1.2 V/µs

Figure 7. Test Circuit, Short-Circuit Output Current

TEST

100 Ω

0 V

15 µs

−V

TEST

Pulse Generator

15 µs Duration,

1% Duty Cycle

1.5 ms

Figure 8. Test Circuit and Waveform, Transient Over-Voltage

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS

DIFFERENTIAL OUTPUT VOLTAGE

OUTPUT CURRENT

FREE-AIR TEMPERATURE

2.5

3.5

= 5.25 V

= 5 V

= 5.25 V

2.5

1.5

= 5 V

= 4.75 V

0.5

1.5

= 4.75 V

0.5

100

−60 −40 −20

100

− Output Current − mA

− Free-Air Temperature − °C

Figure 9

Figure 10

PROPAGATION DELAY TIME

SUPPLY CURRENT (FOUR CHANNELS)

TEMPERATURE

SIGNALING RATE

8.5

144

142

140

138

136

134

132

130

128

= 54 Ω

= 50 pF

(Each Channel)

= 5.25 V

7.5

= 4.75 V

6.5

5.5

−40

−20

100

T − Temperature − °C

Signaling Rate − Mbps

Figure 11

Figure 12

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS

= 54 Ω

= 50 pF

Figure 13. Eye Pattern, Pseudorandom Data at 30 Mbps

APPLICATION INFORMATION

TMS320F243

DSP

SN65LBC172A

SN65LBC175A

TMS320F241

DSP

(Controller)

(Embedded

Application)

SPISIMO

IOPA1

(Enable)

SPISTE

IOPA1

IOPA2

SPICLK

IOPA0

(Handshake

/Status)

SPISOMI

Figure 14. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

SN65LBC172A16DW

SN65LBC172A16DWG4

SN65LBC172A16DWR

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

65LBC172A

ACTIVE

Green (RoHS

& no Sb/Br)

-40 to 85

65LBC172A

2000

Green (RoHS

& no Sb/Br)

-40 to 85

SN65LBC172A16DWRG4

SN65LBC172ADW

ACTIVE

SOIC

TBD

Call TI

-40 to 85

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

65LBC172A

75LBC172A

SN65LBC172ADWG4

SN65LBC172ADWR

SN65LBC172ADWRG4

SN65LBC172AN

ACTIVE

SOIC

PDIP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 85

0 to 70

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Pb-Free

(RoHS)

SN65LBC172ANE4

Pb-Free

(RoHS)

N / A for Pkg Type

SN75LBC172A16DW

SN75LBC172A16DWG4

SN75LBC172A16DWR

SN75LBC172A16DWRG4

SN75LBC172ADW

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

0 to 70

2000

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

SN75LBC172ADWG4

SN75LBC172ADWR

Green (RoHS

& no Sb/Br)

0 to 70

2000

Green (RoHS

& no Sb/Br)

0 to 70

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

SN75LBC172AN

ACTIVE

PDIP

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

75LBC172A

SN75LBC172ANE4

ACTIVE

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN65LBC172A16DWR

SN65LBC172ADWR

SN75LBC172A16DWR

SN75LBC172ADWR

SOIC

2000

330.0

16.4

24.4

16.4

24.4

10.75 10.7

2.7

12.0

16.0

24.0

16.0

24.0

10.8

13.0

13.3

10.75 10.7

10.8

13.0

13.3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN65LBC172A16DWR

SN65LBC172ADWR

SN75LBC172A16DWR

SN75LBC172ADWR

SOIC

2000

367.0

38.0

45.0

38.0

45.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN75LBC172ADWG4 [TI]

相关型号：

SN75LBC172ADWR

SN75LBC172ADWRG4

SN75LBC172AN

SN75LBC172DW

SN75LBC172DWG4

SN75LBC172DWR

SN75LBC172DWRG4

SN75LBC172N

SN75LBC172NE4

SN75LBC173

SN75LBC173A

SN75LBC173AD